Multi-chip system and pulse width monitoring and calibration method

Abstract

A multi-chip system includes a plurality of chips and a monitoring and calibration system. The plurality of chips includes at least a first chip and a second chip, wherein an output port of the first chip is connected to an input port of the second chip via an inter-chip connection, the first chip transmits an output signal to the second chip via the inter-chip connection, and the second chip processes an input signal derived from the output signal transmitted via the inter-chip connection. The monitoring and calibration system calibrates chip settings of at least one of the first chip and the second chip for pulse width calibration of the input signal.

Description

TECHNICAL FIELD

[0001] The present invention relates to a multi-chip system, and more particularly, to a multi-chip system having signal transmission by high frequency pulses. BACKGROUND

[0002] Process variation is a variation that naturally occurs in properties of semiconductor transistors in a chip when the chip is manufactured. Process variation causes a measurable and predictable variation in the output performance of the chip. Generally, process variation of a chip causes signal distortion in communication between chips. Therefore, there is a need for an innovative signal monitoring and calibration design that can handle the effect of signal distortion on transmission. SUMMARY

[0003] It is an object of the present invention to provide a multi-chip system having pulse width monitoring and calibration and an associated pulse width monitoring and calibration method.

[0004] According to a first aspect of the present invention, an exemplary multi-chip system is disclosed. The exemplary multi-chip system comprises a plurality of chips and a monitoring and calibration system. The plurality of chips comprises at least a first chip and a second chip, wherein an output of the first chip is connected to an input port of the second chip via a chip-to-chip connection, the first chip is arranged to transmit an output signal to the second chip via the chip-to-chip connection, and the second chip is arranged to process an input signal, the input signal being derived from the output signal transmitted via the chip-to-chip connection. The monitoring and calibration system is arranged to calibrate chip settings of at least one of the first chip and the second chip for calibrating a pulse width of the input signal.

[0005] According to a second aspect of the present invention, an exemplary pulse width monitoring and calibration method for a multi-chip system is disclosed. The multi-chip system comprises a plurality of chips, and the plurality of chips comprises at least a first chip and a second chip. The exemplary pulse width monitoring and calibration method comprises estimating and recording a pulse width of an input signal, wherein an output port of the first chip is connected to an input port of the second chip via a chip-to-chip connection. The first chip transmits an output signal to the second chip via the chip-to-chip connection, the second chip processes an input signal, the input signal being derived from the output signal transmitted via the chip-to-chip connection. Based on the recorded pulse width of the input signal, chip settings of at least one of the first chip and the second chip are calibrated for pulse width calibration of the input signal.

[0006] According to a third aspect of the present application, an exemplary pulse width monitoring and calibration method for a multi-chip system is disclosed. The multi-chip system includes a plurality of chips, and the plurality of chips includes at least a first chip and a second chip. The exemplary pulse width monitoring and calibration method includes estimating and recording a pulse width of an input signal, wherein an output port of the first chip is connected to an input port of the second chip via an inter-chip connection. The first chip transmits an output signal to the second chip via the inter-chip connection, and the second chip processes an input signal, which is derived from the output signal transmitted via the inter-chip connection. Based on the recorded pulse width of the input signal, a chip setting of at least one of the first chip and the second chip is calibrated to pulse width calibrate the input signal.

[0007] The embodiments of the present application calibrate the pulse width of the input signal of the second chip by calibrating the chip setting of at least one of the first chip and the second chip to reduce signal distortion.

[0008] These and other objects of the present application will no doubt become obvious to one of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in various drawings and accompanying figures. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a schematic diagram illustrating one multi-chip system according to an embodiment of the present application.

[0010] Figure 2 is a schematic diagram illustrating another multi-chip system according to an embodiment of the present application.

[0011] Figure 3 is a schematic diagram illustrating a pulse width calibration design according to an embodiment of the present application.

[0012] Figure 4 is a flow chart illustrating a pulse width monitoring and calibration method according to an embodiment of the present application.

[0013] Figure 5 is a schematic diagram illustrating pulse width estimation performed by a measurement circuit according to an embodiment of the present application.

[0014] Figure 6 is a schematic diagram illustrating a multi-chip system with many serially connected chips according to an embodiment of the present application. DETAILED DESCRIPTION

[0015] Certain terms are used throughout the following description and claims, which refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers can refer to a component by different names. This application does not intend to distinguish between components that differ in name but not in function. In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "including, but not limited to...." Also, the term "couple" is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection can be a direct electrical connection or an indirect electrical connection via other devices and connections.

[0016] Figure 1 is a schematic diagram illustrating one multi-chip system according to an embodiment of the application. The multi-chip system 100 comprises a plurality of chips 102 and 104 and a monitoring and calibration system 106. The chips 102 and 104 are connected in series. As shown, the output port OUT of the chip 102 is connected to the input port IN of the chip 104 via a chip-to-chip connection 103. Thus, the chip 102 is arranged to transmit an output signal to the chip 104 via the chip-to-chip connection 103, and the chip 104 is arranged to process an input signal derived from the output signal transmitted via the chip-to-chip connection 103. The monitoring and calibration system 106 is arranged to calibrate a chip setting of at least one of the chips 102 and 104 for achieving a calibration of the pulse width. Figure 1

[0017] The multi-chip system 100 is shown with only two chips connected in series. In practice, the proposed pulse width monitoring and calibration method can be applied to a multi-chip system with more than two chips connected in series. Figure 2 ​is a schematic diagram of another multi-chip system according to an embodiment of the present application. The main difference between multi-chip systems 100 and 200 is that multi-chip system 200 includes more than two chips connected in series, including chips 202, 204, 206, and 208, in addition to chips 102 and 104 described above. Chips 102 and 104 described above are two chips included in the plurality of chips connected in series in the first dimension. Chip 202 is the first chip of the plurality of chips connected in series in the first dimension, and is configured to receive raw data to be processed by the plurality of chips connected in series. Chip 204 is the last chip of the plurality of chips connected in series in the first dimension, and is configured to output data processed by the plurality of chips connected in series. In an alternative design, chip 202 can be omitted, and chip 102 can be the first chip of the plurality of chips connected in series, configured to receive raw data to be processed by the plurality of chips connected in series. In another alternative design, chip 204 can be omitted, and chip 104 can be the last chip of the plurality of chips connected in series, configured to output data processed by the plurality of chips connected in series. Furthermore, chips 102 and 206 are two chips of the plurality of chips connected in series in the second dimension, and chips 104 and 208 are two chips of the plurality of chips connected in series in the second dimension. In practice, the present application does not limit the dimension of the multi-chip system. That is, the proposed pulse width monitoring and calibration method can be applied to a single-dimensional multi-chip system or a multi-dimensional multi-chip system, depending on the practical application requirements. Similar to the embodiment shown in Figure 1 monitoring and calibration system 106 is configured to calibrate the chip settings of at least one of the plurality of chips connected in series for pulse width calibration.

[0018] Figure 3 is a schematic diagram of a pulse width calibration design according to an embodiment of the present application. Figure 1 Figure 2 The monitoring and calibration system 106 shown in

[0019] Please refer to Figure 4 for more details. Figure 3 . Figure 4 ​is a flowchart of a pulse width monitoring and calibration method according to an embodiment of the present application. The pulse width monitoring and calibration method can be implemented by Figure 3 The system shown in FIG. 1 can be employed. It is assumed that the results are substantially the same, so that the steps need not be performed in the exact order shown in FIG. 1. Figure 4 For the sake of brevity, the following assumes that the multi-chip system 200 / 300 is implemented by the system shown in FIG. 2, where the monitoring and calibration system 106 is implemented by the monitoring and calibration system 300, and two of the series-connected multiple chips in the multi-chip system 200 / 300 are implemented by the chips 310 and 320. Figure 3

[0020] At step 402, the program code PROG running on the processor 302 instructs the series-connected chips in the multi-chip system 200 / 300 to enter a calibration mode. For example, Figure 1 / Figure 2 The chip 102 shown in FIG. 1 can be implemented by the chip 310, and Figure 1 / Figure 2 The chip 104 shown in FIG. 1 can be implemented by the chip 320. The series-connected multiple chips in the multi-chip system 200 / 300 can be the same chip. However, this does not mean a limitation on the present application.

[0021] During the calibration mode, each of the series-connected multiple chips in the multi-chip system 100 / 200 can transmit the data signal at its own input port to its own output port through an internal signal processing path. As shown in FIG. 1, the chip 102 includes an input circuit 112, a processing circuit 114, an output circuit 116, an on-chip storage device 118, and a measurement circuit 119; the chip 104 includes an input circuit 122, a processing circuit 124, an output circuit 126, an on-chip storage device 128, and a measurement circuit 129. For example, the on-chip storage devices 118 and 128 can be registers or static random access memories (SRAMs). It should be noted that only the components related to the present application are shown in FIG. 1. In practice, each of the chips 102 and 104 can have other components for specified functions. Figure 3 Figure 3 The chip 310 includes an input circuit 312, a processing circuit 314, an output circuit 316, an on-chip storage device 318, and a measurement circuit 319; the chip 320 includes an input circuit 322, a processing circuit 324, an output circuit 326, an on-chip storage device 328, and a measurement circuit 329. For example, the on-chip storage devices 318 and 328 can be registers or static random access memories (SRAMs). It should be noted that only the components related to the present application are shown in FIG. 2. In practice, each of the chips 310 and 320 can have other components for specified functions.

[0022] ​​As to chip 310, input circuit 312 is arranged to obtain input signal S_IN1 from data signal S1 at input port N11, and output circuit 316 is arranged to generate data signal S2 and send data signal S2 to output port N12. As to chip 320, input circuit 322 is arranged to obtain input signal S_IN2 from data signal S2 at input port N21, and output circuit 326 is arranged to generate data signal S3 and send data signal S3 to output port N22. It should be noted that data signal S2 is transmitted through a chip-to-chip connection between chips 310 and 320. During the calibration mode, processing circuit 314 can transmit input signal S_IN1 (which is the output of input circuit 312) to output circuit 316, and processing circuit 324 can transmit input signal S_IN2 (which is the output of input circuit 322) to output circuit 326.

[0023] At step 404, program code PROG running on processor 302 generates and sends test data D_CAL for pulse width calibration. For example, test data D_CAL can be set to 0xAA so that 1 and 0 are transmitted alternately. Test data D_CAL is fed into the first chip of the series-connected multiple chips of multi-chip system 100 / 200. Thus, during the calibration mode, the input signal and the output signal of the series-connected multiple chips are obtained from the same test data D_CAL. Ideally, the waveforms of the input signal and the output signal of the series-connected multiple chips should be the same as the waveform of test data D_CAL. Unfortunately, the series-connected multiple chips have process variations, and the waveform of the input signal or the output signal of at least one of the series-connected multiple chips can be distorted, thereby being different from the waveform of test data D_CAL.

[0024] In another implementation, test data D_CAL is fed into the first chip of the series-connected multiple chips of multi-chip system 100 / 200, and processing circuit 314 in chip 310 can process input signal S_IN1 so that the pulse width of input signal S_IN1 is changed, at which time, due to the processing function of processing circuit 314 itself, the pulse width of the signal output by output circuit 316 is different from the pulse width of input signal S_IN1, at which time, the ideal waveform of input signal S_IN2 of chip 320 can be the waveform after performing the corresponding processing on test data D_CAL.

[0025] In step 406, the pulse width of the input signal of each of the multiple chips connected in series in the multi-chip system 100 / 200 is estimated and recorded. For example, when the chips 310 and 320 are operating in the calibration mode, the measurement circuit 319 estimates the pulse width of the input signal S_IN1, and the measurement circuit 329 estimates the pulse width of the input signal S_IN2. In this embodiment, the measurement circuit 319 receives the high-frequency clock CLK generated by the clock generation circuit 306 (e.g., a phase-locked loop (PLL) circuit) and uses the clock edge (edge) of the high-frequency clock CLK, such as the rising edge, to sample the input signal S_IN1 for counting the pulse width of the input signal S_IN1. Similarly, the measurement circuit 329 receives the high-frequency clock CLK generated by the clock generation circuit 306 and uses the clock edge (e.g., the rising edge) of the high-frequency clock CLK to sample the input signal S_IN2 for counting the pulse width of the input signal S_IN2.

[0026] Figure 5 is a schematic diagram of pulse width estimation performed by a measurement circuit according to an embodiment of the present invention. A data signal on a chip (for example, the input signal S_IN1 of chip 310 or the input signal S_IN2 of chip 320) is sampled by a high-frequency clock CLK. When the test data D_CAL is set to 0xAA, the high-frequency clock CLK should have M pulses (or M rising edges) in the time it takes to send a data bit "1", and the high-frequency clock CLK should have N pulses (or N rising edges) in the time it takes to send a data bit "0", where M=N. As described above, process variations will cause signal distortion in transmission, resulting in M≠N. As Figure 5 As shown, the high-frequency clock CLK has 14 pulses (or 14 rising edges) during the time it takes to transmit one data bit "1," and has 10 pulses (or 10 rising edges) during the time it takes to transmit one data bit "0." The estimated pulse widths of each chip operating in calibration mode are recorded for use in subsequent pulse width calibration procedures. In this embodiment, measurement circuit 319 records count value CNT1 (representing the pulse width of input signal S_IN1) to on-chip memory device 318 of chip 310, and measurement circuit 329 records count value CNT2 (representing the pulse width of input signal S_IN2) to on-chip memory device 328 of chip 320.

[0027] After the pulse width estimation of the series-connected multiple chips (and in particular the measurement circuits included in the series-connected multiple chips) is completed in the same multiple-chip system 100 / 200, the program code PROG running on the processor 302 reads the recorded pulse width data from the series-connected multiple chips (step 408). At step 410, the program code PROG running on the processor 302 references the recorded pulse width data of the series-connected multiple chips to find any chips that do not meet the distortion requirements. For example, the program code PROG running on the processor 302 checks the count value CNT1 read from the on-chip storage device 318 to determine whether pulse width calibration is needed for the input signal S_IN1 generated by the input circuit 312 to the processing circuit 315, and checks the count value CNT2 read from the on-chip storage device 328 to determine whether pulse width calibration is needed for the input signal S_IN2 generated by the input circuit 322 to the processing circuit 324.

[0028] When a particular chip does not meet the distortion requirement, the program code PROG running on the processor 302 calibrates (modifies) the chip settings of the particular chip and / or the chip settings of another chip before the particular chip based on the recorded pulse width data of the particular chip (step 412). Assume that the chip 320 is found to have a recorded pulse width (i.e., the count value CNT2) that does not meet the distortion requirement because the pulse width of the input signal S_IN2 of the chip 320 is greater than the upper limit of the pulse width range or less than the lower limit of the pulse width range, where the pulse width range is the pulse width range of the chip 320 under ideal conditions, e.g., the upper limit and the lower limit of the pulse width range are 14 pulses and 16 pulses, respectively, and the pulse width of the input signal S_IN2 of the chip 320 is greater than 16 pulses (i.e., the count value CNT2) of the high frequency clock CLK, which does not meet the recorded pulse width range requirement and needs to be calibrated. In one exemplary design, the program code PROG running on the processor 302 calibrates the pulse width of the input signal S_IN2 (which is generated from the input circuit 322 and to the processing circuit 324) by adjusting the output circuit 316 of the chip 310. In another exemplary design, the program code PROG running on the processor 302 calibrates the pulse width of the input signal S_IN2 (which is generated from the input circuit 322 and to the processing circuit 324) by adjusting the input circuit 322 of the chip 320. In another exemplary design, the program code PROG running on the processor 302 calibrates the pulse width of the input signal S_IN2 (which is generated from the input circuit 322 and to the processing circuit 324) by adjusting the output circuit 316 of the chip 310 and the input circuit 322 of the chip 320. The way of adjusting the output circuit 316 of the chip 310 can include controlling the output circuit 316 of the chip 310 to adjust the delay of the rising edge and / or the delay of the falling edge of the signal received by the output circuit 316. The way of adjusting the input circuit 322 of the chip 320 can include controlling the input circuit 322 of the chip 320 to adjust the delay of the rising edge and / or the delay of the falling edge of the signal received by the input circuit 322.

[0029] Briefly summarized, the proposed pulse width calibration technique can be employed by a multi-chip system having two or more chips connected in series, where the pulse width of the input signal of each chip is estimated and recorded by the chip itself, the recorded pulse width data is read from the plurality of chips connected in series to find any chip that does not meet the distortion requirement, and the pulse width calibration is achieved by modifying the chip settings based on the recorded pulse width data.

[0030] The proposed pulse width monitoring and calibration method can eliminate the signal distortion effects during serial transmission. Therefore, the proposed pulse width monitoring and calibration method can maximize the number of serially connected chips implemented on a multi-chip system, thereby improving the computing power. Figure 6 is a schematic diagram of a multi-chip system with many serially connected chips according to an embodiment of the present application. By way of example and not limitation, the multi-chip system 600 can be used for artificial intelligence (AI) applications or any applications that require high computing power. In this embodiment, the multi-chip system 600 has 72 chips serially connected. When step 410 finds that the chips indexed with “48”, “62” and “70” do not meet the distortion requirement, step 412 modifies the chip settings to achieve pulse width calibration of the input signal at the chips indexed with “48”, “62” and “70”. With the help of the proposed signal calibration technique, the multi-chip system 600 is allowed to have a large number of chips to provide the high computing power required by certain applications.

[0031] In the above embodiment, the program code PROG running on the processor 302 is designed to control the signal calibration procedure. However, this is for illustrative purposes only and is not meant to limit the present application. In fact, depending on the actual design considerations, the multi-chip system with pulse width calibration can employ software-based calibration control or hardware-based calibration control. For example, Figure 1 and The monitoring and calibration system 106 shown in Figure 2 may be implemented by hardware only. Therefore, Figure 4 The signal calibration procedure in may be controlled by hardware without software intervention.

[0032] In the above embodiment, the term “pulse width” represents the high pulse width (e.g., the time duration to send one data bit “1”). However, this is for illustrative purposes only and is not meant to limit the present application. In some embodiments of the present application, the term “pulse width” can represent the low pulse width (e.g., the time duration to send one data bit “0”). In short, the pulse width estimation can be achieved by any means capable of capturing the signal change of each chip. These alternative designs all fall within the scope of the present application.

[0033] Those skilled in the art will readily observe that numerous modifications and variations can be made to the devices and methods without departing from the teachings of the present application. Accordingly, the above disclosure is intended to be illustrative only and not limiting.

Claims

1. A multi-chip system, characterized in that: include: a plurality of chips comprising at least a first chip and a second chip, wherein an output port of the first chip is connected to an input port of the second chip via an inter-chip connection, the first chip is arranged to transmit an output signal to the second chip via the inter-chip connection, and the second chip is arranged to process an input signal, the input signal being derived from the output signal transmitted via the inter-chip connection; wherein a pulse width of the input signal is estimated and recorded; and A monitoring and calibration system is arranged to calibrate the chip settings of at least one of the first chip and the second chip according to the recorded pulse width of the input signal when the recorded pulse width of the input signal does not meet the pulse width range requirement, so as to calibrate the pulse width of the input signal.

2. The multi-chip system according to claim 1, wherein: The plurality of chips includes more than two chips connected in series.

3. The multi-chip system according to claim 1, wherein: The monitoring and calibration system is further configured to generate test data for calibrating pulse width and instruct each of the first chip and the second chip to enter a calibration mode; in the calibration mode, the output signal is obtained from the test data, and the second chip estimates and records the pulse width of the input signal; The monitoring and calibration system is also used to read the recorded pulse width of the input signal. When the recorded pulse width of the input signal does not meet the pulse width range requirement, the chip setting of at least one of the first chip and the second chip is calibrated according to the recorded pulse width of the input signal.

4. The multi-chip system according to claim 3, wherein: The first chip has an output circuit arranged to provide the output signal, and calibrating chip settings of at least one of the first chip and the second chip for calibrating the pulse width of the input signal includes adjusting the output circuit of the first chip.

5. The multi-chip system according to claim 3, wherein: The second chip has an input circuit arranged to provide the input signal, and calibrating chip settings of at least one of the first chip and the second chip for calibrating a pulse width of the input signal includes adjusting the input circuit of the second chip.

6. The multi-chip system according to claim 3, wherein: The second chip is also arranged to use a reference clock to sample the pulse width of the input signal to generate a count value representing the pulse width of the input signal and record the count value; the monitoring and calibration circuit is also configured to check the recorded count value to determine whether the pulse width of the input signal needs to be calibrated, wherein the count value is the number of reference clocks in the pulse width of the input signal.

7. The multi-chip system according to claim 3, wherein: The monitoring and calibration system includes a processor that loads and executes program code to generate the test data and instruct the first chip and the second chip to enter the calibration mode.

8. The multi-chip system according to claim 1, wherein: The multiple chips are arranged to process multiple input signals respectively; each chip in the multiple chips is arranged to use a reference clock to sample the pulse width of the corresponding input signal to generate a count value representing the pulse width of the corresponding input signal and record the count value; the monitoring and calibration circuit is also used to check the recorded count values ​​of the multiple chips to select the second chip whose pulse width needs to be calibrated, and the count value is the number of reference clocks in the pulse width of the corresponding input signal.

9. A pulse width monitoring and calibration method for a multi-chip system comprising a plurality of chips, the plurality of chips comprising at least a first chip and a second chip, the pulse width monitoring and calibration method comprising: estimating and recording a pulse width of an input signal, wherein an output port of the first chip is connected to an input port of a second chip via an inter-chip connection, the first chip transmits an output signal to the second chip via the inter-chip connection, and the second chip processes an input signal, the input signal being derived from the output signal transmitted via the inter-chip connection; as well as When the recorded pulse width of the input signal does not meet the pulse width range requirement, a chip setting of at least one of the first chip and the second chip is calibrated according to the recorded pulse width of the input signal to calibrate the pulse width of the input signal.

10. The pulse width monitoring and calibration method according to claim 9, characterized in that: Test data for calibrating the pulse width is generated in a calibration mode; wherein the input signal is derived from the test data.

11. The pulse width monitoring and calibration method according to claim 9, wherein: The plurality of chips includes more than two chips connected in series.

12. The pulse width monitoring and calibration method according to claim 9, wherein: The first chip has an output circuit for providing the output signal, and calibrating chip settings of at least one of the first chip and the second chip includes adjusting the output circuit of the first chip.

13. The pulse width monitoring and calibration method according to claim 9, wherein: The second chip has an input circuit for providing the input signal, and calibrating chip settings of at least one of the first chip and the second chip includes adjusting the input circuit of the second chip.

14. The pulse width monitoring and calibration method according to claim 9, wherein: Estimating and recording the pulse width of the input signal includes: using a reference clock to sample the pulse width of the input signal to generate a count value representing the pulse width of the input signal and recording the count value; The method further includes checking the recorded count value to determine whether the pulse width of the input signal needs to be calibrated.

15. A pulse width monitoring and calibration method for a multi-chip system comprising a plurality of chips, comprising: estimating and recording a pulse width of each of a plurality of input signals, wherein the plurality of chips are arranged to process the plurality of input signals respectively; as well as Check the recorded pulse widths of the multiple input signals. When the recorded pulse widths of the input signals do not meet the pulse width range requirements, calibrate the chip settings of the chip that processes the input signals and / or the chip settings of another chip connected in series before the chip to calibrate the pulse widths of the input signals.

16. The pulse width monitoring and calibration method according to claim 15, characterized in that: The method further comprises: generating test data for calibrating the pulse width in a calibration mode; wherein each of the plurality of input signals is obtained from the test data.

17. The pulse width monitoring and calibration method according to claim 15, wherein: The estimating and recording the pulse width of each input signal of the plurality of input signals comprises: A reference clock is used to sample the pulse width of a corresponding input signal of each of the plurality of chips to generate and record a count value representing the pulse width of the corresponding input signal.

18. The pulse width monitoring and calibration method according to claim 15, wherein: in, The plurality of chips includes more than two chips connected in series.

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