Local silicon oxidation with sidewall spacers for capacitors with different capacitance densities

Abstract

An integrated circuit (IC) (100) comprises a first capacitor (150a), a second capacitor (150b) and a functional circuit (180) configured together with the capacitors for implementing at least one circuit function in a semiconductor surface layer (106) on a substrate (102). The capacitor comprises a top plate (112) on a local oxidation of silicon (LOCOS) oxide (110a, 110b), wherein the thickness of the LOCOS oxide for the second capacitor is thicker than the thickness of the LOCOS oxide for the first capacitor. There are contacts (122a) for the top plate and contacts (122b) for the bottom plate for the first and second capacitors.

Description

Technical Field

[0001] The present description relates to integrated circuits having LOCOS capacitors. Background Art

[0002] Local oxidation of silicon (LOCOS) is a semiconductor manufacturing process that uses a patterned oxygen diffusion barrier layer, typically a silicon nitride layer on areas not intended to be oxidized, in which a thermally grown silicon dioxide layer is formed in etched pores in the oxygen diffusion barrier layer of a given thickness, wherein a thinner tapered silicon oxide region is formed along the edge of the oxygen diffusion barrier layer. The Si-silicon oxide interface is formed at a lower point than the rest of the silicon surface. Some capacitors utilize LOCOS oxide as their dielectric. Although the width of the active area surrounded by the LOCOS oxide can vary, LOCOS, like other oxide growth processes, provides a single given oxide thickness throughout the die and throughout the wafer. Summary of the invention

[0003] This Summary is provided to introduce a brief selection of described concepts in a simplified form that are further described below in the Detailed Description (including the provided Figures). This Summary is not intended to limit the scope of the claimed subject matter.

[0004] The disclosed aspects include an integrated circuit (IC) formed in a semiconductor surface layer on a substrate including a first capacitor and a second capacitor. The first and second capacitors include a top plate on a LOCOS oxide, and the thickness of the LOCOS oxide for the second capacitor is thicker than the thickness of the LOCOS oxide for the first capacitor. For the first and second capacitors, there are contacts for the top plate and contacts for the bottom plate. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and in which:

[0006] Figure 1 is a cross-sectional depiction of an example IC including first and second LOCOS capacitors having different LOCOS oxide thicknesses to provide different capacitance densities, according to an example.

[0007] Figures 2A to 2F is a cross-sectional diagram showing processing progression of an example method of forming an IC including first and second planar LOCOS capacitors having different capacitance densities according to an example.

[0008] Figures 3A to 3G is a cross-sectional diagram showing processing progression of an example method of forming an IC including first and second trench LOCOS capacitors having different capacitance densities according to an example.

[0009] Figures 4A to 4F is a cross-sectional diagram showing processing progression of another example method of forming an IC having first planar LOCOS capacitors and second trench LOCOS capacitors having different capacitance densities according to an example. DETAILED DESCRIPTION

[0010] Examples are described with reference to the accompanying drawings, in which like reference numerals are used to represent similar or equivalent elements. The order of the acts or events described should not be considered limiting, as some acts or events may occur in a different order and / or simultaneously with other acts or events. In addition, some of the acts or events described may not be required to implement the methods described herein.

[0011] Furthermore, the terms "coupled to" or "coupled with..." (and the like) as used herein, without further limitation, are intended to describe either an indirect or direct electrical connection. Thus, if a first device is "coupled" to a second device, the connection may be a direct electrical connection through the presence of only parasitics in the path, or an indirect electrical connection through intermediary items including other devices and connections. For indirect coupling, the intermediary items generally do not modify the information of the signal, but may adjust its current level, voltage level, and / or power level.

[0012] The disclosed aspects recognize that it is desirable to be able to form capacitors of different capacitance density (capacitance / unit area) using a single mask level and a single patterning step. For some power transistors integrated into a bipolar complementary metal oxide semiconductor (BiCMOS) process, this presents a cost and / or complexity issue because multiple capacitors of different capacitance density need to coexist in the same technology, including in some cases on the same IC product. It is also recognized that some LOCOS methods, like other oxidation processes, have the disadvantage of only providing a single oxide thickness. This description describes a LOCOS oxidation process flow that utilizes sidewall spacers to produce two or more different LOCOS oxide thicknesses.

[0013] Forming sidewall spacers in a wider oxygen diffusion barrier (ODB) layer opening on the semiconductor surface layer rather than forming sidewall spacers in a narrower width ODB layer opening on the semiconductor surface enables at least two different LOCOS oxide thicknesses to be produced from a single mask level and patterning step. The thicker LOCOS oxide for a planar LOCOS capacitor will be thicker in the thickest center region of the LOCOS oxide and in the thinner bird's beak region at the edge of the LOCOS oxide than the thinner LOCOS oxide. Sidewall spacers (e.g., comprising silicon nitride) formed in the wider first ODB layer opening rather than in the narrower first ODB layer opening produce two (or more) different LOCOS layer thicknesses, which therefore depend on the width of the first ODB layer opening. The width of the wider first ODB layer opening (referred to herein as the second first ODB layer opening) is typically at least 0.05 μm wider than the width of the narrower first ODB layer opening (referred to herein as the first first ODB layer opening).

[0014] Figure 1 1 is a cross-sectional depiction of an example IC 100 including a first trench capacitor 150a and a second trench capacitor 150b having different LOCOS oxide thicknesses to provide different capacitance densities. As compared to the width and thickness of the LOCOS oxide 110a for the first trench capacitor 150a, it can be seen that the second trench capacitor 150b is significantly wider and has a significantly thicker LOCOS oxide 110b thickness. The trench capacitors 150a, 150b each have a top plate 112. The IC 100 also includes a functional circuit 180 shown as a block, the block including circuit elements (including transistors, and typically including diodes, resistors, capacitors, etc.) formed in or on a semiconductor surface layer 106 of a substrate 102, the substrate 102 being configured together with the trench capacitors 150a and 150b for implementing at least one circuit function, such as an analog (e.g., an amplifier, a power converter, or a power field effect transistor (FET)), RF, digital, or memory function.

[0015] Although field oxide is not shown, IC 100 typically includes a field oxide, which may include a shallow trench isolation (STI) structure or the field oxide may also have a LOCOS oxide structure. A pre-metal dielectric (PMD) layer is shown as 159, with a pad oxide layer 158 therebelow. Topside contacts are shown as being formed through PMD layer 159 and pad oxide layer 158, including contact 122a to top plate 112 and contact 122b to a portion of semiconductor surface layer 106, which provides a bottom plate having metal contacts 123a and 123b thereon (shown as metal 1 (M1) contacts). The topside contacts shown also include contact 122c to functional circuit 180 having M1 contact 123c thereon. Although trench capacitor 150a is shown as having two trenches, and trench capacitor 150b as having one trench, trench capacitors may typically have any number of trenches.

[0016] Figure 2A 2G is a cross-sectional diagram showing a process progression of an example method of forming an IC including a first planar capacitor 180a and a second planar capacitor 180b having different LOCOS oxide thicknesses to provide different capacitance densities. Figure 2A , shows the process IC after forming a relatively narrow first ODB layer opening 164a and a relatively wide second first ODB layer opening 164b in the first ODB layer 160 on the pad oxide layer 158 layer on the semiconductor surface layer 106 of the substrate 102. The ODB layer openings 164a, 164b are typically formed by using a photoresist pattern as an etching mask and then etching a hole including a first width and at least a second width in the first ODB layer 160.

[0017] The substrate 102 may be formed by starting with a p-type silicon wafer, which may have at least one epitaxial layer thereon, and by 15 cm -2 to 1×10 16 cm -2 The n-type buried layer is formed by implanting an n-type dopant (e.g., antimony or arsenic) at a dosage of 100 μm. The thermally driven process heats the wafer to activate and diffuse the implanted n-type dopant. By using an epitaxial process of in-situ p-type doping, a p-type layer for the semiconductor surface layer 106 can be formed on the wafer. The epitaxially formed material can be, for example, 4 microns to 6 microns thick. Although not shown, there can be an n-type buried layer overlapping the boundary between the original silicon wafer and the epitaxially grown material for the semiconductor surface layer 106. The average bulk resistivity of the p-type layer can be, for example, 1 ohm-cm to 10 ohm-cm. In the case of the p-type semiconductor surface layer 106, an optional p-type buried layer can also be formed by implanting boron at an energy of, for example, 2 megaelectronvolts (MeV) to 3MeV.

[0018] The pad oxide layer 158 may be, for example, 20 to 250 Å thick, 100 Å thick, and may be formed by thermal oxidation or by any of several chemical vapor deposition (CVD) processes. The first ODB layer 160 may include, for example, silicon nitride, such as formed by a low pressure chemical vapor deposition (LPCVD) process using dichlorosilane and ammonia. Alternatively, the silicon nitride for the first ODB layer 160 may be formed by the decomposition of bis(tert-butylamino)silane (BTBAS). Other processes for forming the first ODB layer 160 are possible.

[0019] The etching mask may include a photoresist formed by a photolithography process, and may also include a hard mask material, such as amorphous carbon, and may include an anti-reflective layer such as an organic bottom anti-reflective coating (BARC). The exposed area of ​​the top surface of the semiconductor surface layer 106 is defined by a second first ODB layer opening 164b for the second planar capacitor 180b, and the second first ODB layer opening 164b has a size wider than the width of the first first ODB layer opening 164a for the first planar capacitor 180a. The second first ODB layer opening 164b is wide enough so that the second first ODB layer opening 164b is not as wide as the first first ODB layer opening 164a for the first planar capacitor 180a. Figure 2C After etching the second ODB layer 181 as described, the central portion of the etched area becomes clear, resulting in the formation of sidewall spacers, while the first first ODB layer opening 164a for the first planar capacitor 180a has a sufficiently narrow width so that after etching the second ODB layer 181, the entire first first ODB layer opening 164a remains covered by the second ODB layer 181. The first ODB layer 160 in the area exposed by the etching mask can be removed by wet etching (e.g., aqueous phosphoric acid) that undercuts the etching mask. A portion of the pad oxide 158 can also be removed in the area exposed by the etching mask.

[0020] Reference now Figure 2B , this figure shows the result after growing the first LOCOS oxide layer 210, with an example thickness between 200 and 1,000 Å. The characteristic LOCOS oxide bird's beak with thinner LOCOS oxide at the edge below the first ODB layer 160 is shown.

[0021] An example furnace thermal oxidation process for growing the first LOCOS oxide layer 210 may include using an environment with 2% to 10% oxygen, increasing the furnace temperature to approximately 1000° C. over a period of 45 minutes to 90 minutes, maintaining the furnace temperature at approximately 1000° C. for a period of 10 minutes to 20 minutes while increasing the oxygen in the environment to 80% to 95% oxygen, maintaining the furnace temperature at approximately 1000° C. for a period of 60 minutes to 120 minutes while maintaining the oxygen in the environment at 80% to 95% oxygen, and adding hydrogen chloride gas to the environment, maintaining the furnace temperature at approximately 1000° C. for a period of 30 minutes to 90 minutes while maintaining the oxygen in the environment at 80% to 95% oxygen in the absence of hydrogen chloride, and reducing the furnace temperature in a nitrogen environment.

[0022] Figure 2C The result is shown after depositing the second ODB layer 181 and then depositing a sacrificial sidewall film 182 serving as a sacrificial sidewall layer on the second ODB layer 181, and then performing maskless etching on the sacrificial sidewall film 182 to form a spacer 182a in the second first ODB layer opening 164b because it is wide enough. The second ODB layer 181 is removed in the second first ODB layer opening 164b because it is not protected by the sacrificial sidewall film 182. The sidewall spacer is not shown in the first first ODB layer opening 164a because it is narrower than the second first ODB layer opening 164b, so that the first first ODB layer opening 164a is shown again as the sacrificial sidewall film 182 on the second ODB layer 181 in the first first ODB layer opening 164a.

[0023] Figure 2D The result is shown after stripping off the sacrificial sidewall film 182 and the spacer 182a, which reveals the spacer 181a in the second first ODB layer opening 164b. Figure 2E The result is shown after growing a second LOCOS oxide layer, thereby producing an additional LOCOS portion, which is shown as LOCOS 2 having portions above and below the first LOCOS oxide layer 210, which is typically 500 to 1,500A of LOCOS 2 at the center of the wider second first ODB layer opening 164b of the second planar capacitor 180b. Due to the presence of the second ODB layer 181 over the entire opening, the growth of LOCOS 2 in the first first ODB layer opening 164a, which is a narrower opening, is not shown.

[0024] Thus, for the narrower first first ODB layer opening 164a, the sidewalls of the second ODB layer 181 remain merged so that only the first LOCOS oxidation process can oxidize the exposed silicon surface. This thinner LOCOS oxide is used to form all of the oxide for the first planar capacitor 180a. For the wider second first ODB layer opening 164b, the sidewalls are different (as shown in FIG. Figure 2D The spacer 181a in the second LOCOS layer 164b allows the second LOCOS oxide to thicken the LOCOS layer by adding LOCOS 2 in the second first ODB layer opening 164b. Like the first LOCOS oxide layer 210, the LOCOS 2 oxide will taper below the spacer 181a, which corresponds to the bird's beak area.

[0025] This completes the oxide thickness so that the LOCOS oxide for the second planar capacitor 180b is thicker because it includes LOCOS oxide from both the first LOCOS oxide layer 210 and the LOCOS 2 oxide compared to the LOCOS oxide of the first planar capacitor 180a which includes only the first LOCOS oxide layer 210. Figure 2F The result is shown after removing the first ODB layer 160 and the second ODB layer 181, and then depositing a top plate layer and patterning this top plate layer to form a top plate 112 (e.g., a top plate comprising polysilicon on LOCOS oxide for the first and second planar capacitors 180a, 180b). Spacers 191 are shown on the sidewalls of the top plate 112.

[0026] Figures 3A to 3G is a cross-sectional diagram showing a processing progression of an example method of forming an IC including a first trench capacitor 350a and a second trench capacitor 350b having different LOCOS oxide thicknesses to provide different capacitance densities. Figure 3A The result is shown after forming a first first ODB layer opening 164a (shown as relatively narrow) and a second first ODB layer opening 164b (shown as relatively wide) in the first ODB layer 160 on the pad oxide layer 158 layer on the semiconductor surface layer 106 on the substrate 102. The ODB layer openings are typically formed by patterning an etch mask using a photoresist, and then etching the first ODB layer 160 to form a first first ODB layer opening 164a for the trench capacitor 350a and a second first ODB layer opening 164b for the trench capacitor 350b. Figure 3B The results are shown after silicon etching the top surface of the semiconductor surface layer 106 after the oxide etch used to remove the pad oxide 158 in the first and second first ODB layer openings 164a, 164b. Example silicon etch depths are 100A to 6000A.

[0027] Figure 3C Results are shown after growing a first LOCOS oxide layer 210, with example thicknesses between 200 A and 1,000 A. The characteristic LOCOS oxide bird's beak is shown. Figure 3D The result is shown after depositing the second ODB layer 181, then depositing a sacrificial sidewall film 182 serving as a sacrificial sidewall layer on the second ODB layer 181, then masklessly etching the sacrificial sidewall film 182 to form a spacer 182a in the relatively wider second first ODB layer opening 164b, but not forming a sidewall spacer shown as the sacrificial sidewall film 182 on the relatively narrow entire first first ODB layer opening 164a, and then removing the second ODB layer 181 not protected by the sacrificial sidewall film 182. Figure 3E The result after removing the sacrificial sidewall film 182 including the spacers 182a is shown.

[0028] Figure 3F The result is shown after growing a second LOCOS oxide layer in the second first ODB layer opening 164b for the trench capacitor 350b, resulting in additional LOCOS portions, shown as LOCOS 2 above and below the first LOCOS oxide layer 210, which is typically 500 to 1,500 Å of LOCOS at the center of the wider second first ODB layer opening 164b. The growth of LOCOS 2 in the narrower first ODB layer opening 164a is not shown due to the presence of the second ODB layer 181 over the entire opening.

[0029] Thus, for the narrower first first ODB layer opening 164a, the sidewalls of the second ODB layer 181 remain merged and only the first LOCOS oxidation process is able to oxidize the exposed silicon. This thinner oxide is used to form the LOCOS oxide for the trench capacitor 350a. For the wider second first ODB layer opening 164b, the sidewalls are different (eg, Figure 3D 182a in the trench capacitor 350b), so that the second LOCOS oxide adds LOCOS 2, which makes the LOCOS layer thicker in the middle of the second first ODB layer opening 164b for the trench capacitor 350b. The LOCOS oxide will taper under the spacer 182a, which is equivalent to the bird's beak area controlled by the spacer thickness. This thicker LOCOS oxide is used to form the trench capacitor 350b.

[0030] This completes the oxide thickness so that the LOCOS oxide for trench capacitor 350b is thicker than the LOCOS oxide for trench capacitor 350a. Figure 3GThe result is shown after removing the first ODB layer 160 and the second ODB layer 181, and then forming a patterned top plate 112, which may include polysilicon on LOCOS oxide for trench capacitors 350a and 350b.

[0031] Figures 4A to 4F is a cross-sectional diagram showing processing progression of another example method of forming an IC including a first planar capacitor shown as 450a and a second trench capacitor shown as 450b having different LOCOS thicknesses according to one example. Figure 4A The result is shown after forming a relatively narrow first first ODB layer opening 164a for a first trench capacitor and a relatively wide second first ODB layer opening 164b for a second trench capacitor 164b in the first ODB layer 160 on the pad oxide layer 158 layer on the substrate 102 having the semiconductor surface layer 106. This process typically includes patterning an etch mask using a photoresist, and then etching the first ODB layer 160 to form the first and second first ODB layer openings 164a, 164b.

[0032] Figure 4B Results are shown after growing a first LOCOS oxide layer 210, with example thicknesses between 200 and 1,000 A. The characteristic LOCOS oxide bird's beak is shown. Figure 4C The result is shown after depositing the second ODB layer 181, then depositing a sacrificial sidewall film 182 serving as a sacrificial sidewall layer on the second ODB layer 181, and then maskless etching of the sacrificial sidewall film 182 and the second ODB layer 181. In the second first ODB layer opening 164b associated with the second trench capacitor 450b, because it is relatively wide, etching of the sacrificial sidewall film 182 forms spacers 182a as shown, which enables maskless etching to etch away the second ODB layer 181 from the edge in the second first ODB layer opening 164b to form spacers 181a because the second ODB layer 181 is not protected there by the sacrificial sidewall film 182. The sidewall spacers are not shown in the first first ODB layer opening 164a associated with the first trench capacitor 450a because it is narrow, so after maskless etching, the sacrificial sidewall film 182 is present on the second ODB layer 181 over the entire area of ​​the first first ODB layer opening 164a.

[0033] Figure 4DThe result is shown after stripping off the sacrificial sidewall film 182 in the first first ODB layer opening 164a for the first trench capacitor 450a and the spacer 182a in the second first ODB layer opening 164b for the second trench capacitor 450b, and then performing silicon etching in the exposed semiconductor surface layer 106 in the second first ODB layer opening 164b, wherein the second ODB layer 181 extends over the entire first first ODB layer opening 164a for the first trench capacitor 450a to prevent any etching of the semiconductor surface layer 106. The silicon etching depth for the second trench capacitor 450b may be 100A to 30μm, with an example silicon etching depth being between 500A to 2μm.

[0034] Figure 4E The result is shown after growing a second LOCOS oxide layer to produce a LOCOS portion, which is shown as LOCOS 2 above and below the first LOCOS oxide layer 210, which is typically 500 to 1,500A of LOCOS oxide at the center of the wider second first ODB layer opening 164b for the second trench capacitor 450b, where LOCOS 2 is not shown grown in the narrower first first ODB layer opening 164a for the first trench capacitor 450a due to the presence of the second ODB layer 181 over the entire opening.

[0035] Thus, for the narrower first first ODB layer opening 164a for the first trench capacitor 450a, the sidewalls of the second ODB layer 181 remain merged, and only the first LOCOS oxidation process is able to oxidize the exposed silicon. This thinner oxide is used to form the oxide for the first trench capacitor 450a. For the wider second first ODB layer opening 164b for the second trench capacitor 450b, the sidewalls are different, so the second LOCOS oxide can grow in the middle of the second first ODB layer opening 164b. The oxide will taper below the spacer 182a, which is equivalent to the bird's beak area controlled by the spacer thickness. This thicker oxide is used to form the trench capacitor 450b. Figure 4E The result after removing the sacrificial sidewall film 182 including the spacers 182a is shown. Figure 4F The results are shown after removing the first and second ODB layers 160, 181 and the spacers 181a, and then forming a patterned top plate 112 that may include polysilicon on LOCOS oxide for the trench capacitors 450a, 450b.

[0036] The following describes the front end of line (FEOL) MOS processing used to complete the formation of the capacitor (including the formation of the top plate and contacts). Figure 1The top plate 112 may include, for example, polycrystalline silicon (hereinafter referred to as polysilicon), which may be doped with n-type dopants. The polysilicon as a layer of the top plate 112 may be, for example, 300 nanometers to 800 nanometers thick.

[0037] The disclosed aspects can be used to form semiconductor dies that can be integrated into various assembly processes to form a variety of different devices and related products. The semiconductor die can include various components and / or layers thereon, including barrier layers, dielectric layers, device structures, active components and passive components, including source regions, drain regions, bit lines, bases, emitters, collectors, conductive lines, conductive vias, etc. In addition, the semiconductor die can be formed by a variety of processes, including bipolar, insulated gate bipolar transistors (IGBT), CMOS, BiCMOS, and MEMS.

[0038] Those skilled in the art to which this description relates will appreciate that many other aspects are possible within the scope of the claimed invention, and that further additions, deletions, substitutions and modifications may be made to the aspects described without departing from the scope of this description.

Claims

1. A method for manufacturing an integrated circuit IC, comprising: depositing a first ODB layer on the pad oxide layer on the semiconductor surface layer; forming a first opening and a second opening in the first ODB layer, wherein a width of the second opening is greater than a width of the first opening; growing a first LOCOS oxide layer in each of the first opening and the second opening to form a LOCOS oxide layer for a first capacitor; depositing a second ODB layer on the first LOCOS oxide layer; depositing a sacrificial sidewall film on the second ODB layer, wherein the first opening is completely filled with the deposited sacrificial sidewall film; etching the sacrificial sidewall film to form a spacer in the second opening, wherein the first opening remains filled with the sacrificial sidewall film; removing the second ODB layer in the second opening that is not covered by the sacrificial sidewall film; peeling off the sacrificial sidewall film; growing a second LOCOS oxide layer in the second opening instead of the first opening to form a LOCOS oxide layer for a second capacitor, wherein a thickness of the LOCOS oxide layer for the second capacitor is thicker than a thickness of the LOCOS oxide layer for the first capacitor; removing the first ODB layer and the second ODB layer; and A first top plate is formed over the first opening for the first capacitor and over the second opening for the second capacitor. 2 . The method of claim 1 , wherein both the first capacitor and the second capacitor comprise planar capacitors.

3. The method of claim 1 , further comprising etching the semiconductor surface layer to a predetermined depth in the first opening and in the second opening after forming a first opening and a second opening in the first ODB layer and before the growing the first LOCOS oxide layer, wherein both the first capacitor and the second capacitor comprise trench capacitors.

4. The method of claim 1 , further comprising etching the semiconductor surface layer in the second opening to a predetermined depth after the stripping of the sacrificial sidewall film and before the growing of the second LOCOS oxide layer, wherein the first capacitor is a planar capacitor and the second capacitor is a trench capacitor.

5. The method according to claim 1, wherein the thickness of the first LOCOS oxide layer is 200 to The method of claim 1 , wherein both the first ODB layer and the second ODB layer comprise silicon nitride. 7 . The method of claim 1 , wherein the width of the second opening is at least 0.05 μm greater than the width of the first opening. The method of claim 1 , wherein the first ODB layer comprises silicon nitride.

9. The method of claim 1, wherein the first top plate comprises polysilicon.

10. An integrated circuit IC, comprising: A first capacitor, a second capacitor and a functional circuit; The first capacitor and the second capacitor include: a LOCOS oxide layer disposed between a top plate and a bottom plate, wherein a thickness of the LOCOS oxide layer for the second capacitor is thicker than a thickness of the LOCOS oxide layer for the first capacitor, and the second capacitor is wider than the first capacitor, and Contacts for the top plate and contacts for the bottom plate for the first and second capacitors.

11. The IC of claim 10, wherein both the first capacitor and the second capacitor comprise planar capacitors.

12. The IC of claim 10, wherein both the first capacitor and the second capacitor comprise trench capacitors.

13. The IC of claim 10, wherein a semiconductor surface layer is recessed for the second capacitor compared to the first capacitor.

14. The IC of claim 10, wherein a width of the opening of the LOCOS oxide layer for the second capacitor is at least 0.05 μm greater than a width of the opening of the LOCOS oxide layer for the first capacitor.

15. The IC of claim 10, wherein the top plate comprises polysilicon.

16. The IC of claim 13, wherein the semiconductor surface layer comprises an epitaxial layer.

17. The IC of claim 10, wherein the contacts for the top plate and the bottom plate for the first and second capacitors are both top side contacts.

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