Memory, memory pad structure and preparation method thereof

Abstract

The present disclosure provides a memory, a pad structure of the memory, and a method for preparing the pad structure of the memory. The pad structure of the memory includes an insulating support layer, a conductive layer, and a metal layer. The insulating support layer includes a first region and an annular groove surrounding the first region. The first region includes a plurality of first grooves and a plurality of second grooves. The plurality of first grooves are all connected to the annular groove. Any second groove is not connected to the annular groove and any first groove. The conductive layer is filled in the annular groove and each first groove. The metal layer is filled in each second groove. The present disclosure can improve the life of the memory.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technology, and in particular to a memory, a pad structure of the memory, and a method for preparing the pad structure of the memory. Background Art

[0002] With the rapid development of integrated circuit technology, memory has attracted more and more attention.

[0003] In the process of preparing the memory, it is necessary to prepare a transistor on a substrate first. The transistor includes a channel region, a gate oxide layer covering the channel region, and a gate covering the gate oxide layer. After the transistor is prepared, a pad structure and a capacitor structure need to be prepared to form a memory. However, the gate oxide layer of the transistor is easily damaged by plasma during the preparation of the memory, thereby reducing the life of the prepared memory.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The purpose of the present disclosure is to provide a memory, a pad structure of the memory and a method for preparing the pad structure of the memory, which can reduce plasma damage to a gate oxide layer and increase the life of the memory.

[0006] According to one aspect of the present disclosure, there is provided a pad structure of a memory, comprising:

[0007] An insulating support layer, comprising a first region and an annular groove surrounding the first region, wherein the first region comprises a plurality of first grooves and a plurality of second grooves, wherein the plurality of first grooves are all connected to the annular groove, and any of the second grooves is not connected to the annular groove and any of the first grooves;

[0008] A conductive layer filled in the annular groove and each of the first grooves;

[0009] A metal layer is filled in each of the second grooves.

[0010] In an exemplary embodiment of the present disclosure, a plurality of the first grooves are all straight lines, and both ends of each of the first grooves are connected to the annular groove.

[0011] In an exemplary embodiment of the present disclosure, part of the first grooves extend along a first direction, and the rest of the first grooves extend along a second direction, and the first direction is perpendicular to the second direction.

[0012] In an exemplary embodiment of the present disclosure, part of the second grooves extend along the first direction, and the rest of the second grooves extend along the second direction.

[0013] In an exemplary embodiment of the present disclosure, the conductive layer and the metal layer are made of the same material.

[0014] In an exemplary embodiment of the present disclosure, the conductive layer and the metal layer are both made of copper.

[0015] According to one aspect of the present disclosure, a method for preparing a pad structure of a memory is provided, comprising:

[0016] forming an insulating support layer;

[0017] forming an annular groove on the insulating support layer;

[0018] A plurality of first grooves and a plurality of second grooves are formed in the first region of the insulating support layer, the annular groove surrounds the first region, a plurality of the first grooves are all connected to the annular groove, and any of the second grooves is not connected to the annular groove and any of the first grooves;

[0019] Filling a conductive layer in the annular groove and each of the first grooves;

[0020] A metal layer is filled in each of the second trenches.

[0021] In an exemplary embodiment of the present disclosure, a plurality of the first grooves are all straight lines, and both ends of each of the first grooves are connected to the annular groove.

[0022] In an exemplary embodiment of the present disclosure, part of the first grooves extend along a first direction, and the rest of the first grooves extend along a second direction, and the first direction is perpendicular to the second direction.

[0023] In an exemplary embodiment of the present disclosure, part of the second grooves extend along the first direction, and the rest of the second grooves extend along the second direction.

[0024] In an exemplary embodiment of the present disclosure, the conductive layer and the metal layer are made of the same material.

[0025] In an exemplary embodiment of the present disclosure, the conductive layer and the metal layer are both made of copper, tungsten or aluminum.

[0026] According to one aspect of the present disclosure, a memory is provided, comprising the pad structure of the memory as described in any one of the above.

[0027] The memory, the pad structure of the memory and the method for preparing the pad structure of the memory disclosed in the present invention have the following advantages: since the second groove is located in the first area and is not connected to the annular groove and any first groove, the metal layer filled in the second groove is not electrically connected to the conductive layer, thereby reducing the area of ​​the conductor in the pad structure, reducing the antenna ratio, and reducing the plasma damage to the gate oxide layer, thereby improving the life of the memory; at the same time, the metal layer arranged in the second groove can improve the mechanical strength of the pad structure, thereby also improving the life of the memory.

[0028] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other features and advantages of the present disclosure will become more apparent by describing in detail its exemplary embodiments with reference to the accompanying drawings. Obviously, the drawings described below are only some embodiments of the present disclosure, and for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative work.

[0030] Figure 1 A schematic diagram of a pad structure of a memory device not including a conductive layer and a metal layer in an embodiment of the present disclosure;

[0031] Figure 2 is a schematic diagram of a pad structure of a memory including a conductive layer and a metal layer in an embodiment of the present disclosure;

[0032] Figure 3 The present invention is a flow chart of a method for preparing a pad structure of a memory device according to an embodiment of the present invention.

[0033] In the figure: 1. Insulating support layer; 2. Annular groove; 3. First groove; 4. Second groove; 5. Conductive layer; 6. Metal layer; 7. Longitudinal connecting channel. DETAILED DESCRIPTION

[0034] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the disclosure will be comprehensive and complete, and the concept of the example embodiments will be fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, materials, devices, etc. may be employed. In other cases, known technical solutions are not shown or described in detail to avoid blurring various aspects of the present disclosure. The same reference numerals in the figures represent the same or similar structures, and thus their detailed descriptions will be omitted.

[0035] In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings represent the same or similar parts, and thus their repeated description will be omitted. The terms "a", "an" and "the" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to indicate an open-ended inclusive meaning and mean that in addition to the listed elements / components / etc., additional elements / components / etc. may exist.

[0036] In the manufacturing process of memory, plasma is used in many process steps such as dry etching, ion implantation and chemical vapor deposition. In theory, the plasma is electrically neutral to the outside, that is, the number of positive ions and negative ions is equal, but in fact, the positive ions and negative ions entering the local area of ​​the wafer are not equal, which leads to the generation of a large number of free charges, making the metal wires or conductors such as polysilicon exposed to the plasma environment act like antennas to collect these free charges. The longer the length of these antennas and the larger the area, the more charges they collect. When the charges collected by these antennas reach a certain level, a discharge phenomenon will occur. The above discharge phenomenon is what is commonly known as the Plasma Induced Damage (PID) effect, also known as the antenna effect.

[0037] As the size of memory continues to decrease, the thickness of the gate oxide layer of the metal oxide semiconductor transistor in the memory also continues to decrease. The current generated by the discharge of the charge collected by the antenna structure can easily pass through the gate oxide layer, thereby increasing the leakage current of the metal oxide semiconductor transistor. In severe cases, it may even cause the metal oxide semiconductor transistor to be scrapped. Therefore, measures need to be taken to solve the antenna effect.

[0038] The present disclosure provides a pad structure of a memory. Figure 1 and Figure 2 As shown, the pad structure of the memory may include an insulating support layer 1, a conductive layer 5 and a metal layer 6, wherein:

[0039] The insulating support layer 1 includes a first region and an annular groove 2 surrounding the first region. The first region includes a plurality of first grooves 3 and a plurality of second grooves 4. The plurality of first grooves 3 are all connected to the annular groove 2. Any second groove 4 is not connected to the annular groove 2 and any first groove 3. The conductive layer 5 is filled in the annular groove 2 and each first groove 3. The metal layer 6 is filled in each second groove 4.

[0040] In the pad structure of the memory of the embodiment disclosed in the present invention, since the second groove 4 is located in the first area and is not connected to the annular groove 2 and any first groove 3, the metal layer 6 filled in the second groove 4 is not electrically connected to the conductive layer 5, thereby reducing the area of ​​the conductor in the pad structure, reducing the antenna ratio, and reducing the plasma damage to the gate oxide layer, thereby improving the life of the memory; at the same time, the metal layer 6 arranged in the second groove 4 can improve the mechanical strength of the pad structure, thereby also improving the life of the memory.

[0041] The following is a detailed description of each part of the pad structure of the memory according to the embodiment of the present disclosure:

[0042] like Figure 1 As shown, the material of the insulating support layer 1 can be an insulating material such as silicon oxide, but the embodiments of the present disclosure are not limited thereto. The insulating support layer 1 can be provided on a substrate structure of a memory. A transistor can be provided on the substrate structure. The transistor can be a metal oxide semiconductor transistor.

[0043] like Figure 1 As shown, the insulating support layer 1 may include an annular groove 2. The annular groove 2 may be in the form of a circular ring, or of course, a rectangular ring, but the embodiments of the present disclosure do not specifically limit this. For example, the annular groove 2 is in the form of a rectangular ring. The length and width of the rectangular ring may also be the same, or of course, they may be different. Taking the rectangular ring having the same length and width as an example, the length and width of the rectangular ring are both 60μm. The width of the annular groove 2 may be 0.5-3μm, such as 0.5μm, 0.7μm, 0.9μm, 1.3μm, 2.5μm, 3μm, etc. The insulating support layer 1 may include a first region. The annular groove 2 surrounds the first region, that is, the region surrounded by the annular groove 2 on the insulating support layer 1 is the first region, that is, the boundary of the first region is the inner wall of the annular groove 2.

[0044] like Figure 1As shown, the first region may include a first groove 3. The number of the first grooves 3 may be one, two, four, or ten, but is not limited thereto, and may also be more. Taking the case where the number of the first grooves 3 is multiple as an example, the multiple first grooves 3 are all connected to the annular groove 2. The first groove 3 may be linear, and of course, may also be curved, but the embodiments of the present disclosure are not limited thereto. Taking the case where the first groove 3 is linear as an example, both ends of the first groove 3 are connected to the annular groove 2. Some of the multiple first grooves 3 may extend along the first direction, and the remaining first grooves 3 may extend along the second direction. The first direction may be the X direction. The second direction may be the Y direction. The first direction and the second direction are perpendicular. Further, the number of the first grooves 3 extending along the first direction may be the same as the number of the first grooves 3 extending along the second direction, and of course, may also be different. For example, the number of the first grooves 3 extending along the first direction may be greater than the number of the first grooves 3 extending along the second direction. A plurality of first grooves 3 extending along the first direction may be distributed along the second direction, and the distance between any two adjacent first grooves 3 is the same. A plurality of first grooves 3 extending along the second direction may be distributed along the first direction, and the distance between any two adjacent first grooves 3 is the same. Taking the annular groove 2 as a rectangular ring as an example, the first direction may be the length direction of the rectangular ring, and the second direction may be the width direction of the rectangular ring. The width of the first groove 3 may be 0.5-3μm, for example, 0.5μm, 0.7μm, 0.9μm, 1.3μm, 2.5μm, 3μm, etc. The width of the first groove 3 may be equal to the width of the annular groove 2, and of course, may also be different.

[0045] like Figure 1 As shown, the first region may include a second groove 4. The second groove 4 may be formed in a portion of the first region outside the first groove 3. The number of the second grooves 4 may be one, nine, or twenty-seven, but is not limited thereto, and may be more. Taking the case where the number of the first groove 3 and the second groove 4 are both multiple as an example, any second groove 4 is not connected to the annular groove 2, and any second groove 4 is not connected to any first groove 3. The second groove 4 may be linear, or, of course, curved, but the embodiments of the present disclosure are not limited thereto. Some of the second grooves 4 in the multiple second grooves 4 may extend along the first direction, and the remaining second grooves 4 may extend along the second direction. The width of the second groove 4 may be 0.5-3μm, for example, 0.5μm, 0.7μm, 0.9μm, 1.3μm, 2.5μm, 3μm, etc. Among them, the width of the second groove 4 may be the same as the width of the first groove 3, or, of course, may be different.

[0046] like Figure 1As shown, the plurality of second grooves 4 can be divided into a plurality of groove groups, and each groove group includes a plurality of second grooves 4. Some of the second grooves 4 in each groove group can extend along the first direction, and the remaining second grooves 4 can extend along the second direction. Further, the number of second grooves 4 extending along the first direction in each groove group can be the same as the number of second grooves 4 extending along the second direction, and of course, can also be different. For example, the number of second grooves 4 extending along the first direction can be greater than the number of second grooves 4 extending along the second direction. The plurality of second grooves 4 extending along the first direction in each groove group can be distributed along the second direction, and the distance between any two adjacent second grooves 4 is the same. The plurality of second grooves 4 extending along the second direction in each groove group can be distributed along the first direction, and the distance between any two adjacent second grooves 4 is the same. In addition, any first groove 3 in each groove group and the remaining second grooves 4 are not connected, but the embodiments of the present disclosure do not specifically limit this. Taking the example that the number of first grooves 3 extending along the first direction and the number of first grooves 3 extending along the second direction are both two, the first area is divided into nine spaced groove areas by the first grooves 3; the multiple second grooves 4 can be divided into nine groove groups, and the nine groove groups are located in the nine groove areas one by one.

[0047] like Figure 1 and Figure 2 As shown, the conductive layer 5 is filled in the annular groove 2 and each first groove 3 to form a conductor of the pad structure. The material of the conductive layer 5 can be copper, of course, it can also be aluminum, but not limited to this, it can also be tungsten, etc. In addition, a plurality of longitudinal connection channels (vias) 7 can be formed in the conductive layer 5. The longitudinal connection channel 7 can be filled with conductive materials, such as tungsten embolism structures, etc. The tungsten embolism structure can be connected to the gate of the transistor in the substrate structure.

[0048] like Figure 1 and Figure 2 As shown, the metal layer 6 is filled in the second groove 4 to enhance the mechanical strength of the pad structure, for example, the mechanical strength of the pad structure during bonding can be enhanced. The metal layer 6 can be made of the same material as the conductive layer 5. The material of the metal layer 6 can be copper, of course, can also be aluminum, but is not limited thereto, and can also be tungsten, etc.

[0049] The present disclosure also provides a method for preparing a pad structure of a memory device, which is used to prepare the pad structure of the memory device described in any of the above embodiments. Figure 3 As shown, the method for preparing the liner structure may include steps S100 to S140, wherein:

[0050] Step S100: forming an insulating support layer.

[0051] Step S110: forming an annular groove on the insulating support layer.

[0052] Step S120, forming a plurality of first grooves and a plurality of second grooves in the first region of the insulating support layer, wherein the annular groove surrounds the first region, the plurality of first grooves are all connected to the annular groove, and any second groove is not connected to the annular groove or any first groove.

[0053] Step S130 , filling a conductive layer in the annular groove and each first groove.

[0054] Step S140 , filling a metal layer in each second trench.

[0055] In the method for preparing the pad structure of the memory device of the embodiment disclosed in the present invention, since the second groove is formed in the first area and is not connected to the annular groove and any first groove, the metal layer filled in the second groove is not electrically connected to the conductive layer, thereby reducing the area of ​​the conductor in the pad structure, reducing the antenna ratio, and reducing the plasma damage to the gate oxide layer, thereby improving the life of the memory device; at the same time, the metal layer filled in the second groove can improve the mechanical strength of the pad structure, thereby also improving the life of the memory device.

[0056] The following is a detailed description of each step of the method for preparing the pad structure of the memory according to the embodiment of the present disclosure:

[0057] In step S100 , an insulating support layer is formed.

[0058] like Figure 1 As shown, the insulating support layer 1 can be formed on a substrate structure. A transistor can be provided on the substrate structure. The insulating support layer 1 can be prepared by vapor deposition, and of course, can also be prepared by atomic layer deposition, but is not limited thereto, and can also be prepared by other methods. The material of the insulating support layer 1 can be an insulating material such as silicon oxide, silicon nitride, etc., but the embodiments of the present disclosure are not limited thereto.

[0059] In step S110 , a ring-shaped groove is formed on the insulating support layer.

[0060] like Figure 1 As shown, the annular groove 2 is prepared by a patterning process. The annular groove 2 can be a circular ring, or a rectangular ring, but the embodiments of the present disclosure do not specifically limit this. For example, the annular groove 2 is a rectangular ring. The length and width of the rectangular ring can also be the same, or different. Taking the rectangular ring having the same length and width as an example, the length and width of the rectangular ring are both 60μm. The width of the annular groove 2 can be 0.5-3μm, such as 0.5μm, 0.7μm, 0.9μm, 1.3μm, 2.5μm, 3μm, etc.

[0061] In step S120, a plurality of first grooves and a plurality of second grooves are formed in the first region of the insulating support layer, the annular groove surrounds the first region, the plurality of first grooves are connected to the annular groove, and any second groove is not connected to the annular groove or any first groove.

[0062] like Figure 1 As shown, the insulating support layer 1 may include a first region. The annular groove 2 surrounds the first region, that is, the region surrounded by the annular groove 2 on the insulating support layer 1 is the first region, that is, the boundary of the first region is the inner wall of the annular groove 2. The first groove 3 and the second groove 4 can be prepared by a patterning process. Among them, the first groove 3 and the second groove 4 can be formed at the same time, but the embodiment of the present disclosure does not specifically limit this.

[0063] like Figure 1 As shown, the number of the first grooves 3 can be one, two, six, or ten, but is not limited thereto, and can also be more. Taking the number of the first grooves 3 as an example, the multiple first grooves 3 are all connected to the annular groove 2. The first groove 3 can be linear, and of course, it can also be curved, but the embodiments of the present disclosure are not limited thereto. Taking the first groove 3 as an example, both ends of the first groove 3 are connected to the annular groove 2. Some of the multiple first grooves 3 can extend along the first direction, and the remaining first grooves 3 can extend along the second direction. The first direction is perpendicular to the second direction. Further, the number of the first grooves 3 extending along the first direction can be the same as the number of the first grooves 3 extending along the second direction, and of course, it can also be different. For example, the number of the first grooves 3 extending along the first direction can be greater than the number of the first grooves 3 extending along the second direction. The multiple first grooves 3 extending along the first direction can be distributed along the second direction, and the distance between any two adjacent first grooves 3 is the same. The plurality of first grooves 3 extending along the second direction may be distributed along the first direction, and the distances between any two adjacent first grooves 3 are the same. Taking the annular groove 2 as a rectangular ring as an example, the first direction may be the length direction of the rectangular ring, and the second direction may be the width direction of the rectangular ring. The width of the first groove 3 may be 0.5-3 μm, such as 0.5 μm, 0.7 μm, 0.9 μm, 1.3 μm, 2.5 μm, 3 μm, etc. The width of the first groove 3 may be equal to the width of the annular groove 2, or may be different.

[0064] like Figure 1As shown, the number of the second grooves 4 can be one, nine, or twenty-seven, but is not limited thereto, and can also be more. Taking the case where the number of the first grooves 3 and the second grooves 4 are both multiple as an example, any second groove 4 is not connected to the annular groove 2, and any second groove 4 is not connected to any first groove 3. The second groove 4 can be linear, and of course, can also be curved, but the embodiments of the present disclosure are not limited thereto. Some of the second grooves 4 in the multiple second grooves 4 can extend along the first direction, and the remaining second grooves 4 can extend along the second direction. The width of the second groove 4 can be 0.5-3μm, for example 0.5μm, 0.7μm, 0.9μm, 1.3μm, 2.5μm, 3μm, etc. Among them, the width of the second groove 4 can be the same as the width of the first groove 3, and of course, it can also be different.

[0065] like Figure 1 As shown, the plurality of second grooves 4 can be divided into a plurality of groove groups, and each groove group includes a plurality of second grooves 4. Some of the second grooves 4 in each groove group can extend along the first direction, and the remaining second grooves 4 can extend along the second direction. Further, the number of second grooves 4 extending along the first direction in each groove group can be the same as the number of second grooves 4 extending along the second direction, and of course, can also be different. For example, the number of second grooves 4 extending along the first direction can be greater than the number of second grooves 4 extending along the second direction. The plurality of second grooves 4 extending along the first direction in each groove group can be distributed along the second direction, and the distance between any two adjacent second grooves 4 is the same. The plurality of second grooves 4 extending along the second direction in each groove group can be distributed along the first direction, and the distance between any two adjacent second grooves 4 is the same. In addition, any first groove 3 in each groove group and the remaining second grooves 4 are not connected, but the embodiments of the present disclosure do not specifically limit this. Taking the example that the number of first grooves 3 extending along the first direction and the number of first grooves 3 extending along the second direction are both two, the first area is divided into nine spaced groove areas by the first grooves 3; the multiple second grooves 4 can be divided into nine groove groups, and the nine groove groups are located in the nine groove areas one by one.

[0066] In step S130 , a conductive layer is filled in the annular trench and each first trench.

[0067] like Figure 1 and Figure 2As shown, the conductive layer 5 can be prepared by vapor deposition, but the embodiments of the present disclosure are not limited thereto. The conductive layer 5 is filled in the annular groove 2 and each first groove 3 to form a conductor of the pad structure. The material of the conductive layer 5 can be copper, of course, it can also be aluminum, but it is not limited thereto, it can also be tungsten, etc. In addition, a plurality of longitudinal connection channels (vias) 7 can be formed in the conductive layer 5. The longitudinal connection channel 7 can be filled with conductive materials, such as a tungsten plug structure, etc. The tungsten plug structure can be connected to the gate of the transistor in the substrate structure.

[0068] In step S140 , a metal layer is filled in each second trench.

[0069] like Figure 1 and Figure 2 As shown, the metal layer 6 can be prepared by vapor deposition, but the embodiments of the present disclosure are not limited thereto. The metal layer 6 is filled in the second groove 4 to enhance the mechanical strength of the pad structure, for example, to enhance the mechanical strength of the pad structure during bonding. The metal layer 6 can be made of the same material as the conductive layer 5. The metal layer 6 can be copper, of course, can also be aluminum, but is not limited thereto, and can also be tungsten, etc.

[0070] The present disclosure also provides a memory. The memory may include the pad structure of the memory described in any of the above embodiments. Since the pad structure included in the memory of the present disclosure is the same as the pad structure in the embodiment of the pad structure of the above memory, it has the same beneficial effects and is not described here.

[0071] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practice. This application is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A pad structure of a memory, characterized in that: include: An insulating support layer, comprising a first region and an annular groove surrounding the first region, wherein the first region comprises a plurality of first grooves and a plurality of second grooves, wherein the plurality of first grooves are all connected to the annular groove, and any of the second grooves is not connected to the annular groove and any of the first grooves; A conductive layer filled in the annular groove and each of the first grooves, wherein the conductive layer has a plurality of longitudinal connection channels; A metal layer is filled in each of the second grooves.

2. The pad structure of the memory according to claim 1, characterized in that: The plurality of first grooves are all straight lines, and both ends of each of the first grooves are connected to the annular groove.

3. The pad structure of the memory according to claim 2, characterized in that: Part of the first grooves extends along a first direction, and the rest of the first grooves extends along a second direction, and the first direction is perpendicular to the second direction.

4. The pad structure of the memory according to claim 3, characterized in that: Part of the second trenches extends along the first direction, and the rest of the second trenches extends along the second direction.

5. The pad structure of the memory according to claim 1, characterized in that: The conductive layer and the metal layer are made of the same material.

6. The pad structure of the memory according to claim 5, characterized in that: The conductive layer and the metal layer are made of copper, tungsten or aluminum.

7. A method for preparing a pad structure of a memory, characterized in that: include: forming an insulating support layer; forming an annular groove on the insulating support layer; A plurality of first grooves and a plurality of second grooves are formed in the first region of the insulating support layer, the annular groove surrounds the first region, a plurality of the first grooves are all connected to the annular groove, and any of the second grooves is not connected to the annular groove and any of the first grooves; Filling a conductive layer in the annular groove and each of the first grooves; A metal layer is filled in each of the second trenches.

8. The method for preparing a pad structure of a memory according to claim 7, characterized in that: The plurality of first grooves are all straight lines, and both ends of each of the first grooves are connected to the annular groove.

9. The method for preparing a pad structure of a memory according to claim 8, characterized in that: Part of the first grooves extends along a first direction, and the rest of the first grooves extends along a second direction, and the first direction is perpendicular to the second direction.

10. The method for preparing a pad structure of a memory according to claim 9, characterized in that: Part of the second trenches extends along the first direction, and the rest of the second trenches extends along the second direction.

11. The method for preparing a pad structure of a memory according to claim 7, characterized in that: The conductive layer and the metal layer are made of the same material.

12. The method for preparing a pad structure of a memory according to claim 11, characterized in that: The conductive layer and the metal layer are made of copper, tungsten or aluminum.

13. A memory, characterized in that: A pad structure comprising a memory as claimed in any one of claims 1 to 6.

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