Leadless pacemaker and method of storing event data in a leadless pacemaker

Abstract

The invention relates to a leadless pacemaker (1) comprising a central processing unit (2); a first logic circuit (11) configured to generate event data based on a first event (E1) occurring during operation of the leadless pacemaker (1); a first hardware event counter (21) configured to increment if the first logic circuit (11) generates a specific event data; a first memory unit (30) comprising a first bit configured to be set if the first hardware event counter (21) increments to a first maximum count number; a second memory unit (40) in communication with the first memory unit (30), wherein the central processing unit (2) is configured to transfer the first bit to the second memory unit (40); a first RAM event counter (51) in a random access memory of the leadless pacemaker (1), wherein the central processing unit (2) is configured to increment the first RAM event counter (51) if the first bit is transferred to the second memory unit (40). The invention further relates to a method for storing event data in a leadless pacemaker (1).

Description

Technical Field

[0001] This invention relates to leadless cardiac pacemakers and methods for storing event data in leadless cardiac pacemakers. Background Technology

[0002] A pacemaker is an implantable device that delivers electrical pulses to the heart to stimulate it and maintain a heart rhythm in patients with heart disease.

[0003] Compared to traditional pacemakers implanted subcutaneously, leadless pacemakers are small enough to be implanted directly into the heart, thus eliminating the need for electrical leads to guide the pacemaker to the heart.

[0004] To monitor and optimize performance and monitor patient health, some pacemakers are able to detect, count, and store events that occur during pacemaker operation. Based on the stored event data, pacemaker statistics such as event counters, histograms (including a series of categorized counters), and trends can be derived.

[0005] According to existing technology, the typical way to collect and store data in a pacemaker is to use an event-driven central processing unit (CPU) to process events and analyze and classify them into counts, trends, and histograms (the so-called CPU-centric approach). The CPU typically stores the resulting data in random access memory (RAM), which can be queried and processed by a clinical programmer to display to the user.

[0006] Pacemaker events occur with each heartbeat. Wake up the CPU to handle each event incurs significant overhead to manage context switching. Performing event-related timing measurements may require CPU power expenditures exceeding expected CPU performance levels, such as supporting higher clock rates, including additional timing peripherals, and handling complex software algorithms to keep the CPU active for longer periods.

[0007] CPU-centric approaches have a significant impact on pacemaker service time. Furthermore, alternative methods using dedicated logic to collect and store data increase the size of integrated circuits, potentially affecting pacemaker volume. Summary of the Invention

[0008] Therefore, the object of the present invention is to provide a leadless pacemaker that improves upon the aforementioned disadvantages of the prior art and a method for storing event data in a leadless pacemaker, particularly a pacemaker capable of storing short-term statistical data without invoking CPU operations and without imposing strict tolerances on the timing capabilities of the CPU.

[0009] This objective is achieved through the subject matter of independent claims 1 (leadless pacemaker) and 11 (method). Advantageous embodiments of the invention are claimed as dependent claims 2 to 10 and dependent claims 12 to 15, and are described below.

[0010] A first aspect of the present invention relates to a leadless pacemaker comprising at least the following components:

[0011] The central processing unit is configured to control the operation of the leadless pacemaker.

[0012] The first logic circuit is configured to generate event data based on a first event occurring during operation of the leadless pacemaker.

[0013] The first hardware event counter is configured to increment if the first logic circuit generates specific event data.

[0014] The first memory cell includes a first bit, which is configured to be set if the first hardware event counter increments to a first maximum count, specifically set to a range from 0 to 1.

[0015] A second memory unit communicates with a first memory unit, wherein the central processing unit is configured to transfer a first bit from the first memory unit to the second memory unit.

[0016] A first RAM event counter in the random access memory of a leadless pacemaker, wherein the central processing unit is configured to increment the first RAM event counter if the first bit is transferred to a second memory unit.

[0017] In the context of this specification, the term "leadless pacemaker" refers to an artificial heart pacemaker that can be directly implanted into the heart.

[0018] As used herein, "CPU" or "central processing unit" is a microprocessor configured to control the operation of a leadless pacemaker, which may include controlling the generation of voltage at the pacing electrodes of the leadless pacemaker, controlling the sensing of electrical signals to the heart, and general control and organization of data processing.

[0019] In the context of this specification, the term "logic circuit" refers to a hardware component that performs processing functions in an embedded system of the leadless pacemaker according to the present invention. Specifically, the logic circuit may incorporate selector logic configured to process two binary inputs into a single binary output. Because they are hardware components, the logic circuits described herein operate independently of the CPU and do not trigger CPU tasks. The logic circuit may receive input data relating to events occurring during the operation of the leadless pacemaker, particularly input data from sensors or other components of the leadless pacemaker embedded system. This input data is processed by the corresponding logic circuit to generate event data as described below.

[0020] As used herein, the term “event data” describes any data associated with and representing events that occur during operation of a leadless pacemaker.

[0021] In the context of this specification, the term "hardware event counter" refers to a hardware component including memory configured to count the number of inputs to the hardware event counter. For example, in the case of simple event data, the hardware event counter can receive an input signal whenever pacing is delivered by the pacing electrode of a leadless pacemaker. Each time an input signal occurs, a bit in the memory of the hardware event counter is set, specifically from 0 to 1, in such a way that the number of received input signals is counted; in other words, the hardware event counter increments. The bit size or storage space of the hardware event counter is limited, resulting in a maximum number of counts that the hardware event counter can count. Specifically, the size of the hardware event counter is determined to be sufficient to cover the number of expected events within a specific time period, which is optimized to contribute to a minimum size for the leadless pacemaker to have maximum service time. Importantly, the hardware event counter is a hardware component capable of operating independently of the CPU and not triggering CPU tasks.

[0022] In the context of this specification, the term "memory cell" (such as a first memory cell and a second memory cell) refers to a cell used to store information in a computer system. For example, a memory cell as used herein may be a register or a latch. A "register" or "processor register" is a quickly accessible location in the storage device available to a leadless pacemaker CPU. The term "latch" describes an electronic circuit that has two stable states and can be used to store information.

[0023] The corresponding bit (e.g., the first bit mentioned above) is transferred from the first memory cell to the second memory cell via the CPU. In other words, the bit in the second memory cell is set, specifically from 0 to 1, and when the corresponding hardware event counter overflows, the bit set in the first memory cell is cleared, specifically from 1 to 0.

[0024] As used herein, the term "RAM event counter" describes a dedicated area in the system's random access memory, defined by the CPU, configured to count specific inputs. The CPU generates these inputs into the corresponding RAM event counter based on bits set in a second memory cell. According to the invention, this process is used to count the number of times a specific hardware event counter has overflowed and to store that number in the RAM event counter. If the maximum count of the corresponding hardware event counter is known, the total number of events is equal to the product of the total count of the corresponding RAM event counter multiplied by the maximum count of the corresponding RAM event counter, plus the count of the corresponding hardware event counter.

[0025] When the maximum count of the corresponding hardware event counter is reached, in other words, when the memory of the hardware event counter overflows, the corresponding bit in the first memory cell, particularly in a register or latch, is set, specifically from 0 to 1, wherein the hardware event counter wraps back to zero. In other words, the hardware event counter is reset at the same time as or shortly after the maximum count of the corresponding hardware event counter is reached, wherein the count stored in the hardware event counter is cleared.

[0026] Storing statistics for a leadless pacemaker in RAM cells requires significantly less silicon area in the integrated circuit than an equivalent register, allowing large amounts of data to be stored in a small pacemaker. Furthermore, the described embedded system architecture allows for storing statistics with far less CPU work than is required in prior art leadless pacemakers. This is achieved by using a hardware element (hardware event counter) for actual event counting, where the CPU task is only required to transfer the corresponding bit representing an overflow event from the hardware event counter to random access memory.

[0027] In some embodiments, the leadless pacemaker further includes a second logic circuit configured to generate event data based on a second event occurring during operation of the leadless pacemaker, and the leadless pacemaker includes a second hardware event counter configured to increment if the second logic circuit generates specific event data, wherein a first memory unit includes a second bit configured to be set if the second hardware event counter increments to a second maximum count number, and wherein a central processing unit is configured to transfer the second bit from the first memory unit to the second memory unit, and wherein the leadless pacemaker includes a second RAM event counter in the random access memory of the leadless pacemaker, wherein the central processing unit is configured to increment the second RAM event counter if the second bit is transferred from the first memory unit to the second memory unit.

[0028] In some embodiments, the leadless pacemaker includes at least one additional logic circuit configured to generate event data based on additional events occurring during operation of the leadless pacemaker, and the leadless pacemaker includes at least one additional hardware event counter configured to increment if the additional logic circuit generates specific event data, wherein the first memory unit includes additional bits configured to be set if the additional hardware event counter increments to an additional maximum count number, and wherein the central processing unit is configured to transfer the additional bits from the first memory unit to a second memory unit, and wherein the leadless pacemaker includes at least one additional RAM event counter in the random access memory of the leadless pacemaker, wherein the central processing unit is configured to increment the additional RAM event counter if the additional bits are transferred from the first memory unit to the second memory unit.

[0029] In other words, the leadless pacemaker may also include any number of additional logic circuits and additional associated hardware event counters, which have the properties of the first and second logic circuits and the hardware event counters described above.

[0030] By utilizing more than one logic circuit and a hardware event counter, different events occurring during leadless pacemaker operation can be detected, counted, and stored.

[0031] In some embodiments, the first event may be described by a binary variable, wherein the event data generated from the first event is the value or characteristic of the binary variable.

[0032] In some embodiments, the second event or other events may be described by binary variables, wherein the event data generated from the second event or other events is the value or characteristic of the binary variables.

[0033] In the context of this specification, a binary variable is a variable that has two possible values ​​(such as 0 and 1). Such variables are typically represented using bits. In particular, the value of a binary variable indicates whether an event has occurred. For example, a binary variable with a value of 1 can indicate that the pacing electrodes of a leadless pacemaker have delivered pacing.

[0034] In some embodiments, the first event may be described by a first binary variable and a second binary variable, wherein event data generated from the first event is a third binary variable representing a specific combination of the values ​​of the first binary variable and the second binary variable.

[0035] In some embodiments, a second event or another event may be described by a first binary variable and a second binary variable, wherein event data generated from the first event is a third binary variable representing a specific combination of the values ​​of the first binary variable and the second binary variable.

[0036] For example, this embodiment can be used to implement logic gates, such as OR gates or AND gates. In this case, if the value of the first binary variable or the value of the second binary variable is 1, the value of the third binary variable can be set to 1 (OR gate), or if the values ​​of the first binary variable and the second binary variable are both 1, the value of the third binary variable can be set to 1 (AND gate).

[0037] In this way, combinations of events occurring during leadless pacemaker operation can be tracked as event data. For example, the number of heartbeats with atrial sensing and ventricular pacing can be counted (implementing an AND gate).

[0038] In some embodiments, the first event may be described by a binary variable and a metric variable, wherein event data generated from the first event represents a combination of the value of the binary variable and the range of the metric variable.

[0039] In some embodiments, a second event or additional event may be described by binary variables and metric variables, wherein event data generated from the second event or additional event represents a combination of the values ​​of the binary variables and the ranges of the metric variables.

[0040] The value of a metric variable can be, for example, an integer or a floating-point number. Specifically, a metric variable represents a measured parameter, such as a voltage detected by a sensor or a time period measured using the clock of an embedded system.

[0041] Specifically, the events represented by the range of binary and metric variables can be events belonging to a specific category of histograms, such as atrial sensing with intervals between 900 and 1000 milliseconds (ms), or atrial sensing with intervals between 1000 and 1100 ms. Based on this event data, histograms can be generated by detecting events of different categories and counting them.

[0042] In some embodiments, the leadless pacemaker includes a clock configured to generate clock data.

[0043] Advantageously, the system clock allows for optimization of the timing of steps during event detection, event data counting, and event data storage in the pacemaker, contributing to the small size and maximum lifespan of the leadless pacemaker. The optimal timing for setting the RAM event counter can be determined using the system clock.

[0044] In some embodiments, the first memory cell is double-buffered, such that its contents can be transferred to the second memory cell while the first memory cell is cleared in a single operation, wherein the operation is timed based on clock data.

[0045] This further reduces the necessary CPU tasks and contributes to the small size and long lifespan of leadless pacemakers.

[0046] In some embodiments, the central processing unit is configured to periodically transfer the first and / or second bit to a second memory unit.

[0047] This process can also be optimized in timing to help minimize the size and maximize the lifespan of the pacemaker.

[0048] In some embodiments, the first hardware event counter and / or the second hardware event counter are memory-mapped or I / O-mapped.

[0049] The term "memory mapping" refers to the mapping of the contents of the first hardware event counter and / or the second hardware event counter (representing the counts of the first and / or second hardware event counters) to the random access memory of the leadless pacemaker.

[0050] The term "I / O mapping" refers to the assignment of the contents of a first hardware event counter and / or a second hardware event counter (representing the counts of the first and / or second hardware event counters) to an I / O port address, such that the contents of the first hardware event counter and / or the second hardware event counter can be mapped to an external device connected to the corresponding I / O port of the leadless pacemaker.

[0051] External clinical programmers can easily read the contents of the pacemaker's hardware event counters via memory mapping or I / O mapping. Along with reading the RAM blocks representing the RAM event counters, the total number of events can be accurately determined at any time by calculating the product of the maximum count of the corresponding hardware counter and the overflow events stored in the corresponding RAM event counter, and adding any remaining counts in the corresponding hardware event counter.

[0052] In some embodiments, the first memory cell and / or the second memory cell are registers or latches, wherein, in particular, the second memory cell is a tri-state latch. The term "tri-state latch" describes a latch capable of presenting three states (0, 1, and high impedance).

[0053] A second aspect of the invention relates to a method for storing event data in a leadless pacemaker, particularly a leadless pacemaker according to the first aspect of the invention, wherein event data is generated based on a first event occurring during operation of the leadless pacemaker, and wherein if specific event data is generated based on the first event, a first hardware counter is incremented, and wherein if the first hardware event counter increments to a first maximum count, a first bit in a first memory unit is set, and wherein the first bit is transferred from the first memory unit to a second memory unit, and wherein if the first bit is transferred from the first memory unit to the second memory unit, a first RAM event counter in the random access memory of the leadless pacemaker is incremented.

[0054] In some embodiments of the method, additional event data is generated based on a second event occurring during operation of the leadless pacemaker, wherein if specific event data is generated based on the second event, a second hardware counter is incremented, and wherein if the second hardware event counter increments to a second maximum count, a second bit in the first memory cell is set, and wherein the second bit is transferred from the first memory cell to the second memory cell, and wherein if the second bit is transferred from the first memory cell to the second memory cell, a second RAM event counter in the random access memory of the leadless pacemaker is incremented.

[0055] In some embodiments of the method, additional event data is generated based on at least one additional event occurring during operation of the leadless pacemaker, wherein if specific event data is generated based on the additional event, an additional hardware counter is incremented, and wherein if the additional hardware event counter increments to an additional maximum count, an additional bit in the first memory cell is set, and wherein the additional bit is transferred from the first memory cell to the second memory cell, and wherein if the additional bit is transferred from the first memory cell to the second memory cell, an additional RAM event counter in the random access memory of the leadless pacemaker is incremented.

[0056] In some embodiments of the method, the first event may be described by a binary variable, wherein event data generated from the first event is the value or characteristic of the binary variable, wherein, in particular, the first event is pacing delivered by a leadless pacemaker or ventricular sensing detected by a leadless pacemaker.

[0057] In some embodiments, the first event may be described by a first binary variable and a second binary variable, wherein event data generated from the first event is a third binary variable representing a specific combination of the values ​​of the first binary variable and the second binary variable, and in particular, wherein the first event is a cardiac cycle with atrial sensing and ventricular pacing.

[0058] In some embodiments, a second event or another event may be described by a first binary variable and a second binary variable, wherein event data generated from the second event or another event is a third binary variable representing a specific combination of the values ​​of the first binary variable and the second binary variable, and in particular, wherein the second event or another event is a cardiac cycle with atrial sensing and ventricular pacing.

[0059] In some embodiments, the first event may be described by a binary variable and a measurement variable, wherein event data generated from the first event represents a combination of the values ​​of the binary variable and the ranges of the measurement variable, and in particular, wherein the first event is a heartbeat cycle having atrial sensing and the time interval between atrial sensing is within a specific range.

[0060] In some embodiments, the second event or other event may be described by binary variables and measurement variables, wherein event data generated from the second event or other event represents a combination of the values ​​of the binary variables and the ranges of the measurement variables, and in particular, wherein the second event or other event is a cardiac cycle with atrial sensing and the time interval between atrial sensing is within a certain range.

[0061] Wherein, alternatives to individual separable features are described herein as “embodiments”, and it should be understood that these alternatives may be freely combined to form discrete embodiments of the invention disclosed herein. Attached Figure Description

[0062] The present invention is further illustrated by the following embodiments and accompanying drawings, from which further embodiments and advantages can be derived. These embodiments are intended to illustrate the invention, and not to limit its scope.

[0063] Figure 1 A schematic cross-sectional view of an example of a leadless pacemaker according to the present invention is shown;

[0064] Figure 2 A schematic diagram of an embedded system included in a leadless pacemaker according to the present invention is shown. Detailed Implementation

[0065] Figure 1 A leadless pacemaker 1 is shown in cross-section, comprising an electronics module 4, an energy storage device 5, and a conductive connector 6 connecting the energy storage device 5 to the electronics module 4 to provide energy to the electronics module 4. The pacemaker 1 also includes electrodes 7 configured to contact cardiac tissue when the pacemaker 1 is implanted in the heart, wherein the electrodes 7 are configured to generate electrical pulses and stimulate the heart. Furthermore, the pacemaker 1 includes a fixation element 8 (shown here as a hook) for securing the pacemaker 1 in the cardiac tissue. An implant / explant port 9 of the leadless pacemaker 1 is also shown. Figure 1 middle.

[0066] The electronic module 4 of the pacemaker 1 includes an embedded system 3, which includes a central processing unit (CPU) 2. Figure 2 Detailed description is provided.

[0067] The embedded system 3 includes a first logic circuit 11 and a second logic circuit 12. The first logic circuit 11 receives an input signal based on a first event E1 occurring during operation of the leadless pacemaker 1, and the second logic circuit 12 receives an input signal based on a second event E2 occurring during operation of the leadless pacemaker 1. For example, the input signal may be generated by a sensor of the leadless pacemaker 1. Alternatively, the CPU 2 may provide the input signal, for example, whenever the CPU 2 sends a control signal to the electrode 7 of the leadless pacemaker 1 to initiate pulse generation. Of course, in the case of events E1 and E2, the first logic circuit 11 and the second logic circuit 12 may each receive more than one signal. The first logic circuit 11 and the second logic circuit 12 also receive clock data C from the clock 70 of the embedded system 3, so that the input signals based on events E1 and E2 can be timed.

[0068] The first logic circuit 11 and the second logic circuit 12 are configured to process one or more input signals and generate event data representing events E1 and E2 based on the input signals. For example, the first logic circuit 11 can be configured to generate event data representing pacing whenever the electrode 7 of the leadless pacemaker has generated pacing. If the event data indicates that pacing has been generated, an output signal is sent from the first logic circuit to a first hardware event counter 21, thereby incrementing the first hardware event counter 21.

[0069] Similarly, the second logic circuit 12 can be adapted to generate event data indicating whether a cardiac cycle with atrial sensing and ventricular pacing has occurred, and send a corresponding output signal to the second hardware event counter 22, which increments accordingly.

[0070] Importantly, the first logic circuit 11, the second logic circuit 12, the first hardware event counter 21, and the second hardware event counter 22 are hardware components that operate independently of the CPU, which reduces the necessary CPU workload. The first logic circuit 11 and the second logic circuit 12 are used to identify event conditions representing statistics being collected. This may include logic for timing the intervals between events. In the case of histogram data, logic (including, for example, logic for measuring intervals) can be used to select which hardware event counters 21, 22 will be incremented using selector logic.

[0071] For simplicity, Figure 2 The diagram depicts two logic circuits 11 and 12 and two hardware event counters 21 and 22. Of course, the embedded system 3 may include two or more logic circuits configured to generate event data and two or more hardware event counters to count events for detecting and processing further events.

[0072] The first hardware event counter 21 and the second hardware event counter 22 can each count to their respective maximum count based on their allocated memory size. If the maximum count is reached, either the first hardware event counter 21 or the second hardware event counter 22 overflows. During the overflow of the hardware event counter, an output signal is sent to the first memory cell 30, which can be an active register or a latch. Based on which hardware event counter 21, 22 generated the output signal, the corresponding bit in the first memory cell 30 is set from 0 to 1 (set operation S), and the corresponding hardware event counter 21, 22 is cleared and can start counting again.

[0073] The first memory unit 30 is double-buffered. Periodically, during optimized time periods that contribute to the minimum size and maximum lifespan of the pacemaker 1, a CPU task is triggered that transfers overflow bits from the first memory unit 30 to the second memory unit 40, which can be a working register or a tri-state latch (transfer operation T).

[0074] Overflow bits associated with the first hardware event counter 21 and the second hardware event counter 22 are transferred to the second memory cell 40 in a single clock operation, which further reduces CPU workload.

[0075] Specifically, the first memory unit 30 and the second memory unit 40 are connected via a data bus 60 to transmit corresponding bits.

[0076] For each of the hardware event counters 21 and 22 in the embedded system 3, the CPU task defines storage space in random access memory (RAM) 50 to count how many overflows have occurred for the corresponding hardware event counter 21, 22. In other words, a first RAM event counter 51 that counts overflows of the first hardware event counter 21 and a second RAM event counter 52 that counts overflows of the second hardware event counter 22 are defined in RAM 50. The CPU task sequentially identifies which bits have been set in the second memory cell 40 and increments the associated first RAM event counter 51 or second RAM event counter 52 accordingly. The size of the space allocated in RAM 50 for each RAM event counter 51, 52 is set to be able to count to the expected maximum number of overflows during the lifetime of the leadless pacemaker 1 or between subsequent checks that allow event counting to restart to generate statistics.

[0077] Specifically, hardware event counters 21 and 22 are cleared only upon power-up and when a command to restart the statistics is received from an external programmer. This command will also specifically cause the associated RAM event counters 51 and 52 to be cleared.

[0078] Hardware event counters 21 and 22 are, in particular, memory-mapped or I / O-mapped, making them queried by an external clinical programmer capable of reading the contents of the memory of the leadless pacemaker 1. The corresponding RAM blocks associated with RAM event counters 51 and 52 used to count the overflow counts of each hardware event counter 21 and 22 are also readable by an external programmer.

[0079] The programmer uses the overflow counts of RAM event counters 51 and 52 as the high-order part of the total count and the counts of hardware event counters 21 and 22 as the low-order part of the total count, wherein, in particular, the total count is equal to the product of the overflow count and the known maximum count of the associated hardware event counters 21 and 22 plus the current count of the associated hardware event counters 21 and 22.

[0080] Embedded system 3 is suitable for any number of n input signals based on any number of events En. Corresponding to the signal processing structure based on signals E1 and E2, any further signals can be processed by logic unit 1n, followed by hardware event counter 2n, which stores the overflow bit in memory unit 30 and transmits the overflow bit to memory unit 40 via data bus 60 for further processing by the CPU.

[0081] List of reference numerals in the attached figures

[0082] 1 leadless pacemaker

[0083] 2 Central Processing Units

[0084] 3 Embedded Systems

[0085] 4 electronic modules

[0086] 5 Energy storage devices

[0087] 6 Electrical connections

[0088] 7 electrodes

[0089] 8 Fixing Components

[0090] 9 Implant / Explant Ports

[0091] 11 First Logic Circuit

[0092] 12 Second Logic Circuit

[0093] 21 First Hardware Event Counter

[0094] 22 Second Hardware Event Counter

[0095] 30 First Memory Unit

[0096] 40 Second Memory Unit

[0097] 50 Random Access Memory (RAM)

[0098] 51 First RAM Event Counter

[0099] 60 data bus

[0100] 70 clocks

[0101] C clock data

[0102] E1 First Event

[0103] E2 Second Event

[0104] O overflow

[0105] S settings operation

[0106] T transfer operation

Claims

1. A leadless pacemaker (1), comprising: The central processing unit (2) is configured to control the operation of the leadless pacemaker. The first logic circuit (11) is configured to generate event data based on a first event (E1) occurring during operation of the leadless pacemaker (1), wherein the first event (E1) can be described by a binary variable. The first hardware event counter (21) is configured to increment if the first logic circuit (11) generates specific event data. The first memory unit (30) includes a first bit, which is configured to be set if the first hardware event counter (21) increments to a first maximum count number. The second memory unit (40) communicates with the first memory unit (30), wherein the central processing unit (2) is configured to periodically transfer the first bit to the second memory unit (40). The first RAM event counter (51) in the random access memory of the leadless pacemaker (1), wherein the central processing unit (2) is configured to increment the first RAM event counter (51) if the first bit is transferred to the second memory unit (40).

2. The leadless pacemaker (1) according to claim 1, characterized in that, The leadless pacemaker (1) further includes a second logic circuit (12) and a second hardware event counter (22), the second logic circuit (12) being configured to generate event data based on a second event (E2) occurring during operation of the leadless pacemaker (1), the second hardware event counter (22) being configured to increment if the second logic circuit (12) generates specific event data, wherein the first memory unit (30) includes a second bit configured to be set if the second hardware event counter (22) increments to a second maximum count number, and wherein the central processing unit (2) is configured to transfer the second bit to the second memory unit (40), and wherein the leadless pacemaker (1) includes a second RAM event counter (52) in the random access memory of the leadless pacemaker (1), wherein the central processing unit (2) is configured to increment the second RAM event counter (52) if the second bit is transferred from the first memory unit (30) to the second memory unit (40).

3. The leadless pacemaker (1) according to claim 1, characterized in that, The event data generated from the first event (E1) is the value of the binary variable.

4. The leadless pacemaker (1) according to claim 1, characterized in that, The first event (E1) can be described by a first binary variable and a second binary variable, wherein the event data generated from the first event (E1) is a third binary variable representing a combination of the values ​​of the first binary variable and the second binary variable.

5. The leadless pacemaker (1) according to claim 1, characterized in that, The first event (E1) can be described by a binary variable and a metric variable, wherein the event data generated from the first event (E1) represents a combination of the value of the binary variable and the range of the metric variable.

6. The leadless pacemaker (1) according to claim 1, characterized in that, The leadless pacemaker (1) includes a clock (70) configured to generate clock data (C).

7. The leadless pacemaker (1) according to claim 6, characterized in that, The first memory cell (30) is double-buffered, such that its contents can be transferred to the second memory cell (40) while the first memory cell (30) is cleared in a single operation, wherein the operation is timed based on the clock data (C).

8. The leadless pacemaker (1) according to claim 2, characterized in that, The central processing unit (2) is configured to periodically transfer the second bit to the second memory unit (40).

9. The leadless pacemaker (1) according to claim 2, characterized in that, The first hardware event counter (21) and / or the second hardware event counter (22) are memory-mapped or I / O-mapped.

10. The leadless pacemaker (1) according to claim 1, characterized in that, The first memory unit (30) and / or the second memory unit (40) are registers or latches, wherein the second memory unit (40) is a tri-state latch.

11. A method for storing event data in a leadless pacemaker (1), the leadless pacemaker (1) being the leadless pacemaker (1) according to claim 1, wherein event data is generated based on a first event (E1) occurring during operation of the leadless pacemaker (1), and wherein if specific event data is generated based on the first event (E1), a first hardware event counter (21) is incremented, and wherein if the first hardware event counter (21) increments to a first maximum count, a first bit in a first memory unit (30) is set, and wherein the first bit is periodically transferred from the first memory unit (30) to a second memory unit (40), and wherein if the first bit is periodically transferred to the second memory unit (40), a first RAM event counter (51) in the random access memory of the leadless pacemaker (1) is incremented, wherein the first event (E1) can be described by a binary variable.

12. The method of claim 11, wherein additional event data is generated based on a second event (E2) occurring during operation of the leadless pacemaker (1), and wherein if specific event data is generated based on the second event (E2), a second hardware event counter (22) is incremented, and wherein if the second hardware event counter (22) increments to a second maximum count, a second bit in the first memory unit (30) is set, and wherein the second bit is transferred from the first memory unit (30) to the second memory unit (40), and wherein if the second bit is transferred to the second memory unit (40), a second RAM event counter (52) in the random access memory of the leadless pacemaker (1) is incremented.

13. The method of claim 11, wherein the event data generated from the first event (E1) is the value of the binary variable, the first event (E1) being a pacing delivered by the leadless pacemaker (1) or a ventricular sensing detected by the leadless pacemaker (1).

14. The method of claim 11, wherein the first event (E1) may be described by a first binary variable and a second binary variable, wherein the event data generated from the first event (E1) is a third binary variable representing a combination of the values ​​of the first binary variable and the second binary variable, wherein the first event (E1) is a cardiac cycle with atrial sensing and ventricular pacing.

15. The method of claim 11, wherein the first event (E1) may be described by a binary variable and a metric variable, wherein the event data generated from the first event (E1) represents a combination of the value of the binary variable and the range of the metric variable, wherein the first event (E1) is a cardiac cycle having a time interval between atrial sensing and atrial sensing within a specific range.

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