Storage device and method for controlling a storage device

Abstract

A multi-level content addressable memory device is provided. Some embodiments relate to a memory device including a plurality of rows of memory cells, a plurality of match lines, and a plurality of precharge circuits. A first row of the plurality of rows includes a first segment and a second segment. The first segment includes a first subset of the memory cells of the first row, and the second segment includes a second subset of the memory cells of the first row. A first match line is coupled to the memory cells of the first subset, and a second match line is coupled to the memory cells of the second subset. A first precharge circuit is configured to precharge the first match line to a first precharge voltage, and a second precharge circuit is configured to precharge the second match line to a second precharge voltage different from (e.g., greater than) the first precharge voltage.

Description

Technical Field

[0001] This application generally relates to a storage device, and more particularly, to a low-power multi-stage / multi-segment storage device and a method for controlling the storage device. Background Technology

[0002] Content-addressable memory (CAM) is a type of computer memory specifically designed for search-intensive applications. Some CAMs are designed to search their entire contents within a single clock cycle. Data stored in the CAM can be accessed by searching the data itself, and then the memory retrieves the address where that data is located. Due to its parallel nature, CAM search speeds are significantly faster than random access memory (RAM) architectures. CAMs are commonly used in internet routers and switches to improve the speed of route lookup, datagram classification, and datagram forwarding. Summary of the Invention

[0003] The following summary is illustrative only and is not intended to be limiting in any way. That is, it provides an overview to introduce the concepts, key points, benefits, and advantages of the novel and non-obvious techniques described herein. Selected embodiments are further described in the detailed description below. Therefore, the following summary is neither intended to identify the essential features of the claimed subject matter nor to define the scope of the claimed subject matter.

[0004] Some embodiments relate to a storage device including a plurality of rows of storage cells, wherein a first row of the plurality of rows includes a first segment and a second segment, the first segment including a first subset of the storage cells of the first row, and the second segment including a second subset of the storage cells of the first row; a first match line is coupled to the storage cells of the first subset; a second match line is coupled to the storage cells of the second subset; a first precharge circuit is configured to precharge the first match line to a first precharge voltage; and a second precharge circuit is configured to precharge the second match line to a second precharge voltage different from the first precharge voltage.

[0005] In some embodiments, the storage device further includes: a first clock circuit configured to provide a clock at a first clock rate to the first segment; and a second clock circuit configured to provide a clock at a second clock rate to the second segment.

[0006] In some embodiments, the first precharge voltage is less than the second precharge voltage, and the first clock rate is less than the second clock rate.

[0007] In some embodiments, the first row is configured to store a numerical sequence, the storage units of the first subset are configured to store a first portion of the numerical sequence, and the storage units of the second subset are configured to store a second portion of the numerical sequence; and the storage device further includes a first input circuit and a second input circuit; the first input circuit is configured to provide the first portion of the input numerical sequence to the first segment of the first row, and the second input circuit is configured to provide the second portion of the input numerical sequence to the second segment of the first row.

[0008] In some embodiments, the second segment of the first line is configured to compare the second portion of the input numerical sequence with the second portion of the numerical sequence only if the first portion of the input numerical sequence matches the first portion of the numerical sequence.

[0009] In some embodiments, the storage device further includes a first power supply circuit and a second power supply circuit, the first power supply circuit being configured to provide a first power supply voltage to the first input circuit, and the second power supply circuit being configured to provide a second power supply voltage to the second input circuit that is different from the first power supply voltage.

[0010] In some embodiments, the storage device further includes a first clock circuit and a second clock circuit, the first clock circuit being configured to provide a clock at a first clock rate to the first input circuit, and the second clock circuit being configured to provide a clock at a second clock rate to the second input circuit, the second clock rate being different from the first clock rate.

[0011] In some embodiments, the first power supply voltage is less than the second power supply voltage, and the first clock rate is less than the second clock rate.

[0012] In some embodiments, the storage device is a content addressable memory (CAM), and each of the plurality of rows further includes a plurality of comparators, each comparator being coupled to a corresponding storage cell.

[0013] In some embodiments, the first precharge circuit includes a first transistor, and the second precharge circuit includes a second transistor; wherein the first transistor and the second transistor have different dimensions.

[0014] In some embodiments, the first precharge circuit includes a first transistor, and the second precharge circuit includes a second transistor; wherein the first transistor and the second transistor have different threshold voltages.

[0015] In some embodiments, the storage device further includes a first delay unit and a second delay unit, the first delay unit being configured to provide a first clock to the first segment based on a common input clock, and the second delay unit being configured to provide a second clock to the second segment based on the common input clock, wherein the first delay unit and the second delay unit generate different delay amounts.

[0016] Some embodiments relate to a storage device comprising a plurality of rows of storage cells, wherein a first row of the plurality of rows includes a first segment and a second segment, the first segment including a first subset of the storage cells of the first row, and the second segment including a second subset of the storage cells of the first row, wherein the storage cells of the first subset are configured to store a first portion of a numerical sequence, and the storage cells of the second subset are configured to store a second portion of the numerical sequence; a first input circuit configured to provide the first portion of the input numerical sequence to the first segment of the first row; a second input circuit configured to provide the second portion of the input numerical sequence to the second segment of the first row; a first power supply circuit configured to provide a first power supply voltage to the first input circuit; and a second power supply circuit configured to provide a second power supply voltage different from the first power supply voltage to the second input circuit.

[0017] In some embodiments, the first segment of the first row includes a plurality of first comparators configured to compare the first portion of the input numerical sequence with the first portion of the numerical sequence; and wherein the second segment of the first row includes a plurality of second comparators configured to compare the second portion of the input numerical sequence with the second portion of the numerical sequence.

[0018] In some embodiments, the plurality of second comparators are configured to compare the second portion of the input numerical sequence with the second portion of the numerical sequence only if the first portion of the input numerical sequence matches the first portion of the numerical sequence.

[0019] In some embodiments, the storage device further includes a first clock circuit and a second clock circuit, the first clock circuit being configured to provide a clock at a first clock rate to the first input circuit, and the second clock circuit being configured to provide a clock at a second clock rate to the second input circuit, the second clock rate being different from the first clock rate.

[0020] In some embodiments, the first power supply voltage is less than the second power supply voltage, and the first clock rate is less than the second clock rate.

[0021] Some embodiments relate to a method for controlling a storage device including a plurality of rows of storage cells, wherein a first row of the plurality of rows includes a first segment and a second segment, the first segment including a first subset of the storage cells of the first row, and the second segment including a second subset of the storage cells of the first row. The method includes: pre-charging a first matching line to a first pre-charge voltage, wherein the first matching line is coupled to the storage cells of the first subset; pre-charging a second matching line to a second pre-charge voltage different from the first pre-charge voltage, wherein the second matching line is coupled to the storage cells of the second subset; providing a first portion of an input value sequence to the first segment of the first row via a first input circuit; and providing a second portion of the input value sequence to the second segment of the first row via a second input circuit.

[0022] In some embodiments, a first portion of the numerical sequence is stored in a storage unit of the first subset, a second portion of the numerical sequence is stored in a storage unit of the second subset, and the method further includes comparing the second portion of the input numerical sequence with the second portion of the numerical sequence only when the first portion of the input numerical sequence matches the first portion of the numerical sequence.

[0023] In some embodiments, the method further includes: providing a first power supply voltage to the first input circuit; and providing a second power supply voltage different from the first power supply voltage to the second input circuit.

[0024] The above description of the invention is provided by way of example and is not intended to limit the scope of the invention. Those skilled in the art will readily understand these and other objectives of the invention after reading the following detailed description of the preferred embodiments shown in the accompanying drawings. A detailed description will be given in the following embodiments with reference to the accompanying drawings. Attached Figure Description

[0025] The accompanying drawings are included to provide a further understanding of the embodiments of this disclosure, and are incorporated in and constitute a part of the embodiments of this disclosure. The drawings illustrate implementations of the embodiments of this disclosure and, together with the description, serve to explain the principles of the embodiments of this disclosure. It is understood that the drawings are not necessarily drawn to scale, as some components may be shown out of proportion to actual dimensions in order to clearly illustrate the concepts of the embodiments of this disclosure.

[0026] Figure 1A This is a block diagram of a storage device divided into multiple stages, according to some embodiments.

[0027] Figure 1B The embodiments are shown in more detail below. Figure 1AA block diagram of the storage unit of a storage device.

[0028] Figure 2A It is shown according to some embodiments Figure 1A A block diagram of one row of a storage device.

[0029] Figure 2B As shown in some embodiments Figure 2A The following is a signal diagram showing the timing of some control signals.

[0030] Figure 3A (by) Figure 3A-1 and Figure 3A-2 The composition (as shown in some embodiments) may be Figure 1A A block diagram of the first example of a row of a storage device.

[0031] Figure 3B This is a block diagram of the first stage pre-charge circuit of the row in FIG3A, shown according to some embodiments.

[0032] Figure 3C This is a block diagram of the second-stage pre-charge circuit of the row in Figure 3A, shown according to some embodiments.

[0033] Figure 3D This is a block diagram of the third stage pre-charge circuit of the row in Figure 3A, as shown in some embodiments.

[0034] Figure 3E This is a block diagram of the first stage input circuit of the row in Figure 3A, shown according to some embodiments.

[0035] Figure 3F This is a block diagram of the second-stage input circuit of row 3A shown according to some embodiments.

[0036] Figure 3G This is a block diagram of the third-stage input circuit of row 3A shown according to some embodiments.

[0037] Figure 4A (by) Figure 4A-1 and Figure 4A-2 The composition (as shown in some embodiments) may be Figure 1A A second example block diagram of a row of a storage device.

[0038] Figure 4B This is a block diagram of the first stage pre-charge circuit of the row in Figure 4A, shown according to some embodiments.

[0039] Figure 4C This is a block diagram of the second-stage pre-charge circuit of the row in Figure 4A, shown according to some embodiments.

[0040] Figure 4DThis is a block diagram of the third stage pre-charge circuit of row 4A shown according to some embodiments.

[0041] Figure 5A (by) Figure 5A-1 and Figure 5A-2 The composition (as shown in some embodiments) may be Figure 1A A block diagram of the third example of a row of a storage device.

[0042] Figure 5B This is a block diagram of the first stage pre-charge circuit of the row in FIG5A, shown according to some embodiments.

[0043] Figure 5C This is a block diagram of the second-stage pre-charge circuit of the row in FIG5A, shown according to some embodiments.

[0044] Figure 5D This is a block diagram of the third stage pre-charge circuit of row 5A shown according to some embodiments.

[0045] Figure 6 This is based on some embodiments. Figure 1A A block diagram of one row of another architecture for a storage device.

[0046] In the following detailed description, numerous specific details are set forth for illustrative purposes so that those skilled in the art can more thoroughly understand the embodiments of the invention. However, it will be apparent that one or more embodiments may be practiced without these specific details, and different embodiments may be combined as needed, and should not be limited to the embodiments illustrated in the accompanying drawings. Detailed Implementation

[0047] The following description illustrates preferred embodiments of the present invention and is intended only to exemplify the technical features of the invention, not to limit the scope of the invention. Throughout this specification and claims, certain terms are used to refer to specific elements. Those skilled in the art should understand that manufacturers may use different names for the same element. Therefore, this specification and claims do not distinguish elements by differences in name, but rather by differences in function. The terms "element," "system," and "device" used in this invention can refer to computer-related entities, where the computer can be hardware, software, or a combination of hardware and software. The terms "comprising" and "including" as used in the following description and claims are open-ended terms and should be interpreted as "comprising, but not limited to...". Furthermore, the term "coupled" refers to an indirect or direct electrical connection. Therefore, if a device is described as coupled to another device, it means that the device can be directly electrically connected to the other device, or indirectly electrically connected to the other device through other devices or connection means.

[0048] The terms "basically" or "roughly" as used in this document mean that, within an acceptable range, a person skilled in the art can solve the technical problem to be solved and basically achieve the desired technical effect. For example, "roughly equal to" means a method that a person skilled in the art can accept with a certain margin of error from "exactly equal to" without affecting the correctness of the result.

[0049] The applicant has recognized that, while providing high performance, the highly parallel design and operation of CAMs also result in significant peak current and high average power consumption. This limits the applicability of these types of memories. Compared to other memory architectures such as RAM, CAMs typically dissipate more power and have higher peak current, primarily because CAMs include additional circuitry for performing compare operations in a highly parallelized manner.

[0050] The applicant has recognized that partitioning the memory architecture in stages can partially reduce the peak current and power consumption of the CAM. In such an architecture, instead of comparing the input data (the data to be searched in memory) as a whole against rows of memory, comparisons are made segment by segment. For example, consider a 64-bit CAM with 512 rows, where memory is searched to identify the presence (and location) of a 64-bit input numeric sequence. In a single clock cycle, a conventional architecture compares each bit of the input numeric sequence against the corresponding memory cell for each row. Therefore, 32,768 comparisons (64 x 512) are performed in a single clock cycle. The number of comparisons performed within a clock cycle is generally unrelated to whether a match is found. Because the existence of the input numeric sequence in memory is unknown beforehand, the memory searches the entire memory (or, in some cases, searches until a match is found).

[0051] Conversely, the partitioned architecture is designed to compare segments of the input numerical sequence with segments of the row. First, the first segment of the input numerical sequence is compared with the first segment of the row. If this comparison produces a match, the memory compares the second segment of the input numerical sequence with the second segment of the row. Furthermore, if the second comparison produces a match, the memory compares the third segment of the input numerical sequence with the third segment of the row. However, if the comparison does not produce a match, the memory skips the comparison of subsequent segments, thus saving power, which would otherwise be futile if performed. In some embodiments, segment-wise comparisons are performed serially within the same clock cycle. In other embodiments, the comparisons are pipelined across different clock cycles (this is referred to as "multi-stage comparisons").

[0052] While these techniques reduce power consumption, the applicant has realized that in some cases, this reduction is insufficient. Therefore, the applicant has developed techniques to further reduce power consumption, enabling the use of CAMs in a wider range of applications. Additionally, this developed technique reduces peak current. This technique utilizes the aforementioned multi-level architecture and further involves operating the individual levels of the memory with different power regimes. In the first level (when comparing the first segment of the input numerical sequence with the first segment of a row), the memory operates in a first power regime. In the second level (when comparing the second segment of the input numerical sequence with the second segment of a row), the memory operates in a second power regime. These power regimes differ from each other, resulting in different power requirements for performing bit comparisons. Therefore, it is possible to essentially control the memory to consume more or less power depending on the level / segment. For example, in the first level, the memory can operate in a state where comparisons are performed using the lowest power consumption. Each level can be compared sequentially in the same clock cycle or in a pipelined manner.

[0053] In some embodiments, a multi-stage architecture can be arranged such that comparisons in the first stage occur more frequently than in subsequent stages, because comparisons in subsequent stages depend on finding a match in the first stage. The applicant has recognized that power consumption can be significantly reduced by decreasing the power dissipated in the first stage (where comparisons are most frequent or more generally performed). In one example, the power consumption of the stage can be reduced by decreasing the amplitude of the voltage supplied to the stage. In another example, the power consumption of the stage can be reduced by decreasing the amplitude of the voltage pre-charging the matching line.

[0054] However, the applicant further recognizes that reducing the voltage amplitude (and / or power consumption) associated with a stage leads to several disadvantages. One such disadvantage is the increased time required to perform compare operations, which in turn reduces the speed of memory search. In some embodiments, this disadvantage can be mitigated by operating the low-power stage at a low speed while simultaneously operating at least some other stages at a higher speed. For example, a low-speed clock can be used to perform / time operations on the low-power stage, while a high-speed clock is used to perform / time operations on at least some less frequently used subsequent stages. In some embodiments, this disadvantage can be mitigated by allocating a higher percentage of the total compare time to the low-amplitude voltage stage and a smaller percentage to the higher amplitude voltage stage. Similarly, fewer bit comparisons can be performed on the lower-amplitude comparison stages and more bit comparisons can be performed on the higher-amplitude stages to avoid performance degradation.

[0055] Some embodiments relate to a storage device (e.g., a CAM) including multiple rows of storage cells, multiple matching lines, and multiple precharge circuits. For example, a first row of the multiple rows includes a first segment and a second segment. The first segment may include a first subset of the storage cells in the first row, and the second segment may include a second subset of the storage cells in the first row. A first matching line is coupled to the storage cells of the first subset, and a second matching line is coupled to the storage cells of the second subset. A first precharge circuit is configured to precharge the first matching line to a first precharge voltage, and a second precharge circuit is configured to precharge the second matching line to a second precharge voltage different from (e.g., greater than) the first precharge voltage. In this way, a comparison in the first segment requires a different amount (e.g., less) of power compared to a comparison in the second segment. In some embodiments, comparisons on certain stages are performed only if a match is found in a comparison on a preceding stage.

[0056] In some embodiments, a first input circuit may be configured to provide a first portion of an input value sequence to a first segment of a row in a storage device, and a second input circuit may be configured to provide a second portion of an input value sequence to a second segment of the row. In some such embodiments, a first clock circuit may be configured to operate the first input circuit at a first clock rate (or, the first clock circuit is configured to provide a clock at the first clock rate to the first input circuit), and a second clock circuit may be configured to operate the second input circuit at a second clock rate different from (e.g., greater than) the first clock rate (or, the second clock circuit is configured to provide a clock at the second clock rate to the second input circuit). This allows the comparison of the second segment to be performed at a different rate than the comparison of the first segment (e.g., faster). In some embodiments, the first segment of the row includes a plurality of first comparators configured to collectively compare a first portion of the input value sequence with a first portion of a value sequence stored in memory, and the second segment of the first row includes a plurality of second comparators configured to collectively compare a second portion of the input value sequence with a second portion of a value sequence stored in memory.

[0057] Figure 1A This is a block diagram illustrating a storage device divided into multiple stages according to some embodiments. In this example, the storage device 100 (which may be arranged as a CAM in some embodiments) includes stages 102 and 104. However, in other embodiments, the storage device 100 may include more than two stages. The first row of the storage device 100 includes memory cells 112. 11 112 12 ...112 1N 114 11 114 12 114 1M (Where M and N can be the same or different). Storage unit 112 11 112 12 …112 1N The first segment that constitutes this line, and memory unit 114 11 114 12 114 1M This constitutes the second segment of the row. Other rows can also be arranged in segments. For example, the second row has storage unit 112. 21 112 22 、…、112 2N The first segment and including storage unit 114 11 114 12114 1M The second paragraph. Similarly, the Rth row has storage unit 112. R1 112 R2 、…、112 RN The first segment and including storage unit 114 R1 114 R2 114 RM The second paragraph.

[0058] Taking the first row as an example, in some embodiments, only in storage unit 112 11 112 12 、…、112 1N Only when a match is found in the comparison on the above is it stored in storage unit 114. 11 114 12 114 1M Perform a comparison above.

[0059] In other architectures, storage device 100 can be arranged as a binary CAM or a ternary CAM. In a binary CAM implementation, only two states can be represented, namely 0 and 1. In a ternary CAM implementation, the memory can store and retrieve data using three different inputs (0, 1, and X). The "X" input is called the "wildcard" state. For example, a ternary CAM can store a numerical sequence "10XX0", which will match any one of the four input numerical sequences "10000", "10010", "10100", and "10110".

[0060] Figure 1B A representative memory cell is shown in more detail. In this example, memory cell 112 11The system includes memory 124 and a comparator 126. Memory 124 can be configured to store a single numerical value (e.g., binary, ternary, or x-ary). For example, memory 124 can include static RAM, dynamic RAM, or other types of memory. Comparator 126 can be designed to compare an input numeric value with a numeric value stored in memory 124. If the input matches, the comparator outputs 1; otherwise, if the input does not match, the comparator outputs 0 (the reverse logic is also possible; therefore, the present invention does not limit the output value of the comparator, as long as it reflects a match or mismatch). In some embodiments, in a ternary CAM implementation, each memory cell may further include additional memory for storing a mask indicating whether the value stored in that memory cell is considered a wildcard.

[0061] Figure 1A The storage device can be designed to perform search operations to identify the presence and location of a specific input numerical sequence. Representative numerical sequences are in... Figure 1A The bottom shows that DIN1 <1> DIN1 <2> , ...,DIN1 <n>Represents the first bit of the input numerical sequence, DIN2 <1> DIN2 <2> , ...,DIN2 <m>This represents the second segment of the input numerical sequence. In the first step of the search operation, the first segment of the input numerical sequence is compared with the first segment of the row in the storage device. If there is no match, the search operation ends, thus saving power; otherwise, comparing the second segment would be futile. However, if a match exists, the second segment of the input numerical sequence is compared with the second segment of the row. If a complete match is identified, the storage device returns the address of the matching row or a match flag indicating the specific row that was matched.

[0062] In some embodiments, the first-stage comparison is performed at a lower voltage / power and optionally at a low speed. In contrast, the second-stage comparison is performed using a higher voltage (and therefore consumes more power) and optionally a faster clock, thereby improving accuracy and / or speed. Figure 2A A portion of a storage device arranged in this manner is shown. Specifically, Figure 2A One row of the storage device is shown, but other rows can use a similar architecture. As will be further understood below, input circuits 232 and 234 can be shared across several rows. In this example, the storage device is divided into two levels. The first level includes storage cell 112. 11 112 12 、…、112 1N The system includes an input circuit 232, a match line (ML) 212, a pre-charge circuit (labeled "PRCHG CKT" in the figure) 202, a delay unit 242, a detector (labeled "DETECT CKT" in the figure) 222, and a flip-flop (FF) 252. The second stage includes a storage unit 114. 11 114 12 114 1M The circuit includes an input circuit 234, a matching line 214, a precharge circuit 204, an enable line 264, a detector 224, a delay unit 244, and a trigger 254.

[0063] Input circuit 232 receives the first portion of the input value sequence and provides it to the first segment of the row of the storage device, thereby performing a comparison operation. In this example, the input circuit is implemented using NAND gates and NOT gates, but other implementations are also possible. In this implementation, the input circuit provides the first portion of the input value sequence to the first segment of the row with timing determined by clock SRCLK. The output of the storage cell is coupled to match line 212. For example, each comparator 126 ( Figure 1B The output of (as shown) is coupled to the matching line 212.

[0064] Initially, before the first-stage search operation, the matching line 212 is precharged with a certain precharge voltage (Vml-1). The value of this precharge voltage is set by the precharge circuit 202. If all outputs of the memory cell are 1 (indicating a match), the voltage on the matching line remains constant and equal to the precharge voltage. However, if a comparison with one of the memory cells does not produce a match, the unmatched memory cell forms a path between the matching line 212 and ground, thereby reducing the voltage on the matching line.

[0065] Detector 222 determines whether the first segment of the input numerical sequence matches the first segment of the row. For example, in some embodiments, detector 222 compares the voltage on the matching line with a threshold voltage and determines whether a match exists based on the comparison result.

[0066] If detector 222 determines that a match exists, line "MATCH_S1" is asserted, thereby enabling line 264 via trigger 252. For clarity, for example, the voltage on line "MATCH_S1" is low by default; when detector 222 determines a match, the voltage on line "MATCH_S1" is set to high, meaning line "MATCH_S1" is asserted or enabled. It should be noted that this example is not intended to limit the invention, but rather as an illustrative description for clarity. The asserted enable line indicates that a second-stage comparison can proceed. Therefore, the value provided by input circuit 234 is compared with the value of the memory cell stored in the second segment of that line. As described above in conjunction with the first stage, pre-charge circuit 204 pre-charges match line 214 with a pre-charge voltage (Vml-2). If all outputs of the memory cell are 1, the voltage on match line 214 remains constant. However, if at least one mismatch exists, the voltage will decrease. Detector 224 determines whether the second segment of the input numerical sequence matches the second segment of the storage cell in that row based on the voltage on the match line 214 (e.g., by comparing the voltage on the match line with a threshold voltage). If detector 224 determines that a match exists, trigger 254 is used to activate the "MATCH" line.

[0067] The clock SRCLK is used to control the operation of storage devices. For example... Figure 2A As shown, the clock SRCLK controls the timing of input circuits 232 and 234, as well as flip-flops 252 and 254. However, the clock SRCLK is delayed by t1 before reaching flip-flop 252 and by t2 before reaching flip-flop 254. In some embodiments, precharge circuits 202 and 204 can be programmed to allow time-borrowing between stages / segments. For example, the time for performing a comparison in one stage is delayed relative to the time for performing a comparison in another stage. For example, the time for performing a comparison in the second segment is delayed relative to the time for performing a comparison in the first segment, such as by delaying the time corresponding to one clock cycle. The delay amount can be set according to one or more factors, including, for example, the relative magnitudes of Vml-1 and Vml-2 and / or the number of comparisons to be performed in each stage. Delay units 242 and 106 are used to set the delay amount, such as setting delay amounts t1 and t2 respectively. Figure 2B This is a signal diagram illustrating the timing of the above comparison according to some embodiments. The clock CLK-1 controlling flip-flop 252 is delayed by t1 relative to the clock SRCLK. Clock CLK-2 controls the timing of flip-flop 254, and clock CLK-2 is delayed by t2 relative to the clock SRCLK. Therefore, the enable line (as shown) is... Figure 2A Online match (e.g., marked "enable") Figure 2A The clock (marked "MATCH") is activated before the circuit is activated. In some embodiments, the delay of the clock of the stage operating at a lower voltage (e.g., CLK-1) is less than the delay of the clock of the stage operating at a higher voltage (e.g., CLK-2). In this way, the circuit can operate at a higher speed.

[0068] In some embodiments, reducing the pre-charge voltage for matching line 212 relative to the pre-charge voltage for matching line 214 (or, in other words, making the pre-charge voltage for matching line 212 less than the pre-charge voltage for matching line 214) can reduce the power required to operate the first stage. For example, matching line 212 is pre-charged using voltage Vml-1, and matching line 214 is pre-charged using voltage Vml-2, wherein voltage Vml-1 is less than the pre-charge voltage Vml-2. An example of a pre-charge circuit for controlling the magnitude of the pre-charge voltage is described in detail with reference to Figures 3A, 4A, and 5A.

[0069] Figure 3A illustrates a storage device with three stages: the first stage (labeled "20-bit Stage-1") comprises 20 columns, the second stage (labeled "40-bit Stage-2") comprises 40 columns, and the third stage (labeled "60-bit Stage-3") comprises 60 columns. Of course, not all embodiments are limited to this particular implementation, and the present invention does not impose any limitations on this. The first stage includes a pre-charge circuit 302, the second stage includes a pre-charge circuit 304, and the third stage includes a pre-charge circuit 306. Each pre-charge circuit is configured to pre-charge a corresponding mating line.

[0070] In some embodiments, the pre-charge circuit 302 pre-charges the corresponding matching line with a first voltage, which is lower than the second voltage used to pre-charge any one or both subsequent matching lines, thereby reducing the power demand of the first stage (which is the most frequently operated stage).

[0071] Figure 3B , Figure 3C and Figure 3D The pre-charge circuits 302, 304, and 306 are shown in more detail. For example... Figure 3B As shown, the pre-charge circuit 302 is enabled by control signals VBIT and PRCHG. When both signals are asserted, transistor T... 11 The circuit is switched on. Transistor T 11 The voltage (V1) at the point is determined by transistor T. 12 Threshold voltage (V) th1 ) Determined. Specifically, V1 = V DD -V th1 When transistor T 11 When in the on-state, the matching line is precharged to V1 (or a portion thereof).

[0072] The precharge circuit 304 operates in a similar manner. When a match is found between the first segment of the input numerical sequence and the first segment of the row, the enable line enable-2 is activated. This activation, in turn, enables transistor T. 21 ,like Figure 3C As shown, this enables the pre-charge circuit 304. Transistor T 21 The voltage (V2) on the transistor T is determined by the transistor T. 22 Threshold voltage (V) th2 ) Determined. Specifically, V2 = V DD -V th2 When transistor T 21 When in the ON state, the matching line is precharged to V2 (or a portion thereof).

[0073] In these examples, transistor T 12 and T 22 It is implemented as an NMOS transistor. However, other types of transistors are also possible, for example, combined with... Figure 4B and Figure 4C As described.

[0074] Finally, when a match is found between the second segment of the input numerical sequence and the second segment of the row, enable line enable-3 is activated. This activation then turns transistor T on / off. 31 ,like Figure 3D As shown, this enables the pre-charge circuit 306. Transistor T 31 The voltage at point (V3) is equal to V DD When transistor T 31 When in the ON state, the matching line is precharged to V3 (or a portion thereof).

[0075] In some embodiments, the pre-charge voltages V1, V2, and V3 can be different from each other, thereby allowing / enabling control over the power required to operate each stage of the memory device. For example, in some embodiments, transistor T 12 The threshold voltage is greater than that of transistor T. 22 The threshold voltage. Therefore, the power required to operate the first stage is less than the power required to operate the second stage.

[0076] In addition, alternatively, in some embodiments, besides changing the pre-charge voltage across stages, the power of a stage can be controlled by changing the power supply voltage supplied to the input circuit across stages. Figure 3E , Figure 3F and Figure 3G Input circuits 332, 334, and 336 are shown in more detail. For example... Figure 3E As shown, the port of input circuit 332 receives a power supply voltage equal to VDD, where VDD is less than the power supply voltage of transistor T. S1 The threshold voltage. For example... Figure 3F As shown, the port of input circuit 334 receives a power supply voltage equal to VDD, where VDD is less than transistor T. S2 The threshold voltage. Finally, as... Figure 3G As shown, the port of input circuit 336 receives a power supply voltage equal to VDD. In some embodiments, transistor T S1 The threshold voltage is greater than that of transistor T. S2 The threshold voltage is such that the power supply voltage received by input circuit 332 is less than that received by input circuit 334. Therefore, input circuit 332 uses less power than input circuit 334, and input circuit 334 uses less power than input circuit 336.

[0077] In some embodiments, the matching line operating at a higher voltage can also operate at a higher clock rate, thereby increasing the operating speed of subsequent stages. For example, referring back to FIG3A, clock CLK-1 has a lower rate than clock CLK-2, and clock CLK-2 has a lower rate than clock CLK-3. Additionally or alternatively, input circuitry operating at a higher voltage can also operate at a higher clock rate, thus improving the operating speed of subsequent input circuitry. For example, referring again to FIG3A... Figures 3E to 3G The rate of clock SRCLK-1 is lower than the rate of clock SRCLK-2, and the rate of clock SRCLK-2 is lower than the rate of clock SRCLK-3.

[0078] Figure 3A illustrates one possible implementation of the pre-charge circuit. Figures 4A and 5A illustrate another possible implementation.

[0079] In the example of Figure 4A, for T in Figure 3A 12 and T 22 Use a PMOS transistor, instead of the one for T shown in Figure 3A. 12 and T 22 Use NMOS transistors. Figure 4B , Figure 4C and Figure 4D The pre-charge circuits 402, 404, and 406 of Figure 4A are described in more detail. For example... Figure 4B As shown, the pre-charge circuit 402 is enabled by control signals VBIT and PRCHG. When both signals are activated, transistor T... 11 The circuit is switched on. Transistor T 11 The voltage (V1) on the transistor T is determined by the transistor T. 12 Threshold voltage (V) th1 ) Determined. Specifically, V1 = V DD -V th1 When transistor T 11 When in the ON state, the matching line is pre-charged to V1 (or a portion thereof). In this example, transistor T 12 It is implemented using PMOS.

[0080] The precharge circuit 404 operates in a similar manner. When a match is found between the first segment of the input numerical sequence and the first segment of the row, the enable line enable-2 is activated. This activation then turns on transistor T. 21 ,like Figure 4C As shown, this enables the pre-charge circuit 404. Transistor T 21 The voltage (V2) on the transistor T is determined by the transistor T. 22 Threshold voltage (V) th2 ) Determined. Specifically, V2 = V DD -V th2 When transistor T 21 When in the ON state, the matching line is pre-charged to V2 (or a portion thereof). In this example, transistor T 22 It is also implemented using PMOS.

[0081] Finally, when a match is found between the second segment of the input numerical sequence and the second segment of the row, enable line enable-3 is activated. This activation then enables transistor T. 31 ,like Figure 4D As shown, this enables the pre-charge circuit 306. Transistor T 31 The voltage across (V3) is equal to V. DD When transistor T 31 When in the ON state, the matching line is precharged to V3 (or a portion thereof).

[0082] In some embodiments, transistor T 12 The threshold voltage is greater than that of transistor T. 22 The threshold voltage. Therefore, the power required to operate the first stage is less than the power required to operate the second stage.

[0083] In the example of Figure 5A, a single transistor is used instead of multiple transistors to allow charging of the mating line. Figure 5B , Figure 5C and Figure 5D The pre-charge circuits 502, 504, and 506 of Figure 5A are described in more detail. In this example, transistor T... 11 T 21 and T 31 Designed to be different from each other, thus enabling transistor T 11 The voltage drop across the terminals (and / or the charging rate of the matching line) differs from that of transistor T. 21 The voltage drop across the transistor (and / or the charging rate of the matching line), transistor T 21 The voltage drop across the terminals (and / or the charging rate of the matching line) differs from that of transistor T. 31 The voltage drop across the terminals (and / or the charging rate of the matching line). For example, transistors can have different sizes and / or threshold voltages. Therefore, Figures 5B to 5D The matching lines are pre-charged to different voltage levels. In some embodiments, transistor T can be switched on by inserting an inverter after the NAND gate. 11 T 21 T 31 It is made into an NMOS type. Specifically, the embodiments of the present invention do not impose any limitations on the transistors in each embodiment; they can be PMOS type, NMOS type, or other types of transistors, such as bipolar junction type.

[0084] In some embodiments, segment-wise comparisons are pipelined across different clock cycles, while in other embodiments, the comparisons are performed sequentially within the same clock cycle. According to some embodiments, examples of a serial architecture are shown in... Figure 6 As shown in the figure. This implementation is in some respects similar to Figure 2A The implementation is similar. However, with Figure 2A The implementation differs, with the stages placed in series. The output of detector 222, connected to match line 212, is connected to the input of detector 224. Detector 224 is also connected to match line 214 and provides a global line match (labeled "GLOBAL MATCH" in the figure) to trigger 254. Therefore, the comparisons performed at each stage are conducted serially, rather than as... Figure 2A The example is performed in parallel.

[0085] The use of ordinal terms such as "first," "second," and "third" in the claims to modify claim elements does not indicate any priority, precedence, or order of one claim element relative to another, or the chronological order of the actions of the method. These terms are merely used as markers to distinguish one claim element with the same name from another element with the same name (but using ordinal numbers). Furthermore, the use of VDD and V in this specification and drawings... DD Both represent power supply voltage.

[0086] Furthermore, for any plural and / or singular forms used herein, those skilled in the art can convert the plural to the singular and / or the singular to the plural depending on the appropriateness of the context and / or application. For clarity, all substitutions between singular and plural forms are explicitly defined herein.

[0087] Furthermore, those skilled in the art will understand that, generally, the terms used herein, particularly those in the appended claims, such as those used in the body of the claims, often have an "open-ended" meaning. For example, the word "comprising" should be understood as "comprising but not limited to," the word "having" should be understood as "having at least," and the word "including" should be understood as "including but not limited to," etc. Those skilled in the art will further understand that if an introductory claim intends to include a specific numerical value, then this intention will be explicitly stated in the claim; if it is not stated, then this intention does not exist. For example, the appended claims may contain introductory phrases such as "at least one" and "one or more" to introduce the claim enumeration. However, such a phrase should not be interpreted as limiting any particular claim containing such an introductory claim to only one embodiment of that introductory claim, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a," i.e., "a" should be interpreted as "at least one" or "one or more." Similarly, the use of definite articles to introduce a claim list is analogous. Furthermore, even if a specific numerical value is explicitly listed in an introductory claim list, those skilled in the art will recognize that such a list should be understood to include at least the listed value; for example, "two listed" without any other limitation implies at least two listed values, or two or more listed values. Furthermore, if phrases such as "at least one of A, B, and C" are used, those skilled in the art will generally understand that "a system having at least one of A, B, and C" includes, but is not limited to, a system having only A, a system having only B, a system having only C, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B, and C, etc. If phrases such as "at least one of A, B, or C" are used, those skilled in the art will understand that, for example, "a system having at least one of A, B, or C" includes, but is not limited to, a system having only A, a system having only B, a system having only C, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B, and C, etc. Those skilled in the art will further understand that almost all separators and / or phrases connecting two or more alternative terms appearing in the specification, claims, or drawings should be understood to account for all possibilities, i.e., including one of all terms, any one of two terms, or including two terms. For example, the phrase "A or B" should be understood to include the following possibilities: "A", "B", or "A and B".

[0088] While the invention has been described by way of example and according to preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various variations and similar structures (as will be apparent to those skilled in the art), such as combinations or substitutions of different features in different embodiments. Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such variations and similar structures.< / m> < / n>

Claims

1. A storage device, characterized in that, include: A storage unit with multiple rows, wherein a first row of the multiple rows includes a first segment and a second segment, the first segment including a first subset of the storage units of the first row, and the second segment including a second subset of the storage units of the first row; The first matching line is coupled to the storage unit of the first subset; The second matching line is coupled to the storage unit of the second subset; A first pre-charge circuit is configured to pre-charge the first matching line to a first pre-charge voltage; and The second pre-charge circuit is configured to pre-charge the second matching line to a second pre-charge voltage that is different from the first pre-charge voltage. The storage device further includes a first delay unit and a second delay unit. The first delay unit is configured to provide a first clock to the first segment based on a common input clock, and the second delay unit is configured to provide a second clock to the second segment based on the common input clock. The first delay unit and the second delay unit generate different delay amounts.

2. The storage device according to claim 1, characterized in that, The storage device also includes: A first clock circuit is configured to provide a clock at a first clock rate to the first segment; and, The second clock circuit is configured to provide a clock at a second clock rate to the second segment.

3. The storage device according to claim 1, characterized in that, The first row is configured to store a numerical sequence, the storage units of the first subset are configured to store a first part of the numerical sequence, and the storage units of the second subset are configured to store a second part of the numerical sequence; as well as, The storage device also includes a first input circuit and a second input circuit; The first input circuit is configured to provide a first portion of the input value sequence to the first segment of the first row, and the second input circuit is configured to provide a second portion of the input value sequence to the second segment of the first row.

4. The storage device according to claim 3, characterized in that, The second segment of the first line is configured to compare the second part of the input numerical sequence with the second part of the numerical sequence only if the first part of the input numerical sequence matches the first part of the numerical sequence.

5. The storage device according to claim 3, characterized in that, The storage device further includes a first power supply circuit and a second power supply circuit, the first power supply circuit being configured to provide a first power supply voltage to the first input circuit, and the second power supply circuit being configured to provide a second power supply voltage to the second input circuit that is different from the first power supply voltage.

6. The storage device according to claim 5, characterized in that, The storage device further includes a first clock circuit and a second clock circuit, the first clock circuit being configured to provide a clock at a first clock rate to the first input circuit, and the second clock circuit being configured to provide a clock at a second clock rate to the second input circuit, the second clock rate being different from the first clock rate.

7. The storage device according to claim 6, characterized in that, The first power supply voltage is less than the second power supply voltage, and the first clock rate is less than the second clock rate.

8. The storage device according to claim 1, characterized in that, The storage device is a content-addressable memory (CAM), and each of the plurality of rows further includes a plurality of comparators, each comparator being coupled to a corresponding storage cell.

9. The storage device according to claim 1, characterized in that, The first pre-charge circuit includes a first transistor, and the second pre-charge circuit includes a second transistor; wherein the first transistor and the second transistor have different dimensions.

10. The storage device according to claim 1, characterized in that, The first pre-charge circuit includes a first transistor, and the second pre-charge circuit includes a second transistor; wherein the first transistor and the second transistor have different threshold voltages.

11. A storage device, characterized in that, include: A plurality of rows of storage units, wherein a first row of the plurality of rows includes a first segment and a second segment, the first segment including a first subset of the storage units of the first row, the second segment including a second subset of the storage units of the first row, wherein the storage units of the first subset are configured to store a first part of a numerical sequence, and the storage units of the second subset are configured to store a second part of the numerical sequence. A first input circuit is configured to provide a first portion of an input numerical sequence to the first segment of the first row; The second input circuit is configured to provide a second portion of the input value sequence to the second segment of the first row; A first power supply circuit is configured to provide a first power supply voltage to the first input circuit; and The second power supply circuit is configured to provide the second input circuit with a second power supply voltage that is different from the first power supply voltage. The storage device further includes a first delay unit and a second delay unit. The first delay unit is configured to provide a first clock to the first segment based on a common input clock, and the second delay unit is configured to provide a second clock to the second segment based on the common input clock. The first delay unit and the second delay unit generate different delay amounts.

12. The storage device according to claim 11, characterized in that, The first segment of the first line includes a plurality of first comparators configured to compare the first portion of the input numerical sequence with the first portion of the numerical sequence; as well as, The second segment of the first line includes multiple second comparators configured to compare the second part of the input numerical sequence with the second part of the numerical sequence.

13. The storage device according to claim 12, characterized in that, The plurality of second comparators are configured to compare the second part of the input numerical sequence with the second part of the numerical sequence only if the first part of the input numerical sequence matches the first part of the numerical sequence.

14. The storage device according to claim 11, characterized in that, The storage device further includes a first clock circuit and a second clock circuit, the first clock circuit being configured to provide a clock at a first clock rate to the first input circuit, and the second clock circuit being configured to provide a clock at a second clock rate to the second input circuit, the second clock rate being different from the first clock rate.

15. The storage device according to claim 14, characterized in that, The first power supply voltage is less than the second power supply voltage, and the first clock rate is less than the second clock rate.

16. A method for controlling a storage device, wherein, The storage device includes multiple rows of storage cells, a first row of which includes a first segment and a second segment, the first segment including a first subset of the storage cells in the first row, and the second segment including a second subset of the storage cells in the first row. The method includes: The first matching line is precharged to a first precharge voltage, wherein the first matching line is coupled to the memory cells of the first subset; The second matching line is precharged to a second precharge voltage different from the first precharge voltage, wherein the second matching line is coupled to the memory cells of the second subset; The first part of the input numerical sequence is provided to the first segment of the first row through the first input circuit; and, The second part of the input value sequence is provided to the second segment of the first row through the second input circuit; The storage device further includes a first delay unit and a second delay unit. The first delay unit is configured to provide a first clock to the first segment based on a common input clock, and the second delay unit is configured to provide a second clock to the second segment based on the common input clock. The first delay unit and the second delay unit generate different delay amounts.

17. The method according to claim 16, characterized in that, The method further includes storing a first portion of the numerical sequence in the storage units of the first subset, storing a second portion of the numerical sequence in the storage units of the second subset, and: The second part of the input numerical sequence is compared with the second part of the numerical sequence only if the first part of the input numerical sequence matches the first part of the numerical sequence.

18. The method according to claim 16, characterized in that, The method also includes: Provide a first power supply voltage to the first input circuit; and, A second power supply voltage, different from the first power supply voltage, is provided to the second input circuit.

Images