Memory device with repair matching mechanism and operation method thereof

Abstract

The present application relates to a memory device with a repair matching mechanism and an operation method thereof. A memory device includes a fuse and a latch for storing a repair address and a plane locator. A matching circuit generates a repair enable flag based on the plane locator, wherein the repair state represents an enable, disable and / or unused setting of the repair address with respect to implementing a global replacement for the repair address with a redundant cell on a repair plane.

Description

Technical Field

[0001] The disclosed embodiments relate to devices, and in particular to semiconductor memory devices having a memory repair matching mechanism and methods of operating the same. Background Art

[0002] A memory device may include semiconductor circuits configured to utilize electrical energy to store and access information. Some examples of memory devices include volatile memory devices such as dynamic random access memory (DRAM), nonvolatile memory devices, or a combination device.

[0003] Memory devices often include defects that prevent power / information from being properly stored and / or accessed. As such, some memory devices include redundant memory circuits (i.e., redundant memory cells) that are configured to replace defective memory circuits. Because the number and location of defects are unpredictable, memory devices are often designed for worst-case scenarios. In other words, memory devices often include more redundant memory circuits than actual defects, thereby leaving a number of redundant memory circuits unused. Summary of the invention

[0004] In one aspect, the present invention is directed to an apparatus comprising: a memory array, the memory array including: a plurality of memory planes, each memory plane having a plurality of memory cells, and one or more repair planes, each repair plane having a plurality of redundant cells configured to replace a set of defective memory cells in one of the memory planes; a set of address latches configured to latch a repair address corresponding to the set of defective memory cells; a set of locator latches configured to latch a plane locator identifying the one of the memory planes for which a global repair is targeted; and a matching circuit coupled to the set of address latches and the set of locator latches, the matching circuit configured to: generate an address comparison result based on comparing a repair address with an address for an operation; and generate a repair enable flag based on the plane locator, wherein a repair state represents an enabled, disabled and / or unused setting for the global repair; wherein the address comparison result and the repair enable flag indicate whether to access a redundant cell in one of the repair planes in place of a memory cell indicated by the address for the operation.

[0005] In another aspect, the present invention is directed to a method for operating a memory device, the memory device comprising a plurality of memory cells and a plurality of redundant cells configured to replace one or more defective memory cells among the plurality of memory cells, the method comprising: obtaining a repair address representing a location of the one or more defective memory cells; obtaining a plane locator representing a plane within the memory array that includes the one or more defective memory cells, wherein the plurality of memory cells are grouped into planes and the redundant cells are grouped into one or more repair planes; determining an enable state for the repair address based on the plane locator; and performing a global repair according to the enable state.

[0006] In another aspect, the present invention is directed to a method of manufacturing a memory device, the method comprising: providing a memory array, the memory array comprising: (1) memory planes, each having a plurality of memory cells, and (2) one or more repair planes, each comprising a plurality of redundant cells configured to replace a group of defective memory cells in the plurality of memory cells; providing latches comprising a set of address latches and a set of locator latches for each repair, wherein: the set of address latches are configured to store a repair address representing a location of the group of defective memory cells within a segment, and the set of locator latches are configured to store a plane locator representing a plane targeted for a global replacement; and connecting a matching circuit to the latches, wherein the matching circuit is configured to: determine whether the repair address matches an address for an operation, and generate a repair enable flag based on the plane locator, wherein a repair state represents an enabled, disabled, and / or unused setting for the global replacement. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of an example memory device in accordance with an embodiment of the present technology.

[0008] Figure 2 is a partial block diagram of an example memory device including a set of repairable memory cells.

[0009] Figure 3A According to an embodiment of the present invention Figure 2 A block diagram of a portion of a memory device.

[0010] Figure 3B According to an embodiment of the present invention Figure 2 A block diagram of a portion of a memory device.

[0011] Figure 4A is a block diagram of a first example matching circuit according to an embodiment of the present technology.

[0012] Figure 4Bis a first example decoding mechanism according to an embodiment of the present technology.

[0013] Figure 5A is a block diagram of a second example matching circuit according to an embodiment of the present technology.

[0014] Figure 5B is a second example decoding mechanism according to an embodiment of the present technology.

[0015] Figure 6 is a flowchart illustrating an example method of operating a device according to an embodiment of the present technology.

[0016] Figure 7 is a schematic diagram of a system including an apparatus according to an embodiment of the present technology. DETAILED DESCRIPTION

[0017] As described in more detail below, the technology disclosed herein relates to an apparatus (e.g., a memory device, a memory system), a system having one or more memory devices, and a method for repairing memory cells therein. The apparatus includes a matching circuit that facilitates repair using redundant memory cells. For example, the matching circuit can implement a global column repair scheme for an apparatus having a number of planes (e.g., column planes) that is not a power of 2 (e.g., 2, 4, 8, 16, etc.), such as due to error correction code (ECC) planes for holographic random access memory (HRAM), double data rate 5 (DDR5) memory, and / or low power DDR4 (LPDDR4) memory.

[0018] As an illustrative example, for example, for a DDR5 device, each global column repair may repair 1 of 17 column planes (CP), which may require five fused CP address bits. Five bits result in 32 decodes, even though only 17 decodes are required. As described in detail below, the device and the matching circuit therein may be configured to utilize the remaining CP decodings to represent unused / disabled redundant resources (e.g., redundant columns). Therefore, the device may implement the repair with fewer circuit components (e.g., enabling fuses, fuse latches, and / or XOR logic) at each repair. Compared to previous methods, the matching circuit may be implemented with one less fuse and one less latch for each column repair segment on the die. Compared to some methods, the matching circuit may be implemented with four or fewer additional logic gates for a repair group. However, the reduction in the number of components (e.g., fuses and / or latches) may be greater than the number of additional logic gates, which results in a reduction in the overall number of components compared to conventional devices. For example, the matching circuits may be implemented using less than 100 additional logic circuits per die compared to conventional devices while reducing the number of required fuses / latches by 2000 to 2500. Thus, the apparatus described below may provide die size savings while providing the necessary features to recover from any blown repair to a disabled state, such as to undo a repair when a redundant resource is defective or becomes defective.

[0019] Figure 1 1 is a block diagram of an example memory device 100 (e.g., a semiconductor die assembly, including a three-dimensional integration (3DI) device or a die stack package) according to an embodiment of the present technology. For example, the memory device 100 may include a DRAM or a portion thereof including one or more dies / chips.

[0020] The memory device 100 may include an array of memory cells, such as the memory array 150. The memory array 150 may include a plurality of banks (e.g., banks 0 to 15), and each bank may include a plurality of word lines (WL), a plurality of bit lines (BL), and a plurality of memory cells arranged at the intersections of the word lines and the bit lines. The memory cells may include any of a number of different memory media types, including capacitive, magnetoresistive, ferroelectric, phase change, and the like. The selection of the word lines WL may be performed by a row decoder 140, and the selection of the bit lines BL may be performed by a column decoder 145. A sense amplifier (SAMP) may be provided for the corresponding bit lines BL and may be connected to at least one corresponding local I / O line pair (LIOT / B), which in turn may be coupled to at least one corresponding main I / O line pair (MIOT / B) via a transfer gate (TG) that may be used as a switch. The memory array 150 may also include plate lines and corresponding circuitry for managing their operation.

[0021] The memory device 100 may employ a plurality of external terminals, including command and address terminals coupled to a command bus and an address bus, respectively, to receive a command signal (CMD) and an address signal (ADDR). The memory device 100 may further include a chip select terminal for receiving a chip select signal (CS), a clock terminal for receiving clock signals CK and CKF, a data clock terminal for receiving data clock signals WCK and WCKF, data terminals DQ, RDQS, DBI, and DMI, power supply terminals VDD, VSS, and VDDQ.

[0022] The command terminal and address terminal can be provided with address signals and bank address signals from the outside ( Figure 1 140). The address signal and the bank address signal supplied to the address terminal may be transferred to the address decoder 110 via the command / address input circuit 105. The address decoder 110 may receive the address signal and supply a decoded row address signal (XADD) to the row decoder 140 and a decoded column address signal (YADD) to the column decoder 145. The address decoder 110 may also receive the bank address signal and supply the bank address signal to both the row decoder 140 and the column decoder 145.

[0023] The command and address terminals may be provided with a command signal (CMD), an address signal (ADDR), and a chip select signal (CS) from a memory controller and / or a nefarious chipset. The command signal may represent various memory commands from the memory controller (e.g., including access commands that may include a read command and a write command). The chip select signal may be used to select the memory device 100 in response to the command and address provided to the command and address terminals. When a valid chip select signal is provided to the memory device 100, the command and address may be decoded and a memory operation may be performed. The command signal may be provided to the command decoder 115 as an internal command signal ICMD via the command / address input circuit 105. The command decoder 115 may include a circuit for decoding the internal command signal ICMD to generate various internal signals and commands for performing memory operations (e.g., a row command signal for selecting a word line and a column command signal for selecting a bit line). The command decoder 115 may further include one or more registers for tracking various counts or values ​​(eg, a count of refresh commands received by the memory device 100 or self-refresh operations performed by the memory device 100 ).

[0024] Read data may be read from a memory cell specified by a row address (e.g., an address with a valid command) and a column address (e.g., an address with a read) in the memory array 150. The read command may be received by the command decoder 115, which may provide an internal command to the input / output circuit 160, so that the read data may be output from the data terminals DQ, RDQS, DBI, and DMI via the read / write amplifier 155 and the input / output circuit 160 according to the RDQS clock signal. The read data may be output from the data terminals DQ, RDQS, DBI, and DMI in the memory device 100, for example, in the mode register ( Figure 1 The read data is provided at a time defined by the read delay information RL programmed in the memory device 100 (not shown). The read delay information RL may be defined in terms of clock cycles of the CK clock signal. For example, when providing the associated read data, after receiving a read command by the memory device 100, the read delay information RL may be a number of clock cycles of the CK signal.

[0025] The write data may be supplied to the data terminals DQ, DBI, and DMI according to the WCK and WCKF clock signals. The write command may be received by the command decoder 115, which may provide an internal command to the input / output circuit 160, so that the write data may be received by the data receiver in the input / output circuit 160 and supplied to the memory array 150 via the input / output circuit 160 and the read / write amplifier 155. The write data may be written into the memory cell specified by the row address and the column address. The write data may be provided to the data terminal at a time defined by the write delay WL information. The write delay WL information may be programmed in the memory device 100, for example, in the mode register. The write delay WL information may be defined according to the clock cycle of the CK clock signal. For example, when receiving the associated write data, after the write command is received by the memory device 100, the write delay information WL may be several clock cycles of the CK signal.

[0026] The power supply terminal may be provided with power supply potentials VDD and VSS. These power supply potentials VDD and VSS may be supplied to the internal voltage generator circuit 170. The internal voltage generator circuit 170 may generate various internal potentials VPP, VOD, VARY, VPERI, etc. based on the power supply potentials VDD and VSS. The internal potential VPP may be used in the row decoder 140, the internal potentials VOD and VARY may be used in the sense amplifiers included in the memory array 150, and the internal potential VPERI may be used in many other circuit blocks.

[0027] The power supply terminal may also be provided with a power supply potential VDDQ. The power supply potential VDDQ may be supplied to the input / output circuit 160 together with the power supply potential VSS. In an embodiment of the present technology, the power supply potential VDDQ may be the same potential as the power supply potential VDD. In another embodiment of the present technology, the power supply potential VDDQ may be a different potential from the power supply potential VDD. However, a dedicated power supply potential VDDQ may be used for the input / output circuit 160 so that the power supply noise generated by the input / output circuit 160 is not propagated to other circuit blocks.

[0028] The clock terminal and the data clock terminal may be provided with an external clock signal and a complementary external clock signal. The external clock signals CK, CKF, WCK, WCKF may be supplied to the clock input circuit 120. The CK and CKF signals may be complementary, and the WCK and WCKF signals may also be complementary. The complementary clock signals may have relative clock levels and simultaneously switch between relative clock levels. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. In addition, when the clock signal switches from a low clock level to a high clock level, the complementary clock signal switches from a high clock level to a low clock level, and when the clock signal switches from a high clock level to a low clock level, the complementary clock signal switches from a low clock level to a high clock level.

[0029] The input buffer included in the clock input circuit 120 may receive an external clock signal. For example, when enabled by the clock / enable signal from the command decoder 115, the input buffer may receive the clock / enable signal. The clock input circuit 120 may receive the external clock signal to generate an internal clock signal ICLK. The internal clock signal ICLK may be supplied to the internal clock circuit 130. The internal clock circuit 130 may generate an internal clock signal ICLK based on the received internal clock signal ICLK and the clock enable ( Figure 1 The internal clock circuit 130 may include a clock path (not shown) that receives the internal clock signal ICLK and provides various clock signals to the command decoder 115. Figure 1100). The internal clock circuit 130 may further provide an input / output (IO) clock signal. The IO clock signal may be supplied to the input / output circuit 160 and may be used as a timing signal to determine the output timing of read data and / or the input timing of write data. The IO clock signal may be provided at multiple clock frequencies so that data may be output from or input to the memory device 100 at different data rates. When a higher memory speed is desired, a higher clock frequency may be desired. When lower power consumption is desired, a lower clock frequency may be desired. The internal clock signal ICLK may also be supplied to the timing generator 135 and various internal clock signals may be generated accordingly.

[0030] The memory device 100 may be connected to any of a number of electronic devices or components thereof that are capable of using the memory for temporary or permanent storage of information. For example, the host device of the memory device 100 may be a computing device, such as a desktop or portable computer, a server, a handheld device (e.g., a mobile phone, a tablet computer, a digital reader, a digital media player), or some component thereof (e.g., a central processing unit, a co-processor, a dedicated memory controller, etc.). The host device may be a networking device (e.g., a switch, a router, etc.) or a recorder, a vehicle, an appliance, a toy, or any of a number of other products of digital images, audio, and / or video. In one embodiment, the host device may be directly connected to the memory device 100; although in other embodiments, the host device may be indirectly connected to the memory device (e.g., via a networking connection or through an intermediate device).

[0031] The memory device 100 may include a repair circuit 111, which may be coupled to one or more address decoders, such as the address decoder 110, the row decoder 140, and / or the column decoder 145. The repair circuit 111 may be configured to repair defects in memory cells. For example, the repair circuit 111 may replace defective memory cells with redundant memory cells in the memory array 150. As described in more detail below, the repair circuit 111 may include fuses and local fuse latches configured to store location information (e.g., addresses and / or affected domain identifiers) associated with defective memory cells. The repair circuit 111 may further include a matching circuit configured to implement a repair (e.g., a global column repair). In some embodiments, the repair circuit 111 may utilize an addressing scheme to specify and detect global column repair, enable / disable, and / or other repair conditions. Therefore, the repair circuit 111 may reduce fuses and / or latches (e.g., fuses / latches associated with an enable bit), thereby reducing resources and / or device footprint associated with repairs, fuses, latches, etc.

[0032] Memory device 100 may be configured to implement global repair and / or regional repair. To illustrate regional repair, Figure 2 2 is a partial block diagram of a memory device 200 including a group of repairable memory cells. The memory device 200 includes repair circuitry coupled to and / or integral with the memory cells 202 and configured to repair / replace one or more defective cells 204 within a corresponding group of memory cells 202 (e.g., within a portion of a memory array, such as within the same plane). The memory cells 202 include repair or redundant cells designated to replace defective cells 204 in the same portion of the memory array. In other words, the repair cells are configured as spare memory cells that are not utilized in normal operation unless they are used to replace defective cells 204. The repair cells may be arranged in rows and columns (e.g., redundant rows 212 and redundant columns 214) similarly to other memory cells 202 in the same portion.

[0033] In replacing defective cells 204, memory device 200 may implement repairs for rows, columns, and / or sectors therein. For row repair, memory device 200 may deploy and utilize redundant rows 212 to replace rows including defective cells 204. Figure 2 As illustrated in , memory device 200 may replace row R0 containing defective cell 204 with redundant row RR0. For column repair, memory device 200 may deploy and utilize redundant column 214 to replace the column including defective cell 204. Figure 2 , memory device 200 may replace column C0 containing defective cell 204 therein with redundant column RC1.

[0034] The repair circuit includes fuse blocks configured to facilitate memory cell replacement. Each of the blocks includes a set of fuse latches directly coupled (i.e., with a one-to-one dedicated and fixed electrical and functional connection) to a redundant row or redundant column. The memory device 200 includes fuses or non-volatile memory (not shown) located in a fuse array on the die. The information stored in the fuse array is broadcast and loaded into the fuse blocks in each bank at initialization.

[0035] As in Figure 2 , the fuse blocks include row fuse blocks 222 that are each directly coupled to one of the redundant rows 212, and column fuse blocks 224 that are each directly coupled to each of the redundant columns 214. Each fuse block is configured to store the address of the row / column that includes the defective cell 204. For example, when a redundant column is used to replace a defective column, the fuse block for the corresponding redundant column can be programmed (via, for example, blowing / setting fuse latches and / or associated fuses) to store the address of the defective column, effectively removing the defective column from operation of the memory device 200. Subsequently, the redundant column is used to store and provide access to data in place of the replaced defective column.

[0036] Figure 3A According to an embodiment of the present invention Figure 1 1 is a block diagram of a portion of a memory device 100. For example, Figure 3A Graphical instructions Figure 1 The repair circuit 111, the position decoder (for example, Figure 1 The repair circuit 111 may include a local fuse latch region 302 coupled to a matching circuit 304. The local fuse latch region 302 may include fuse latches and / or fuses configured to store / latch location information (e.g., addresses) associated with a repair. As described in detail below, the repair circuit 111 may be configured to effectively assign fuses and / or latches to repairs for different portions of the memory array 150. The matching circuit 304 may include circuitry configured to select a repair location / address corresponding to a current read / write operation and compare an incoming address (e.g., a read or write address from a host) with the latched address for any match. In some embodiments, the matching circuit 304 may include a selection circuit, a comparator circuit for each redundant memory grouping (e.g., for each redundant column or row). The output of comparator circuit 304 may be used by a location decoder to access a target location within memory plane 310 (eg, a portion of memory array 150, such as a region within one of the arrays).

[0037] The memory array 150 may include memory cells arranged in one or more planes. Each plane may include memory cells organized in a cross-point architecture so that the memory cells may be arranged in a matrix of rows and columns as described above. The memory device 100 may include multiple vertically stacked layers of memory cells. In other words, the layers of memory cells organized according to the cross-point architecture may be formed at different heights from each other. Vertically stacked layers may be used to form a plane. For example, a column plane may include a set of columns arranged along a plane or another structural connection across different heights / dimensions.

[0038] In some embodiments, the memory device 100 may include one or more repair planes 315 (eg, column planes) that include dedicated memory cells for repairing defective memory cells in the memory planes 310 (eg, Figure 2In other words, rather than having memory cells and repair cells in the same plane, the memory device 100 may include redundant memory 314 organized into one or more dedicated planes to replace memory cells in other planes. Thus, repair may be a global repair using repair cells in one plane to replace defective cells in another plane. For example, the memory device 100 may implement global column repair by storing information to or accessing information from the repair plane rather than a different column plane. Repair may also use the repair plane 315 instead of or in addition to the repair elements within each of the planes.

[0039] As an illustrative example, information stored in the fuse (e.g., an address associated with the repair) may be loaded or latched into a corresponding latch in the local fuse latch region 302. Thus, the local fuse latch region 302 may store repair addresses 322 and plane locators 323. Each of the repair addresses 322 may include an address of an original memory cell, such as a column that includes one or more defective cells. Each of the plane locators 323 may include an address of a memory plane (e.g., a column plane) that includes one or more defective cells. The memory device 100 may use matching circuits 304 to exchange memory input / output (MIO) from the repair plane 315 with the repaired main array plane (e.g., defective column plane) in the data path.

[0040] The selection circuit 304 may select one of the repair addresses 322 associated with the memory cells valid for the current read / write operation (repairing the corresponding redundant memory on one of the planes 315). Using column repair as an illustrative example, the repair address 322 may represent a memory column that includes one or more defective cells. The matching circuit 304 may use the repair address to determine when a read or write operation is directed to a defective memory column. A portion of the matching circuit 304 may compare the read / write column address (RD / WR CA) to the address / locator stored in the latch and generate a flag when the RD / WR CA matches the address of the defective column represented by the corresponding repair address 322 and the plane locator 323. The decoder may use the output of the matching circuit 304 to access a redundant column assigned to replace the defective column for reading or writing instead of the defective column.

[0041] As a graphic illustration of global repair, Figure 3B According to an embodiment of the present invention Figure 1 1. A block diagram of a portion of a memory device 100 of FIG. 1. In some embodiments, for example, the memory array 150 may include 16 CPs (e.g., CP0 to CP15) and an ECC CP. Global column repair may be performed by moving column repair to a separate redundant plane (e.g., Figure 3Aexample of a repair plane 315).

[0042] Figure 3B Graphic instructions for use Figure 3A 310 for repair of the memory plane 310. For a global column repair scheme, the columns (e.g., redundant memory 314) may be located in a separate column plane 362 (e.g., an instance of the repair plane 315) and separate from the main array column planes (e.g., memory plane 310). In some embodiments (e.g., for DDR4), the global column repair scheme may include a redundant column plane 362 as a separate sub-array corresponding to a separate column decoder (RYDEC) and parallel to other main array column planes. Figure 3B In the example illustrated in , a defective column plane 352 or a portion thereof (eg, a column) may be replaced by a separate redundant column plane 354 or a corresponding portion thereof. In some embodiments, such repair may be performed once per x8 region.

[0043] To implement global column repair, the local fuse latch area 302 and / or matching circuit 304 may indicate that the column plane is targeted for repair. Therefore, additional fuses / latches may be required in the local fuse latch area 302 to identify the target column plane. The matching routing layer 364 (GRCS matching routing layer) may include circuits that connect the output to the target resource (e.g., redundant column plane). A combination of decoders and / or dedicated circuit layers 366 (GRCSDPTIER) may exchange memory input / output (MIO) from the repair plane 315 with the repaired main array plane (e.g., defective column plane) in the data path.

[0044] The memory array 150 may also include planes (e.g., column planes) associated with error correction codes (ECC). Thus, the local fuse latch area 302 may include fuses / latches associated with the ECC planes. For example, the memory array 150 may be configured to repair the ECC planes with redundant memory cells. Thus, the local fuse latch area 302 may also include a number of fuses / latches corresponding to CP addresses / decodes for accessing the ECC planes in addition to other repair planes. For example, each global column repair may repair 1 of 17 CPs (e.g., 16 column planes and one ECC plane), which may require five fused CP address bits.

[0045] Figure 4A is a first example matching circuit 400 (first circuit 400) according to an embodiment of the present technology (eg, Figure 3A 304 is a block diagram of an example of a matching circuit 304. Figure 3A The first circuit 400 may be implemented when the local fuse latch region 302 of EMBODIMENT 1 includes an enable fuse / latch.

[0046] Figure 4B 4 is a first example decoding mechanism 450 (first mechanism 450) according to an embodiment of the present technology. The first mechanism 450 can be used with the first circuit 400. The first mechanism 450 can represent the decoding required to identify the target column plane. The first mechanism 450 can include decoded values ​​mapped to CP identifiers. For example, a decoded value of '0' with a valid enable (e.g., a bit value of '1') can indicate repair of CP0. In addition, a decoded value of '1' with a valid enable can indicate repair of CP1. The first mechanism 450 can further include decoded values ​​for repairing ECC planes.

[0047] Return to reference Figure 4A , the first circuit 400 may be configured to detect a repair status for a column plane according to a first mechanism 450. The first circuit 400 may include an address comparison circuit 402, an access enable circuit 404, and / or a repair detection circuit 406.

[0048] The address comparison circuit 402 may be configured to compare the column address (CAL<9:4>) with the incoming fuse value (EFnF<9:4>). The address comparison circuit 402 may be configured to detect a match between the column address and the incoming fuse value. For example, the address comparison circuit 402 may include XOR circuits each configured to receive and compare a unique set of corresponding bits in the column address and the incoming fuse value. The address comparison circuit 402 may generate an address comparison result indicating whether the column address matches the incoming fuse value. For example, the address comparison result may include a plurality of bits (Cn<2:0>) each indicating a bit-by-bit match status between the column address and the incoming fuse value.

[0049] The enable access circuit 404 may be configured to provide the state / value of the enable fuse / latch to the repair detection circuit 406. The enable access circuit 404 may include a buffer for controlling the timing or output voltage level representing the value represented by the enable fuse / latch.

[0050] The repair detection circuit 406 may be configured to determine whether an address (e.g., a read / write column address) and an enable setting indicate a repair. For example, the repair detection circuit 406 may generate a valid output (e.g., a column match signal (ColMatch)) when the enable is valid and when the column address matches the incoming fuse value. The repair detection circuit 406 may detect a repair condition and generate a valid output when the read / write column address matches the value stored in the fuse latch and when the enable is valid. In some embodiments, the repair detection circuit 406 may include a set of NAND, NOR, inverter, and / or XOR devices that generate a column match signal based on the enable value and the address comparison result. For example, the repair detection circuit 406 may include a logic device configured to generate a valid value (e.g., '1') when the enable is valid and when the address comparison result indicates a match between the column address and the incoming fuse value.

[0051] For global repair, CP matching can be done by targeting Figure 4A and 4B 406. In other words, the first circuit 400 can be configured to ignore or not analyze the CP address. Thus, the memory device 100 can implement a global repair (e.g., a global column repair) based on the CP match and the valid output from the repair detection circuit 406. Thus, the memory device 100 can access the memory based on the valid output from the repair detection circuit 406. Figure 3A One or more redundant memory cells in the repair plane 315 other than the memory cells indicated by the read / write column address.

[0052] As in Figure 4B As illustrated in FIG. 4 , the first mechanism 450 may include a set of decodings (in Figure 4B For example, five bits (CP<4:0>) can be used to represent 17 CPs, leaving 15 undefined decodings.

[0053] In some embodiments, Figure 1 The memory device 100 may use alternative matching circuits and decoding mechanisms that use undefined decoding for other information. For example, the memory device 100 may use alternative matching circuits and decoding mechanisms to indicate enable / disable for repair rather than dedicated enable fuses / latches. As described in detail below, Figure 3AThe plane locator 323 may include one or more predetermined bit patterns representing a repair state (e.g., an unused repair state and / or a disabled repair state). The memory device 100 may further use an alternative matching circuit and decoding mechanism to use one dedicated decode / address and not merge or combine (via, for example, XOR) multiple decode values ​​or address indications for repair of a particular plane. Thus, the memory device 100 may provide improved / reduced resources and footprint associated with each die (via, for example, elimination of dedicated enable fuses / latches) without sacrificing repair flexibility associated with reserved address / decode combinations.

[0054] To illustrate these schemes, Figure 5A is a second example matching circuit 500 (second circuit 500) according to an embodiment of the present technology (eg, Figure 3A 2 is a block diagram of an example matching circuit 304. Figure 5B is a second example decoding mechanism 550 (second mechanism 550) according to an embodiment of the present technology. The second circuit 500 can be configured to detect repair status / information according to a decoding mechanism (such as second mechanism 550) that utilizes previously unused decoding.

[0055] The second mechanism 550 may represent the decoding required to identify the target column plane without using a dedicated enable bit (e.g., the value of the plane locator 323 mapped to the CP identifier). The second mechanism 550 may include a pattern for mapping the plane locator 323 to the CP identifier. For example, the second mechanism 550 may use a sequence / pattern of '0' values ​​to indicate that repair is not used, and a sequence / pattern of '1' values ​​to indicate that repair is disabled. Thus, the decoding corresponding to the column plane may be assigned a unique value that excludes a sequence / pattern of 0s (e.g., all 0s) and excludes a sequence / pattern of 1s (e.g., all 1s). As an illustrative example, with Figure 4B Compared to the first mechanism 450, the second mechanism 550 can shift all decodings for CP fuses. In addition, the second mechanism 550 can reserve a decoded value for the plane locator 323 including two '0' values ​​to indicate that the column plane is not used. By retaining a '0' value to indicate an unused repair and a '1' value to indicate a disabled state, the second mechanism 550 can retain a path to reach the disabled state. In addition, the second mechanism 550 can be configured to reduce or minimize '1' values ​​overall. In addition, the second mechanism 550 can use a bit pattern and indicate an unused / disabled state without a dedicated enable bit. Therefore, the second mechanism 550 can be non-incremental. In other words, the decoded value may not be directly matched to the CP identifier like the first mechanism 450.

[0056] Return to reference Figure 5A, the second circuit 500 may be configured to detect the repair state for the column plane according to a decoding scheme that utilizes a decoding bit (i.e., without a dedicated enable bit) to indicate a mode of disable / enable along with a repair assignment. For example, the second circuit 500 may be configured to detect the repair state for the column plane according to a second mechanism 550. The second circuit 500 may include an address comparison circuit 502, a state detection circuit (e.g., an unused detection circuit 504 and / or a disabled detection circuit 505), and / or a repair detection circuit 506. The second circuit 500 may include a state detection circuit instead of Figure 4A The enable access circuit 404 is not used because the second mechanism 550 does not use or include an enable bit. As described in detail below, the unused detection circuit 504 and the disabled detection circuit 505 can be configured to analyze the plane locator 323 to determine the repair state information.

[0057] The address comparison circuit 502 may be configured to compare the column address (CAL<9:4>) with the incoming fuse value (EFnF<9:4>). The address comparison circuit 502 may be similar to Figure 4A For example, the address comparison circuit 502 may include an XOR circuit configured to detect a match between a column address and an incoming fuse value and generate an address comparison result (Cn<2:0>) accordingly.

[0058] The state detection circuit may be configured to generate a repair state based on the plane locator 323. The repair state may indicate whether the plane locator 323 indicates when the repair is unused / disabled or otherwise indicates that the memory plane is subject to global repair. The repair state may include an unused state flag from the unused detection circuit 504, and / or a disabled state flag from the disabled detection circuit 505.

[0059] The unused detection circuit 504 may be configured to determine whether the plane locator 323 indicates an unused repair state. The unused detection circuit 504 may be configured to generate an unused state flag based on the plane locator. For example, the unused detection circuit 504 may be configured to detect a reserved pattern of '0' values ​​representing an unused repair state (e.g., an unused repair pattern) and generate an unused state flag accordingly. As shown in Figure 4A and 4B As illustrated in FIG. 5 , the unused detection circuit 504 may be configured (via, for example, a NOR device) to detect <4> and CP <3> When the plane locator 323 includes the unused repair pattern, the unused detection circuit 504 may activate the unused status flag (by, for example, generating the unused status flag to have an active value / state, such as logic '1').

[0060] The disabled detection circuit 505 may be configured to determine whether the plane locator 323 indicates a disabled repair state. The disabled detection circuit 505 may be configured to generate a disabled state flag based on the plane locator. For example, the disabled detection circuit 505 may be configured to detect a reserved pattern of '1' values ​​representing a disabled repair state (e.g., a disabled repair mode) and generate a disabled state flag accordingly.

[0061] In some embodiments, the decoding mechanism may reserve one or more patterns for a set of bits to indicate a disabled state. The set of bits used to indicate a disabled state may at least partially overlap with bits used to indicate an unused state detected by unused detection circuit 504. Figure 4A and 4B As illustrated in FIG. 5 , the disabled detection circuit 505 may be configured (via, for example, a NAND device, an AND device, and / or an inverter) to detect the disabled detection circuit 505 for CP <4> ,CP <3> and CP <2> When the plane locator 323 includes a disabled repair mode, the disabled detection circuit 505 may activate the disabled state flag.

[0062] The repair detection circuit 506 may be configured to determine whether the address (e.g., read / write column address) and the plane locator 323 indicate a repair. The repair detection circuit 406 may receive outputs from the address comparison circuit 502, the unused detection circuit 504, and the disabled detection circuit 505. The repair detection circuit 506 may be configured to analyze the plane locator 323 and / or its derivative (e.g., unused repair status). The repair detection circuit 506 may generate a match status (e.g., a column match signal (ColMatch)).

[0063] In some embodiments, the repair detection circuit 506 may include a CP analysis circuit (e.g., a NOR gate) configured to receive and evaluate the results of the CP address analysis (e.g., outputs from the unused detection circuit 504 and the disabled detection circuit 505). The CP analysis circuit may further receive and evaluate the system disable (ColRedDis). When the output of the unused detection circuit 504 is invalid, when the output of the disabled detection circuit 505 is invalid, and / or when the system disable is invalid, the CP analysis circuit may be configured to generate a valid repair enable signal. In other words, the CP analysis circuit may drive the repair enable signal to an active state to indicate that the plane locator 323 indicates a repair location and an unused mode or a disabled mode.

[0064] The repair detection circuit 506 may further include a detection circuit (e.g., NAND, NOR, XOR, or a combination thereof) configured to compare / evaluate an output from the address comparison circuit 502 (e.g., an address comparison result) and an enable output from the CP analysis circuit. The detection circuit may generate a match status (e.g., a column match signal (ColMatch)) based on the comparison. For example, the detection circuit may generate an output indicating (via, for example, a valid state) when a column address matches an incoming fuse value and when the plane locator 323 indicates a plane for which a repair is targeted. In some embodiments, the output of the detection circuit may be negated (via, for example, an inverter), for example, to reduce the occurrence of a '1' value.

[0065] The second circuit 500 may use the output from the detection circuit to indicate whether column repair is applicable. The CP match may be further determined via a different circuit (e.g., DPTIER) external to the second circuit 500. Thus, the memory device 100 may implement a global repair (e.g., global column repair) based on the CP match and the output from the repair detection circuit 506. Thus, the memory device 100 may access the memory based on the valid output from the repair detection circuit 506. Figure 3A One or more redundant memory cells in the repair plane 315 other than the memory cells indicated by the read / write column address.

[0066] Figure 6 is a diagram illustrating the operation of a device (e.g., Figure 1 100) is a flowchart of an example method 600 of a memory device 100. For example, the method 600 may be used to operate Figure 3A The local fuse latch area 302, Figure 3A The matching circuit 306 is based on Figure 3A Repair address 322 and Figure 3A The method 600 may effectively or functionally couple (i.e., not have or replace a direct one-to-one connection) the fuses and / or fuse latches for the repair address 322 to the plane locator 323 of the repair address 322. Figure 3A One or more repair planes 315 of redundant memory.

[0067] At block 602, the memory device 100 may detect defective memory (eg, Figure 2 In some embodiments, the memory device 100 may implement a built-in self-test (BIST) design that may be online and / or offline to test the memory cells (e.g., Figure 1150). For example, the memory device 100 may perform a test sequence (via, for example, a memory controller, a finite state machine, and / or a processor) using a predetermined sequence of test elements including memory operations, data patterns, and / or addresses. For testing, the memory device 100 may write a predetermined data pattern to a corresponding address and then read the same address to confirm the same data pattern. When the read pattern does not match the predetermined written data pattern, the memory device 100 may identify the memory cell corresponding to the difference as defective. Thus, the memory device 100 may detect Figure 3A The memory plane 310 and / or Figure 3A Repair defective memory in plane 315.

[0068] At block 604, the memory device 100 may identify defect locations (e.g., locations of defective memory cells). For example, the memory device 100 may identify internal addresses of defective memory cells. Using a predetermined table and / or a predetermined procedure, the memory device 100 may identify addresses / identifiers for memory planes 310 and / or columns within the memory array 150 that include one or more defective memory cells. Thus, the memory device 100 may determine a repair address 322 and / or a plane locator 323 that represents the identified location.

[0069] At block 606, the memory device 100 may determine a plane locator (e.g., plane locator 323) that identifies a memory plane 310 having defective memory therein. The memory device 100 may determine a plane locator that identifies a swapped out memory plane 310 (e.g., a column plane). When the redundant memory (e.g., a portion of the repair plane 315) includes a defect, the memory device 100 may determine the plane locator 323 as a disabled repair state. At block 608, the memory device 100 may determine a repair address for the defective memory cell (e.g., an address of a column that includes the defective memory cell, such as the repair address 422 and / or the repair address 510).

[0070] At block 610, the memory device 100 may store defect locations to repair defective memory cells. The memory device 100 may store defect locations, for example, by setting fuses and / or writing to other non-volatile memory. In storing the defect locations, the memory device 100 may store both the repair address 322 and the plane locator 323 for each defective memory cell or each group thereof. For example, at block 612, the memory device 100 may store the plane locator 323 in a first set of fuses configured to identify the memory plane 310 in which the defective cell is included. In addition, at block 614, the memory device 100 may store the repair address 322 in a second set of fuses paired with the first set of fuses. When a repair is not necessary, the memory device 100 may store a first data pattern (e.g., a combination of '0' values) predetermined to indicate that a repair is not used into the corresponding plane locator 323. When repair is disabled, such as when the redundant memory is defective, the memory device may store a second data pattern (eg, a combination of '1' values) predetermined to indicate disabled repair into the corresponding plane locator 323. Thus, the plane locator 323 may include a replacement for the Figure 4A The first circuit 400 and / or Figure 4B The state of the enable bit used in the first mechanism 450 is represented.

[0071] In some embodiments, blocks 602 to 614 may represent a test and / or preset portion of a manufacturing process. For example, during a manufacturing process, a Figure 1 The memory array 150 may include memory planes 310 each having a plurality of memory cells and repair planes 315 each including a plurality of redundant cells configured to replace a set of defective memory cells in the plurality of memory cells. The manufacturing process may further include providing a latch (e.g., Figure 3A As described above, the latches may include a set of address latches and a set of locator latches for each repair. The address latches may store the repair address 322 and the locator latches may store the plane locator 323. As described above, the test / preset portion may be implemented based on the test memory array 150. The manufacturing process may also include Figure 3A The matching circuit 306 is connected to the latch.

[0072] The stored location information of the defective memory cell may be used for repair, for example, by accessing / utilizing a redundant memory cell in place of the defective memory cell. As an illustrative example, the memory device 100 may load / obtain the stored repair address 322 and the stored plane locator 323 into corresponding latches (e.g., latches in the local fuse latch region 302) during initialization or power reset. When a memory operation references a column, row, and / or plane that includes a defective memory cell, the memory device 100 may use or access the redundant column, row, and / or plane associated with the defective memory cell.

[0073] At block 652, the memory device 100 may issue an active command (ACT). Based on the active command, the memory device 100 may activate the idle bank, thereby causing that row to be read into the array of banks of column sense amplifiers. In other words, the memory device 100 may issue an active command to turn on a row.

[0074] At block 656, the memory device 100 may begin performing an operation (e.g., a read or write operation) in response to a command from the host. At block 658, the memory device 100 may receive an operation address (e.g., a read or write address) associated with the operation. For example, the memory device 100 may determine a column address (e.g., a read / write column address (CA)) associated with the commanded operation.

[0075] At decision block 662, the memory device 100 (eg, Figure 5A The unused detection circuit 504 of the memory device 100 (e.g., the unused repair pattern) may determine whether the plane locator 323 matches a predetermined bit pattern indicating an unused state. Figure 5A The disabled detection circuit 505 of the memory device may determine whether the plane locator 323 matches a predetermined bit pattern representing a disabled state (eg, a disabled repair pattern). Therefore, the memory device may determine the enabled state of the repair address 322 based on the plane locator 323.

[0076] When the plane locator 323 indicates a disabled state or an unused state, such as illustrated at block 666, the memory device 100 (eg, Figure 5A The repair detection circuit 506 of the memory device 100 may determine a mismatch scenario for repair. At block 668, the memory device 100 may access an operation address (e.g., a read / write column address) for a read / write operation. Since the operation address corresponds to a non-defective / disabled repaired memory cell as indicated by the comparison, the memory device 100 may implement a global repair scheme accordingly using the location originally referenced (i.e., without repair) and perform a memory operation.

[0077] When the plane locator 323 matches an unused repair mode or a disabled repair mode, the memory device 100 (e.g., the repair detection circuit 506) may determine that the plane locator 323 indicates a valid / enabled state for repair and / or indicates a target memory plane for repair. In response, the memory device 100 may determine a repair enablement state based on the plane locator 323 (e.g., by activating a corresponding flag).

[0078] At decision block 670, the memory device 100 (eg, Figure 5A The address comparison circuit 502 of the embodiment can determine whether the address (eg, the repair address 322) passed in from the latch matches the operation address (eg, the read / write column address). In some embodiments, the address comparison circuit 502 can generate an address comparison result based on the comparison.

[0079] When the incoming address does not match the operating address, the memory cell may access the operating address as described above for block 668. Otherwise, the memory device 100 may identify access to a defective / repaired memory cell via the address comparison result and the memory plane (e.g., CP) identified by the plane locator 323.

[0080] At block 674, the memory device 100 (eg, column decoder) may access redundant memory (eg, redundant columns) as indicated by the repair address 322. Furthermore, the memory device 100 may multiplex data paths via the DPTIER based on the plane locator 323 to implement a global repair scheme.

[0081] Figure 7 is a schematic diagram of a system including a device according to an embodiment of the present technology. Figures 1 to 6 Any of the foregoing apparatus (e.g., memory devices) described may be incorporated into any of a myriad of larger and / or more complex systems, representative examples of which are schematically shown in FIG. Figure 7 780. The system 780 may include a memory device 700, a power supply 782, a driver 784, a processor 786, and / or other subsystems or components 788. The memory device 700 may include a substantially similar Figures 1 to 6The system 780 may include features of those features of the apparatus described herein, and thus may include various features for performing direct read requests from a host device. The resulting system 780 may perform any of a wide variety of functions, such as memory storage, data processing, and / or other suitable functions. Thus, the representative system 780 may include, without limitation, handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, appliances, and other products. The components of the system 780 may be housed in a single unit or distributed over multiple interconnected units (e.g., via a communications network). The components of the system 780 may also include any of a wide variety of computer-readable media and remote devices.

[0082] In light of the foregoing, it should be understood that, although specific embodiments of the present technology have been described herein for the purpose of illustration, various modifications may be made without departing from the present invention. In addition, certain aspects of the new technology described in the context of specific embodiments may also be combined or eliminated in other embodiments. Moreover, although the advantages associated with certain embodiments of the new technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages and not all embodiments must exhibit such advantages to fall within the scope of the present technology. Therefore, the present invention and associated technology may encompass other embodiments not explicitly shown or described herein.

[0083] In the illustrated embodiments above, the apparatus has been described in the context of DRAM devices. However, apparatus configured in accordance with other embodiments of the present technology may include other types of suitable storage media in addition to or in place of DRAM devices, such as devices incorporating NAND-based or NOR-based non-volatile storage media (e.g., NAND flash memory), magnetic storage media, phase-change storage media, ferroelectric storage media, etc.

[0084] As used herein, the term "processing" includes manipulating signals and data, such as writing or programming, reading, erasing, refreshing, adjusting or changing values, calculating results, executing instructions, assembling, transferring and / or manipulating data structures. The term data structure includes information arranged as bits, words or codewords, blocks, files, input data, system-generated data (e.g., calculated or generated data), and program data. In addition, as used herein, the term "dynamic" describes a process, function, action, or implementation that occurs during operation, use, or deployment of a corresponding device, system, or embodiment, and after or while running manufacturer or third-party firmware. A process, function, action, or implementation that occurs dynamically may occur after or subsequent to design, manufacturing, and initial testing, setup, or configuration.

[0085] The above embodiments are described in sufficient detail to enable those skilled in the art to make and use the embodiments. However, those skilled in the art will appreciate that the present technology may have additional embodiments and may be used without the above reference. Figures 1 to 7 The present technology is practiced without the use of numerous details of the described embodiments.

Claims

1. A memory device, comprising: A memory array having a plurality of memory cells arranged according to rows and columns, the memory array comprising: a plurality of memory planes, the plurality of memory planes corresponding to the column planes, and one or more repair planes, each repair plane having a plurality of redundant cells configured to replace a set of defective memory cells in one of the memory planes; a set of address latches configured to latch repair addresses corresponding to the set of defective memory cells; a set of locator latches configured to latch a plane locator identifying the one of the memory planes for which a global repair is targeted; and a matching circuit coupled to the set of address latches and the set of locator latches, the matching circuit being configured to-- generating an address comparison result based on comparing the repair address with the address for operation; and generating a repair enable flag based on the plane locator, wherein a repair state represents an enabled, disabled, and / or unused setting for the global repair; Wherein the address comparison result and the repair enable flag indicate whether to access a redundant cell in one of the repair planes in place of a memory cell indicated by the address for the operation. 2 . The memory device of claim 1 , wherein the repair enable replaces an enable bit associated with the repair address for indicating an enable or disable state of the repair associated with the repair address.

3. The memory device of claim 1 , wherein the matching circuit comprises: an address comparison circuit coupled to the set of address latches and configured to generate the address comparison result based on comparing the repair address from the set of address latches with the address for the operation; a state detection circuit coupled to the set of locator latches and configured to generate a repair state based on the plane locator; and A repair detection circuit coupled to the address comparison circuit and the state detection circuit, the repair detection circuit being configured to-- generating the repair activation based on the repair status; and A match status is generated based on the address comparison result and the repair enable.

4. The memory device of claim 3, wherein the status detection circuit comprises an unused detection circuit configured to generate an unused status flag based on the plane locator, wherein the unused status flag indicates whether the repair address has not been used for any repair.

5. The memory device of claim 4, wherein the unused detection circuit is configured to generate the unused status flag based on detecting a predetermined bit pattern in the plane locator.

6. The memory device of claim 5, wherein the unused detection circuit is configured to activate the unused status flag when one or more predetermined bits in the plane locator are '0'.

7. The memory device of claim 6, wherein the unused detection circuit comprises a NOR device configured to receive the one or more predetermined bits and generate the unused status flag accordingly.

8. The memory device of claim 3, wherein the status detection circuit comprises a disabled detection circuit configured to generate a disabled status flag based on the plane locator, wherein the disabled status flag indicates whether a corresponding set of the redundant cells is disabled for any repair.

9. The memory device of claim 8, wherein the disabled detection circuit is configured to generate the disabled state flag based on detecting a predetermined bit pattern in the plane locator.

10. The memory device of claim 9, wherein the disabled detection circuit is configured to generate the disabled status flag when one or more predetermined bits in the plane locator are '1'.

11. The memory device of claim 10, wherein the disabled detection circuit comprises an AND device or a NAND device configured to receive the one or more predetermined bits and generate the disabled status flag accordingly.

12. The memory device of claim 3, wherein the status detection circuit is configured to: detecting an unused state based on a first set of bits in the plane locator; and A disabled state is detected based on a second set of bits in the plane locator, wherein the second set of bits at least partially overlaps the first set of bits.

13. The memory device of claim 1, wherein the plane locator corresponds to a decoding mechanism that reserves one or more sets of bit patterns to indicate a repair state and reserves other bit patterns to indicate a plane for which the repair is targeted, wherein the other bit patterns exclude the reserved bit patterns.

14. The memory device of claim 13, wherein the plane locator corresponds to a combination that reserves a '0' value to represent that repair is not used and a combination that reserves a '1' value to represent that the decoding mechanism has repair disabled.

15. The memory device of claim 13, wherein the other bit pattern of the plane locator represents the column plane comprising columns in one of the memory planes for globally replacing the set of defective memory cells.

16. The memory apparatus of claim 1, wherein the memory device comprises a random access memory (RAM) device.

17. The memory device of claim 16, wherein the RAM comprises a holographic RAM (HRAM), a double data rate 5 DDR5 RAM, or a low power DDR4 RAM.

18. The memory apparatus of claim 1, wherein a memory device comprises the memory array having a number of the memory planes, wherein the number is not equal to a power of 2.

19. The memory apparatus of claim 18, wherein the memory device comprises 16 planes and one error correction code (ECC) plane.

20. The memory device of claim 1, wherein the matching circuit is configured to directly generate the repair enable flag based on the plane locator and without combining an address.

21. A method of operating a memory device, the memory device comprising a plurality of memory cells arranged according to rows and columns and a plurality of redundant cells configured to replace one or more defective memory cells of the plurality of memory cells, the method comprising: obtaining a repair address representing a location of the one or more defective memory cells; obtaining a plane locator representing a column plane within a memory array that includes the one or more defective memory cells, wherein the plurality of memory cells are grouped into column planes and the redundant cells are grouped into one or more repair planes; Determining an enablement state for the repair address based on the plane locator, wherein determining the enablement state includes: activating a repair enablement flag when one or more predetermined bits of the plane locator do not indicate an unused state or a disabled state; and A global repair is performed according to the enablement state, wherein performing the global repair includes globally replacing the one or more defective memory cells when the repair enablement flag is activated.

22. The method of claim 21 , wherein implementing the global repair comprises: when the enable state is valid, globally replacing the one or more defective memory cells with columns in a repair plane according to the repair address and the plane locator, wherein the one or more defective memory cells are included in the columns indicated by the repair address and are located on the plane indicated by the plane locator.

23. A method of manufacturing a memory device, the method comprising: A memory array is provided, the memory array having a plurality of memory cells arranged according to rows and columns, the memory array comprising: (1) a memory plane, the memory plane corresponding to the column plane, and (2) one or more repair planes, each of which comprises a plurality of redundant cells configured to replace a group of defective memory cells in the plurality of memory cells; A latch is provided comprising a set of address latches and a set of locator latches for each repair, wherein-- The set of address latches is configured to store a repair address representing a location of the set of defective memory cells within the segment, The set of locator latches is configured to store a plane locator representing a plane targeted by a global replacement; and connecting a matching circuit to the latch, wherein the matching circuit is configured to-- determining whether the repair address matches the address for the operation, and A repair enable flag is generated based on the plane locator, wherein a repair state represents an enabled, disabled, and / or unused setting for the global replacement.

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