Method for manufacturing an electronic chip

Abstract

The present disclosure relates to a method for manufacturing an electronic chip. The method includes forming a plurality of trenches on a first surface of a semiconductor substrate, and a plurality of integrated circuits have been formed in and on the semiconductor substrate. The trenches laterally define a plurality of chips, and each of the chips includes a single integrated circuit. The method further includes electrically isolating the flanks of each of the chips by forming an electrically isolating layer on the lateral walls of the trenches.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing an electronic chip. More specifically, it relates to a method for manufacturing electronic chips whose lateral sides are protected by an electrically insulating material layer. Background Art

[0002] Electronic chips conventionally include integrated circuits formed in and on a semiconductor substrate. For many applications, it is desirable to have electronic chips in which the lateral sides of the substrate are covered by an electrically insulating material layer. This allows protecting the substrate from the possible climbing of soldering materials on its lateral sides during mounting the chip in an external device.

[0003] Known methods for manufacturing chips with isolated lateral sides have various drawbacks. Summary of the Invention

[0004] It is desirable to at least partially improve certain aspects of known methods for manufacturing electronic chips.

[0005] One embodiment provides a method for manufacturing an electronic chip, the method comprising the following steps:

[0006] a. Forming trenches on the lateral sides of a first face of a semiconductor substrate, in which and on which a plurality of integrated circuits have been pre-formed, the trenches laterally defining a plurality of chips, each of the plurality of chips including a single integrated circuit; and

[0007] b. Depositing an electrically insulating layer on the lateral walls of the trenches by an ALD deposition method to isolate the lateral sides of each chip.

[0008] According to one embodiment, during steps a) and b), the chips are held fixed by a support film on a side of the semiconductor substrate opposite to its first face.

[0009] According to one embodiment, the trenches formed in step a) end at the support film.

[0010] According to one embodiment, the electrically insulating layer deposited in step b) further extends on the lateral sides of the first face of the semiconductor substrate on each chip.

[0011] According to one embodiment, each chip includes at least one metal connection pad on a side of the semiconductor substrate opposite to its first face.

[0012] According to one embodiment, in step a), the trenches are formed by sawing. In some embodiments, the trenches may be formed by etching or ablation (e.g., by plasma etching or laser ablation).

[0013] According to one embodiment, before step b), there is a step of depositing a protective resin layer on the first face of the substrate.

[0014] According to one embodiment, before step a), there is a step of thinning the semiconductor substrate via its first face.

[0015] According to one embodiment, the electrical isolation layer comprises at least one oxide layer.

[0016] According to one embodiment, the electrical isolation layer comprises at least one layer made of a material from the group comprising alumina, silica and titania. Description of the Drawings

[0017] The foregoing features and advantages and other features and advantages will be described in detail below in the description of specific embodiments, with reference to the drawings, which are given by way of illustration and not limitation, in which:

[0018] Figure 1 Steps of a method for manufacturing an electronic chip according to one embodiment are depicted;

[0019] Figure 2 Further steps of a method for manufacturing an electronic chip according to one embodiment are depicted;

[0020] Figure 3 Further steps of a method for manufacturing an electronic chip according to one embodiment are depicted;

[0021] Figure 4 Further steps of a method for manufacturing an electronic chip according to one embodiment are depicted;

[0022] Figure 5 Further steps of a method for manufacturing an electronic chip according to one embodiment are depicted;

[0023] Figure 6 Further steps of a method for manufacturing an electronic chip according to one embodiment are depicted;

[0024] Figure 7 Further steps of a method for manufacturing an electronic chip according to one embodiment are depicted;

[0025] Figure 8 Further steps of a method for manufacturing an electronic chip according to one embodiment are depicted; and

[0026] Figure 9 Depicted is an example of an electronic chip obtained by Figures 1 to 8 the method shown. Detailed Description

[0027] In the various figures, similar features are designated by similar reference numerals. Specifically, structural and / or functional features common between the various embodiments may have the same reference numeral and may have exactly the same structure, dimensions, and material properties.

[0028] For clarity, only the operations and elements useful for the understanding of the embodiments described herein are detailed and described. Specifically, the implementation of the integrated circuits present in the electronic chip is not described in detail.

[0029] Unless otherwise stated, when referring to two elements connected together, this means a direct connection without any intermediate element other than a conductor, and when referring to two elements coupled together, this means that the two elements can be connected or coupled by means of one or more other elements.

[0030] In the following disclosure, unless otherwise stated, when referring to absolute position qualifiers such as the terms "front", "rear", "top", "bottom", "left", "right", etc., or when referring to relative position qualifiers such as the terms "above", "below", "higher", "lower", etc., or when referring to orientation qualifiers such as "horizontal", "vertical", etc., reference is made to the orientation shown in the figures.

[0031] Unless otherwise stated, the expressions "around", "approximate", "substantially", and "about" mean within 10%, and preferably within 5%.

[0032] Figures 1 to 8 is a cross-sectional view depicting successive steps of an example of a method for manufacturing an electronic chip according to one embodiment.

[0033] Figure 1 is a cross-sectional view of an initial structure including a semiconductor substrate 11 in and on which an integrated circuit 17 has been pre-formed. For example, except for manufacturing dispersions, the circuits 17 are all exactly the same. The substrate 11 may correspond to a wafer of semiconductor material (e.g., silicon). For example, the substrate 11 has a thickness included between 300 μm and 900 μm, e.g., a thickness of approximately 725 μm.

[0034] Figure 1 The structure shown further includes a stack 13 (referred to as an interconnect stack) of a conductive layer and an isolation layer covering the upper surface of the substrate 11 in which elements for interconnecting the components of each circuit 17 can be formed. For each integrated circuit 17, the interconnect stack 13 further includes one or more metal contact pads 15 flush with the upper surface of the integrated circuit 17 and intended to be connected to external devices. In Figure 1In [the figure], three metal contact pads 15 are illustrated. It should be understood that the number of metal contact pads 15 may actually be different from three.

[0035] For example, each integrated circuit 17 includes one or more electronic components (transistors, diodes, thyristors, triacs, etc.).

[0036] In Figure 1 In [the figure], three integrated circuits 17 are illustrated. It should be understood that the number of integrated circuits 17 formed in and on the substrate 11 may actually be different from three.

[0037] Figure 2 is a cross-sectional view depicting the step of forming metal connection posts 19 on the metal pads 15 and forming the metal connection posts 19 in contact with the metal pads 15.

[0038] More specifically, in this example, connection posts 19 are formed on each pad 15. For example, when viewed from above, each post 19 extends over the entire surface of the underlying pad 15. For example, when viewed from above, each post 19 has a square or rectangular shape. Alternatively, the post can have other shapes, such as a circular shape. For example, the upper surface of the post 19 is substantially flat. For example, the post 19 can be formed by electrolytic growth. The post 19 can be made of a tin-based alloy, such as an alloy based on tin and silver (SnAg), such as a tin-silver-copper alloy.

[0039] In the following description, in accordance with Figure 2 the orientation shown, the underside of the structure is regarded as the back, and in accordance with Figure 2 the orientation shown, the upper surface of the structure is regarded as the front.

[0040] Figure 3 depicts the step of thinning the structure obtained at the end of the step shown in Figure 2 by its back. Before this thinning, the structure is fixed to a support film 21 (such as an adhesive film) by its front. For example, the thinning is then achieved by mechanical grinding. In a variant, the thinning is achieved by CMP (chemical mechanical polishing).

[0041] In this example, the substrate 11 is thinned by its back until reaching the underside of the circuit 17. At the end of this step, the thickness of the substrate 11 can be in the range from about 50 μm to about 400 μm. In some embodiments, for example, the thickness of the substrate 11 after thinning is equal to approximately 200 μm.

[0042] Figure 4 is a depiction of Figure 3Cross-sectional view of the step of depositing the protective resin layer 23 on the back surface of the structure obtained at the end of the steps shown. For example, the resin layer 23 extends over the entire back surface of the substrate 11 in a continuous manner and with a substantially constant thickness.

[0043] For example, the resin 23 is an epoxy resin. In some embodiments, the resin layer 23 may have a thickness in the range from about 5 μm to about 50 μm. In some embodiments, for example, the resin layer 23 has a thickness of about 25 μm. The resin layer 23 may be optional, and in some embodiments, the resin layer 23 may be omitted. As described in further detail below, the resin layer 23 can be used as a medium for marking. In embodiments where the resin layer 23 is omitted, the marking can be achieved by other techniques, such as marking directly on the substrate 11, or through an epoxy layer or other layer on which the marking can be provided on the back surface of the substrate 11.

[0044] The resin 23 can be an opaque resin, such as a black resin. By means of the resin 23, it is possible to give the back surface of the chip the visual appearance sought by certain manufacturers. The use of an opaque resin further allows the substrate to be protected from ultraviolet radiation.

[0045] Figure 4 The step depicted can be followed by the step of marking the chip by etching a marking pattern (such as an identification code or logo) on the back surface of the resin layer 23 on each chip. For example, the marking is achieved by laser etching. Other techniques can be utilized to mark the chip, for example, in various embodiments, inkjet marking or any suitable marking technique can be utilized. Moreover, in embodiments where the resin 23 is omitted, the marking can be done directly on the substrate 11, or on another layer such as an epoxy layer that can be provided on the back surface of the substrate 11.

[0046] Figure 5 Depicts the step of removing the support film 21 on the front surface of the structure.

[0047] Figure 6 Depicts the step of fixing the structure to the support film 25 through its front surface. It should be noted that in Figure 6 the example shown, the orientation of the structure is reversed with respect to the cross-sectional view shown in the foregoing figures.

[0048] Figure 7 is at Figure 6Cross-sectional view in the same orientation, which depicts the steps of cutting the structure into individual chips, each individual chip including a single integrated circuit 17. During this step, the trench 27 is implemented from the back of the structure. When viewed from above, the trench 27 extends between the integrated circuits 17 such that each integrated circuit 17 is separated from its neighbor by the trench 27. For example, each integrated circuit 17 is completely laterally bounded by the trench 27. In this example, the trench 27 extends vertically from above the protective resin layer 23 to above the support film 25. In other words, in this example, the trench 27 completely spans the resin layer 23, the substrate 11, and the interconnect stack 13. For example, the trench 27 is implemented by sawing. During this step, the alignment of the cutting tool is based on the front of the structure. For this purpose, a film 25 that is transparent to the irradiation wavelength of the alignment tool will preferably be selected.

[0049] At the end of this step, a plurality of individual chips joined only by the support film 25 are obtained.

[0050] Figure 8 is in the same orientation as Figure 7 Cross-sectional view, which depicts the step of depositing the electrical isolation layer 29 on the back of the structure obtained at the end of the step shown in Figure 7 In this example, the layer 29 is deposited in a continuous manner and with a substantially constant thickness over the entire back surface of the structure (i.e., on top of the layer 23), as well as on the lateral walls and bottom of the trench 27. Specifically, in this example, the layer 29 is deposited on and in contact with the flanks of the substrate 11 of each chip.

[0051] The layer 29 is deposited by ALD (atomic layer deposition). The deposition of the layer 29 can be achieved at low temperature, for example at a temperature below 100 °C, such as approximately 80 °C. For example, the layer 29 has a thickness included between 5 nm and 50 nm, and in some embodiments, has a thickness included between 20 nm and 40 nm (preferably between 20 nm and 40 nm). The thickness of the layer 29 can be selected as desired according to design considerations (such as the desired amount of electrical isolation or electrical insulation).

[0052] For example, the layer 29 can be an oxide layer, such as an aluminum oxide (Al 2 O 3 ) layer, a titanium dioxide (TiO 2 ) layer, a silicon dioxide (SiO 2 ) layer, or any other material capable of being deposited by ALD. Alternatively, the layer 29 can include a stack of multiple individual material layers deposited continuously by ALD.

[0053] The chips can then be removed from the support film 25 in order to mount them in external devices.

[0054] Figure 9 is a sectional view in the same orientation as Figure 8 and depicts an exemplary electronic chip obtained by the manufacturing method shown after removal from the support film 25. Figures 1 to 8

[0055] The advantage of the above method is that its implementation is particularly simple and, by using the ALD deposition method, it allows for obtaining thin and effective lateral electrical isolation.

[0056] Various embodiments and alternatives have been described. Those skilled in the art will understand that certain features of these embodiments can be combined and that other alternatives will readily occur to those skilled in the art. Specifically, the described embodiments are not limited to the example dimensions and materials mentioned above.

[0057] Moreover, as an alternative, the step of depositing the protective resin layer 23 on the back side as described with respect to Figure 6 can be omitted, and thus, the back side isolation of the chip is achieved only by the layer 29.

[0058] In addition, as an alternative, the support film 21 fixed to the front side of the structure before the thinning step shown in Figure 3 can be retained until the step of depositing the isolation layer 29 by ALD (after forming the trench 27). In this case, the step of fixing the structure to the support film 25 shown in Figure 6 can be omitted.

[0059] Furthermore, as an alternative, the step of depositing the metal connection posts 19 on top of the metal contact pads 15 of the integrated circuit shown in Figure 2 can be omitted. In this case, the electrical connection of each chip to an external device is established directly through the contact pads 15.

[0060] The various embodiments described above can be combined to provide further embodiments. Based on the detailed description above, these and other changes can be made to the embodiments. In summary, in the appended claims, the terms used should not be construed as limiting the claims to the specific embodiments disclosed in this specification and the claims, but should be construed as including all possible embodiments and equivalents of the full scope enjoyed by these claims. Therefore, the claims are not limited by this disclosure.​

Claims

1. A method for manufacturing chips, comprising: forming a plurality of trenches through a semiconductor substrate and an interconnect layer, each of the plurality of trenches extending through a first surface of the semiconductor substrate and a second surface of the semiconductor substrate opposite the first surface, the interconnect layer being on the second surface of the semiconductor substrate, the semiconductor substrate including a plurality of integrated circuits, the plurality of trenches laterally defining a plurality of chips, each of the plurality of chips including an integrated circuit among the plurality of integrated circuits, and the interconnect layer including at least one metal connection pad for each of the plurality of chips; and electrically isolating the flanks of each of the plurality of chips by forming an electrically isolating layer on the first surface of the semiconductor substrate and the lateral walls of the plurality of trenches, the electrically isolating layer being provided on the lateral walls of the semiconductor substrate in the plurality of trenches and the lateral walls of the interconnect layer, and the electrically isolating layer including at least one oxide layer.

2. The method according to claim 1, wherein forming the electrically isolating layer on the lateral walls of the plurality of trenches comprises: forming the electrically isolating layer by atomic layer deposition (ALD).

3. The method according to claim 1, wherein during forming the plurality of trenches and electrically isolating the flanks of each of the plurality of chips, the plurality of chips are fixed to the second surface of the semiconductor substrate by a support film.

4. The method according to claim 3, wherein the trenches extend through the semiconductor substrate to the support film.

5. The method according to claim 1, wherein the trenches are formed by at least one of sawing, etching or ablation.

6. The method according to claim 1, further comprising: depositing a protective resin layer on the first surface of the semiconductor substrate before forming the plurality of trenches.

7. The method according to claim 1, further comprising: exposing the first surface by thinning the semiconductor substrate before forming the plurality of trenches.

8. The method according to claim 1, wherein the electrically isolating layer includes at least one of aluminum oxide, silicon dioxide or titanium dioxide.

9. A method for manufacturing chips, comprising: attaching a support film to an interconnect layer, the interconnect layer being on a first side surface of a semiconductor substrate, the semiconductor substrate having a plurality of integrated circuits at the first side surface; forming a plurality of trenches extending through the semiconductor substrate and the interconnect layer and extending to the support film, the plurality of trenches laterally defining a plurality of chips, each of the plurality of chips including at least one integrated circuit among the plurality of integrated circuits, and the interconnect layer including at least one metal connection pad for each of the plurality of chips; and An electrical isolation layer is formed on a second side of the semiconductor substrate opposite to the first side, on a lateral surface of the semiconductor substrate exposed through the plurality of trenches, on a portion of the support film exposed through the plurality of trenches, and on a lateral surface of the interconnect layer exposed through the plurality of trenches, and the electrical isolation layer is a dielectric oxide layer.

10. The method according to claim 9, further comprising: forming a protective layer on the first side of the semiconductor substrate, and the plurality of trenches extend through the protective layer.

11. The method according to claim 10, wherein the protective layer comprises epoxy resin.

12. The method according to claim 9, further comprising: forming a plurality of metal pillars on metal pads of the plurality of integrated circuits at the first side of the semiconductor substrate, and the plurality of metal pillars are in contact with the metal pads, wherein the support film covers the plurality of metal pillars.

13. The method according to claim 9, further comprising: removing a portion of the support film and the electrical isolation layer on the portion of the support film exposed through the plurality of trenches.

14. The method according to claim 9, wherein forming the electrical isolation layer comprises: forming the electrical isolation layer by atomic layer deposition (ALD).

15. The method according to claim 14, wherein forming the electrical isolation layer comprises: forming the electrical isolation layer to have a thickness between 20 nm and 40 nm.

16. A method for manufacturing a chip, comprising: forming a plurality of metal pillars on metal pads of a plurality of integrated circuits at a first side of a semiconductor substrate; attaching a first support film to the first side of the semiconductor substrate, and the first support film covers the plurality of metal pillars; thinning a second side of the semiconductor substrate opposite to the first side; removing the first support film; attaching a second support film to the first side of the semiconductor substrate; forming a plurality of trenches extending through the semiconductor substrate to the second support film, the plurality of trenches laterally defining a plurality of chips, and each chip of the plurality of chips includes at least one of the plurality of integrated circuits; and depositing an electrical isolation layer on a lateral surface of the semiconductor substrate exposed through the plurality of trenches.

17. The method according to claim 16, further comprising: forming a protective layer on the second side of the semiconductor substrate, and the plurality of trenches extend through the protective layer.

Images