Semiconductor device including epitaxial region

Abstract

A semiconductor device is provided. The semiconductor device includes: an active region on a semiconductor substrate; a channel region on the active region; a source / drain region adjacent to the channel region on the active region; a gate structure on the channel region and overlapping the channel region; a contact structure on the source / drain region; a gate spacer between the contact structure and the gate structure; and a contact spacer surrounding a side surface of the contact structure. The source / drain region includes a first epitaxial region having a recessed surface, and a second epitaxial region on the recessed surface of the first epitaxial region, wherein the second epitaxial region includes an extension portion that extends horizontally from a portion that vertically overlaps the contact structure and vertically overlaps the contact spacer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2019-0148399 filed on November 19, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including an epitaxial region and a method of forming the same. Background Art

[0004] As demand for higher performance, higher speed, and / or more multifunctional semiconductor devices increases, the integration density of such semiconductor devices is also increasing. This trend toward higher integration of semiconductor devices has led to a reduction in the size of planar metal oxide semiconductor field effect transistors (MOSFETs). To overcome the limitations in operating characteristics caused by this reduction in MOSFET size, efforts are underway to develop MOSFETs that include channels with three-dimensional structures. Summary of the Invention

[0005] An aspect of the inventive concept is to provide a semiconductor device capable of improving integration.

[0006] An aspect of the inventive concept is to provide a semiconductor device with improved performance.

[0007] An aspect of the inventive concept is to provide a method of forming a semiconductor device with improved productivity of the semiconductor device.

[0008] According to one aspect of the present invention, a semiconductor device is provided. A semiconductor device includes: an isolation layer defining a first active region on a semiconductor substrate; an interlayer insulating layer on the isolation layer; a channel region on the first active region; a source / drain region on the first active region adjacent to the channel region in a first horizontal direction; a gate structure on the channel region, overlapping the channel region and extending longitudinally in a second horizontal direction perpendicular to the first horizontal direction; a contact structure on the source / drain region; a gate spacer between the contact structure and the gate structure; and a contact spacer disposed between the contact structure and the gate spacer and between the contact structure and the interlayer insulating layer. The lower end of the contact spacer and the lower end of the gate spacer are set at different height levels, the contact structure includes: a metal semiconductor composite layer and a contact plug on the metal semiconductor composite layer, the source / drain region includes a first epitaxial region having a recessed surface, and a second epitaxial region on the recessed surface of the first epitaxial region, the upper surface of the second epitaxial region contacts the metal semiconductor composite layer, and the second epitaxial region includes an extension portion, which extends longitudinally in a first horizontal direction from a portion overlapping with the contact structure in a vertical direction to a portion overlapping with the contact spacer in a vertical direction.

[0009] According to one aspect of the present invention, a semiconductor device is provided. The semiconductor device includes: an active region on a semiconductor substrate; a channel region on the active region; a source / drain region on the active region and adjacent to the channel region; a gate structure on the channel region and overlapping the channel region; a contact structure on the source / drain region; a gate spacer between the contact structure and the gate structure; and a contact spacer surrounding a side surface of the contact structure. The contact structure includes a metal semiconductor composite layer and a contact plug on the metal semiconductor composite layer, the source / drain region includes a base epitaxial region, a first epitaxial region on the base epitaxial region, and a second epitaxial region on the first epitaxial region, the source / drain region includes Si elements and Ge elements, the Ge element concentration in the base epitaxial region, the Ge element concentration in the first epitaxial region, and the Ge element concentration in the second epitaxial region are different from each other, the upper surface of the second epitaxial region is in contact with the metal semiconductor composite layer, and the second epitaxial region includes an extension portion, which extends in the horizontal direction from a portion overlapping with the contact structure in the vertical direction to a portion overlapping with the contact spacer in the vertical direction.

[0010] According to one aspect of the present invention, a semiconductor device is provided. The semiconductor device includes: an active region on a semiconductor substrate; a channel region on the active region; a source / drain region adjacent to the channel region on the active region; a gate structure overlapping the channel region on the channel region; a contact structure on the source / drain region; a gate spacer between the contact structure and the gate structure; and a contact spacer surrounding a side surface of the contact structure. The lower end of the contact spacer and the lower end of the gate spacer are arranged at different height levels, the source / drain region includes a first epitaxial region having a recessed surface, and a second epitaxial region on the recessed surface of the first epitaxial region, and the second epitaxial region includes an extension portion, the extension portion extending in the horizontal direction from a portion overlapping with the contact structure in the vertical direction to a portion overlapping with the contact spacer in the vertical direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description given in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a plan view illustrating a semiconductor device according to example embodiments;

[0013] Figure 2A 、 Figure 2B and Figure 2C is a partially enlarged cross-sectional view illustrating a semiconductor device according to an example embodiment of the present disclosure;

[0014] Figure 3A 、 Figure 3B 、 Figure 3C and Figure 3D are partially enlarged cross-sectional views illustrating various modified examples of the semiconductor device according to the exemplary embodiment of the present disclosure;

[0015] Figure 4A 、 Figure 4B and Figure 4C are partially enlarged cross-sectional views illustrating various modified examples of the semiconductor device according to the exemplary embodiment of the present disclosure;

[0016] Figure 5 is a cross-sectional view illustrating a modified example of the semiconductor device according to the exemplary embodiment of the present disclosure;

[0017] Figure 6 is a cross-sectional view illustrating a modified example of the semiconductor device according to the exemplary embodiment of the present disclosure;

[0018] Figure 7 is a plan view illustrating a modified example of the semiconductor device according to the exemplary embodiment of the present disclosure;

[0019] Figure 8 is a cross-sectional view illustrating a modified example of the semiconductor device according to the exemplary embodiment of the present disclosure;

[0020] Figure 9A 、 Figure 9B 、 Figure 9C and Figure 9D are cross-sectional views illustrating various modified examples of the semiconductor device according to an example embodiment of the present disclosure;

[0021] Figure 10 is a plan view illustrating a modified example of the semiconductor device according to the exemplary embodiment of the present disclosure;

[0022] Figure 11A 、 Figure 11B and Figure 11C is a diagram illustrating a modified example of the semiconductor device according to an exemplary embodiment of the present disclosure;

[0023] Figure 12A 、 Figure 12B and Figure 12C are cross-sectional views illustrating various modified examples of the semiconductor device according to an example embodiment of the present disclosure;

[0024] Figure 13 is a cross-sectional view illustrating a modified example of the semiconductor device according to the exemplary embodiment of the present disclosure;

[0025] Figure 14 is a cross-sectional view illustrating a modified example of the semiconductor device according to the exemplary embodiment of the present disclosure;

[0026] Figure 15 is a process flow chart illustrating a method of manufacturing a semiconductor device according to an example embodiment of the present disclosure;

[0027] Figure 16A and Figure 16B is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an example embodiment of the present disclosure;

[0028] Figure 17A and Figure 17B is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an example embodiment of the present disclosure; and

[0029] Figure 18A and Figure 18B is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] First, refer to Figure 1 、 Figure 2A and Figure 3B A semiconductor device according to example embodiments of the present disclosure is described. Figure 1is a plan view showing a semiconductor device according to an example embodiment of the present disclosure, Figure 2A FIG. 1 is a diagram illustrating a semiconductor device according to an exemplary embodiment of the present disclosure. Figure 1 A cross-sectional view of an area taken along line Ia-Ia' and an area taken along line IIa-IIa', Figure 2B It is magnified Figure 2A A partial enlarged view of the portion indicated by 'A', and Figure 2C FIG. 1 is a diagram illustrating a semiconductor device according to an exemplary embodiment of the present disclosure. Figure 1 sectional view of the region taken along line IIIa-IIIa'.

[0031] refer to Figure 1 ,as well as Figures 2A to 2C The semiconductor device 1 according to the example embodiment includes a semiconductor substrate 3, an active region 6, an isolation layer 9 on the semiconductor substrate 3, and a channel region 6p and source / drain regions 21a on the active region 6. The semiconductor substrate 3 may be formed of a semiconductor material such as silicon.

[0032] In an example, the active region 6 may have a linear shape or a stripe shape extending lengthwise in a first horizontal direction D1 . The first horizontal direction D1 may be parallel to the upper surface of the semiconductor substrate 3 .

[0033] In an example, the isolation layer 9 may be a trench isolation layer (eg, a shallow trench isolation layer). The isolation layer 9 may be formed of an insulating material (eg, silicon oxide, etc.).

[0034] In an example, the channel region 6p may extend in the vertical direction D3 from the active region 6. For example, the channel region 6p may be formed at a vertical level higher than the upper surface of the isolation layer 9. The channel region 6p may be referred to as an active fin.

[0035] In an example, when the channel region 6p is a channel region of a PMOS transistor, the channel region 6p may have N-type conductivity, and the source / drain region 21a may have P-type conductivity. As another example, when the channel region 6p is a channel region of an NMOS transistor, the channel region 6p may have P-type conductivity, and the source / drain region 21a may have N-type conductivity.

[0036] The semiconductor device 1 may further include a gate structure 36 that overlaps the channel region 6p on the active region 6, extends longitudinally in a second horizontal direction D2 perpendicular to the first horizontal direction D1, and overlaps the isolation layer 9 in a vertical direction D3; and gate spacers 15 on side surfaces of the gate structure 36. The gate structure 36 may extend longitudinally in the second horizontal direction D2 while covering the upper surface and side surfaces of the channel region 6p.

[0037] The gate structure 36 may include a gate electrode 42, a gate dielectric layer 39 covering the lower surface and side surfaces of the gate electrode 42, and a gate capping layer 45 on the gate electrode 42. The gate capping layer 45 may cover the upper end of the gate dielectric layer 39. In some embodiments, the gate dielectric layer 39 may contact the lower surface and side surfaces of the gate electrode 42. The upper surface of the gate dielectric layer 39 may be coplanar with the upper surface of the gate electrode 42. The gate capping layer 45 may contact and cover the upper surfaces of the gate dielectric layer 39 and the gate electrode 42. The side surfaces of the gate dielectric layer 39 and the gate capping layer 45 may be aligned with each other in a vertical direction, and the gate spacer 15 may contact the side surfaces of the gate dielectric layer 39 and the gate capping layer 45. Unless the context indicates otherwise, the term "contact" as used herein means direct connection (i.e., touching).

[0038] The gate dielectric layer 39 may include silicon oxide and / or a high-k dielectric. The gate electrode 42 may be formed of a conductive material such as doped silicon, a metal nitride (e.g., TiN, TaN, WN, etc.), or a metal (e.g., W, etc.). The gate cap layer 45 may be formed of an insulating material (e.g., SiN, SiON, etc.). For example, the gate spacer 15 may be formed of an insulating material (e.g., SiO, SiN, SiON, SiOC, etc.).

[0039] The source / drain regions 21a may be adjacent to the channel regions 6p in the first horizontal direction D1 on the active region 6. For example, each channel region 6p may be disposed between adjacent pairs of source / drain regions 21a.

[0040] A contact hole 48 may be provided on the source / drain region 21a. The contact hole 48 may be defined by the interlayer insulating layer 30 in the second horizontal direction D2 and by the gate spacer 15 in the first horizontal direction D1.

[0041] Semiconductor device 1 may further include a contact structure 57 on source / drain region 21 a. Contact structure 57 may include a metal-semiconductor composite layer 60 and a contact plug 63 on metal-semiconductor composite layer 60. Contact structure 57 may be disposed in contact hole 48. Metal-semiconductor composite layer 60 may be a metal-silicon alloy layer, a metal-germanium alloy layer, or a metal-silicon-germanium alloy layer. Here, the metal in metal-semiconductor composite layer 60 may be titanium (Ti), tantalum (Ta), nickel (Ni), or cobalt (Co).

[0042] In an example, the metal semiconductor composite layer 60 may have a thickness of about 1 nm to about 10 nm in the vertical direction D3 .

[0043] In an example, contact plug 63 may include a first conductive layer 66 and a second conductive layer 69. First conductive layer 66 may cover the lower surface and side surfaces of second conductive layer 69. First conductive layer 66 may contact the lower surface and side surfaces of second conductive layer 69, and the lower surface of first conductive layer 66 may contact the upper surface of metal semiconductor composite layer 60. First conductive layer 66 may include a metal nitride (e.g., TiN, TaN, WN, etc.), while second conductive layer 69 may include a metal (e.g., tungsten (W), etc.).

[0044] Semiconductor device 1 may further include a contact spacer 51 in contact hole 48 and surrounding side surfaces of contact structure 57. Contact spacer 51 may be interposed between contact structure 57 and interlayer insulating layer 30 in second horizontal direction D2, and between contact structure 57 and gate spacer 15 in first horizontal direction D1. Contact spacer 51 may be formed of an insulating material (e.g., silicon oxide). An outer surface of contact spacer 51 may contact interlayer insulating layer 30 and gate spacer 15, while an inner surface of contact spacer 51 may contact contact structure 57.

[0045] In an example, the lower end of the contact spacer 51 may be disposed at a lower height (vertical) level than the lower end of the gate spacer 15. For example, the lower end of the contact spacer 51 may be disposed at a lower vertical level than the upper surface of the channel region 6p.

[0046] In an example, a maximum thickness of the gate spacer 15 in the first horizontal direction D1 may be greater than a maximum thickness of the contact spacer 51 in the first horizontal direction D1 .

[0047] The source / drain region 21a may include a first epitaxial region 27 having a recessed surface 27r and a second epitaxial region 54 on the recessed surface 27r of the first epitaxial region 27. The first epitaxial region 27 may further include an upper end 27t contacting a lower surface of the gate spacer 15.

[0048] When the lower surface of the gate spacer 15 or the upper surface of the channel region 6p is regarded as a reference plane, the maximum depth of the recessed surface 27r of the first epitaxial region 27 may be about 5 nm to about 50 nm. For example, the maximum depth of the recessed surface 27r may be about 5 nm to about 50 nm below the reference plane defined by the lower surface of the gate spacer 15 or the upper surface of the channel region 6p.

[0049] The source / drain region 21a may further include a base epitaxial region 24. The base epitaxial region 24 may be disposed between the first epitaxial region 27 and the channel region 6p and may be disposed between the first epitaxial region 27 and the active region 6. The base epitaxial region 24 may include an upper end 24t coplanar with an upper end 27t of the first epitaxial region 27.

[0050] In an example, an upper end 24 t of the base epitaxial region 24 and an upper end 27 t of the first epitaxial region 27 may contact a lower surface of the gate spacer 15 .

[0051] An upper surface 54U of the second epitaxial region 54 may be in contact with the metal-semiconductor composite layer 60 of the contact structure 57 .

[0052] In an example, the upper surface 54U of the second epitaxial region 54 may have a downwardly curved shape. For example, the upper surface 54U of the second epitaxial region 54 may have a convex shape.

[0053] In an example, an upper surface 54U of the second epitaxial region 54 may be disposed at a lower level than lower surfaces of the gate spacer 15 and the gate structure 36 . An upper surface 54U of the second epitaxial region 54 may be disposed at a lower level than lower surfaces of the contact spacers 51 .

[0054] The second epitaxial region 54 may include an extension portion 54p extending in the first horizontal direction D1 from a portion overlapping the contact structure 57 in the vertical direction D3 and overlapping the contact spacer 51 in the vertical direction D3. For example, the width of the second epitaxial region 54 including the extension portion 54p in the first horizontal direction D1 may be greater than the width of the contact structure 57 in the first horizontal direction D1.

[0055] The extension 54p of the second epitaxial region 54 may overlap the gate spacer 15 in the vertical direction D3. The extension 54p of the second epitaxial region 54 may be spaced apart from the gate spacer 15. The second epitaxial region 54 may be in contact with the lower end 51L of the contact spacer 51.

[0056] The first epitaxial region 27 may include: a first lower epitaxial region 27L located below the extension 54p of the second epitaxial region 54, and a first upper epitaxial region 27U located above the extension 54p of the second epitaxial region 54. For example, the first lower epitaxial region 27L may be a portion of the first epitaxial region 27 formed at a vertical level lower than the extension 54p, and the first upper epitaxial region 27U may be a portion of the first epitaxial region 27 formed at a vertical level equal to or higher than the extension 54p. The first lower epitaxial region 27L and the first upper epitaxial region 27U may be connected to each other. For example, the first lower epitaxial region 27L and the first upper epitaxial region 27U may have material continuity with each other. As used herein, the term "material continuity" may refer to structures, patterns and / or layers formed from the same material at the same time, with no interruption in the continuity of the materials forming them.

[0057] The maximum width of the second epitaxial region 54 in the first horizontal direction D1 may be greater than the maximum width of the metal semiconductor composite layer 60 in the first horizontal direction D1. The maximum width of the second epitaxial region 54 in the second horizontal direction D2 may be greater than the maximum width of the metal semiconductor composite layer 60 in the second horizontal direction D2.

[0058] The transistor including the channel region 6p, the source / drain region 21a, and the gate structure 36 may be a PMOS transistor. The source / drain region 21a may include Si and Ge. The Ge concentration in the first epitaxial region 27 may be higher than the Ge concentration in the base epitaxial region 24. The Ge concentration in the second epitaxial region 54 may be higher than the Ge concentration in the first epitaxial region 27.

[0059] In an example, the Ge element concentration in the base epitaxial region 24 may be about 1% to about 40%.

[0060] In an example, the Ge element concentration in the first epitaxial region 27 may be about 30% to about 90%.

[0061] The Ge element concentration in the second epitaxial region 54 may be approximately 50% to approximately 100%. The second epitaxial region 54, having a higher Ge element concentration than the base epitaxial region 24 and the first epitaxial region 27, may be a stressor that applies compressive stress to the channel region 6p. Therefore, since the charge mobility in the channel region 6p can be increased, the performance of the PMOS transistor including the channel region 6p, the source / drain regions 21a, and the gate structure 36 can be improved.

[0062] Base epitaxial region 24 may have a thickness in a vertical direction D3 of about 1 nm to about 40 nm.

[0063] The first epitaxial region 27 may have a thickness of about 1 nm to about 50 nm in the vertical direction D3 .

[0064] The second epitaxial region 54 may have a thickness of about 1 nm to about 50 nm in the vertical direction D3 .

[0065] The source / drain regions 21 a may include at least one of boron (B), aluminum (Al), gallium (Ga), and indium (In) as P-type impurities. The concentration of the P-type impurities in the source / drain regions 21 a may be about 1E17 to about 1E22 atoms / cc.

[0066] The maximum concentration of the P type impurities in the second epitaxial region 54 may be higher than the minimum concentration of the P type impurities in the first epitaxial region 27 . The maximum concentration of the P type impurities in the first epitaxial region 27 may be higher than the minimum concentration of the P type impurities in the base epitaxial region 24 .

[0067] The second epitaxial region 54 may be spaced apart from the channel region 6p and may contact the contact structure 57. For example, the base epitaxial region 24 and the first epitaxial region 27 may be between the second epitaxial region 54 and the channel region 6p, separating the second epitaxial region 54 from the channel region 6p. Among the base epitaxial region 24, the first epitaxial region 27, and the second epitaxial region 54, the impurity concentration of the second epitaxial region 54 in the source / drain region 21a is the highest. Therefore, the channel region 6p can be prevented from being degraded by P-type impurities, and the contact resistance between the source / drain region 21a and the contact structure 57 can be significantly reduced. Therefore, the performance of the transistor can be improved.

[0068] Hereinafter, a modified example of the semiconductor device according to the exemplary embodiment of the present disclosure will be described. Hereinafter, the same reference numerals may refer to the same components. Therefore, in the following description of the modified example, the description of the components that overlap with the above components will be omitted, and the description will be based on the components that are modified or to be replaced.

[0069] Next, we will refer to Figures 3A to 3D Various modified examples of the semiconductor device according to the example embodiment of the present disclosure are described. Figures 3A to 3D Various modification examples of the semiconductor device according to the exemplary embodiment of the present disclosure are described. Figure 2A The portion indicated by 'A' corresponds to the enlarged region of the partial enlarged view.

[0070] In reference Figure 3A In the modified example, you can set it to replace Figure 2B The source / drain region 21a and the source / drain region 21b.

[0071] The source / drain region 21 b may include a base epitaxial region 24 , a first epitaxial region 27 b on the base epitaxial region 24 , and a second epitaxial region 54 b on the first epitaxial region 27 b .

[0072] The second epitaxial region 54b may include an extension 54p' that extends from a portion overlapping with the contact structure 57 and the contact spacer 51 in a direction toward the channel region 6p and overlaps with the gate spacer 15 in the vertical direction D3. The second epitaxial region 54b may contact the base epitaxial region 24. For example, the extension 54p' of the second epitaxial region 54b may contact the base epitaxial region 24.

[0073] The first epitaxial region 27b may include a second lower epitaxial region 27L' and a second upper epitaxial region 27U' divided in the vertical direction D3 by an extension portion 54p' of the second epitaxial region 54b. The second upper epitaxial region 27U' may be disposed on the second lower epitaxial region 27L'. An upper end 27t of the second upper epitaxial region 27U' may contact the lower surface of the gate spacer 15.

[0074] In reference Figure 3B In the modified example, you can set it to replace Figure 2B The source / drain region 21a is connected to the source / drain region 21c.

[0075] The source / drain region 21 c may include a base epitaxial region 24 , a first epitaxial region 27 on the base epitaxial region 24 , and a second epitaxial region 54 c on the first epitaxial region 27 .

[0076] In another example, Figure 3B In the embodiment, the first epitaxial region 27 may be referred to as Figure 3A The first epitaxial region 27b is replaced by the depicted one.

[0077] An upper surface 54cU of the second epitaxial region 54c may be disposed at a higher level than a lower surface of the gate spacer 15 and an upper surface of the channel region 6p.

[0078] The second epitaxial region 54c may include Figure 2B The extension portion 54p of the second epitaxial region 54 is shown in FIG.

[0079] In another example, Figure 3B In the embodiment of the present invention, the extension portion 54p of the second epitaxial region 54c can be referred to as Figure 3A The depicted second epitaxial region 54b is replaced by an extension 54p'.

[0080] In reference Figure 3C In the modified example, you can set it to replace Figure 2B The contact spacer 51 of the contact spacer 51 ', and the contact spacer 51 that can replace Figure 2B The source / drain region 21a is the source / drain region 21d.

[0081] A lower end 51L′ of the contact spacer 51 ′ may be disposed at a height level higher than a lower surface of the gate spacer 15 . The metal semiconductor composite layer 60 may contact the gate spacer 15 .

[0082] The source / drain region 21 d may include a base epitaxial region 24 , a first epitaxial region 27 d on the base epitaxial region 24 , and a second epitaxial region 54 d on the first epitaxial region 27 d . The metal semiconductor composite layer 60 may contact the base epitaxial region 24 .

[0083] The first epitaxial region 27d may have a recessed surface 27r.

[0084] The first epitaxial region 27 d may have a pointed upper end 27 t ′, and the recessed surface 27 r may be recessed from the upper end 27 t ′. The first epitaxial region 27 d may be spaced apart from the contact spacer 51 ′ and the gate spacer 15 .

[0085] The second epitaxial region 54d may be formed in a direction toward the channel region 6p (eg, Figure 1 The second epitaxial region 54d may extend from a portion overlapping the contact structure 57 in the vertical direction D1 (direction D2) and may overlap the contact spacer 51' and the gate spacer 15 in the vertical direction D3.

[0086] The second epitaxial region 54d may be spaced apart from the contact spacer 51 ′ and the gate spacer 15 . An upper surface 54dU of the second epitaxial region 54d may be disposed at a lower height level than an upper surface of the channel region 6p and a lower surface of the gate spacer 15 .

[0087] In reference Figure 3D In the modified example, with Figure 3C The contact spacer 51 'can be provided together with a replaceable Figure 3C The source / drain region 21d is the source / drain region 21e.

[0088] The source / drain region 21e may include a base epitaxial region 24, a Figure 3C The first epitaxial region 27d and the second epitaxial region 54e on the first epitaxial region 27d.

[0089] The upper surface 54eU of the second epitaxial region 54e may be disposed at a higher level than the upper surface of the channel region 6p and the lower surface of the gate spacer 15. The upper surface 54eU of the second epitaxial region 54e may be planar and parallel to the upper surface of the semiconductor substrate 3. The second epitaxial region 54e may be in contact with the contact spacer 51' and the gate spacer 15.

[0090] Next, we will refer to Figures 4A to 4C Various modified examples of the semiconductor device according to the example embodiment of the present disclosure are described. Figures 4A to 4C is an illustration describing various modified examples of the semiconductor device according to an exemplary embodiment of the present disclosure. Figure 2C Cross-sectional views of various modified examples of the cross-sectional structure.

[0091] In reference Figure 4A In the modified example, you can set it to replace Figure 2C The source / drain region 21a is the source / drain region 21f.

[0092] The source / drain region 21 f may include a base epitaxial region 24 , a first epitaxial region 27 on the base epitaxial region 24 , and a second epitaxial region 54 f on the first epitaxial region 27 .

[0093] An upper surface 54fU of the second epitaxial region 54f may be disposed at a higher height level than a lower surface of the contact spacer 51. The upper surface 54fU of the second epitaxial region 54f may have a convex shape in an upwardly rounded form.

[0094] In the second epitaxial region 54 f , a maximum width of a portion located at a lower height level than the lower end of the contact spacer 51 may be greater than a maximum width of a portion located at a higher height level than the lower end of the contact spacer 51 .

[0095] In reference Figure 4B In the modified example, you can set it to replace Figure 4A The source / drain region 21f is the source / drain region 21g.

[0096] The source / drain region 21 g may include a base epitaxial region 24 , a first epitaxial region 27 on the base epitaxial region 24 , and a second epitaxial region 54 g on the first epitaxial region 27 .

[0097] An upper surface 54gU of the second epitaxial region 54g may be disposed at a height level higher than a lower end of the contact spacer 51. The upper surface 54gU of the second epitaxial region 54g may have an upward pointed shape.

[0098] In reference Figure 4C In the modified example, you can set it to replace Figure 4A The source / drain region 21f is the source / drain region 21h.

[0099] The source / drain region 21 h may include a base epitaxial region 24 , a first epitaxial region 27 on the base epitaxial region 24 , and a second epitaxial region 54 h on the first epitaxial region 27 .

[0100] The upper surface 54hU of the second epitaxial region 54h may be disposed at a higher level than the lower end of the contact spacer 51. The upper surface 54hU of the second epitaxial region 54h may include a flat upper end and side surfaces inclined in a direction toward the contact spacer 51 from the flat upper end.

[0101] Next, we will refer to Figure 5 and Figure 6 Various modified examples of the semiconductor device according to the example embodiment of the present disclosure are described. Figure 5 and Figure 6 is an illustration for describing various modified examples of the semiconductor device according to an exemplary embodiment of the present disclosure. Figure 2A Cross-sectional views of various modified examples of the cross-sectional structure of .

[0102] In reference Figure 5 In the modified example, Figure 2AThe contact structure 57 may be replaced by a contact structure 57', and the contact structure 57' may include a lower region W1 having a first width, a middle region W2 having a second width smaller than the first width on the lower region W1, and an upper region W3 having a third width wider than the second width on the middle region W2. The first width of the lower region W1 may be the same as the third width of the upper region W3.

[0103] Can be set and replaced Figure 2A The contact spacer 51' of the contact spacer 51". The portion of the contact spacer 51" that contacts the portion with the smallest width of the middle region W2 of the contact structure 57' may have the maximum width. The portion of the contact spacer 51" that contacts the lower region W1 and the portion of the contact spacer 51" that contacts the upper region W3 may have the same width.

[0104] In reference Figure 6 In the modified example, Figure 2A The channel region 6p may be replaced by a plurality of active layers 6p', which are stacked on the active region 6 in the vertical direction D3 while being spaced apart from each other. Figure 2A The gate structure 36 is a gate structure 36a.

[0105] The gate structure 36 a may longitudinally extend in the second horizontal direction D2 while covering the upper surface, side surfaces, and lower surface of each of the plurality of active layers 6 p ′.

[0106] The gate structure 36 a may include a gate dielectric layer 39 a , a gate electrode 42 a , and a gate capping layer 45 a .

[0107] The gate electrode 42a can extend longitudinally in the second horizontal direction D2 while covering the upper surface, side surface and lower surface of each of the multiple active layers 6p', and the gate dielectric layer 39a can be interposed between the gate electrode 42a and the multiple active layers 6p', between the gate electrode 42a and the active region 6, and between the gate electrode 42a and the isolation layer 9, while covering the side surface of the gate electrode 42a.

[0108] In an example, an inner insulating spacer 34 may be further included between the source / drain regions 21a and the gate dielectric layer 39a and below each of the plurality of active layers 6p'. The inner insulating spacer 34 may be omitted.

[0109] refer to Figures 2A to 2C The upper surface of the channel region 6p described above can be regarded as the upper surface of the uppermost active layer among the plurality of active layers 6p'. Figure 1 as well as Figures 2A to 2CAs described above, when the upper surface of the uppermost active layer is regarded as a reference plane, the maximum depth of the recessed surface 27 r of the first epitaxial region 27 may be about 5 nm to about 50 nm.

[0110] Next, we will refer to Figure 7 and Figure 8 Modified examples of the semiconductor device according to the exemplary embodiment of the present disclosure are described. Figure 7 is a plan view showing a modified example of the semiconductor device according to the exemplary embodiment of the present disclosure, and Figure 8 is shown along Figure 7 A cross-sectional view of a region taken along line IIIa1–IIIa1′.

[0111] In reference Figure 7 and Figure 8 In a modified example, the semiconductor device 100 may include a plurality of active regions 106, which may replace the reference Figures 1 to 2C The active region described ( Figures 1 to 2C active region 6).

[0112] In an example, the active region 106 may be provided as two or more active regions.

[0113] Hereinafter, for convenience of description, an example in which the active region 106 includes a pair of a first active region and a second active region parallel to each other will be mainly described.

[0114] The semiconductor device 100 may include a gate structure 136, as shown in FIG. Figures 1 to 2C The gate structure 36 corresponds to the above.

[0115] The gate structure 136 may overlap the first active region and the second active region of the active region 106 , which are parallel to each other.

[0116] The gate structure 136 may be connected to the reference Figures 1 to 2C The gate structure 36 described is the same.

[0117] The semiconductor device 100 may further include an isolation layer 109 defining an active region 106 on the semiconductor substrate 103. The semiconductor substrate 103 and the isolation layer 109 may be respectively connected to the reference Figures 1 to 2C The semiconductor substrate 3 and the isolation layer 9 described are identical.

[0118] The semiconductor device 100 may further include a gate spacer 115 on the side surface of the gate structure 136. The gate spacer 115 may be formed by Figures 1 to 2C The gate spacer 15 is formed of the same material.

[0119] The semiconductor device 100 may further include an interlayer insulating layer 130 on the isolation layer 109, a source / drain region 121a overlapping the first active region and the second active region of the active region 106 and adjacent to the gate structure 136, a contact plug 163 on the source / drain region 121a, and a contact spacer 151 surrounding the side surface of the contact plug 163. The contact plug 163 may be disposed in a contact hole 148 passing through the interlayer insulating layer 130. The interlayer insulating layer 130 and the contact spacer 151 may be formed by contact holes 148 and 151, respectively. Figures 1 to 2C The interlayer insulating layer 30 and the contact spacer 51 are formed of the same material.

[0120] In the semiconductor device 100, a cross-sectional structure taken along the first horizontal direction D1 based on the center of each of the active regions 106 may be Figure 1 Therefore, in the semiconductor device 100, the cross-sectional structure taken along the line Ia-Ia' is the same. Figure 1 The cross-sectional structure taken along line Ia-Ia' (eg, Figure 2A It can be easily understood that the cross-sectional structure is a cross-sectional structure taken in the first horizontal direction D1 based on the center of each of the active regions 106, and thus a description thereof will be omitted.

[0121] The source / drain region 121a may be formed by Figures 2A to 2C The source / drain region 121a may be formed of the same material as the source / drain region 21a. For example, the source / drain region 121a may include: a base epitaxial region 124 formed on the first and second active regions of the active region 106, parallel to and spaced apart from each other; a first epitaxial region 127 in contact with the base epitaxial region 124, extending from a portion overlapping with the first active region to a portion overlapping with the second active region in the second horizontal direction D2; and a second epitaxial region 154 epitaxially grown from a recessed surface 127r of the first epitaxial region 127. The second epitaxial region 154 may extend from a portion overlapping with the first active region to a portion overlapping with the second active region in the second horizontal direction D2. For example, each of the first epitaxial region 127 and the second epitaxial region 154 may overlap with both the first and second active regions in the vertical direction D3.

[0122] An air gap 120 may be formed between the first epitaxial region 127 and the isolation layer 109 .

[0123] In an example, the lowest surface portion of the upper surface 154U of the second epitaxial region 154 may be located at a lower height level than the lower end of the contact spacer 151 .

[0124] The contact plug 157 may be formed by Figures 2A to 2CThe contact plug 157 may be formed of the same material as the contact structure 57 of the second epitaxial region 154. For example, the contact plug 157 may include a metal-semiconductor composite layer 160 in contact with the second epitaxial region 154, and a contact plug 163 on the metal-semiconductor composite layer 160. The contact plug 163 may include a first conductive layer 166 and a second conductive layer 169. The first conductive layer 166 may cover the lower surface and side surfaces of the second conductive layer 169 and contact the lower surface and side surfaces of the second conductive layer 169.

[0125] Next, we will refer to 9A to 9D Various modified examples of the semiconductor device according to the example embodiment of the present disclosure are described. 9A to 9D is an illustration for describing various modified examples of the semiconductor device according to an exemplary embodiment of the present disclosure. Figure 8 Cross-sectional views of various modified examples of the cross-sectional structure of .

[0126] In reference Figure 9A In the modified example, you can set it to replace Figure 8 The source / drain region 121a and the source / drain region 121b.

[0127] The source / drain region 121 b may include a base epitaxial region 124 , a first epitaxial region 127 on the base epitaxial region 124 , and a second epitaxial region 154 b on the first epitaxial region 127 .

[0128] The upper surface 154bU of the second epitaxial region 154b may be disposed at a height level higher than the lower end of the contact spacer 151. The upper surface 154bU of the second epitaxial region 154b may have a convex shape that is rounded upward. In the second epitaxial region 154b, the maximum width of a portion located at a height level lower than the lower end of the contact spacer 151 may be greater than the maximum width of a portion located at a height level higher than the lower end of the contact spacer 151.

[0129] In reference Figure 9B In the modified example, you can set it to replace Figure 8 The source / drain region 121a is connected to the source / drain region 121c.

[0130] The source / drain region 121 c may include a base epitaxial region 124 , a first epitaxial region 127 on the base epitaxial region 124 , and a second epitaxial region 154 c on the first epitaxial region 127 .

[0131] The upper surface of the second epitaxial region 154c may be disposed at a height level higher than the lower end of the contact spacer 151. The upper surface of the second epitaxial region 154c may include convex portions 154cU having an upwardly rounded form and downwardly recessed concave portions 154t between the rounded convex portions 154cU.

[0132] In reference Figure 9C In the modified example, you can set it to replace Figure 8 The source / drain region 121a is connected to the source / drain region 121d.

[0133] The source / drain region 121 d may include a base epitaxial region 124 , a first epitaxial region 127 on the base epitaxial region 124 , and a second epitaxial region 154 d on the first epitaxial region 127 .

[0134] The upper surface of the second epitaxial region 154d may be disposed at a higher level than the lower end of the contact spacer 151. The upper surface of the second epitaxial region 154d may include an upwardly pointed portion. Therefore, the upper surface of the second epitaxial region 154d may include: an inclined surface 154dU; an upwardly pointed portion 154dt1 where two inclined surfaces 154dU intersect each other at an upper position; and a downwardly pointed portion 154dt2 where two inclined surfaces 154dU intersect each other at a lower position.

[0135] In reference Figure 9D In the modified example, you can set it to replace Figure 8 The source / drain region 121a is connected to the source / drain region 121e.

[0136] The source / drain region 121 e may include a base epitaxial region 124 , a first epitaxial region 127 on the base epitaxial region 124 , and a second epitaxial region 154 e on the first epitaxial region 127 .

[0137] The upper surface of the second epitaxial region 154e may be disposed at a height level higher than the lower end of the contact spacer 151. The upper surface of the second epitaxial region 154e may include flat upper ends 154et1 spaced apart from each other, inclined surfaces 154e1 inclined downward from the flat upper ends 154e1, and downward pointed portions 154et2 formed where the inclined surfaces between the flat upper ends 154e1 intersect each other.

[0138] Next, we will refer to Figure 10 as well as Figures 11A to 11C Modified examples of the semiconductor device according to the exemplary embodiment of the present disclosure are described.

[0139] Figure 10 FIG. 11 is a plan view showing a modified example of the semiconductor device according to the exemplary embodiment of the present disclosure, and FIG. 12 is a plan view showing a modified example of the semiconductor device according to the exemplary embodiment of the present disclosure. Figure 10 A cross-sectional view of an area taken along line Ib-Ib' and an area taken along line IIb-IIb', Figure 11B It is magnified Figure 11A A partial enlarged view of the portion indicated by 'B', Figure 11Cis a diagram illustrating a semiconductor device according to an exemplary embodiment of the present disclosure. Figure 10 A cross-sectional view of the area cut off along line IIIb-IIIb'.

[0140] refer to Figures 10 to 11C The semiconductor device 200 may include: a semiconductor substrate 203 , an active region 206 and an isolation layer 209 on the semiconductor substrate 203 , and a channel region 206 p and source / drain regions 221 a on the active region 206 .

[0141] In an example, the active region 206 may be provided as a single active region (eg, see Figure 1 active region 6) or multiple active regions (see, for example, Figure 7 Hereinafter, the case where the active region 206 is provided as a plurality of active regions will be mainly described.

[0142] The isolation layer 209 may be a trench isolation layer defining the active region 206. The semiconductor substrate 203 and the isolation layer 209 may be formed of a substrate having a plurality of substrates. Figures 1 to 2C The semiconductor substrate 3 and the isolation layer 9 are formed of the same material.

[0143] In an example, the channel region 206p may extend in the vertical direction D3 from each of the active regions 206. Therefore, the channel region 206p may be provided as a plurality of channel regions.

[0144] When channel region 206 p is a channel region of an NMOS transistor, channel region 206 p may have P-type conductivity, and source / drain regions 221 a may have N-type conductivity.

[0145] The semiconductor device 200 may include: a gate structure 236, a gate spacer 215, an interlayer insulating layer 230, a contact hole 248, a contact structure 257 and a contact spacer 251, which are similar to the reference Figures 1 to 2C The gate structure 36, gate spacer 15, interlayer insulating layer 30, contact hole 48, contact structure 57 and contact spacer 51 correspond to each other and are formed of the same material. For example, the contact structure 257 may include a metal semiconductor composite layer 260 and a contact plug 263 including a first conductive layer 266 and a second conductive layer 269, which is the same as the reference numeral 264. Figures 1 to 2C The metal semiconductor composite layer 60 and the contact plug 63 including the first conductive layer 66 and the second conductive layer 69 correspond to each other. The metal semiconductor composite layer 260 may have a thickness of about 1 nm to about 10 nm in the vertical direction D3.

[0146] The semiconductor device 200 may include: Figures 1 to 2C The source / drain region 21a is a source / drain region 221a.

[0147] In the region between the active regions 206 , an air gap 220 may be provided between the source / drain regions 221 a and the isolation layer 209 .

[0148] The source / drain region 221a may include: a base epitaxial region 224 formed on the first and second active regions of the active region 206, parallel to and spaced apart from each other; a first epitaxial region 227 in contact with the base epitaxial region 224, extending from a portion overlapping with the first active region to a portion overlapping with the second active region in a second horizontal direction D2; and a second epitaxial region 254 epitaxially grown from a recessed surface 227r of the first epitaxial region 227. The second epitaxial region 254 may extend from a portion overlapping with the first active region to a portion overlapping with the second active region in the second horizontal direction D2. For example, each of the first epitaxial region 227 and the second epitaxial region 254 may overlap with both the first and second active regions in a vertical direction D3.

[0149] An air gap 220 may be formed between the first epitaxial region 227 and the isolation layer 109 .

[0150] Will refer to Figure 11B The source / drain region 221 a will be mainly described.

[0151] refer to Figure 11B , the source / drain regions 221 a may be disposed in the recessed regions 218 in the active region 206 and the channel region 206 p .

[0152] The source / drain regions 221 a may include N-type impurities, for example, phosphorus (P), arsenic (As), etc. The N-type impurities in the source / drain regions 221 a may have a concentration of 1E17 to 1E22 atoms / cc.

[0153] The source / drain regions 221 a may be a Si epitaxial layer. In another example, the source / drain regions 221 a may be a Si epitaxial layer including antimony (Sb) or carbon (C).

[0154] The base epitaxial region 224 may have a thickness that decreases toward the upper surface of the channel region 206p. Here, the thickness may refer to the distance from the outer surface of the base epitaxial region 224 (e.g., the surface in contact with the channel region 206p) to the inner surface of the base epitaxial region 224 (e.g., the surface in contact with the first epitaxial region 227). The base epitaxial region 224 may have a thickness in the vertical direction D3 below the lower surface of the first epitaxial region 227 of approximately 1 nm to approximately 40 nm.

[0155] In an example, the base epitaxial region 224 may be omitted.

[0156] In an example, the first epitaxial region 227 may have a thickness of about 1 nm to about 50 nm in the vertical direction D3 .

[0157] In an example, the second epitaxial region 254 may have a thickness of about 1 nm to about 50 nm in the vertical direction D3 .

[0158] In an example, the impurity concentration in the second epitaxial region 254 may be higher than the impurity concentration in the first epitaxial region 227 .

[0159] In an example, the impurity concentration in the first epitaxial region 227 may be higher than the impurity concentration in the base epitaxial region 224 .

[0160] In an example, when the upper surface of the channel region 206p or the lower surface of the gate spacer 215 is considered as a reference plane, the maximum depth of the recessed surface 227r of the first epitaxial region 227 may be approximately 5 nm to approximately 50 nm. For example, the maximum depth of the recessed surface 227r may be approximately 5 nm to approximately 50 nm below the reference plane defined by the lower surface of the gate spacer 215 or the upper surface of the channel region 206p.

[0161] The second epitaxial region 254 may include an extension 254p extending in the first horizontal direction D1 from a portion overlapping the contact structure 257 to a portion overlapping the contact spacer 251. For example, the extension 254p of the second epitaxial region 254 may overlap the contact structure 257 and the contact spacer 251 in the vertical direction D3.

[0162] The extension 254p of the second epitaxial region 254 may overlap the gate spacer 215 in the vertical direction D3. The extension 254p of the second epitaxial region 254 may be spaced apart from the gate spacer 215. The second epitaxial region 254 may be in contact with the lower end 251L of the contact spacer 251.

[0163] The first epitaxial region 227 may include a first lower epitaxial region 227L positioned below the extension 254p of the second epitaxial region 254, and a first upper epitaxial region 227U positioned above the extension 254p of the second epitaxial region 254. For example, the first lower epitaxial region 227L may be a portion of the first epitaxial region 227 formed at a vertical level lower than the extension 254p, and the first upper epitaxial region 227U may be a portion of the first epitaxial region 227 formed at a vertical level equal to or higher than the extension 254p. The first lower epitaxial region 227L and the first upper epitaxial region 227U may be connected to each other. For example, the first lower epitaxial region 227L and the first upper epitaxial region 227U may have material continuity with each other. The upper end 227t of the first epitaxial region 227 may contact the lower surface of the gate spacer 215.

[0164] In an example, a lowest surface portion of an upper surface 254U of the second epitaxial region 254 may be located at a lower height level than a lower end of the contact spacer 251. The upper surface 254U of the second epitaxial region 254 may be disposed at a lower height level than an upper surface of the channel region 206p.

[0165] Next, we will refer to 12A to 12C Various modified examples of the semiconductor device according to the example embodiment of the present disclosure are described. 12A to 12C is a diagram for describing various modified examples of the semiconductor device according to the exemplary embodiment of the present disclosure. Figure 11A The portion indicated by 'B' corresponds to the enlarged region of the partial enlarged view.

[0166] In reference Figure 12A In the modified example, you can set it to replace Figure 11B The source / drain region 221a and the source / drain region 221b.

[0167] The source / drain region 221 b may include a base epitaxial region 224 , a first epitaxial region 227 on the base epitaxial region 224 , and a second epitaxial region 254 b on the first epitaxial region 227 .

[0168] An upper surface 254U of the second epitaxial region 254 b may be disposed at a higher height level than an upper surface of the channel region 206 p .

[0169] In reference Figure 12B In the modified example, you can set and replace Figure 11B The source / drain regions 221 a and the contact spacers 251 and the source / drain regions 221 c and the contact spacers 251 ′.

[0170] A lower end 251L′ of the contact spacer 251 ′ may be disposed at a height level higher than a lower surface of the gate spacer 215 .

[0171] The source / drain region 221 c may include a base epitaxial region 224 , a first epitaxial region 227 on the base epitaxial region 224 , and a second epitaxial region 254 c on the first epitaxial region 227 .

[0172] An upper surface 254cU of the second epitaxial region 254c may be disposed at a lower height level than an upper surface of the channel region 206p.

[0173] In reference Figure 12C In the modified example, with Figure 12B The contact spacer 251' can be provided together with a replaceable Figure 11B The source / drain region 221a is connected to the source / drain region 221d.

[0174] The source / drain region 221d may include a base epitaxial region 224, a first epitaxial region 227 on the base epitaxial region 224, and a second epitaxial region 254d on the first epitaxial region 227. An upper surface 254dU of the second epitaxial region 254d may be disposed at a higher height level than an upper surface of the channel region 206p.

[0175] Next, we will refer to Figure 13 Various modified examples of the semiconductor device according to the example embodiment of the present disclosure are described. Figure 13 is an illustration for describing a modified example of the semiconductor device according to an exemplary embodiment of the present disclosure. Figure 11C sectional view of a modified example of the cross-sectional structure of .

[0176] refer to Figure 13 , can be set to replace Figure 11C The source / drain region 221a is connected to the source / drain region 221e.

[0177] The source / drain region 221 e may include a base epitaxial region 224 , a first epitaxial region 227 on the base epitaxial region 224 , and a second epitaxial region 254 e on the first epitaxial region 227 .

[0178] The upper surface 254eU of the second epitaxial region 254e may be disposed at a higher level than the lower surface of the contact spacer 251. The upper surface 254eU of the second epitaxial region 254e may have a convex shape that is rounded upward. In the second epitaxial region 254e, the maximum width of a portion located at a lower level than the lower end of the contact spacer 251 may be greater than the maximum width of a portion located at a higher level than the lower end of the contact spacer 251.

[0179] Next, we will refer to Figure 14 Modified examples of the semiconductor device according to the exemplary embodiment of the present disclosure are described. Figure 14 1 and 2 include diagrams for describing various modified examples of the semiconductor device according to the exemplary embodiment of the present disclosure. Figure 11A Cross-sectional views of various modified examples of the cross-sectional structure of .

[0180] In reference Figure 14 In the modified example, Figure 11A The channel region 206p may be replaced with a plurality of active layers 206p', which are stacked in the vertical direction D3 on the active region 206 while being spaced apart from each other. Figure 11A The gate structure 236 is a gate structure 236a.

[0181] The gate structure 236 a may extend in the second horizontal direction D2 while covering the upper surface, side surfaces, and lower surface of each of the plurality of active layers 206 p ′.

[0182] The gate structure 236a may include a gate dielectric layer 239a, a gate electrode 242a, and a gate cap layer 245a. The gate dielectric layer 239a, the gate electrode 242a, and the gate cap layer 245a may be connected to the reference Figure 6 The gate dielectric layer 39a, gate electrode 42a and gate cap layer 45a described correspond to each other.

[0183] In an example, an inner insulating spacer 234 between the source / drain region 221a and the gate dielectric layer 239a and below each of the plurality of active layers 206p' may be further included. The inner insulating spacer 234 may be omitted.

[0184] Next, a method of forming a semiconductor device according to an example embodiment of the present disclosure will be described. Figure 15 is a process flow diagram illustrating a method of forming a semiconductor device according to an example embodiment of the present disclosure; and Figures 16A to 18B is a cross-sectional view illustrating a method of forming a semiconductor device according to an exemplary embodiment of the present disclosure. Figures 16A to 18B middle, Figure 16A 、 Figure 17A and Figure 18A is shown along Figure 1 A cross-sectional view of an area taken along line Ia-Ia' and an area taken along line IIa-IIa', and Figure 16B 、 Figure 17B and Figure 18B yes Figure 1 sectional view of the region taken along line IIIa-IIIa'.

[0185] refer to Figure 15 、 Figure 16A and Figure 16B , an isolation layer 9 defining the active region 6 may be formed on the semiconductor substrate 3 .

[0186] In an example, the active region 6 may have a line shape or a strip shape extending longitudinally in the first horizontal direction D1 .

[0187] The first horizontal direction D1 may be parallel to the upper surface of the semiconductor substrate 3 .

[0188] In an example, the isolation layer 9 may be a trench isolation layer (shallow trench isolation layer). The isolation layer 9 may be formed of an insulating material (eg, silicon oxide, etc.).

[0189] In an example, the active region 6 may include a channel region 6 p located at a higher level than an upper surface of the isolation layer 9 .

[0190] The channel region 6p of the active region 6 may have N-type conductivity or P-type conductivity. For example, when the channel region 6p is a channel region of an NMOS transistor, the channel region 6p may have P-type conductivity. Alternatively, when the channel region 6p is a channel region of a PMOS transistor, the channel region 6p may have N-type conductivity.

[0191] A sacrificial structure 12 may be formed ( S10 ). The sacrificial structure 12 may cover the active region 6 and the isolation layer 9 on the semiconductor substrate 3 .

[0192] The sacrificial structure 12 may have a line shape or a bar shape longitudinally extending in a second horizontal direction D2 perpendicular to the first horizontal direction D1 .

[0193] The second horizontal direction D2 may be parallel to the upper surface of the semiconductor substrate 203 .

[0194] The sacrificial structure 12 may be provided as a plurality of sacrificial structures.

[0195] In an example, the sacrificial structure 12 may include polysilicon.

[0196] Gate spacers 15 may be formed on side surfaces of the sacrificial structure 12 .

[0197] The gate spacer 15 may be formed of a single material layer or a mixed material layer.

[0198] Source / drain recessed regions 18 may be formed ( S20 ). Forming source / drain recessed regions 18 may include etching the channel region 6 p of the active region 6 using an etching process using the sacrificial structure 12 and the gate spacer 15 as an etching mask. Source / drain recessed regions 18 may be formed in the channel region 6 p of the active region 6 .

[0199] A first epitaxial region 27 may be formed in the source / drain recess region 18 ( S30 ).

[0200] In another example embodiment, before forming the first epitaxial region 27 , a base epitaxial region 24 may be further formed, and the base epitaxial region 24 may be epitaxially grown from the surface of the source / drain recess region 18 of the channel region 6 p .

[0201] The first epitaxial region 27 may be epitaxially grown from a surface of the base epitaxial region 24 .

[0202] When channel region 6 p has N-type conductivity, base epitaxial region 24 and first epitaxial region 27 may be formed to have P-type conductivity.

[0203] In an example, the base epitaxial region 24 and the first epitaxial region 27 may form preliminary source / drain regions 21 .

[0204] refer to Figure 15 、 Figure 17Aand Figure 17B An interlayer insulating layer 30 may be formed (S40). The interlayer insulating layer 30 may cover the preliminary source / drain regions 21 and the isolation layer 9 while being adjacent to the sacrificial structure 12. The interlayer insulating layer 30 may be formed of an insulating material (eg, silicon oxide).

[0205] The gate structure 36 may be replaced Figure 16A and 16B The sacrificial structure 12 is formed (S50).

[0206] Replaced by gate structure 36 Figure 16A and 16B The sacrificial structure 12 may include: forming a gate trench 33 by selectively removing the sacrificial structure 12 , and forming a gate structure 36 in the gate trench 33 .

[0207] Forming the gate structure 36 in the gate trench 33 may include: forming a gate dielectric layer 39 covering the inner wall of the gate trench 33; forming a gate electrode 42 on the gate dielectric layer 39 to partially fill the gate trench 33; and forming a gate cap layer 45 on the gate electrode 42 to fill the remaining portion of the gate trench 33.

[0208] refer to Figure 15 、 Figure 18A and Figure 18B Then, a contact hole 48 may be formed ( S60 ). The contact hole 48 may expose the preliminary source / drain region 21 while passing through the interlayer insulating layer 30 .

[0209] Contact spacers 51 may be formed on sidewalls of the contact holes 48 ( S70 ).

[0210] The first epitaxial region 27 of the preliminary source / drain region 21 is partially etched to form a recessed surface 27 r of the first epitaxial region 27 .

[0211] In an example, the recessed surface 27 r may be spaced apart from a lower end of the contact spacer 51 .

[0212] Combine Figure 15 ,refer to Figure 1 、 Figure 2A 、 Figure 2B and Figure 2C A second epitaxial region 54 epitaxially grown from the recessed surface 27 r may be formed ( S90 ). The second epitaxial region 54 , the first epitaxial region 27 , and the base epitaxial region 24 may form the source / drain region 21 a .

[0213] A contact structure 57 may be formed ( S100 ). The contact structure 57 may fill the contact hole 48 . The contact structure 57 may include a metal semiconductor composite layer 60 contacting the second epitaxial region 54 of the source / drain region 21 a and a contact plug 63 on the metal semiconductor composite layer 60 .

[0214] Forming the contact structure 57 may include forming a metal semiconductor composite layer 60 in contact with the second epitaxial region 54 of the source / drain region 21 a by performing a silicide process; and forming a contact plug 63 filling the contact hole 48 on the metal semiconductor composite layer 60 .

[0215] Forming the contact plug 63 may include forming a first conductive layer 66 covering the inner wall of the contact hole 48 ; and forming a second conductive layer 69 filling the contact hole 48 on the first conductive layer 66 .

[0216] As described above, according to an example embodiment of the present invention, the source / drain region may include a base epitaxial region, a first epitaxial region on the base epitaxial region, and a second epitaxial region on the first epitaxial region. The second epitaxial region may be a stressor that can apply stress to the channel region to improve charge mobility. The second epitaxial region may be spaced apart from the channel region and may be in contact with the contact plug. Because the impurity concentration of the second epitaxial region in the source / drain region is the highest, degradation of the channel region due to impurities in the source / drain region can be prevented, while the contact resistance between the source / drain region and the contact plug can be significantly reduced. Therefore, the performance of the transistor can be improved.

[0217] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor device comprising: an isolation layer defining a first active region on the semiconductor substrate; an interlayer insulating layer on the isolation layer; a channel region on the first active region; a source / drain region, on the first active region and adjacent to the channel region in a first horizontal direction; a gate structure on the channel region, overlapping the channel region and extending longitudinally in a second horizontal direction perpendicular to the first horizontal direction; a contact structure on the source / drain region; a gate spacer between the contact structure and the gate structure; as well as a contact spacer disposed between the contact structure and the gate spacer in the first horizontal direction and between the contact structure and the interlayer insulating layer in the second horizontal direction, Wherein, the contact spacer is formed of an insulating material, wherein the lower end of the contact spacer is at a lower height level than the lower end of the gate spacer, The contact structure includes a metal-semiconductor composite layer and a contact plug on the metal-semiconductor composite layer. The source / drain region includes: a base epitaxial region, a first epitaxial region on the base epitaxial region and having a recessed surface, and a second epitaxial region on the recessed surface of the first epitaxial region. wherein the uppermost surface of the base epitaxial region is at the same height level as the uppermost surface of the first epitaxial region, or at a height level higher than the uppermost surface of the first epitaxial region, wherein the uppermost surface of the base epitaxial region is disposed below the lower surface of the gate spacer, vertically overlaps with the gate spacer, and does not vertically overlap with the contact spacer; Wherein, the upper surface of the second epitaxial region is in contact with the metal-semiconductor composite layer, The second epitaxial region includes an extension portion extending longitudinally in the first horizontal direction from a portion overlapping with the contact structure in the vertical direction to a portion overlapping with the contact spacer in the vertical direction, and Wherein, the vertical direction is perpendicular to the upper surface of the semiconductor substrate.

2. The semiconductor device according to claim 1, in, The source / drain region has P-type conductivity, Wherein, the base epitaxial region and the first epitaxial region include silicon Si elements and germanium Ge elements, and The concentration of Ge in the first epitaxial region is higher than the concentration of Ge in the base epitaxial region.

3. The semiconductor device according to claim 2, wherein The second epitaxial region includes a Ge element, and a concentration of the Ge element is higher than a concentration of the Ge element in the first epitaxial region.

4. The semiconductor device according to claim 2, wherein The first epitaxial region further includes an upper end contacting a lower surface of the gate spacer.

5. The semiconductor device according to claim 2, wherein The extension of the second epitaxial region is spaced apart from the base epitaxial region. The semiconductor device according to claim 2 , wherein: The extension of the second epitaxial region is in contact with the base epitaxial region.

7. The semiconductor device according to claim 1, wherein The first epitaxial region is divided into a first lower epitaxial region and a first upper epitaxial region by the extension of the second epitaxial region.

8. The semiconductor device according to claim 1, wherein The extending portion of the second epitaxial region overlaps the gate spacer in the vertical direction.

9. The semiconductor device according to claim 1, wherein A lower surface of the contact structure is disposed at a lower height level than a lower end of the gate spacer.

10. The semiconductor device according to claim 1, wherein A lower surface of the contact structure is disposed at a higher height level than a lower end of the gate spacer.

11. The semiconductor device according to claim 1, wherein An upper surface of the first epitaxial region is disposed at a lower height level than an upper surface of the second epitaxial region.

12. The semiconductor device according to claim 1, wherein The contact structure includes a lower region having a first width, a middle region on the lower region and having a second width smaller than the first width, and an upper region on the middle region and having a third width wider than the second width.

13. The semiconductor device according to claim 1, in, The channel region extends from the first active region in the vertical direction, and The gate structure extends longitudinally in the second horizontal direction and covers the upper surface and side surfaces of the channel region.

14. The semiconductor device according to claim 1, in, The channel region includes: a plurality of active layers stacked in the vertical direction on the first active region and spaced apart from each other, and The gate structure extends longitudinally in the second horizontal direction and covers the upper surface, the side surface and the lower surface of each of the plurality of active layers.

15. The semiconductor device according to claim 1, further comprising: a second active region on the semiconductor substrate parallel to the first active region, Wherein, the gate structure overlaps with the first active area and the second active area, wherein the first epitaxial region extends from a portion overlapping with the first active region to a portion overlapping with the second active region in the second horizontal direction, and The second epitaxial region extends from a portion overlapping with the first active region to a portion overlapping with the second active region in the second horizontal direction.

16. A semiconductor device comprising: an active region on a semiconductor substrate; a channel region on the active region; a source / drain region on the active region adjacent to the channel region; a gate structure on the channel region and overlapping the channel region; a contact structure on the source / drain region; a gate spacer between the contact structure and the gate structure; as well as a contact spacer surrounding a side surface of the contact structure, a lower end of the contact spacer being at a lower height level than a lower end of the gate spacer, Wherein, the contact spacer is formed of an insulating material, The source / drain region includes a base epitaxial region, a first epitaxial region on the base epitaxial region, and a second epitaxial region on the first epitaxial region. Wherein, the source / drain region includes Si element and Ge element, wherein the Ge element concentration in the base epitaxial region, the Ge element concentration in the first epitaxial region, and the Ge element concentration in the second epitaxial region are different from each other, The second epitaxial region includes an extension portion extending in a horizontal direction from a portion overlapping with the contact structure in a vertical direction to a portion overlapping with the contact spacer in the vertical direction, wherein the second epitaxial region is spaced apart from the channel region, wherein a portion of the base epitaxial region is between the second epitaxial region and the channel region, and The uppermost surface of the base epitaxial region is arranged below the lower surface of the gate spacer, vertically overlaps with the gate spacer, and does not vertically overlap with the contact spacer.

17. The semiconductor device according to claim 16, in, The contact structure includes a metal-semiconductor composite layer and a contact plug on the metal-semiconductor composite layer. Wherein, the metal semiconductor composite layer is in contact with the second epitaxial region, The Ge element concentration in the first epitaxial region is higher than the Ge element concentration in the base epitaxial region, and The Ge element concentration in the second epitaxial region is higher than the Ge element concentration in the first epitaxial region.

18. A semiconductor device comprising: an active region on a semiconductor substrate; a channel region on the active region; a source / drain region on the active region adjacent to the channel region; a gate structure on the channel region and overlapping the channel region; a contact structure on the source / drain region; a gate spacer between the contact structure and the gate structure; as well as a contact spacer surrounding a side surface of the contact structure, a lower end of the contact spacer being at a lower height level than a lower end of the gate spacer, Wherein, the contact spacer is formed of an insulating material, The source / drain region includes: a base epitaxial region, a first epitaxial region having a recessed surface and on the base epitaxial region, and a second epitaxial region on the recessed surface of the first epitaxial region. The second epitaxial region includes an extension portion extending in a horizontal direction from a portion overlapping with the contact structure in a vertical direction to a portion overlapping with the contact spacer in the vertical direction, and wherein the extension portion of the second epitaxial region overlaps the gate spacer in the vertical direction, and The uppermost surface of the base epitaxial region is arranged below the lower surface of the gate spacer, vertically overlaps with the gate spacer, and does not vertically overlap with the contact spacer.

19. The semiconductor device according to claim 18, in, The channel region includes: a plurality of active layers stacked in the vertical direction on the active region and spaced apart from each other, The gate structure covers the upper surface, side surface and lower surface of each of the plurality of active layers, and The maximum depth of the recessed surface of the first epitaxial region is 5 nm to 50 nm, and the upper surface of the uppermost active layer among the plurality of active layers is regarded as a reference plane.

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