Arrangement of memory cells in a quantum computing device

Abstract

Disclosed herein is an array of interconnected memory cells for storing fractional quantum Hall effect droplets therein, the state of which can be controlled using voltages applied to the cell electrodes. In example embodiments, the memory cells are arranged and linked together, such as to reduce the geometric size of the array, such as compared to the geometric size of a linear array having the same number of memory cells. For example, one or more spoke arrangements of the memory cells may be used for this purpose. The smaller geometric size of the array may result in better coherence across the droplets confined therein, which may be advantageously used to improve the reliability and / or performance of a corresponding quantum computing device.

Description

[0001] CROSS REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 751,078, filed on October 26, 2018, and entitled “ARRANGEMENT OF MEMORY CELLS FOR AQUANTUM-COMPUTING DEVICE,” which is incorporated herein by reference in its entirety. Technical Field

[0003] Various example embodiments relate to quantum computing. Background Art

[0004] This section introduces aspects that may help facilitate a better understanding of the present invention. Therefore, the statements in this section should be read in light of this and should not be understood as an admission as to what is or is not in the prior art.

[0005] Quantum computing devices have been made or proposed based on various technologies, such as superconducting junction devices, ion trap devices, and fractional quantum Hall effect (FQHE) devices. Quantum computing devices typically use memory to store states and use hardware to write the states to and read the states from the memory. Reliable methods for writing to and reading from memory are useful for various types of quantum computing devices.

[0006] For example, it has been shown that FQHE states associated with filling factors of 5 / 2 and 3 / 5 may be useful for quantum computing devices. For some such states, interferometric devices have been proposed to define FQHE states, change the states, and perform computations using the states. That is, interferometric devices can be used to write and read quantum bits (commonly referred to as qubits) and enable interactions so that different qubits can be manipulated for quantum computing, such as in quantum gates. Summary of the invention

[0007] Various embodiments of an array of interconnected memory cells for storing fractional quantum Hall effect droplets therein, the state of which can be controlled using voltages applied to the cell electrodes, are disclosed herein. In example embodiments, the memory cells are arranged and linked together, such as to reduce the geometric size of the array, such as compared to the geometric size of a linear array having the same number of memory cells. For example, one or more spoke or star arrangements of the memory cells may be used for this purpose. The smaller geometric size of the array may result in better coherence across the droplets confined therein, which may be advantageously used to improve the reliability and / or performance of a corresponding quantum computing device.

[0008] According to an example embodiment, an apparatus is provided that includes: a substrate having a semiconductor quantum well structure along a planar surface of the substrate; a plurality of memory cells along the planar surface of the substrate, each of the memory cells having a first pattern of controllable electrodes on the planar surface of the substrate, the electrodes of the first pattern defining a sequence of three or more lateral regions of the semiconductor quantum well structure joined by intra-cell channels; and one or more memory cell connectors on the substrate, each of the one or more memory cell connectors having a respective second pattern of controllable electrodes on the planar surface of the substrate to define selectable inter-cell channel connections for at least some of the memory cells; and wherein the electrodes of the first and second patterns are controllable to deplete lateral regions of the quantum well structure of charge carriers such that droplets of the charge carriers in the semiconductor quantum well structure are laterally localized along the planar surface, with respective portions of the droplets being localized in each of the three or more memory cells and each of the one or more memory cell connectors. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Other aspects, features and benefits of the various disclosed embodiments will become more apparent from the following detailed description and accompanying drawings, by way of example, in which:

[0010] Figure 1 A schematic top view of a memory cell that can be used in a quantum computing device for a single qubit based on FQHE according to an embodiment is shown;

[0011] Figure 2 A schematic diagram showing a memory cell that can be used in a quantum computing device according to another embodiment;

[0012] Figure 3 Showing a device having a plurality of connected devices according to an embodiment Figure 2 A schematic diagram of a memory cell array having a plurality of memory cells;

[0013] Figure 4 Showing another embodiment of the invention having a plurality of Figure 2 A schematic diagram of a memory cell array having a plurality of memory cells;

[0014] Figure 5 Showing a device having a plurality of connected devices according to yet another embodiment Figure 2 a schematic diagram of a memory cell array having a plurality of memory cells; and

[0015] Figure 6 Showing a device having a plurality of connected devices according to yet another embodiment Figure 2Schematic diagram of a memory cell array having a plurality of memory cells. DETAILED DESCRIPTION

[0016] Some embodiments may benefit from at least some of the features disclosed in U.S. Pat. Nos. 8,324,120, 8,987,703, and 8,633,092 and in the revised edition of the paper “Non-Abelian Anyons and Topological Quantum Computation” by Chetan Nayak, Steven H. Simon, Ady Stern, et al., Phys., Vol. 80, 2008, pp. 1083-1155, all of which are incorporated herein by reference in their entirety.

[0017] Various memories for storing, reading, and manipulating qubits herein are based on laterally confined droplets of 2-dimensional (2D) charge carrier gas (2DCCG) (e.g., electron gas or hole gas positioned in a quantum well), which are maintained in a special FQHE state. Typically, the charge carrier gas in the FQHE state is maintained to have a fixed Landau level filling factor of, for example, 5 / 2, 12 / 5, or 3 / 5 for the laterally confined droplets of the 2D charge carrier gas in a transverse magnetic field. The FQHE state is generated by subjecting the 2DCCG to a perpendicular magnetic field at a suitable low temperature (e.g., below 150 mK). The corresponding cooling system may include, for example, a He-based dilution refrigerator. The magnetic field strength may be about 5 Tesla or greater, which may be generated in a conventional manner, such as a superconducting magnet.

[0018] In the following, Figure 1 and 2 An example of a memory cell for storing, manipulating, and reading a single qubit is described.

[0019] Figure 1 A schematic top view of a memory cell 10 for a single qubit based on FQHE that can be used in a quantum computing device according to an embodiment is shown. The memory cell 10 includes an electrode pattern (on or above the top surface of a planar semiconductor quantum well structure) Figure 1 The top surface generally extends perpendicular to the stacking direction of the semiconductor layers in the planar semiconductor quantum well structure. Parts of the electrode pattern may be on the surface, and other parts of the electrode pattern may be close to and above the surface, but for simplicity, the top surface is shown in FIG. Figure 1 Shown on the top surface.

[0020] The planar semiconductor quantum well structure is configured only to vertically trap a 2D CCG gas, such as an electron gas. For example, the planar semiconductor quantum well structure may have a 2D gallium nitride (GaN) well region vertically surrounded by an aluminum gallium nitride (AlGaN) barrier layer and may have other layers that carry dopants to provide charge carriers to the well region. The planar semiconductor quantum well structure may also have a more complex multi-quantum well structure to better screen defects associated with charged dopant atoms, for example, may include a narrower screening quantum well surrounding the main quantum well, and / or the planar semiconductor quantum well structure may be based on different semiconductor alloy layers.

[0021]

[0013] The above-referenced US Patents Nos. 8,324,120, 8,987,703, and 8,633,092 describe examples of planar semiconductor quantum well structures that may be used in at least some embodiments.

[0022] In the memory cell 10, the electrode pattern is formed by a metal gate pattern, which may be voltage biased to deplete the region below the electrode pattern of the 2D CCG gas and thereby provide a voltage between the electrodes for lateral confinement of a 2D droplet of the 2D CCG gas. The upper and lower edges of the 2D droplet, labeled U and L, respectively, are indicated by Figure 1 In the memory cell 10, the metal gate essentially laterally surrounds three separate lateral regions 1, 2, 3 for storing and manipulating a single qubit.

[0023] In an alternative embodiment, additional metal gates may be used to substantially surround three or more separate lateral regions similar to lateral regions 1, 2, 3. An example of this alternative embodiment is shown in FIG. Figure 2 This is described in more detail below.

[0024] exist Figure 1 In the embodiment shown in , the metal gate pattern includes a top electrode T′, a bottom electrode B′, and channel electrodes A, B, C, D, E, F, G, and H.

[0025] In each of the three regions 1, 2, 3, the voltage bias of the top electrode T' and the bottom electrode B' and the channel electrodes A to H can be used to deplete the underlying and adjacent regions of the charge carriers of the 2D gas, thereby substantially defining the lateral extension of the droplet of the 2DCCG gas along the top surface of the planar semiconductor quantum well structure. In practice, the bias of the electrodes T', B' can generally be varied to move the upper edge U and lower edge L of the droplet of the 2DCCG gas. The horizontal boundaries of the lateral regions 1, 2, 3 are defined by the bias of the channel electrodes A to H having narrow channels between their facing pairs. Obviously, the voltage bias of the facing pairs (A, B), (C, D), (E, F), and (G, H) of the channel electrodes can be adjusted to narrow or widen one or more of the channels. Narrowing one or more of the channels enables edge excitations to tunnel between the upper edge U and the lower edge L of the droplet when the laterally confined droplet at the channel is maintained in a substantially incompressible FQHE state. Furthermore, charges may thus be enabled to tunnel between the U edge and the L edge of the droplet.

[0026] In some embodiments, one or more small or point electrodes (not shown) may be positioned between each or some of the facing pairs of channel electrodes (i.e., (A, B), (C, D), (E, F), and (G, H)) to enable control of tunneling of charge and / or edge excitation therebetween. The small or point electrodes may also be individually voltage biased to facilitate better control of the tunneling.

[0027] Each region 1, 2, 3 also has at least one small electrode S, for example, a point-shaped or disk-shaped electrode at its interior. The small electrode S may contact or be slightly above the top surface of the planar semiconductor quantum well structure. The small electrode S enables storing a specific excitation of an appropriate FQHE state in a group of adjacent regions 1, 2, 3 by applying an appropriate voltage bias.

[0028]

[0013] U.S. Patent Nos. 8,324,120, 8,987,703, and 8,633,092, cited above, describe example electrode patterns that may be used in some embodiments to cause a corresponding 2DCCG gas to be in the proper FQHE state.

[0029] The memory cell 10 may further include a pair of left measuring electrodes (5, 5') and a pair of right measuring electrodes (7, 7') that can be used to measure the current between the upper edge U and the lower edge L of the droplet carried by the 2DCCG gas on the respective left and right sides of the memory cell 10. The measuring electrodes 5, 5', 7, 7' may have various suitable shapes and positions.

[0030] In some other embodiments, a single qubit memory cell may include at least four separate regions for laterally confining a portion of a droplet of 2DCCG gas along the top surface of a corresponding planar semiconductor quantum well structure. Each of the four or more separate regions typically includes a respective top electrode T' and bottom electrode B' for controlling the upper edge U and lower edge L of the droplet by voltage bias, as already described with reference to Figure 1 Each of the four or more separate regions has a corresponding channel at its opposite side, and each channel is composed of, for example, a similar Figure 1 The faces of the channel electrodes (A, B), (C, D), (E, F), and (G, H) are controlled. For four or more regions, in the neighboring regions, the portions of the droplets of 2DCCG gas are connected by the channels between the neighboring regions. Moreover, each of the four or more regions may include in its interior a corresponding small electrode that may be charged, such as a Figure 1 The electrode S.

[0031] Example methods of operating the memory cell 10 are described in U.S. Provisional Patent Application No. 62 / 751,253, filed on October 26, 2018 and entitled “KEY-BASED MULTI-QUBIT MEMORY”, which is incorporated herein by reference in its entirety. Based on the disclosure of the present application, one of ordinary skill in the relevant art will be able to adapt those methods for operating a memory cell having four or more separate regions for laterally confining a portion of a droplet of 2DCCG gas without any undue experimentation.

[0032] Figure 2 A schematic diagram of a memory cell 200 for a single qubit based on FQHE that can be used in a quantum computing device is shown according to another embodiment. More specifically, Figure 2 The schematic diagram schematically represents a similar Figure 1 A top view of a memory cell 200 is shown in FIG.

[0033] The memory cell 200 and the memory cell 10 ( Figure 1 ) in that memory cell 200 includes four separate regions, labeled 1 to 4, for laterally confining portions of droplets of 2DCCG gas along the top surface of the corresponding planar semiconductor quantum well structure. Memory cell 200 may be improved, for example, by adding lateral region 4 and corresponding electrodes T', B', I, J, and S to memory cell 10 ( Figure 1 Similar to memory cell 10, memory cell 200 may be configured to support a single qubit.

[0034] For example, regions 1 and 2 of memory cell 200 may be configured to support a first topological quantum state, such as |0>. Regions 3 and 4 of memory cell 200 may be similarly configured to support a second topological quantum state, such as |1>. The first and second topological quantum states may be entangled such that regions 1-4 may together support a superposition quantum state |m>=α|0>+β|1>, where (i) the filling factor 5 / 2 is continuous throughout regions 1-4 and (ii) charge may move in unison along the upper edge U and lower edge L of a droplet laterally confined within regions 1-4 (see also Figure 1 ).

[0035] In the following, Figure 3 An example arrangement of coupled memory cells for storing, manipulating, and reading multiple qubits is illustrated. The arrangement is a sequence (eg, a linear array) of single-qubit memory cells.

[0036] Figure 3 A schematic diagram of a memory cell array 300 according to an embodiment is shown. The array 300 includes Figure 3 The two memory cells 200 ( Figure 2 ). Array 300 further includes a connector 310 that connects memory cells 2001 and 2002 so that (i) the fill factor 5 / 2 is continuous throughout memory cells 2001 and 2002 and connector 310 and (ii) charge can move uniformly along the edge of the 2DCCG droplet that is laterally confined within memory cells 2001 and 2002 and connector 310.

[0037] In an example embodiment, connector 310 may be implemented using (i) a quantum well structure similar to that of memory cell 200 and (ii) electrodes 312 and 314 configured to laterally confine a portion of a 2DCCG droplet positioned in the connector. Electrodes 312 and 314 may be similar to, for example, the top electrode T' and bottom electrode B' of memory cell 10 or 200, respectively. Due to the presence of connector 310, the qubits |m1> and |m2> supported in memory cells 2001 and 2002, respectively, may be entangled such that array 300 may support an entangled quantum state |M>=γ|m1>+δ|m2>.

[0038] One of ordinary skill in the art will appreciate that array 300 can be expanded, for example, by connecting more than two memory cells 200 together in a linear geometric arrangement using one or more additional instances (nominal replicas) of connector 310. For a particular number of cells 200 connected in this manner, the resulting linear array can be used to provide reliable entanglement and manipulation of the qubits supported in the connected cells. However, as the number of connected cells 200 increases, the resulting larger linear size of the corresponding linear array can cause some loss of coherence, for example, across 2DCCG droplets, thereby degrading the reliability and / or performance of the corresponding larger array.

[0039] For example, the following reference Figures 4 to 6 At least some of the embodiments described in more detail address this problem and other possible related problems in the state-of-the-art. In example embodiments, a plurality of memory cells 200 are arranged and linked together, e.g., to reduce the geometry of the resulting array, e.g., as compared to the geometry of a linear array having the same number of memory cells 200. Advantageously, the smaller geometry of the corresponding array can result in better coherence across the entire 2DCCG droplet confined therein, which can be used to improve the reliability and / or performance of the corresponding memory as a quantum computing device.

[0040] Figure 4 A schematic diagram of a memory cell array 400 according to another embodiment is shown. The array 400 includes Figure 4 The four memory cells 200 ( Figure 2 ). Array 400 further includes a connector 410 that connects memory cells 2001-2004 so that (i) the fill factor 5 / 2 is continuous throughout the memory cells 2001-2004 and connector 410 and (ii) charge can move uniformly along the edge of the 2DCCG droplet that is laterally confined within the memory cells 2001-2004 and connector 410.

[0041] In an example embodiment, connector 410 may be implemented using (i) a quantum well structure similar to that of memory cell 200 and (ii) electrodes 412-418 configured to laterally confine a portion of a 2DCCG droplet positioned in the connector. Electrodes 412-418 may be similar to, for example, electrodes T' and / or B' of memory cell 10 or 200. Due to the presence of connector 410, the qubits |m1>, ..., |m4> supported in memory cells 2001-2004, respectively, may be entangled such that array 400 may support corresponding entangled quantum states.

[0042] The geometric arrangement of the memory cells 2001-2004 and connectors 410 in the array 400 can be illustratively similar to a four-spoke wheel, where the connector 410 is geometrically similar to the axle of the wheel, and the memory cells 2001-2004 are geometrically similar to the four spokes of the wheel extending outward from the axle along the radius of the wheel. In this geometric arrangement, the angle between two adjacent memory cells 200 is approximately 90 degrees.

[0043] Figure 5 A schematic diagram of a memory cell array 500 according to yet another embodiment is shown. The array 500 includes Figure 5 The eight memory cells 200 ( Figure 2 ). The array 500 further includes a connector 510 that connects the memory cells 2001-2008 so that (i) the fill factor 5 / 2 is continuous throughout the memory cells 2001-2008 and the connector 510 and (ii) charge can move uniformly along the edge of the 2DCCG droplet that is laterally confined within the memory cells 2001-2008 and the connector 510.

[0044] In an example embodiment, connector 510 may be implemented using (i) a quantum well structure similar to that of memory cell 200 and (ii) electrodes 512-526 configured to laterally confine a portion of a 2DCCG droplet positioned in the connector. Electrodes 512-526 may be similar to, for example, electrodes T' and / or B' of memory cell 10 or 200. Due to the presence of connector 510, the qubits |m1>, ..., |m8> supported in memory cells 2001-2008, respectively, may be entangled such that array 500 may support corresponding entangled quantum states.

[0045] The geometric arrangement of memory cells 2001-2008 and connectors 510 in array 500 can be illustratively similar to an eight-spoke wheel, where connector 510 is geometrically similar to the axle of the wheel, and memory cells 2001-2008 are geometrically similar to the eight spokes of the wheel extending outward from the axle. In this geometric arrangement, the angle between two adjacent memory cells 200 is approximately 45 degrees.

[0046] exist Figure 4 and 5 A person of ordinary skill in the art will understand how to make and use a memory cell array having any number of memory cells 200 in a spoke arrangement, such as in the range from three to sixteen.

[0047] Figure 6 A schematic diagram of a memory cell array 600 according to yet another embodiment is shown. The array 600 includes Figure 6 The four arrays 500 ( Figure 2 ). The array 600 further includes Figure 6 3101-3103 interconnecting arrays 5001-5004 as indicated in FIG. 3102. More specifically, connector 3101 directly connects arrays 5001 and 5002. Connector 3102 directly connects arrays 5002 and 5003. Connector 3103 directly connects arrays 5002 and 5004. The connections are such that (i) the fill factor 5 / 2 is continuous throughout the arrays 5001-5004 and connectors 3101-3103 and (ii) charge can move in unison along the edge of a 2DCCG droplet that is laterally confined within the arrays 5001-5004 and connectors 3101-3103.

[0048] exist Figure 6 , those of ordinary skill in the art will understand how to make and use memory cell arrays having a different number of arrays 500 including memory cells 200, or a desired number of arrays 400, or a desired number of other suitable arrays.

[0049] According to the example embodiments disclosed above, for example, in the Summary section and / or with reference to Figures 1 to 6 A device is provided, comprising: a substrate having a semiconductor quantum well structure; a plurality of memory cells (e.g., Figure 2 200), each of the memory cells having a first pattern of controllable electrodes on the top surface of the substrate, the electrodes of the first pattern laterally defining four lateral regions (e.g., Figure 2 1 to 4); and one or more memory cell connectors on the substrate (e.g., Figure 3 , 6 of 310; Figure 4 of 410; Figure 5 , 6510), each of the memory cell connectors has a respective second pattern of controllable electrodes on the top surface of the substrate to define a respective inter-cell channel connecting at least two of the memory cells; and wherein the electrodes of the first and second patterns are controllable to deplete lateral regions of the quantum well structure of charge carriers such that fractional quantum Hall effect droplets of the charge carriers are laterally localized in the semiconductor quantum well structure, wherein different respective portions of the droplets are localized in each of the memory cells and each of the one or more memory cell connectors; and wherein the one or more memory cell connectors include a first memory cell connector configured to directly connect at least three of the memory cells (e.g., Figure 4 of 410; Figure 5 510).

[0050] According to the above, for example in the Summary of the Invention section and / or references Figures 1 to 6 Another example embodiment disclosed in any one or any combination of part or all of the disclosure provides an apparatus comprising: a substrate having a semiconductor quantum well structure; a plurality of memory cells (e.g., Figure 2 200), each of the memory cells having a first pattern of controllable electrodes on a top surface of the substrate, the electrodes of the first pattern defining four lateral regions of the semiconductor quantum well structure joined by intra-cell channels (e.g., Figure 2 1 to 4); and one or more memory cell connectors on the substrate (e.g., Figure 4 of 410; Figure 5 , 6 510), each of the one or more memory cell connectors has a corresponding second pattern of controllable electrodes on the top surface of the substrate to define optional inter-cell channel connections for at least three of the memory cells; and wherein the electrodes of the first and second patterns are controllable to deplete lateral regions of the quantum well structure of charge carriers so that droplets of charge carriers in the semiconductor quantum well structure are laterally localized along the top surface, wherein corresponding portions of the droplets are localized in each of the memory cells and each of the one or more memory cell connectors.

[0051] In some embodiments of the above apparatus, a first one of the one or more memory cell connectors (e.g., Figure 4 410) is configurable to directly connect at least four of the memory cells.

[0052] According to the above, for example in the Summary section and / or reference Figures 1 to 6According to the example embodiments disclosed in any one or any combination of part or all of the disclosures, there is provided an apparatus comprising: a substrate having a semiconductor quantum well structure along a surface thereof; a plurality of memory cells (e.g., Figure 2 200), each of the memory cells having a first pattern of controllable electrodes on the surface of the substrate, the electrodes of the first pattern laterally defining three or more lateral regions of the semiconductor quantum well structure joined by channels (e.g., Figure 2 1 to 4); and one or more memory cell connectors on the substrate (e.g., Figure 4 of 410; Figure 5 , 6 510), each of the one or more memory cell connectors has a corresponding second pattern of controllable electrodes on the surface of the substrate; and wherein the electrodes of the first and second patterns are controllable to deplete lateral regions of the quantum well structure of charge carriers so that droplets of charge carriers in the semiconductor quantum well structure are laterally localized along the surface, and the controllable electrodes of the second pattern are configurable to constrain a portion of the droplets along the surface to connect at least three of the memory cells.

[0053] In some embodiments of the foregoing apparatus, a first of the one or more memory cell connectors is configurable to laterally constrain a portion of the droplet along the surface to connect at least four of the memory cells.

[0054] In some embodiments of any of the above apparatus, the four memory cells are arranged such that any two laterally adjacent memory cells are oriented at a relative angle of about 90 degrees (e.g., as in Figure 4 middle).

[0055] In some embodiments of any of the foregoing apparatus, a first one of the one or more memory cell connectors (e.g., Figure 5 510) is configured to directly connect at least eight of the memory cells.

[0056] In some embodiments of any of the foregoing apparatus, a first one of the one or more memory cell connectors (e.g., Figure 5 510) is configurable to laterally constrain a portion of the droplet along the surface to connect at least eight of the memory cells.

[0057] In some embodiments of any of the above apparatus, the eight memory cells are arranged such that any two laterally adjacent memory cells are oriented at a relative angle of about 45 degrees (e.g., as in Figure 4 middle).

[0058] In some embodiments of any of the apparatus above, each of the one or more memory cell connectors is configured to support entanglement of fractional quantum Hall effect states supported in the at least three of the memory cells.

[0059] In some embodiments of any of the above-described apparatus, at least one of the one or more memory cell connectors is configurable to support entanglement of fractional quantum Hall effect states of at least three of the memory cells and a portion of the droplet in at least one of the one or more memory cell connectors.

[0060] In some embodiments of any of the above apparatus, the apparatus further includes an additional memory cell connector configured to directly connect two of the memory cells (e.g., Figure 6 310).

[0061] In some embodiments of any of the above apparatus, the apparatus further comprises an additional memory cell connector having a third electrode pattern configurable to laterally constrain a portion of the droplet along the surface to directly connect two of the memory cells.

[0062] In some embodiments of any of the above apparatus, the one or more memory cell connectors further include a third memory cell connector (e.g., Figure 6 5002 of 510).

[0063] In some embodiments of any of the foregoing apparatus, the additional memory cell connector is configured to directly connect one of the at least three memory cells directly connected to the first memory cell connector and one of the at least three memory cells directly connected to the third memory cell connector (e.g., as in Figure 6 middle).

[0064] In some embodiments of any of the foregoing apparatus, the additional memory cell connector is configurable to laterally constrain the portion of the droplet along the surface so that one of the at least three memory cells is directly connected to the additional memory cell connector.

[0065] In some embodiments of any of the foregoing apparatus, the at least three of the memory cells include two memory cells whose relative orientations are non-collinear (e.g., Figure 4 , 5 2001 and 2002).

[0066] In some embodiments of any of the foregoing apparatus, the at least three of the memory cells include two memory cells whose relative orientation is co-linear (eg, Figure 5 2001 and 2005).

[0067] In some embodiments of any of the apparatus above, the at least three of the memory cells include at least three memory cells whose relative orientations are approximately co-linear.

[0068] In some embodiments of any of the above apparatus, the electrodes are controllable to perform one or more of: storing a multi-qubit state on the droplet while the droplet is maintained in a fractional quantum Hall effect state; reading a qubit value stored in the memory cell; and performing entangled computing using the multi-qubit state stored on the droplet.

[0069] In some embodiments of any of the foregoing apparatus, the electrodes are controllable to perform two or more of: storing a multi-qubit state on the droplet while the droplet is maintained in a fractional quantum Hall effect state; reading a qubit value stored in the memory cell; and performing entangled computing using the multi-qubit state stored on the droplet.

[0070] In some embodiments of any of the above apparatus, the electrodes are controllable to perform the following: store a multi-qubit state on the droplet while the droplet is maintained in a fractional quantum Hall effect state; read a qubit value stored in the memory cell; and perform entangled computation using the multi-qubit state stored on the droplet.

[0071] Although the present invention includes references to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the described embodiments and other embodiments within the scope of the present invention that are obvious to those skilled in the art to which the present invention belongs are considered to be within the principles and scope of the present invention as expressed in the appended claims.

[0072] Unless expressly stated otherwise, each numerical value and range should be interpreted as being approximate, as if the word "about" or "approximately" preceded the value or range.

[0073] It will be further understood that various changes in details, materials and arrangements of components which have been described and illustrated in order to explain the nature of the invention may be made by those skilled in the art without departing from the scope of the invention, for example as expressed in the appended claims.

[0074] The use of figure numbers and / or figure reference signs in the claims is intended to identify one or more possible embodiments of the claimed subject matter to aid in interpreting the claims. Such use should not be construed as necessarily limiting the scope of the claims to the embodiments shown in the corresponding drawings.

[0075] Although elements in the following method claims (if any) are recited in a specific order with corresponding labels, those elements are not necessarily intended to be limited to implementation in that specific order unless the claim recitation otherwise implies a specific order for implementing some or all of those elements.

[0076] Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present invention. The appearance of the phrase "in one embodiment" in various places in the specification is not necessarily to refer to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments. The same applies to the term "implementation".

[0077] Unless otherwise specified herein, the use of the ordinal adjectives "first," "second," "third," etc., to refer to objects among a plurality of similar objects merely indicates that different instances of such similar objects are referred to and is not intended to imply that the similar objects referred to must be in a corresponding order or sequence, whether in time, space, by ranking or in any other manner.

[0078] Throughout the detailed description, the drawings, which are not drawn to scale, are merely illustrative and are used to explain, not to limit, the present invention. The use of terms such as height, length, width, top, bottom strictly facilitates the description of the embodiments and is not intended to limit the embodiments to a specific orientation. For example, height not only implies a vertical rise limit, but is also used to identify one of the three dimensions of a three-dimensional structure, as shown in the figure. These "heights" are vertical when the electrodes are horizontal, but horizontal when the electrodes are vertical, and so on.

[0079] Moreover, for the purposes of this description, the terms "couple", "coupling", "coupled", "connecting", "connected" refer to any means known in the art or later developed to allow energy to be transferred between two or more elements, and the interposition of one or more additional elements is expected, although not required. In contrast, the terms "directly coupled", "directly connected", etc. imply the absence of such additional elements. The same type of distinction applies to the use of the terms "attachment" and "direct attachment" as applied to the description of the physical structure. For example, a relatively thin layer of adhesive or other suitable bonding agent can be used to implement this "direct attachment" of two corresponding components in this physical structure.

[0080] The description and drawings are merely illustrative of the principles of the invention. Therefore, it should be understood that one of ordinary skill in the art will be able to envision various arrangements that embody the principles of the invention and are included in its spirit and scope, although not explicitly described or shown herein. In addition, all examples described herein are primarily intended to be used explicitly only for teaching purposes to help the reader understand the principles of the invention and the concepts provided by the inventors to advance the technology, and should be understood as not being limited to such specifically described examples and conditions. In addition, all statements describing the principles, aspects, and embodiments of the invention herein and their specific examples are intended to include their equivalents.

[0081] As used in this application, the term "circuitry" may refer to one or more or all of the following: (a) hardware circuit implementations only (e.g., implementations in analog and / or digital circuitry only); (b) combinations of hardware circuitry and software, such as (if applicable): (i) a combination of analog and / or digital hardware circuitry and software / firmware and (ii) any portion of a hardware processor with software (including a digital signal processor, software, and memory that work together to cause a device (e.g., a mobile phone or server) to perform various functions); (c) hardware circuitry and / or processors, such as microprocessors or portions of microprocessors that require software (e.g., firmware) to operate, but software may not be present when software is not required for operation. This definition of circuitry applies to all uses of this term in this application, including in any claims. As another example, as used in this application, the term circuitry also encompasses implementations of hardware circuitry or processor (or multiple processors) or portions of hardware circuitry or processors and their (or their) accompanying software and / or firmware. The term circuitry also covers (for example and if applicable to a particular claim element) a baseband integrated circuit or a processor integrated circuit for a mobile device or a similar integrated circuit in a server, cellular network device, or other computing or networking device.

[0082] It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative circuitry embodying the principles of the invention.

[0083] As used herein and in the claims, the term "providing" with respect to a system, device, or component encompasses specifying or manufacturing the system, device, or component; causing the system, device, or component to be designed or manufactured; and / or acquiring the system, device, or component through purchase, rental, lease, or other contractual arrangement.

Claims

1. A device for quantum computing, comprising: a planar semiconductor quantum well structure having layers extending along its top surface; a plurality of memory cells, each of the plurality of memory cells having a first pattern of controllable electrodes proximate to and above the top surface, the first pattern of electrodes laterally surrounding a corresponding physical sequence of three or more lateral regions of the semiconductor quantum well structure joined by a via; and one or more memory cell connectors configurable to connect the plurality of memory cells, each of the one or more memory cell connectors having a respective second pattern of controllable electrodes proximate to and above the top surface; and wherein the electrodes of the first and second patterns are controllable to deplete an underlying lateral region of the quantum well structure of charge carriers such that a droplet of the charge carriers in the semiconductor quantum well structure is laterally localized along the top surface, and the electrodes of the one or more second patterns are controllable to confine a portion of the droplet along the top surface within the one or more memory cell connectors to connect at least three memory cells of the plurality of memory cells; as well as Wherein at least one memory cell of the one or more memory cell connectors is configurable to support entanglement of fractional quantum Hall effect states of a portion of the droplet in the at least three of the memory cells and at least one memory cell of the one or more memory cell connectors.

2. The apparatus of claim 1, wherein a first of the one or more memory cell connectors is configurable to laterally constrain a portion of the droplet along the top surface to connect at least four memory cells of the plurality of memory cells.

3. The apparatus of claim 2, wherein the four memory cells of the plurality of memory cells are arranged such that any two laterally adjacent memory cells of the four memory cells of the plurality of memory cells are oriented at a relative angle of approximately 90 degrees.

4. The apparatus of claim 1, wherein a first of the one or more memory cell connectors is configurable to laterally constrain a portion of the droplet along the top surface to connect eight memory cells of the plurality of memory cells.

5. The apparatus of claim 4, wherein the eight memory cells of the plurality of memory cells are arranged such that any two laterally adjacent memory cells of the eight memory cells of the plurality of memory cells are oriented at a relative angle of approximately 45 degrees.

6. The apparatus of claim 1 , further comprising an additional memory cell connector having a third electrode pattern proximate to and above the top surface, the third electrode pattern being configurable to laterally constrain a portion of the droplet along the top surface to directly connect two memory cells of the plurality of memory cells.

7. The apparatus of claim 6, wherein the one or more memory cell connectors further comprises a third memory cell connector.

8. The apparatus of claim 6, wherein the additional memory cell connector is configurable to laterally constrain the portion of the droplet along the top surface so that one of the at least three of the plurality of memory cells is directly connected to the additional memory cell connector.

9. The apparatus of claim 1, wherein the at least three of the plurality of memory cells include two of the plurality of memory cells whose orientations are non-collinear.

10. The apparatus of claim 9, wherein the at least three of the plurality of memory cells include at least three of the plurality of memory cells whose orientation is approximately co-linear.

11. The apparatus of claim 1 , wherein the electrodes are controllable to perform one or more of: storing a multi-qubit state on the droplet while the droplet is maintained in a fractional quantum Hall effect state; reading the qubit value stored in the memory cell; and Entangled computing is performed using the multi-qubit state stored on the droplet.

12. The apparatus of claim 1, wherein the electrodes are controllable to perform two or more of: storing a multi-qubit state on the droplet while the droplet is maintained in a fractional quantum Hall effect state; reading the qubit value stored in the memory cell; and Entangled computing is performed using the multi-qubit state stored on the droplet.

13. The apparatus of claim 1, wherein the electrodes are controllable to perform: storing a multi-qubit state on the droplet while the droplet is maintained in a fractional quantum Hall effect state; reading the qubit value stored in the memory cell; and Entangled computing is performed using the multi-qubit state stored on the droplet.

14. A device for quantum computing, comprising: a planar semiconductor quantum well structure having layers extending along its top surface; a plurality of memory cells, each of the plurality of memory cells having a first pattern of controllable electrodes proximate to and above the top surface, the first pattern of electrodes laterally surrounding a corresponding physical sequence of three or more lateral regions of the semiconductor quantum well structure joined by a via; and one or more memory cell connectors configurable to connect the plurality of memory cells, each of the one or more memory cell connectors having a respective second pattern of controllable electrodes proximate to and above the top surface; and wherein the electrodes of the first and second patterns are controllable to deplete an underlying lateral region of the quantum well structure of charge carriers such that a droplet of the charge carriers in the semiconductor quantum well structure is laterally localized along the top surface, and the electrodes of the one or more second patterns are controllable to confine a portion of the droplet along the top surface within the one or more memory cell connectors to connect at least three memory cells of the plurality of memory cells; and The electrodes are controllable to perform one or more of the following: storing a multi-qubit state on the droplet while the droplet is maintained in a fractional quantum Hall effect state; reading a qubit value stored in the memory cell; and Entangled computing is performed using the multi-qubit state stored on the droplet.

15. The apparatus of claim 14, wherein the electrodes are controllable to perform two or more of: storing the multi-qubit state on the droplet while the droplet is maintained in a fractional quantum Hall effect state; reading the qubit value stored in the memory cell; and Entangled computing is performed using the multi-qubit state stored on the droplet.

16. The apparatus of claim 14, wherein the electrodes are controllable to perform: storing the multi-qubit state on the droplet while the droplet is maintained in a fractional quantum Hall effect state; reading the qubit value stored in the memory cell; and Entangled computing is performed using the multi-qubit state stored on the droplet.

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