Method for controlling on-die termination and memory system for executing the method

Abstract

In a method for controlling on-die termination (ODT) in a memory system including a plurality of memory cells that share a common data bus for transmitting data, the ODT circuits of the plurality of memory cells are caused to enter an initial state, during a write operation to a write target memory cell among the plurality of memory cells, the resistance value of the ODT circuit of at least one non-write target memory cell among the plurality of memory cells is set to a first resistance value, and during a read operation to a read target memory cell among the plurality of memory cells, the resistance value of the ODT circuit of at least one non-read target memory cell among the plurality of memory cells is set to a second resistance value.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This U.S. non-provisional application claims priority to Korean Patent Application No. 10-2019-0160408 filed on December 5, 2019 in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments relate generally to a semiconductor integrated circuit, and more particularly to a method of controlling on-die termination and a memory system performing the method. Background Art

[0004] On-die termination (ODT) is a technology in which the termination resistor used for impedance matching in the transmission line is located inside the semiconductor chip rather than on the printed circuit board. ODT can be introduced to enhance signal integrity by reducing signal reflections between the transmitter and the receiver. ODT circuits can reduce signal reflections by providing a termination resistor that matches the impedance of the transmission line. However, when ODT is implemented to enhance the signal integrity of the signal transmitted on the transmission line, power consumption can be increased. Summary of the invention

[0005] At least one exemplary embodiment of the inventive concept provides a method of controlling ODT capable of enhancing performance and signal integrity.

[0006] At least one exemplary embodiment of the inventive concepts provides a memory system capable of enhancing performance and signal integrity.

[0007] According to an exemplary embodiment of the present invention, in a method of controlling on-die termination (ODT) in a memory system including a plurality of memory cells that share a data bus to exchange data, ODT circuits of the plurality of memory cells are caused to enter an initial state, during a write operation to a target memory cell among the plurality of memory cells, a resistance value of the ODT circuit of a non-target memory cell among the plurality of memory cells is set to a first resistance value, and during a read operation to a read target memory cell among the plurality of memory cells, a resistance value of the ODT circuit of a non-read target memory cell among the plurality of memory cells is set to a second resistance value.

[0008] According to an exemplary embodiment of the present invention, a memory system includes a plurality of memory blocks and a memory controller for controlling the plurality of memory blocks. The plurality of memory blocks share a data bus and a command / address bus. The on-die termination (ODT) circuits of the plurality of memory blocks are caused to enter an initial state. During a write operation to a target memory block among the plurality of memory blocks, the resistance value of the ODT circuit of a non-target memory block among the plurality of memory blocks is set to a first resistance value. During a read operation to a read target memory block among the plurality of memory blocks, the resistance value of the ODT circuit of the non-target memory block among the plurality of memory blocks is set to a second resistance value.

[0009] According to an exemplary embodiment of the present invention, a memory system includes a first memory block and a second memory block that share a data bus and a command / address bus, and a memory controller that controls the first memory block and the second memory block. The first memory block includes a first dynamic random access memory (DRAM) chip and the second memory block includes a second DRAM chip. The on-die termination (ODT) circuits of the first and second DRAM chips are caused to enter an initial state. During a write operation to a first DRAM chip corresponding to a write target of the first and second DRAM chips, the resistance value of the ODT circuit of the second DRAM chip corresponding to a non-write target of the first and second DRAM chips is set to a first resistance value. During a read operation to the first DRAM chip, the resistance value of the ODT circuit of the second DRAM chip is set to a second resistance value different from the first resistance value.

[0010] According to an exemplary embodiment of the present invention, a memory system includes a first memory device, a second memory device, and a memory controller configured to control the first and second memory devices. The memory controller is configured to enable an ODT circuit during a write operation and set a resistance value of the ODT circuit to a first resistance value, and disable the first ODT circuit during a read operation of the first memory device and set the resistance value of the second ODT circuit to a second resistance value. When the memory system operates in a first mode, the first and second resistance values ​​are the same as each other, and when the memory system operates in a second mode, the first and second resistance values ​​are different from each other.

[0011] A method of controlling ODT and a memory system performing the same according to at least one exemplary embodiment of the inventive concept may enhance performance and signal integrity through static ODT control by differently setting resistance values ​​of ODT circuits in non-target memory blocks in write and read operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Exemplary embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0013] Figure 1 is a block diagram of a memory system according to an exemplary embodiment of the inventive concept.

[0014] Figure 2 is a diagram showing an exemplary embodiment including an Figure 1 Block diagram of a semiconductor system of a memory system.

[0015] Figure 3 FIG. 1 shows an exemplary embodiment of the present inventive concept. Figure 1 An example of a memory subsystem in .

[0016] Figure 4 FIG. 1 shows an exemplary embodiment of the present inventive concept. Figure 1 An example of a memory subsystem in .

[0017] Figure 5 is a flowchart illustrating a method of controlling on-die termination (ODT) according to an exemplary embodiment of the inventive concept.

[0018] Figure 6 is a timing diagram illustrating a method of controlling ODT according to an exemplary embodiment of the inventive concept.

[0019] Fig. 7A is a diagram illustrating an exemplary embodiment according to the inventive concept Figure 1 A block diagram of an example of a memory chip included in a memory unit in a memory system of FIG.

[0020] Figure 7B FIG. 1 shows an exemplary embodiment of the present inventive concept. Fig. 7A An example of a first bank array in a memory chip.

[0021] Figure 8 is a diagram illustrating an exemplary embodiment according to the inventive concept Figure 1 A block diagram of an example of a memory chip included in a memory unit in a memory system of FIG.

[0022] Fig. 9 is a diagram illustrating an exemplary embodiment according to the inventive concept Fig. 7A A block diagram of an example of a data input / output (I / O) circuit included in a memory chip of FIG.

[0023] Fig. 10A is a diagram illustrating an exemplary embodiment according to the inventive concept Fig. 91 is a circuit diagram of an example of an ODT circuit included in a data I / O circuit.

[0024] Fig. 10B FIG. 1 is a diagram illustrating an exemplary embodiment of the present invention. Fig. 9 1 is a circuit diagram of an example of an ODT circuit included in a data I / O circuit.

[0025] Fig.11 , Fig. 12A and Fig. 12B is a diagram illustrating a method of controlling ODT in a write operation according to an exemplary embodiment of the inventive concept.

[0026] Fig.13 and Fig.14 is a diagram illustrating a method of controlling ODT in a read operation according to an exemplary embodiment of the inventive concept.

[0027] Fig.15 is a diagram illustrating an example of resistance setting used in a method of controlling ODT according to an exemplary embodiment of the inventive concept.

[0028] Fig.16A and Fig. 16B A diagram used to describe center-tapped termination (CTT).

[0029] Fig.17A and Fig. 17B is a diagram for describing the first pseudo-open drain (POD) termination.

[0030] Fig.18A and Fig.18B It is a diagram for describing the termination of the second POD.

[0031] Fig.19A and Fig.19B is a diagram for describing a mode register for ODT according to an exemplary embodiment of the inventive concept.

[0032] Fig. 20 Shown based on Fig.19B An example of the resistance value of the ODT circuit in the non-target memory rank set by the operand in .

[0033] Fig.21 Diagrams illustrate connections of memory dies in a semiconductor memory device (eg, a memory subsystem) according to exemplary embodiments of the inventive concept.

[0034] Fig. 22is a cross-sectional view illustrating a 2.5-dimensional (D) chip structure including stacked memory devices according to an exemplary embodiment of the inventive concept.

[0035] Fig.23 is a perspective view illustrating a semiconductor package according to an exemplary embodiment of the inventive concept.

[0036] Fig.24 is a diagram illustrating a semiconductor package including stacked memory devices according to an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0037] The inventive concept will be described more fully hereinafter with reference to the accompanying drawings, in which some exemplary embodiments of the inventive concept are shown.In the drawings, like reference numerals refer to like elements throughout.

[0038] Figure 1 is a block diagram of a memory system according to an exemplary embodiment of the inventive concept.

[0039] refer to Figure 1 , the memory system 10 includes a memory controller 20 (eg, a control circuit) and a memory subsystem 50 .

[0040] The memory subsystem 50 may include a plurality of memory units (MU1, MU2, ..., MUk) 100a, 100b, ..., 100k. Here, k is an integer greater than 2. For example, each memory unit can be a memory device, a memory card, or a memory chip.

[0041] A plurality of memory cells 100a, 100b, ..., 100k may share a data bus 22 to transfer data DQ and a command / address (CA) bus 21 to transfer commands and addresses CA and may receive a corresponding one of chip select signals CS1, CS2, ..., CSk. The CA bus 21 and the data bus 22 may constitute a channel 23. For example, the command may include a read command, a write command, an erase command, and the like.

[0042] In an exemplary embodiment, the plurality of memory cells 100a, 100b, ..., 100k include a corresponding one of a plurality of memory banks independently selected based on a plurality of chip select signals CS1, CS2, ..., CSk, respectively. In an exemplary embodiment, the plurality of memory cells 100a, 100b, ..., 100k include a corresponding one or more memory chips in a corresponding one of a plurality of memory banks independently selected based on a plurality of chip select signals CS1, CS2, ..., CSk, respectively.

[0043] A memory cell among the plurality of memory cells 100a, 100b, ..., 100k selected by a signal having a first logic level among the chip selection signals CS1, CS2, ..., CSk is referred to as a target memory cell, and at least one memory cell among the plurality of memory cells 100a, 100b, ..., 100k not selected by a signal having a second logic level among the chip selection signals CS1, CS2, ..., CSk is referred to as a non-target memory cell. For example, when a write operation is to be performed on a given one of the memory cells, the given memory cell may be referred to as a target memory cell and the other memory cells may be referred to as non-target memory cells.

[0044] Figure 2 is a diagram showing an exemplary embodiment including an Figure 1 Block diagram of a semiconductor system of a memory system.

[0045] refer to Figure 2 , the semiconductor (memory) system 15 includes sockets 80 and 85 , a memory controller (MCT) 20 , a processor 25 , and a substrate 70 .

[0046] Sockets 80 and 85, memory controller 20, and processor 25 may be attached to substrate 70 and may be electrically connected to each other via electrical conductors included in substrate 70. Memory subsystem 50 may be mounted in semiconductor system 15 via socket 80 and memory subsystem 60 may be mounted in semiconductor system 15 via socket 85.

[0047] In some embodiments, the semiconductor system 15 may be a mainboard or a computing system on which the memory subsystems 50 and 60 are provided, and the memory subsystems 50 and 60 may function as data storage in the semiconductor system. The memory subsystems 50 and 60 may be memory modules and may include two memory cells independently selected based on two chip selection signals, respectively.

[0048] Figure 3 FIG. 1 shows an exemplary embodiment of the present inventive concept. Figure 1 An example of a memory subsystem in .

[0049] refer to Figure 3 , the memory subsystem 50a includes a first memory unit MU1a and a second memory unit MU2a.

[0050] The first memory unit MU1a may correspond to the first memory block RNK1 and may include a plurality of first memory chips (MEM11, MEM12, ... MEM1g) 111, 112, ..., 11g. The second memory unit MU2a may correspond to the second memory block RNK2 and may include a plurality of second memory chips (MEM21, MEM22, ... MEM2g) 121, 122, ..., 12g. Here, g is an integer greater than 2.

[0051] Figure 4 FIG. 1 shows an exemplary embodiment of the present inventive concept. Figure 1 An example of a memory subsystem in .

[0052] refer to Figure 4 , the memory subsystem 50b may include a first memory unit MU1b and a second memory unit MU2b.

[0053] The first memory unit MU1b may correspond to the first memory block RNK1 and include a first memory chip 111a. The second memory unit MU2b may correspond to the second memory block RNK2 and include a second memory chip 121a.

[0054] According to an exemplary embodiment of the inventive concept, each of the plurality of memory cells corresponds to a corresponding one of the plurality of memory blocks selected based on a chip selection signal, and each of the memory cells may include at least one memory chip. The at least one memory chip may be a dynamic random access memory (DRAM) chip or a nonvolatile memory chip.

[0055] Figure 5 is a flowchart illustrating a method of controlling on-die termination (ODT) according to an exemplary embodiment of the inventive concept, and Figure 6 is a timing diagram illustrating a method of controlling ODT according to an exemplary embodiment of the inventive concept.

[0056] refer to Figure 1 , 5 6, when the memory system 10 is powered on (S100), the ODT circuits of the plurality of memory cells 100a, 100b, ..., 100k are caused to enter an initial state (S100). For example, causing the ODT circuit to enter the initial state may be performed by applying power to the ODT circuit and setting the resistance of each of the ODT circuits to a default resistance value.

[0057] During a write operation for a target memory cell among the plurality of memory cells 100a, 100b, ..., 100k, a resistance value of an ODT circuit of at least one non-write target memory cell among the plurality of memory cells 100a, 100b, ..., 100k is set to a first resistance value (S200). For example, the non-write target memory cell is a memory cell that is not a target of the write operation.

[0058] During a read operation for a read target memory cell among the plurality of memory cells 100a, 100b, ..., 100k, a resistance value of an ODT circuit of at least one non-read target memory cell among the plurality of memory cells 100a, 100b, ..., 100k is set to a second resistance value (S300). For example, the non-read target memory cell is a memory cell that is not a target of the read operation.

[0059] Although operation S300 is illustrated as occurring after operation S200, operation S300 may occur before operation S200. Furthermore, operation S200 can be repeated for another group of memory cells before or after operation S300 is performed.

[0060] The memory access operation may include a write operation and a read operation, and the memory access operation may be distinguished from other operations such as a mode register write operation, a mode register read operation, a refresh operation, and the like.

[0061] In the case of a write operation, the plurality of memory cells 100a, 100b, ..., 100k may be divided into write target memory cells that are the object (or target) of the write operation and non-target memory cells excluding the write target memory cells. In the case of a read operation, the plurality of memory cells 100a, 100b, ..., 100k may be divided into read target memory cells that are the object (or target) of the read operation and non-target memory cells excluding the read target memory cells. The write target memory cells or the read target memory cells may be simply referred to as target memory cells or target memory blocks.

[0062] refer to Figure 6 At time point T1, when the memory system 10 is powered on, the ODT circuits of the plurality of memory cells 100a, 100b, ..., 100k are set to an initial state. In some embodiments, each of the ODT circuits of the plurality of memory cells 100a, 100b, ..., 100k is set to have a default resistance value in the initial state.

[0063] Even though Figure 6The diagram shows that the enabling time point of the ODT circuit is consistent with the power-on sequence, but the power-on sequence may be completed first and then after a certain time interval has elapsed, the ODT circuit may be set to the initial state.

[0064] During the T2-T3 and T4-T5 time intervals when performing a write operation, all ODT circuits of the memory cells 100a, 100b, ..., 100k including the write target memory cells and the non-target memory cells maintain an enabled state. In some embodiments, the resistance value of the ODT circuit of the write target memory cell is set to have a first resistance value during the write operation. In an exemplary embodiment, the ODT circuit of the write target memory is set to have a first resistance value during the time intervals T2-T3 and T4-T5.

[0065] In some embodiments, all ODT circuits of the memory cells 100a, 100b, . . . , 100k including the write target memory cell and the non-target memory cells maintain an initial state to have the default resistance value.

[0066] During the time interval T6-T7 when the read operation is performed, the ODT circuit of the read target memory cell is disabled and the ODT circuit of the non-target memory cell is enabled. In some embodiments, the ODT circuit of the non-target memory cell is set to have a second resistance value different from the first resistance value. In an exemplary embodiment, during the time interval T6-T7, the ODT circuit of the non-target memory cell is set to have a second resistance value different from the first resistance value.

[0067] In some embodiments, the first resistance value and the second resistance value may have a ratio of a:b and each of a and b is a natural number less than 9. In an exemplary embodiment, the first resistance value is 120 ohms and the second resistance value is 90 ohms. In an exemplary embodiment, the first resistance value is greater than the second resistance value.

[0068] In some embodiments, all ODT circuits of the memory cells 100a, 100b, . . . , 100k including the write target memory cell and the non-target memory cells maintain an initial state to have the default resistance value.

[0069] In some embodiments, during one of a write operation and a read operation, an ODT circuit of at least one non-target memory cell is set to be disabled to have a high impedance.

[0070] At time point T8, when the memory system 10 is powered off, the power supply is blocked and the ODT circuits of all memory cells 100a, 100b, ..., 100k are disabled.

[0071] As such, a method of controlling ODT and a memory system executing the same according to at least one exemplary embodiment of the inventive concept may improve signal integrity to enhance performance by differently setting resistance values ​​of ODT circuits of non-target memory blocks in write and read operations.

[0072] Fig. 7A is a diagram illustrating an exemplary embodiment according to the inventive concept Figure 1 A block diagram of an example of a memory chip included in a memory unit in a memory system of FIG.

[0073] refer to Fig. 7A The memory chip 200a includes a control logic circuit 210, an address register 220, a bank control logic 230 (e.g., a logic circuit), a refresh counter 245 (e.g., a counting circuit), a row address multiplexer 240, a column address latch 250, a row decoder 260 (e.g., a decoder circuit), a column decoder 270 (e.g., a decoder circuit), a memory cell array 300, a sense amplifier unit 285, an input / output (I / O) selection circuit 290 and a data I / O circuit 400.

[0074] The data I / O circuit 400 may receive or send data DQ through a data I / O pin (or pad) 201 .

[0075] The memory cell array 300 includes first to eighth memory cell arrays 310 to 380. The row decoder 260 includes first to eighth row decoders 260a to 260h respectively coupled to the first to eighth memory cell arrays 310 to 380, the column decoder 270 includes first to eighth column decoders 270a to 270h respectively coupled to the first to eighth memory cell arrays 310 to 380, and the sense amplifier unit 285 includes first to eighth sense amplifiers 285a to 285h respectively coupled to the first to eighth memory cell arrays 310 to 380.

[0076] Each of the first to eighth bank arrays 310 ˜ 380 includes a plurality of volatile memory cells MC formed at intersections of a plurality of word lines WL and a plurality of bit lines BTL.

[0077] The address register 220 receives an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from the memory controller 20. The address register 220 provides the received bank address BANK_ADDR to the bank control logic 230, provides the received row address ROW_ADDR to the row address multiplexer 240, and provides the received column address COL_ADDR to the column address latch 250.

[0078] The bank control logic 230 generates a bank control signal in response to the bank address BANK_ADDR, activates one of the first to eighth row decoders 260a-260h corresponding to the bank address BANK_ADDR in response to the bank control signal, and activates one of the first to eighth column decoders 270a-270h corresponding to the bank address BANK_ADDR in response to the bank control signal.

[0079] The row address multiplexer 240 receives the row address ROW_ADDR from the address register 220 and receives the refresh row address REF_ADDR from the refresh counter 245. The row address multiplexer 240 selectively outputs the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA outputted from the row address multiplexer 240 is applied to the first to eighth row decoders 260a-260h.

[0080] The refresh counter 245 outputs a refresh row address REF_ADDR that may be sequentially changed under the control of the control logic circuit 210 .

[0081] The activated one of the first to eighth row decoders 260a-260h decodes the row address RA output from the row address multiplexer 240 through the bank control logic 230 and activates a word line corresponding to the row address RA. For example, the activated bank row decoder applies a word line driving voltage to the word line corresponding to the row address RA.

[0082] The column address latch 250 receives the column address COL_ADDR from the address register 220 and temporarily stores the received column address COL_ADDR. In some embodiments, in the burst mode, the column address latch 250 generates a column address COL_ADDR incremented from the received column address COL_ADDR. The column address latch 250 applies the temporarily stored or generated column address COL_ADDR to the first to eighth column decoders 270a-270h.

[0083] The activated one of the first to eighth column decoders 270 a ˜ 270 h activates a sense amplifier corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the I / O gating circuit 290 .

[0084] In an exemplary embodiment, the I / O selection circuit 290 includes a circuit for selecting input / output data, and further includes input data mask logic, a read data latch for storing data output from the first to eighth memory arrays 310~380, and a write driver for writing data to the first to eighth memory arrays 310~380.

[0085] Data read from one bank array of the first to eighth bank arrays 310 to 380 is sensed by a sense amplifier coupled to one bank array from which data is read and stored in a read data latch. The data stored in the read data latch may be provided to the memory controller 20 via the data I / O circuit 400.

[0086] Data DQ to be written into one bank array of the first to eighth bank arrays 310 ˜ 380 may be provided from the memory controller 20 to the data I / O circuit 400 , and the I / O gating circuit 290 may write the data into a subpage of a target page in one bank array through a write driver.

[0087] The control logic circuit 210 may control the operation of the memory chip 200a. For example, the control logic circuit 210 may generate a control signal for the memory chip 200a to perform a write operation or a read operation. The control logic circuit 210 includes a command decoder 211 that decodes a command CMD received from the memory controller 20 and a mode register 212 that sets the operation mode of the memory chip 200a.

[0088] The mode register 212 may be used to set the resistance value of the ODT circuit in the data I / O circuit 400. The control logic circuit 210 may generate a first control signal CTL1 based on the value set in the mode register 212 and may provide the first control signal CTL1 to the data I / O circuit 400 to set the resistance value of the ODT circuit in the data I / O circuit 400.

[0089] In an exemplary embodiment, the mode register 212 is used to set the resistance value of the ODT circuit in the data I / O circuit 400 in the non-target memory block to a first resistance value during a write operation, and to set the resistance value of the ODT circuit in the data I / O circuit 400 in the non-target memory block to a second resistance value during a read operation. In an exemplary embodiment of the present inventive concept, the mode register 212 sets the second resistance value to be the same as the first resistance value in a first mode among multiple modes. In an exemplary embodiment, the mode register 212 is used to set the second resistance value to be different from the first resistance value in a second mode among multiple modes. In an exemplary embodiment, the mode register 212 is used to disable the ODT circuit in the data I / O circuit 400 in the non-target memory block so that the ODT circuit has high impedance during one of a write operation and a read operation.

[0090] The memory chip 200 a may include a DRAM chip.

[0091] Figure 7BFIG. 1 shows an exemplary embodiment of the present inventive concept. Fig. 7A An example of a first memory bank array in a memory chip.

[0092] refer to Figure 7B The first memory bank array 310 includes a plurality of word lines WL1-WLm (m is a natural number equal to or greater than 2), a plurality of bit lines BTL1-BTLn (n is a natural number equal to or greater than 2), and a plurality of memory cells MC disposed at intersections between the word lines WL1-WLm and the bit lines BTL1-BTLn. Each of the memory cells MC includes a cell transistor coupled to each of the word lines WL1-WLm and each of the bit lines BTL1-BTLn and a cell capacitor coupled to the cell transistor.

[0093] Figure 8 is a diagram illustrating an exemplary embodiment according to the inventive concept Figure 1 A block diagram of an example of a memory chip included in a memory unit in a memory system of FIG.

[0094] Figure 8 The figure shows the case where the memory chip includes a flash memory chip.

[0095] refer to Figure 8 , the memory chip 200 a includes a memory cell array 420 , an address decoder 450 , a page buffer circuit 430 , a data I / O circuit 440 , a control circuit 460 , and a voltage generator 470 .

[0096] The memory cell array 420 is coupled to the address decoder 450 through one or more string selection lines SSL, a plurality of word lines WL, and one or more ground selection lines GSL. In addition, the memory cell array 420 is coupled to the page buffer circuit 430 through a plurality of bit lines BL. The memory cell array 420 may include a plurality of memory cells coupled to a plurality of word lines WLs and a plurality of bit lines BL.

[0097] In an example embodiment, the memory cell array 420 may be a three-dimensional memory cell array formed on a substrate in a three-dimensional structure (or a vertical structure). In this case, the memory cell array 420 may include vertical cell strings that are vertically oriented so that at least one memory cell is located on another memory cell. For example, the memory cells may be stacked on top of each other.

[0098] In other example embodiments, the memory cell array 420 may be a two-dimensional memory cell array formed on a substrate in a two-dimensional structure (or a horizontal structure).

[0099] The control circuit 460 may receive a command (signal) CMD and an address (signal) ADDR, and control the operation of the memory chip 200 b based on the command signal CMD and the address signal ADDR.

[0100] For example, the control circuit 460 may generate a control signal for controlling the voltage generator 470 and a control signal for controlling the page buffer circuit 430 based on the command signal CMD, and may generate a row address R_ADDR and a column address C_ADDR based on the address signal ADDR. The control circuit 460 may provide the row address R_ADDR to the address decoder 450 and provide the column address C_ADDR to the data input / output circuit 430. In addition, the control circuit 460 may include a mode register 462, generate a control signal CTL2 for controlling the ODT circuit in the data I / O circuit 440, and provide the control signal CTL2 to the data I / O circuit 440.

[0101] The address decoder 450 is coupled to the memory cell array 420 through one or more string selection lines SSL, a plurality of word lines WL, and one or more ground selection lines GSL. During a program operation (e.g., a write operation) or a read operation, the address decoder 450 may determine one of the plurality of word lines WL as a selected word line, and determine the remaining word lines of the plurality of word lines WL other than the selected word line as unselected word lines based on a row address R_ADDR.

[0102] The voltage generator 470 may generate a word line voltage VWL required for the operation of the memory chip 200b based on the control signal CTL from the control circuit 460. The voltage generator 470 may receive power PWR from the memory controller 20. The word line voltage VWL may be applied to a plurality of word lines WL through the address decoder 450.

[0103] The page buffer circuit 430 is coupled to the memory cell array 420 through a plurality of bit lines BL. The page buffer circuit 430 may include a plurality of page buffers. In example embodiments, one page buffer may be connected to one bit line. In other example embodiments, one page buffer may be connected to two or more bit lines.

[0104] The page buffer circuit 430 may temporarily store data to be programmed in a selected page or data read out from a selected page.

[0105] The data I / O circuit 440 is coupled to the page buffer circuit 430 through the data line DL. During a program operation, the data I / O circuit 440 may receive program data DQ from the memory controller 20 based on the column address C_ADDR received from the control circuit 460 and provide the program data DQ to the page buffer circuit 430. During a read operation, the data I / O circuit 440 may provide read data DQ stored in the page buffer circuit 430 to the memory controller 20 based on the column address C_ADDR received from the control circuit 460.

[0106] Fig. 9 is a diagram illustrating an exemplary embodiment according to the inventive concept Fig. 7A A block diagram of an example of a data I / O circuit included in a memory chip of FIG.

[0107] refer to Fig. 9 , the data I / O circuit 400 includes an ODT circuit 500, a data I / O pin 201, a transmission driver DR 610, and a reception buffer BF 620. The transmission driver 610 drives the data I / O pin 201 based on the read data and the reception buffer 620 receives the write data provided through the data I / O pin 201.

[0108] The ODT circuit 500 includes a termination controller 510 (eg, a control circuit) and a termination resistor unit 550 (eg, a circuit including one or more resistors).

[0109] The termination resistor unit 550 is coupled to the data I / O pin 201 and provides termination impedance to the transmission line coupled to the data I / O pin 201 .

[0110] The method of controlling ODT according to an exemplary embodiment of the inventive concept can be applied to control the termination of an I / O pin for bidirectional communication between a memory controller 20 and a memory chip. Thus, in addition to the data I / O pin 201, the method according to the exemplary embodiment can also be applied to a data strobe pin, a data shielding pin, or a termination data strobe pin. The term "pin" broadly refers to an electrical interconnection of an integrated circuit, for example, a pad or other electrical contact on an integrated circuit.

[0111] In an exemplary embodiment, the termination resistor unit 550 performs a pull-up termination operation to provide a termination resistance between a power supply voltage node and the data I / O pin 201 and / or performs a pull-down termination operation to provide a termination resistance between a ground node and the data I / O pin 201 .

[0112] Even though Fig. 9The figure shows an example embodiment in which a different termination resistor unit 550 is included, but a signal driver (not shown) in the transmit driver 610 may instead function as a termination resistor. For example, in a write operation, the transmit driver 610 does not transmit read data and the transmit driver 610 functions as the termination resistor unit 550 while the receive buffer 620 is enabled to receive write data.

[0113] When the termination resistor unit 550 performs a pull-up termination operation, the voltage of the transmission line connected to the data I / O pin 201 can be maintained substantially at the level of the power supply voltage. As a result, only when data of a logic low level is transmitted, current flows through the termination resistor unit 550 and the transmission line. In contrast, when the termination resistor unit 550 performs a pull-down termination operation, the voltage of the transmission line connected to the data I / O pin 201 can be maintained substantially at the ground voltage. As a result, only when data of a logic high level is transmitted, current flows through the termination resistor unit 550 and the transmission line.

[0114] The termination controller 510 receives the control code CCD and the output enable signal OEN. The termination controller 510 generates a termination control signal TCS for controlling the termination resistor unit 550 to adjust the termination impedance based on the control code CCD and the output enable signal OEN.

[0115] In some embodiments, the control code CCD is a plurality of bits associated with the data rate. Fig.19A and 19B Description, can be based on the storage Fig. 7A The value in the mode register 212 is used to provide a control code CCD of multiple bits.

[0116] In some embodiments, the output enable signal OEN is activated during a read operation. For example, when activated, the output enable signal OEN can have a high state, and when deactivated, has a low state. When the output enable signal OEN is activated, the termination controller 510 provides a termination control signal TCS at a predetermined logic level to control the termination resistor unit 550 to not provide a termination impedance. In that case, the termination resistor unit 550 can be electrically decoupled from the data I / O pin 201 in response to the termination control signal TCS having a predetermined logic level. When the termination resistor unit 550 is electrically decoupled from the data I / O pin 201, the ODT circuit 500 or the termination resistor unit 550 can be referred to as "disabled".

[0117] When the output enable signal OEN is deactivated during a write operation, the termination controller 510 generates a termination control signal TCS to control the termination resistor unit 550 to provide a termination impedance. The termination controller 510 can change the logic level of the termination control signal TCS in response to the control code CCD to change the termination impedance. For example, the value of the control code CCD can indicate a specific termination impedance or resistance. If the termination resistor unit 550 was previously electrically decoupled from the data I / O pin 201, the termination resistor unit 550 is recoupled to the data I / O pin 201 in response to the application of the termination control signal TCS. For example, the termination resistor unit 550 may include a plurality of resistors, wherein zero or more resistors are prevented from contributing their resistance to set a specific termination impedance or resistance according to the control code CCD.

[0118] Fig. 10A is a diagram illustrating an exemplary embodiment according to the inventive concept Fig. 9 1 is a circuit diagram of an example of an ODT circuit included in a data I / O circuit.

[0119] refer to Fig. 10A , the ODT circuit 500a includes a termination controller 510 and a termination resistor unit 550a.

[0120] The termination resistor unit 550a includes first to sixth p-channel metal oxide semiconductor (PMOS) transistors 561-566 and first to sixth resistors R11-R16. Each of the first to sixth PMOS transistors 561-566 is connected in series to a corresponding one of the first to sixth resistors R11-R16 between the power supply voltage VDDQ and the data I / O pin 201.

[0121] The termination controller 510 receives the control code CCD and the output enable signal OEN, and generates a termination control signal TCS1 for controlling the termination resistor unit 550a. The termination controller 510 applies each of the bits TCS11-TCS16 in the termination control signal TCS1 to the corresponding gates of the first to sixth PMOS transistors 561-566 to adjust the termination resistance of the termination resistor unit 550a. In some embodiments, each of the first to sixth resistors R11-R16 has a unique resistance or has the same resistance. For example, one or more resistors can have a resistance of 240 ohms or 300 ohms. For example, the resistor can have an error margin of 1%.

[0122] Fig. 10B FIG. 1 is a diagram illustrating an exemplary embodiment of the present invention. Fig. 9 1 is a circuit diagram of an example of an ODT circuit included in a data I / O circuit.

[0123] refer to Fig. 10BThe ODT circuit 500 b includes a pull-up termination control unit 530 , a pull-down termination control unit 540 , a pull-up driver 560 , and a pull-down driver 570 .

[0124] The pull-up termination control unit 530 includes first to third selectors 534-536 (e.g., multiplexers), and the pull-down termination control unit 540 includes fourth to sixth selectors 544-546 (e.g., multiplexers). The pull-up driver 560 includes first to third PMOS transistors 561a-563a and first to third resistors R21-R23. The first to third PMOS transistors 561a-563a are connected to the power supply voltage VDDQ, and each of the first to third resistors R21-R23 is connected between the corresponding PMOS transistor in the first to third PMOS transistors 561a-563a and the data I / O pin 201. The pull-down driver 570 includes first to third n-channel metal oxide semiconductor (NMOS) transistors 571-573 and fourth to sixth resistors R24-R26. The first to third NMOS transistors 571 ˜ 573 are connected to a ground voltage VSSQ, and each of the fourth to sixth resistors R24 ˜ R26 is connected between a corresponding one of the first to third NMOS transistors 571 ˜ 573 and the data I / O pin 201 .

[0125] Each of the first to third selectors 534-536 may receive a power supply voltage VDDQ as each of the first inputs, receive the first to third control code bits CCD1, CCD2, and CCD3 as each of the second inputs, and receive an output enable signal OEN as each of the control signals. Each of the fourth to sixth selectors 544-546 may receive a ground voltage as each of the first inputs, receive the fourth to sixth control code bits CCD4, CCD5, and CCD6 as each of the second inputs, and receive an output enable signal OEN as each of the control signals. The control code CCD may include control code bits CCD1-CCD6.

[0126] When the output enable signal OEN is activated at a logic high level during a read operation, the first to third selectors 534 to 536 output first to third termination control signals TCS21, TCS22 and TCS23 of a logic high level, and the fourth to sixth selectors 544 to 546 output fourth to sixth termination control signals TCS24, TCS25 and TCS26 of a logic low level.

[0127] When the output enable signal OEN is deactivated at a logic low level during a write operation, the first to third selectors 534 to 536 output the first to third control code bits CCD1, CCD2 and CCD3 as the first to third termination control signals TCS21, TCS22 and TCS23, and the fourth to sixth selectors 544 to 546 output the fourth to sixth control code bits CCD4, CCD5 and CCD6 as the fourth to sixth termination control signals TCS24, TCS25 and TCS26.

[0128] As described above, the control code CCD (i.e., the control code bits CCD1 to CCD6) can be associated with the data rate or the operating frequency. Therefore, when the data rate is relatively high, the channel is quickly charged / discharged by reducing the termination impedance. When the data rate is relatively low, the current consumption can be reduced by increasing the termination impedance to reduce the DC current flowing through the channel.

[0129] Despite Fig. 10B , each of the first to sixth resistors R21 to R26 is illustrated as a single resistor, but in an exemplary embodiment, each of the first to sixth resistors R21 to R26 may be implemented using a plurality of resistors connected in parallel and / or in series and a plurality of transistors for controlling the connection of the plurality of resistors.

[0130] Fig. 10B The diagram shows Fig.16A and 16B An exemplary embodiment of a center-tap termination (CTT) scheme is shown, and a pseudo-open drain (POD) termination scheme can be understood therefrom.

[0131] Fig.11 , Fig. 12A and Fig. 12B is a diagram illustrating a method of controlling ODT in a write operation according to example embodiments.

[0132] exist Fig.11 For the convenience of explanation, it is assumed that Figure 1 The memory cells 100a, 100b, . . . , 100k in FIG. 1 include a first memory block RNK1 and a second memory block RNK2.

[0133] like Fig.11As illustrated in FIG. 1 , a memory controller (MCT) 20 is connected in parallel to a plurality of memory blocks RNK1, RNK2 through data I / O pins PADC, PAD1, and PAD2 and a transmission line TL. The transmission line TL branches to the data I / O pins PAD1, PAD2 of the memory blocks RNK1 and RNK2 at a common node NC. For example, the transmission line TL may include a main line connecting PADC to a common node NC, a first branch line connected to connect the common node NC to PAD1, and a second branch line connecting the common node NC to PAD2.

[0134] Fig.11 The figure shows an example case in which the first memory block RNK1 corresponds to a write target memory block and the second memory block RNK2 corresponds to a non-target memory block. Fig.11 , shadows the enabled components.

[0135] In the write operation, in the memory controller 20 corresponding to the data transmitter device, the transmission driver DR0 is enabled and the receiving buffer BF0 is disabled. In addition, the receiving buffer BF1 is enabled in the write target memory block RNK1 corresponding to the data receiver device, while the transmission driver DR1 in the write target memory block RNK1, the receiving buffer BF2 and the transmission driver DR2 in the non-target memory block RNK2 are disabled.

[0136] According to some embodiments, during a write operation, the ODT circuit TER1 in the write target memory block RNK1 and the ODT circuit TER2 in the non-target memory block RNK2 are all enabled. The ODT circuit TER0 in the memory controller 20 is disabled. A current path can be formed from the transmission driver DR0 in the memory controller 20 to all the ODT circuits TER1 and TER2 in the memory blocks RNK1 and RNK2, and thus signal reflection can be reduced and signal integrity can be enhanced. In this case, the resistance value of the ODT circuit TER2 in the non-target memory block RNK2 can be set to have a first resistance value.

[0137] exist Fig. 12A and Fig. 12B, the time points Ta0-Tf1 correspond to the edges of the operating clock signal pair CK_T and CK_C. The first block select signal CS_RNK1 and the first command signal CMD_RNK1 are dedicated to the first memory block RNK1, and the second block select signal CS_RNK2 and the second command signal CMD_RNK2 are dedicated to the second memory block RNK2. The data selection signal pair WCK_T and WCK_C and the data signal DQ[15:0] are provided from the memory controller MC to the write target memory block RNK1. ODT_RNK1 indicates the ODT state of the first memory block RNK1 and ODT_RNK2 indicates the ODT state of the second memory block RNK2. DES means "deselect" and TRS means the transition interval when the ODT state changes.

[0138] Fig. 12A and Fig. 12B An example case of a write operation when the first memory block RNK1 corresponds to a write target memory block and the second memory block RNK2 corresponds to a non-target memory block is shown. When the first block select signal CS_RNK1 is activated, a CAS command and a write command WR are transmitted through the first command signal CMD_RNK1, and the second block select signal CS_RNK2 and the second command signal CMD_RNK2 maintain a deactivated state.

[0139] According to some embodiments, during a write operation, an ODT circuit in the write target memory block RNK1 and an ODT circuit in the non-target memory block RNK2 are enabled. In an exemplary embodiment, Fig. 12A As illustrated in FIG. 1 , when the data signal DQ[15:0] for a write operation is triggered (e.g., applied), the ODT circuits in the write target memory block RNK1 and the non-target memory block RNK2 maintain the initial state NT-ODT. In some embodiments, when the data signal DQ[15:0] for a write operation is triggered (e.g., applied), the ODT circuit in the non-target memory block RNK2 is changed to have a first resistance value NT-ODT-1, and the ODT circuit in the write target memory block RNK1 is changed to a state TG-ODT having a resistance value different from the resistance value of the initial state NT-ODT.

[0140] Fig.13 and 14 is a diagram illustrating a method of controlling ODT in a read operation according to an exemplary embodiment of the inventive concept.

[0141] like Fig.13As shown in FIG. 1 , the memory controller 10 is connected in parallel to a plurality of memory blocks RNK1 and RNK2 through data I / O pins PADC, PAD1 and PAD2 and transmission lines TL. The transmission lines TL branch at a common node NC to the data I / O pins PAD1 and PAD2 of the memory blocks RNK1 and RNK2.

[0142] Fig.13 The figure shows an example case in which the first memory block RNK1 corresponds to a read target memory block and the second memory block RNK2 corresponds to a non-target memory block. Fig.13 , shadows the enabled components.

[0143] In the read operation, in the memory controller 20 corresponding to the data receiver device, the receiving buffer BF0 is enabled and the transmitting driver DR0 is disabled. In addition, the transmitting driver DR1 is enabled in the read target memory block RNK1 corresponding to the data transmitter device, while the receiving buffer BF1 in the read target memory block RNK1, the receiving buffer BF2 and the transmitting driver DR2 in the non-target memory block RNK2 are disabled.

[0144] According to some example embodiments, during a read operation, the ODT circuit TER1 in the read target memory block RNK1 is disabled and the ODT circuit TER2 in the non-target memory block RNK2 is enabled. The ODT circuit TER0 in the memory controller 20 is enabled. A current path may be formed from the transmission driver DR1 in the read target memory block RNK1 to the ODT circuit TER0 in the transmission driver DR0 and the ODT circuit TER2 in the non-target memory block RNK2 and thus signal reflection may be reduced and signal integrity may be enhanced.

[0145] exist Fig.14, the time points Ta0-Tf1 correspond to the edges of the operating clock signal pair CK_T and CK_C. The first block select signal CS_RNK1 and the first command signal CMD_RNK1 are dedicated to the first memory block RNK1, and the second block select signal CS_RNK2 and the second command signal CMD_RNK2 are dedicated to the second memory block RNK2. The data selection signal pair WCK_T and WCK_C and the data signal DQ[15:0] are provided to the memory controller MCT from the read target memory block RNK1. Although the data signal DQ is illustrated as being 16 bits, the embodiments of the inventive concept are not limited thereto, as the data signal DQ can have various sizes. ODT_RNK1 represents the ODT state of the first memory block RNK1 and ODT_RNK2 represents the ODT state of the second memory block RNK2. DES represents "deselect" and TRS represents the transition interval when the ODT state changes.

[0146] Fig.14 An example case of a read operation when the first memory block RNK1 corresponds to a read target memory block and the second memory block RNK2 corresponds to a non-target memory block is shown. When the first block select signal CS_RNK1 is activated, the CAS command and the read command RD are transmitted through the first command signal CMD_RNK1, and the second block select signal CS_RNK2 and the second command signal CMD_RNK2 maintain a deactivated state.

[0147] According to some example embodiments, during a read operation, the ODT circuit in the read target memory block RNK1 is disabled and the ODT circuit in the non-target memory block RNK2 is enabled. Fig.14 As illustrated in the figure, when the data signal DQ[15:0] for the read operation is triggered (e.g., applied), the ODT circuit in the non-target memory block RNK2 is changed to a state having a second resistance value NT-ODT-2, and the ODT circuit in the read target memory block RNK1 is changed to a disabled state NT-ODT OFF.

[0148] Fig.15 is a diagram illustrating an example of resistance setting applied in a method of controlling ODT according to an exemplary embodiment of the inventive concept.

[0149] refer to Fig.15During a write operation, the ODT circuit in the target memory block RNK_TG has a default resistance value Rtt, the ODT circuit in the non-target memory block RNK_NT has a first resistance value Rtt1, and the ODT circuit in the memory controller 20 is disabled. During a read operation, the ODT circuit in the target memory block RNK_TG is disabled, the ODT circuit in the non-target memory block RNK_NT has a second resistance value Rtt2, and the ODT circuit in the memory controller 20 has a default resistance value Rtt.

[0150] In some embodiments, in a write operation, the ODT circuits in the target memory block RNK_TG and the non-target memory block RNK_NT have a default resistance value Rtt. The default resistance value Rtt may correspond to the resistance value in the initial state. Fig. 12A As described, during the write operation, the ODT circuits in the target memory block RNK_TG and the non-target memory block RNK_NT may maintain an initial state to have a default resistance value Rtt.

[0151] Fig.16A and 16B is a diagram used to describe center tap termination (CTT).

[0152] refer to Fig.16A , a transmission driver 40 in the transmitter device drives the input-output pad PADH based on a transmission signal ST from an internal signal of the transmitter device. The input-output pad PADH of the transmitter device is connected to the input-output pad PADS of the receiver device through a transmission line TL. A termination circuit 90 of the CTT scheme is connected to the input-output pad PADS of the receiver device for impedance matching. A receiving buffer BF in the receiver device can compare an input signal SI through the input-output pad PADS with a reference voltage VREF to provide a buffer signal SB to an internal circuit of the receiver device. The receiving buffer BF can be implemented by an operational amplifier.

[0153] The transmission driver 40 includes a pull-up unit connected between a first power supply voltage VDDQ and an input-output pad PADH and a pull-down unit connected between the input-output pad PADH and a second power supply voltage VSSQ lower than the first power supply voltage VDDQ. The pull-up unit may include an on-resistor RON (for example, see Fig.16A The pull-down unit may include an on-resistor RON (see, for example, Fig.16AThe on-resistor RON below in the transistors TP1 and TN1 is switched in response to the transmission signal ST. For example, the transmission signal ST may be applied to the gates of the transistors TP1 and TN1. The on-resistor RON may be omitted and each on-resistor RON may represent a resistance between a voltage node and an input-output pad PADH when each of the transistors TP1 and TN1 is turned on.

[0154] The termination circuit 90 of the CTT scheme may include a first sub-termination circuit connected between the first power supply voltage VDDQ and the input-output pad PADS and a second sub-termination circuit connected between the input-output pad PADS and the second power supply voltage VSSQ. The first sub-termination circuit may include a termination resistor Rtt (for example, see Fig.16A The second sub-termination circuit may include a termination resistor Rtt (for example, see Fig.16A The termination resistors Rtt below and the NMOS transistor TN2 turned on in response to the high voltage. The termination resistors Rtt may be omitted and each termination resistor Rtt may represent a resistance between a voltage node and an input-output pad PADS when each of the transistors TP2 and TN2 is turned on.

[0155] exist Fig.16A In the case of the termination circuit 90 of the CTT scheme, it can be as follows Fig. 16B To represent the high voltage level VIH and the low voltage level VIL of the input signal SI. It can be assumed that the second power supply voltage VSSQ is the ground voltage (i.e., VSSQ=0), and the voltage drop along the transmission line TL can be ignored. Therefore, the high voltage level VIH, the low voltage level VIL and the optimal reference voltage VREF can be calculated according to Expression 1.

[0156] Expression 1

[0157] VIH=VDDQ*(RON+Rtt) / (2RON+Rtt),

[0158] VIL=VDDQ*RON / (2RON+Rtt),

[0159] VREF=(VIH+VIL) / 2=VDDQ / 2

[0160] Fig.17A and 17B is a diagram for describing a first pseudo open drain (POD) termination.

[0161] refer to Fig.17A, the transmission driver 40 in the transmitter device drives the input-output pad PADH based on the transmission signal ST of the internal signal from the transmitter device. The input-output pad PADH of the transmitter device is connected to the input-output pad PADS of the receiver device through the transmission line TL. The termination circuit 91 of the first POD termination scheme can be connected to the input-output pad PADS of the receiver device for impedance matching. The receiving buffer BF in the receiver device can compare the input signal SI through the input-output pad PADS with the reference voltage VREF to provide a buffer signal SB to the internal circuit of the receiver device.

[0162] The transmission driver 40 may include a pull-up unit connected between the first power supply voltage VDDQ and the input-output pad PADH and a pull-down unit connected between the input-output pad PADH and a second power supply voltage VSSQ lower than the first power supply voltage VDDQ. The pull-up unit may include an on-resistor RON (for example, see Fig.17A The pull-down unit may include a turn-on resistor RON (see, for example, Fig.17A The on-resistor RON below in the transistors TP1 and TN1 is switched in response to the transmission signal ST. The on-resistor RON may be omitted and each on-resistor RON may represent a resistance between a voltage node and an input-output pad PADH when each of the transistors TP1 and TN1 is turned on.

[0163] The termination circuit 91 of the first POD termination scheme may include a termination resistor Rtt and an NMOS transistor TN2 turned on in response to a high voltage. The termination resistor Rtt may be omitted and may represent a resistance between a voltage node and an input-output pad PADS when the NMOS transistor TN2 is turned on.

[0164] exist Fig.17A In the case of the termination circuit 91 of the first POD termination scheme, it can be as follows Fig. 17B To represent the high voltage level VIH and the low voltage level VIL of the input signal SI. It can be assumed that the second power supply voltage VSSQ is the ground voltage (i.e., VSSQ=0), and the voltage drop along the transmission line TL can be ignored. Thus, the high voltage level VIH, the low voltage level VIL and the optimal reference voltage VREF can be calculated according to Expression 2.

[0165] Expression 2

[0166] VIH=VDDQ*RTT / (RON+RTT),

[0167] VIL=VSSQ=0,

[0168] VREF=(VIH+VIL) / 2=VDDQ*RTT / 2(RON+RTT)

[0169] Fig.18A and 18B It is a diagram for describing the termination of the second POD.

[0170] refer to Fig.18A , the transmission driver 40 in the transmitter device drives the input-output pad PADH based on the transmission signal ST of the internal signal from the transmitter device. The input-output pad PADH of the transmitter device is connected to the input-output pad PADS of the receiver device through the transmission line TL. The termination circuit 92 of the second POD termination scheme is connected to the input-output pad PADS of the receiver device for impedance matching. The receiving buffer BF in the receiver device can compare the input signal SI through the input-output pad PADS with the reference voltage VREF to provide a buffer signal SB to the internal circuit of the receiver device.

[0171] The transmission driver 40 may include a pull-up unit connected between the first power supply voltage VDDQ and the input-output pad PADH and a pull-down unit connected between the input-output pad PADH and a second power supply voltage VSSQ lower than the first power supply voltage VDDQ. The pull-up unit may include an on-resistor RON (for example, see Fig.18A The pull-down unit may include a turn-on resistor RON (see, for example, Fig.18A The on-resistor RON below in the transistors TP1 and TN1 is switched in response to the transmission signal ST. The on-resistor RON may be omitted and each on-resistor RON may represent a resistance between a voltage node and an input-output pad PADH when each of the transistors TP1 and TN1 is turned on.

[0172] The termination circuit 92 of the second POD termination scheme may include a termination resistor Rtt and a PMOS transistor TP2 turned on in response to a low voltage. The termination resistor Rtt may be omitted and may represent a resistance between a voltage node and an input-output pad PADS when the NMOS transistor TN2 is turned on.

[0173] exist Fig.18A In the case of the termination circuit 92 of the second POD termination scheme, it can be as follows Fig.18BTo represent the high voltage level VIH and the low voltage level VIL of the input signal SI. It can be assumed that the second power supply voltage VSSQ is the ground voltage (i.e., VSSQ=0), and the voltage drop along the transmission line TL can be ignored. Therefore, the high voltage level VIH, the low voltage level VIL and the optimal reference voltage VREF can be calculated according to Expression 3.

[0174] Expression 3

[0175] VIH=VDDQ,

[0176] VIL=VDDQ*RON / (RON+Rtt),

[0177] VREF=(VIH+VIL) / 2=VDDQ*(2RON+Rtt) / 2(RON+Rtt)

[0178] As such, the ODT circuit according to at least one exemplary embodiment of the inventive concept may adopt various termination schemes. In an exemplary embodiment, a training process is performed to obtain an optimal reference voltage VREF according to Expression 1, Expression 2, and Expression 3. In an exemplary embodiment, the memory controller considers ODT resistors of non-target memory blocks, which are continuously enabled to adjust the resistance value of the ODT circuit in the memory controller or the on-resistance value of the transmission driver in the memory controller.

[0179] Fig.19A and 19B is a diagram for describing a mode register of an ODT according to an exemplary embodiment of the inventive concept.

[0180] Information associated with controlling the ODT may be stored in Fig. 7A For example, the associated portion of the mode register 212 may have a Fig.19A and 19B A portion of the values ​​of operands OP0 ˜ OP7 may indicate information on the resistance value of the ODT circuit.

[0181] Fig.19A The value ODT for commonly controlling the resistance value of the ODT circuit in the target memory block and the non-target memory block is shown to be stored in the mode register MR11 among the plurality of mode registers included in the mode register 212. For example, the mode register MR11 can be the twelfth mode register among the plurality of mode registers.

[0182] exist Fig.19AIn the example embodiment, when the operand OP3 has a logic high level, the non-target ODT function is enabled. In an exemplary embodiment, when the memory chip enters a power-down mode, a self-refresh power-down mode, a deep sleep mode, a precharge / activation standby state, a write mode, a write first-in-first-out (FIFO) mode, a read mode, a read FIFO mode, a read DQ calibration mode, or a mode register write mode, the non-target ODT function of the memory block within the memory chip is enabled. The resistance value of the CAODT circuit can be set based on operands OP4 to OP6.

[0183] Fig.19B A value NT-ODT for controlling a resistance value of an ODT circuit in a non-target memory block is shown, which is stored in a mode register MR41 among a plurality of mode registers included in the mode register 212. For example, the mode register MR41 can be a forty-second mode register among the plurality of mode registers.

[0184] The values ​​ODT and NT-ODT may be provided from the memory controller 20 through a mode register write operation. A control code CCD may be provided based on the values ​​ODT and NT-ODT. A resistance value of an ODT circuit in a non-target memory block may be set based on operands OP5 to OP7. Operand OP4 is assigned for post package repair (PPRE) and RFU represents an unused operand. For example, PPRE may allow the memory controller 20 to remap an erroneous row of a memory device (e.g., MU1) to a spare row.

[0185] Fig. 20 Shown based on Fig.19B An example of a resistance value of an ODT circuit in a non-target memory block set by an operand in FIG.

[0186] exist Fig. 20 , RZQ represents a unique resistance and may be 240 ohms (when the memory chip in the memory cell includes a DRAM) or 240 ohms (when the memory chip in the memory cell includes a flash memory). RZQ may have an error margin of 1%. In an exemplary embodiment, when the memory chip in the memory cell includes a DRAM, RZQ is 240 ohms, and when the memory chip in the memory cell includes a flash memory, RZQ is 300 ohms. In an exemplary embodiment, when the memory chip in the memory cell includes a DRAM, RZQ is 300 ohms, and when the memory chip in the memory cell includes a flash memory, RZQ is 240 ohms. For example, as Fig. 20 As shown in , the default resistance value RTT can be set to RZQ / 1, RZQ / 2, RZQ / 3, RZQ / 4, RZQ / 5, RZQ / 6, and so on.

[0187] Fig.21 The diagram illustrates connections of memory dies in a semiconductor memory device (memory subsystem) according to an exemplary embodiment of the inventive concept.

[0188] refer to Fig.21 , the semiconductor memory device 150 includes a first memory die 160 and a second memory die 170 .

[0189] The first memory die 160 includes a first termination resistor R1 for ODT. The first termination resistor R1 may be selectively connected to the first node ND1 based on a switching operation of the first termination connection switch 162. That is, the first termination resistor R1 is selectively connected to the first node ND1 based on the first termination control signal TCS1. The first node ND1 may be connected to the position of an input pad for receiving a signal. A first metal line pattern 166 implemented using, for example, a redistribution layer RDL may be formed between the first node ND1 and one end of the wire bond WB1.

[0190] Therefore, the receiving buffer 164 and the transmitting buffer 165 of the first memory die 160 may be connected to the first node ND1 and may be placed in the central area of ​​the first memory die 160 to transmit and receive signals. The common metal pattern 152 may be placed at the other end of the wire bonding WB1. That is, the common metal pattern 152 and the first metal line pattern 166 may be connected using the wire bonding WB1. In this embodiment, for wire bonding of the first memory die 160, the first metal line pattern 166 may be a wire extending from a pad placed in the center of the die to the edge of the first memory die 160.

[0191] The second memory die 170 includes a second termination resistor R2 for ODT. The second termination resistor R2 can be selectively connected to the second node ND2 based on the switching operation of the second termination connection switch 222. That is, the second termination resistor R2 is selectively connected to the second node ND2 based on the second termination control signal TCS2. The second node ND2 can be connected to the position of the input pad for receiving the signal. The second metal line pattern 176 implemented using, for example, a redistribution layer RDL can be formed between the second node ND2 and one end of the wire bond WB2.

[0192] Therefore, the receiving buffer 174 and the transmitting buffer 175 of the second memory die 170 can be connected to the second node ND2 and can be placed in the central area of ​​the second memory die 170 to send and receive signals. The common metal pattern 152 can be arranged at the other end of the wire bonding WB2. That is, the wire bonding WB2 can be used to connect the common metal pattern 152 and the second metal line pattern 176. In this embodiment, the second metal line pattern 176 can be a wire extending from a pad arranged in the center of the die to the edge of the die for wire bonding of the second memory die 170.

[0193] The first memory die 160 may correspond to a first memory bank and the second memory die 170 may correspond to a second memory bank.

[0194] like Fig.21 As illustrated in FIG. 1 , in a structure in which the first memory die 160 and the second memory die 170 are stacked, one signal line connected to the common metal pattern 152 may have a dual load to perform an operation based on the dual block structure. For example, when a signal applied to one signal line is a command, the command may be sent to the common metal pattern 152 and may be sent to the first metal line pattern 166 connected using the wire bonding WB1 and the second metal line pattern 176 connected using the wire bonding WB2. Therefore, the command may be sent to the receiving buffer 164 of the first memory die 160 and the receiving buffer 174 of the second memory die 170 at the same time.

[0195] Fig. 22 is a cross-sectional view illustrating a 2.5-dimensional (D) chip structure including stacked memory devices according to an exemplary embodiment of the inventive concept.

[0196] refer to Fig. 22 , the 2.5D chip structure 700 may be a chip structure in which a high bandwidth memory (HBM) 740 and a main die 730 are connected using an interposer layer 720. The HBM 740 includes memory dies D11-D14 and the main die functions as a controller (eg, a memory controller).

[0197] The interposer layer 720 may be mounted on a printed circuit board (PCB) and may be electrically connected to the PCB 710 through a flip chip bump FB. The flip chip bump FB may be made of a conductive material.

[0198] The main die 730 and the memory dies D11 to D14 forming the HBM 740 structure may be stacked on the interposer layer 720. Fig. 22In the embodiment of the present invention, the buffer die or the logic die may be omitted. However, the buffer die or the logic die may be placed between the memory die D11 and the interposer layer 720. To implement the structure of HBM 740, through silicon via (TSV) lines may be formed in the memory die D11 to D14. The TSV lines may be electrically connected to micro-bumps (MB) formed between the memory die. Each of the memory die D11 to D14 may correspond to a memory block. The micro-bumps MB may be made of a conductive material.

[0199] Fig.23 is a perspective view illustrating a semiconductor package according to an exemplary embodiment of the inventive concept.

[0200] refer to Fig.23 , the semiconductor package 800 includes a PCB 810, a resistor unit 840, an external connection terminal 860, a first semiconductor chip 820, and a second semiconductor chip 830. A first pad 851 and a second pad 852 may be formed on an upper surface of the PCB 810.

[0201] The first semiconductor chip 820 and the second semiconductor chip 830 may be mounted on the same plane of the PCB 810. The first semiconductor chip 820 and the second semiconductor chip 830 may be mounted on the PCB 810, for example, by a wire bonding method. Therefore, the semiconductor package 800 may include a first bonding wire 821 electrically connecting a first pad 851 of the PCB 810 to the first semiconductor chip 820, and a second bonding wire 831 connecting a second pad 852 of the PCB 810 to the second semiconductor chip 830. In some embodiments, the first semiconductor chip 820 and the second semiconductor chip 830 may be mounted on the PCB 810, for example, by a flip chip bonding method.

[0202] The resistor unit 840 may be mounted on the PCB 810. The resistor unit 810 may include a plurality of connection terminals, including a first connection terminal and a second connection terminal. The first connection terminal of the resistor unit 840 is connected to a first pad 851 on the PCB 810. The second connection terminal of the resistor unit 840 may be connected to a second pad 852 on the PCB 810.

[0203] The first semiconductor chip 820 and the second semiconductor chip 830 may correspond to a first memory chip and a second memory chip respectively corresponding to different memory blocks.

[0204] Fig.24 is a diagram illustrating a semiconductor package including a stacked memory device according to an exemplary embodiment of the inventive concept.

[0205] refer to Fig.24 , the semiconductor package 900 includes one or more stacked memory devices 910 and a memory controller (CONT) 920 .

[0206] The stacked memory device 910 and the memory controller 920 may be mounted on an interposer 930, and the interposer on which the stacked memory device 910 and the memory controller 920 are mounted may be mounted on a package substrate 940. Figure 1 The memory controller 920 is implemented by the memory controller 20 in FIG.

[0207] Each of the stacked memory devices 910 may be implemented in various forms, and each of the stacked memory devices 910 may be a memory device in the HBM form in which a plurality of layers are stacked. Therefore, each of the stacked memory devices 910 may include a buffer die and a plurality of memory dies, and each of the memory dies may include a memory cell array and an ODT circuit connected to a data I / O pin.

[0208] Therefore, in a write operation and a read operation, each of the stacked memory devices 910 or each of the memory dies in the stacked memory device 910 can be identified as a target memory block and a non-target memory block. In an exemplary embodiment, the resistance value of the ODT circuit of the non-target memory block is set to have a first resistance value in a write operation, and the resistance value of the ODT circuit of the non-target memory block is set to have a second resistance value different from the first resistance value in a read operation, and thus performance can be enhanced.

[0209] A plurality of stacked memory devices 910 may be mounted on the interposer 930 , and the memory controller 920 may communicate with the plurality of stacked memory devices 910 .

[0210] For example, each of the stacked memory devices 910 and the memory controller 920 may include a physical region, and communication may be performed between the stacked memory devices 910 and the memory controller 920 through the physical region. Meanwhile, when each of the stacked memory devices 910 includes a direct access region, a test signal may be provided to each of the stacked memory devices 910 through a conductive means (e.g., solder balls 950) mounted under the package substrate 940 and the direct access region.

[0211] Embodiments of the inventive concept can be applied to various systems including multiple memory blocks. For example, the inventive concept can be applied to systems such as memory cards, mobile phones, smart phones, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, video cameras, personal computers (PCs), server computers, workstations, laptop computers, digital TVs, set-top boxes, portable game consoles, and the like.

[0212] The above descriptions illustrate exemplary embodiments of the inventive concept and are not to be construed as limiting thereof. Although some exemplary embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without substantially departing from the inventive concept.

Claims

1. A method for controlling on-die termination of ODT in a memory system, the memory system comprising a plurality of memory cells sharing a data bus to exchange data, the method comprising: causing the ODT circuits of the plurality of memory cells to enter an initial state; During a write operation to a target memory cell among the plurality of memory cells, setting a resistance value of an ODT circuit of a non-target memory cell among the plurality of memory cells to a first resistance value; as well as During a read operation on a target memory cell among the plurality of memory cells, setting a resistance value of an ODT circuit of a non-target memory cell among the plurality of memory cells to a second resistance value, When the current mode of the memory system is the first mode, the first resistance value and the second resistance value are the same, and when the current mode is the other second mode, the first resistance value and the second resistance value are different.

2. The method according to claim 1, wherein: The plurality of memory cells include a plurality of memory blocks, the plurality of memory blocks being independently selected based on a plurality of chip selection signals, respectively; and Each of the plurality of memory blocks includes at least one memory chip.

3. The method according to claim 2, wherein: Each of the plurality of memory units shares one channel including the data bus and a command / address bus.

4. The method according to claim 1, wherein: The plurality of memory units include a plurality of memory chips, the plurality of memory chips being independently selected based on a plurality of chip selection signals, respectively; and Each of the plurality of memory chips includes a nonvolatile memory chip.

5. The method according to claim 1, wherein: The plurality of memory cells are stacked on a substrate and connected to the substrate through wire bonding or through silicon vias.

6. The method according to claim 1, wherein: Each of the plurality of memory cells includes a mode register configured to set a resistance value of a corresponding ODT circuit.

7. The method according to claim 1, further comprising: When the current mode is a third mode, during one of the write operation and the read operation, the ODT circuits of the non-target memory cells are disabled.

8. The method according to claim 1, wherein: When the current mode is the second mode, the first resistance value is 120 ohms and the second resistance value is 90 ohms.

9. The method according to claim 1, wherein: Each of the ODT circuits of the plurality of memory cells includes a plurality of pull-up termination resistors connected between a power supply voltage and a data input / output I / O pin.

10. The method according to claim 1, wherein: When the current mode is the second mode, The first resistance value is RZQ / 2 and the second resistance value is RZQ / 4; RZQ corresponds to a unique resistance of each of the ODT circuits of the plurality of memory cells; and RZQ is one of 240 ohms and 300 ohms and has a 1% error margin.

11. The method according to claim 1, wherein: The plurality of memory cells include a first memory bank and a second memory bank, the first memory bank and the second memory bank being independently selected based on a first chip select signal and a second chip select signal, respectively; The first memory block includes at least a first memory chip; The second memory block includes at least a second memory chip; In response to the first chip select signal, designating the first memory block as a target memory block; In response to the second chip select signal, designating the second memory block as a non-target memory block; A twelfth mode register among the plurality of mode registers in the second memory block is configured to set a non-target ODT function of the second memory block; A forty-second mode register among the plurality of mode registers in the second memory block is configured to set a resistance value of an ODT circuit of the second memory block; and When at least one second memory chip enters a power-down mode, a self-refresh power-down mode, a deep sleep mode, a precharge / activation standby state, a write mode, a write first-in-first-out FIFO mode, a read mode, a read FIFO mode, a read DQ calibration mode or a mode register write mode, the non-target ODT function of the second memory block is enabled.

12. The method according to claim 1, wherein: The target memory cell of the write or read operation is converted from the power-down mode to the normal operation mode to perform the corresponding operation, and the non-target memory cell maintains the power-down mode during the corresponding write operation or read operation.

13. The method of claim 1, wherein: Each of the plurality of memory cells includes a mode register configured to set a resistance value of a corresponding ODT circuit; and The mode register in the non-target memory cell is configured to separately store the first resistance value and the second resistance value.

14. A memory system comprising: multiple memory banks sharing a data bus and a command / address bus; as well as a memory controller configured to control the plurality of memory blocks, Wherein, the on-die termination ODT circuits of the plurality of memory blocks are made to enter an initial state; wherein, during a write operation to a target memory block among the plurality of memory blocks, the resistance value of the ODT circuit of a non-target memory block among the plurality of memory blocks is set to a first resistance value; and wherein, during a read operation on a target memory block among the plurality of memory blocks, the resistance value of the ODT circuit of a non-target memory block among the plurality of memory blocks is set to a second resistance value, When the current mode of the memory system is the first mode, the first resistance value and the second resistance value are the same, and when the current mode is the other second mode, the first resistance value and the second resistance value are different.

15. The memory system of claim 14, wherein: The plurality of memory blocks are independently selected based on a plurality of chip selection signals, respectively; and Each of the plurality of memory blocks includes at least one memory chip.

16. The system of claim 14, wherein each of the plurality of memory blocks comprises a mode register configured to set a resistance value of a corresponding ODT circuit, and in, The mode registers in the non-target memory bank among the plurality of mode registers are configured as follows: In a third mode among the plurality of modes, during one of a write operation being performed and a read operation being performed, the ODT circuit of the non-target memory cell is set to be disabled.

17. The memory system of claim 14, wherein: When the current mode is the second mode, the first resistance value corresponds to 120 ohms and the second resistance value corresponds to 90 ohms.

18. A memory system comprising: A first memory block and a second memory block which share a data bus and a command / address bus; as well as a memory controller configured to control the first memory bank and the second memory bank, Wherein, the first memory block includes a first dynamic random access memory DRAM chip and the second memory block includes a second DRAM chip; Wherein, the on-die termination ODT circuits of the first and second DRAM chips are made to enter an initial state; wherein, during a write operation to a first DRAM chip corresponding to a write target of the first and second DRAM chips, a resistance value of an ODT circuit of the second DRAM chip corresponding to a non-write target of the first and second DRAM chips is set to a first resistance value; and During a read operation on the first DRAM chip, the resistance value of the ODT circuit of the second DRAM chip is set to a second resistance value different from the first resistance value.

19. The memory system of claim 18, wherein: During a write operation to the first DRAM chip, changing the resistance value of the ODT circuit of the second DRAM chip from a default resistance value corresponding to the initial state to the first resistance value; and During a read operation on the first DRAM chip, a resistance value of the ODT circuit of the second DRAM chip is changed from the first resistance value to the second resistance value.

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