Pillar copper bump, semiconductor chip and semiconductor device

Abstract

The present invention provides a pillar-shaped copper bump, a semiconductor chip, and a semiconductor device. The pillar-shaped copper bump is formed on an electrode pad of a semiconductor chip and comprises: a first copper layer; a first metal layer formed directly above the first copper layer; a second copper layer formed directly above the first metal layer; and a second metal layer formed directly above the second copper layer. The first and second metal layers are formed of metals having different etching rates than copper. The outer periphery of the first metal layer forms an annular protrusion outside the side surface of the first copper layer, and the outer periphery of the second metal layer forms an annular protrusion outside the side surface of the second copper layer.

Description

Technical Field

[0001] The present invention relates to a copper pillar bump, a semiconductor chip and a semiconductor device. Background Art

[0002] Semiconductor devices in which a semiconductor chip is mounted on a wiring substrate are well known. In such semiconductor devices, bumps are sometimes provided on the electrode pads of the semiconductor chip to connect to the pads of the wiring substrate. Examples of such bumps include structures in which multiple metal layers of different materials are stacked. The bumps of the semiconductor chip and the pads of the wiring substrate are connected using solder.

[0003] Patent Document 1: (Japanese) Patent Publication No. 2006-295109

[0004] Patent Document 2: U.S. Patent Specification No. 10403590 Summary of the Invention

[0005] [Technical problems to be solved]

[0006] A sufficient amount of solder is required to achieve a highly reliable connection between the semiconductor chip and the wiring substrate. However, if the amount of solder is too high, there is a risk that excess solder will reach the sides of the bumps, causing them to come into contact with the semiconductor chip. In this case, contact between the solder and the semiconductor chip can cause problems such as short circuits.

[0007] The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to provide a pillar-shaped copper bump having a structure in which excess solder is unlikely to reach the side surfaces thereof.

[0008] [Technical solution]

[0009] This pillar-shaped copper bump is formed on an electrode pad of a semiconductor chip and comprises: a first copper layer; a first metal layer formed directly above the first copper layer; a second copper layer formed directly above the first metal layer; and a second metal layer formed directly above the second copper layer. The first and second metal layers are formed of metals having different etching rates than copper. The outer periphery of the first metal layer forms a ring-shaped protrusion outside the side surface of the first copper layer, and the outer periphery of the second metal layer forms a ring-shaped protrusion outside the side surface of the second copper layer.

[0010] [Beneficial Effects]

[0011] According to the disclosed technology, it is possible to provide a pillar-shaped copper bump having a structure in which excess solder is unlikely to reach the side surfaces thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is an exemplary partial cross-sectional view of a semiconductor chip having pillar-shaped copper bumps according to the first embodiment.

[0013] Figure 2 This is an illustrative diagram (part 1) of the steps for manufacturing the pillar-shaped copper bump according to the first embodiment.

[0014] Figure 3 This is an illustrative diagram (part 2) of the manufacturing steps of the pillar-shaped copper bump according to the first embodiment.

[0015] Figure 4 This is an illustrative diagram (part 3) of the manufacturing steps of the pillar-shaped copper bump according to the first embodiment.

[0016] Figure 5 This is a schematic diagram showing a comparative example of a semiconductor chip connected to a pad of a wiring board.

[0017] Figure 6 This is a schematic diagram showing the case where the semiconductor chip of this embodiment is connected to the pad of the wiring board.

[0018] Figure 7 This is an exemplary partial cross-sectional view of a semiconductor chip having pillar-shaped copper bumps according to Modification 1 of the first embodiment.

[0019] Figure 8 This is an exemplary partial cross-sectional view of a semiconductor chip having pillar-shaped copper bumps according to a second modification of the first embodiment.

[0020] Figure 9 This is an exemplary cross-sectional view of a semiconductor device according to a second embodiment.

[0021] Description of reference numerals:

[0022] 1 Semiconductor devices

[0023] 10 Wiring board

[0024] 11 Insulation layer

[0025] 12, 13 wiring layers

[0026] 14, 15 solder mask layer

[0027] 14x, 15x opening

[0028] 16 solder bumps

[0029] 100, 100A, 100B semiconductor chips

[0030] 110 semiconductor substrate

[0031] 110a Circuit formation surface

[0032] 120 electrode pads

[0033] 130, 130A, 130B pillar copper bumps

[0034] 131, 138 metal layer

[0035] 132, 134, 137 copper layers

[0036] 133, 135 nickel layer

[0037] 136 solder layer

[0038] 200 Underfill resin DETAILED DESCRIPTION

[0039] Hereinafter, the embodiment of the present invention will be described with reference to the accompanying drawings. It should be noted that in the drawings, the same components are denoted by the same reference numerals and overlapping descriptions are omitted.

[0040] <First embodiment>

[0041] [Structure of Pillar Copper Bump According to First Embodiment]

[0042] Figure 1 FIG. 1 is a partial cross-sectional view of a semiconductor chip having pillar-shaped copper bumps according to the first embodiment. Figure 1 As shown, the semiconductor chip 100 has a semiconductor substrate 110 , an electrode pad 120 and a pillar-shaped copper bump 130 .

[0043] It should be noted that, in the present embodiment, for the sake of convenience, the electrode pad 120 side of the semiconductor chip 100 is referred to as the upper side or one side, and the opposite side thereof is referred to as the lower side or the other side. In addition, the surface of the electrode pad 120 side of the semiconductor chip 100 is referred to as one face or upper surface, and the surface of the opposite side thereof is referred to as the other face or lower surface. However, the semiconductor chip 100 can also be used inverted (upside down) or can be configured (arranged) at any angle. In addition, a plan view refers to a view obtained when observing an object (object) from the normal direction of the circuit forming surface 110a of the semiconductor chip 100, and a planar shape refers to a shape obtained when observing an object from the normal direction of the circuit forming surface 110a of the semiconductor chip 100.

[0044] The semiconductor chip 100 is a chip in which a semiconductor integrated circuit (not shown) and the like are formed on a thinned semiconductor substrate 110 made of, for example, silicon. Electrode pads 120 electrically connected to the semiconductor integrated circuit (not shown) are formed on the semiconductor substrate 110. Electrode pads 120 can be formed of, for example, aluminum.

[0045] Pillared copper bump 130 is formed on electrode pad 120 of semiconductor chip 100. Specifically, pillared copper bump 130 has a structure in which a metal layer 131, a copper layer 132, a nickel layer 133, a copper layer 134, a nickel layer 135, and a solder layer 136 are stacked in this order from the electrode pad 120 side. For example, in a plan view, the area of ​​pillared copper bump 130 is smaller than that of electrode pad 120, and electrode pad 120 is exposed in a ring shape on the outer periphery of pillared copper bump 130.

[0046] The metal layer 131 is a layer used as a seed layer when forming the copper layer 132, etc., and is formed directly above the electrode pad 120 (directly formed on the upper surface of the electrode pad 120). As the material of the metal layer 131, for example, copper (Cu), titanium (Ti), chromium (Cr), tungsten (W), alloys of two or more of these metals, and stacked films of two or more of these metals can be used. The thickness of the metal layer 131 can be, for example, about 0.01 to 0.3 μm. The planar shape of the metal layer 131 is, for example, roughly circular. In this case, the diameter of the metal layer 131 can be about 10 to 100 μm, preferably about 25 to 50 μm. It should be noted that in this embodiment, as an example, the metal layer 131 can be a stacked film in which a copper layer is stacked on a titanium layer.

[0047] Copper layer 132 is an electrolytically plated layer and is formed directly above metal layer 131. The thickness of copper layer 132 can be, for example, approximately 10 to 200 μm, preferably approximately 20 to 150 μm. The planar shape of copper layer 132 is substantially the same as that of metal layer 131, and copper layer 132 is formed so as to overlap metal layer 131 in plan view.

[0048] The nickel layer 133 is an electrolytic plating layer and is formed directly above the copper layer 132. The thickness of the nickel layer 133 can be, for example, about 2 to 20 μm, preferably about 5 to 10 μm. The planar shape of the nickel layer 133 is, for example, roughly circular. In this case, the diameter of the nickel layer 133 can be about 1 to 20 μm larger than the diameter of the copper layer 132. In other words, the outer peripheral side of the nickel layer 133 is annularly protruding on the outside of the side surface of the copper layer 132, and the protrusion amount can be controlled to be between about 0.5 and 10 μm, but preferably about 2 to 5 μm. It should be noted that the protrusion amount of the outer peripheral side of the nickel layer 133 on the outside of the side surface of the copper layer 132 is greater than the thickness of the metal layer 131 (seed layer) formed directly below the copper layer 132.

[0049] Copper layer 134 is an electrolytically plated layer and is formed directly above nickel layer 133. The thickness of copper layer 134 can be, for example, approximately 2 to 20 μm, preferably approximately 5 to 10 μm. The planar shape of copper layer 134 is substantially the same as that of metal layer 131 and copper layer 132, and copper layer 134 is formed so as to overlap with metal layer 131 and copper layer 132 in a plan view. In a plan view, the area of ​​copper layer 134 is smaller than that of nickel layer 133, and nickel layer 133 is exposed in a ring shape on the outer periphery of copper layer 134.

[0050] The nickel layer 135 is an electrolytic plating layer and is formed directly above the copper layer 134. The thickness of the nickel layer 135 can be, for example, about 2 to 20 μm, preferably about 5 to 10 μm. The planar shape of the nickel layer 135 is substantially the same as the planar shape of the nickel layer 133, and the nickel layer 135 is formed so as to overlap with the nickel layer 133 in a planar view. The planar shape of the nickel layer 135 is, for example, roughly circular. In this case, the diameter of the nickel layer 135 can be about 1 to 20 μm larger than the diameter of the copper layer 134. In other words, the outer peripheral side of the nickel layer 135 is annularly protruding on the outside of the side surface of the copper layer 134, and the protrusion amount can be controlled to be between about 0.5 and 10 μm, but is preferably about 2 to 5 μm. Note that the amount by which the outer peripheral side of the nickel layer 135 protrudes outside the side surface of the copper layer 134 is greater than the thickness of the metal layer 131 (seed layer) formed directly below the copper layer 132 .

[0051] The solder layer 136 is formed directly above the nickel layer 135. The shape of the solder layer 136 is, for example, a dome shape. Here, the dome shape refers to a shape in which the height near the center (nearby) is higher and gradually becomes lower toward the peripheral portion. The thickness of the solder layer 136 (the maximum thickness near the center) can be, for example, about 10 μm. The planar shape of the solder layer 136 is substantially the same as the planar shape of the nickel layer 135, and the solder layer 136 is formed to overlap with the nickel layer 135 in a plan view. As the material of the solder layer 136, for example, an alloy containing Pb, an alloy of Sn and Cu, an alloy of Sn and Ag, an alloy of Sn, Ag and Cu, etc. can be used.

[0052] [Method for Manufacturing Pillar Copper Bump According to First Embodiment]

[0053] Next, a method for manufacturing the pillar-shaped copper bump according to the first embodiment will be described. Figures 2 to 4 1 and 2 are diagrams illustrating exemplary steps of manufacturing a pillar-shaped copper bump according to the first embodiment.

[0054] First, in Figure 2In step (a), a semiconductor substrate 110 having an electrode pad 120 formed on a circuit-forming surface 110a is prepared, and a metal layer 131 is formed on the semiconductor substrate 110 and the electrode pad 120. The material and thickness of the metal layer 131 are as described above. The metal layer 131 can be formed by, for example, electroless plating or sputtering.

[0055] Then, in Figure 2 In step (b), a resist layer 900 is formed on the circuit-forming surface 110a of the semiconductor substrate 110. Specifically, for example, a dry film resist made of a photosensitive resin (photosensitive resin) is laminated on the circuit-forming surface 110a of the semiconductor substrate 110 to serve as the resist layer 900. Next, the resist layer 900 made of the dry film resist is patterned by exposure and development to form openings 900x. The openings 900x selectively expose the upper surface of the metal layer 131, which forms a portion of the copper layer 132, etc.

[0056] Next, in Figure 2 In step (c), copper layer 132 is formed on the upper surface of metal layer 131 exposed in opening 900x of resist layer 900 by electrolytic plating using metal layer 131 as a seed layer (feeding layer). The thickness of copper layer 132 is as described above.

[0057] Afterwards, in Figure 3 In step (a), nickel layer 133, copper layer 134, and nickel layer 135 are sequentially stacked on copper layer 132 by electrolytic plating using metal layer 131 as a seed layer (feeding layer). The thicknesses of nickel layer 133, copper layer 134, and nickel layer 135 are as described above.

[0058] Next, in Figure 3 In the step (b), the solder layer 136 is laminated on the nickel layer 135 by electrolytic plating using the metal layer 131 as a seed layer (feeding layer). The material and thickness of the solder layer 136 are as described above.

[0059] Then, in Figure 3 In the step (c), Figure 3 The resist layer 900 shown in (c) is peeled off. For example, the resist layer 900 can be peeled off using a stripping solution containing sodium hydroxide or the like.

[0060] Next, in Figure 4 In step (a), an etchant capable of etching copper is used to dissolve and remove the metal layer 131 not covered by the copper layer 132. Examples of the etchant include a hydrogen peroxide / sulfuric acid aqueous solution, a sodium persulfate aqueous solution, an ammonium persulfate aqueous solution, and nitric acid.

[0061] During etching, since nickel layers 133 and 135 are insoluble in an etchant capable of etching copper, the copper layer contained in metal layer 131 (a laminated film in which a copper layer is laminated on a titanium layer), copper layer 132, and copper layer 134 are selectively etched. As a result, the portion of metal layer 131 not covered by copper layer 132 is removed, and the outer peripheries of copper layers 132 and 134 are etched.

[0062] Accordingly, the outer circumference of nickel layer 133 can be annularly raised outside the side surface of copper layer 132, and the outer circumference of nickel layer 135 can be annularly raised outside the side surface of copper layer 134. In addition, by controlling the etching time and other factors, the amount of protrusion of nickel layers 133 and 135 can be made greater than the thickness of metal layer 131.

[0063] Next, an etching solution that does not dissolve copper and nickel but dissolves titanium is used to remove the titanium layer included in the metal layer 131. In this way, the metal layer 131 that is not covered by the copper layer 132 can be completely removed.

[0064] Afterwards, in Figure 4 In step (b), the solder layer 136 is melted and solidified by reflow, etc., and is then formed into a dome shape, etc. Thus, the pillar-shaped copper bump 130 is formed on the electrode pad 120, and the semiconductor chip 100 is completed.

[0065] Here, the effects of the pillar-shaped copper bump 130 will be described with reference to a comparative example.

[0066] Figure 5 This is a schematic diagram of a comparative example of a semiconductor chip connected to a pad on a wiring board. Figure 5 In the semiconductor chip 100X shown, a pillar-shaped copper bump 130X is formed on the electrode pad 120. The pillar-shaped copper bump 130X is similar to the pillar-shaped copper bump 130 (see FIG. Figure 1 The difference between the above-mentioned embodiment and the above-mentioned embodiment is that there is no nickel layer 133, copper layer 134 and nickel layer 135.

[0067] like Figure 5 As shown in (a), the semiconductor chip 100X is arranged on the pad 320 of the wiring substrate 310 so that the pillar-shaped copper bump 130X faces the pad 320 side, and the solder layer 136 of the pillar-shaped copper bump 130X is melted and then solidified. For example, if the amount of solder constituting the solder layer 136 is large, as shown in FIG. Figure 5As shown in (b), there is a case where excess solder reaches the side of the pillar-shaped copper bump 130X, causing the solder to come into contact with the circuit forming surface 110a of the semiconductor chip 100X. In this case, since the solder comes into contact with the circuit forming surface 110a, a fault such as a short circuit may occur. However, since a sufficient amount of solder is required to achieve a highly reliable connection, it is difficult to reduce the amount of solder.

[0068] Figure 6 This schematic diagram shows the semiconductor chip of this embodiment connected to a pad on a wiring board. Unlike semiconductor chip 100X, semiconductor chip 100 has pillar-shaped copper bumps 130. Specifically, the outer periphery of nickel layer 133 protrudes in a ring shape outside the side surface of copper layer 132, and the outer periphery of nickel layer 135 protrudes in a ring shape outside the side surface of copper layer 134.

[0069] For this reason, Figure 6 As shown in (a), even if the semiconductor chip 100 is arranged on the solder pad 320 of the wiring substrate 310 in a manner such that the columnar copper bump 130 faces the solder pad 320 side, and the solder layer 136 is melted and then solidified, the excess solder will not reach the side of the columnar copper bump 130. That is, even if the amount of solder constituting the solder layer 136 is large, since the solder wettability of the nickel layers 133 and 135 is worse than that of the copper layer, it is difficult for the excess solder to reach the side of the columnar copper bump 130. In particular, by providing raised portions on the nickel layers 133 and 135, not only the surface area of ​​the portion that the solder can reach is increased, but also the distance to the semiconductor chip 100 is increased, so it is more difficult for the excess solder to reach the side of the columnar copper bump 130. In addition, even if it is assumed that the excess solder reaches the side of the columnar copper bump 130, as shown in FIG. Figure 6 As shown in (b), excess solder is blocked by the protrusions of the nickel layer 133 and thus is unlikely to reach the circuit formation surface 110 a side of the semiconductor chip 100 .

[0070] As described above, in pillar-shaped copper bump 130, nickel layer 133 acts as a dam, so excess solder is blocked by the protruding portion of nickel layer 133 and prevented from reaching circuit-forming surface 110a of semiconductor chip 100. As a result, the occurrence of failures such as circuit shorts caused by solder contact with circuit-forming surface 110a of semiconductor chip 100 can be suppressed.

[0071] It should be noted that it is preferred to form a laminated film composed of at least one copper layer and a nickel layer stacked in sequence between the nickel layer 133 and the copper layer 134, with the outer periphery of the nickel layer in the laminated film forming a ring-shaped protrusion outside the side of the copper layer. This increases the number of nickel layers that can act as dams, so excess solder is blocked by the protrusions of each nickel layer, making it more difficult for it to reach the circuit formation surface 110a of the semiconductor chip 100.

[0072] In addition, although the above description shows an example in which a copper layer and a nickel layer are stacked in the pillar-shaped copper bump 130, a metal layer other than a nickel layer can be used as long as the metal layer is formed of a metal with a different etching rate than copper. As a metal with a different etching rate than copper, in addition to nickel, for example, any one of chromium (Cr), titanium (Ti), tantalum (Ta), cobalt (Co), gold (Au), silver (Ag), platinum (Pt), and palladium (Pd) can be used. Among these metals, any one of Ni, Cr, Ti, Ta, and Co is preferably used. These are materials with poorer solder wettability than copper, so excess solder is unlikely to reach the side surfaces of the pillar-shaped copper bump 130.

[0073] <Modification 1 of the First Embodiment>

[0074] Modification 1 of the first embodiment shows an example of a pillar-shaped copper bump having a different stacked structure from that of the first embodiment. Note that in Modification 1 of the first embodiment, descriptions of components identical to those of the previously described embodiment may be omitted.

[0075] Figure 7 FIG. 1 is a partial cross-sectional view of a semiconductor chip having pillar-shaped copper bumps according to a first modification of the first embodiment. Figure 7 As shown, the semiconductor chip 100A includes a semiconductor substrate 110, an electrode pad 120, and a pillar copper bump 130A. The pillar copper bump 130A and the pillar copper bump 130 (see Figure 1 The difference between the nickel layer 135 and the solder layer 136 is that a copper layer 137 is added between the nickel layer 135 and the solder layer 136. In other words, in the pillar-shaped copper bump 130A, the copper layer 137 is stacked directly on the nickel layer 135, and then the solder layer 136 is stacked directly on the copper layer 137.

[0076] Copper layer 137 is an electrolytically plated layer and is formed directly above nickel layer 135. The thickness of copper layer 137 can be, for example, approximately 2 to 20 μm, preferably approximately 5 to 10 μm. The planar shape of copper layer 137 is substantially the same as the planar shapes of metal layer 131, copper layer 132, and copper layer 134. Copper layer 137 is formed so as to overlap with metal layer 131, copper layer 132, and copper layer 134 in a plan view. In a plan view, the area of ​​copper layer 137 is smaller than that of nickel layer 135, and nickel layer 135 is exposed in a ring shape on the outer periphery of copper layer 137.

[0077] As described above, the lower layer of the solder layer 136 may also be a copper layer. In this case, the outer peripheral side of the nickel layer 133 is annularly raised outside the side surface of the copper layer 132, and the outer peripheral side of the nickel layer 135 is annularly raised outside the side surface of the copper layer 134, so the same effect as the first embodiment is achieved.

[0078] <Modification 2 of the First Embodiment>

[0079] Modification 2 of the first embodiment shows an example in which no solder layer is provided on the uppermost layer. Note that, in Modification 2 of the first embodiment, descriptions of components identical to those of the previously described embodiment may be omitted.

[0080] Figure 8 FIG. 1 is a partial cross-sectional view of a semiconductor chip having pillar-shaped copper bumps according to a second modification of the first embodiment. Figure 8 As shown, the semiconductor chip 100B has a semiconductor substrate 110, an electrode pad 120 and a pillar copper bump 130B. The pillar copper bump 130B and the pillar copper bump 130 (see Figure 1 The difference between the above-mentioned embodiments is that a metal layer 138 is formed as the uppermost layer directly above the nickel layer 135 instead of the solder layer.

[0081] Metal layer 138 is provided to improve connection reliability with solder and can be formed from a material having better solder wettability than nickel layer 135. Examples of metal layer 138 include an Au film, a Pd / Au film (a metal film in which a Pd film and an Au film are stacked in this order), and the like. Metal layer 138 can be formed by either electrolytic or electroless plating.

[0082] As described above, pillar-shaped copper bump 130B may not have a solder layer. In this case, for example, solder can be pre-formed on the pad side of the wiring substrate. Alternatively, when connecting pillar-shaped copper bump 130B to the wiring substrate pad, solder can be applied to metal layer 138 of pillar-shaped copper bump 130B and / or the wiring substrate pad.

[0083] <Second embodiment>

[0084] The second embodiment shows an example of a semiconductor device in which a wiring board and a semiconductor chip are electrically connected via pillar-shaped copper bumps. Note that in the second embodiment, descriptions of components identical to those in the previously described embodiments may be omitted.

[0085] Figure 9 : is an exemplary cross-sectional view of a semiconductor device according to the second embodiment. Figure 9 As shown, semiconductor device 1 includes wiring board 10, semiconductor chip 100, and underfill resin 200. Wiring board 10 includes insulating layer 11 made of insulating resin or the like, wiring layers 12 and 13 made of copper or the like, solder resist layers 14 and 15 made of insulating resin or the like, and solder bumps 16.

[0086] In wiring substrate 10, wiring layer 12 is formed on one surface of insulating layer 11, and wiring layer 13 is formed on the other surface. Furthermore, solder resist layer 14 is formed on one surface of insulating layer 11 to cover wiring layer 12, with a portion of wiring layer 12 exposed through openings 14x in solder resist layer 14. Furthermore, solder resist layer 15 is formed on the other surface of insulating layer 11 to cover wiring layer 13, with a portion of wiring layer 13 exposed through openings 15x in solder resist layer 15. Solder bumps 16 are formed on wiring layer 13 exposed through openings 15x.

[0087] It should be noted that Figure 9 The insulating layer 11 is shown as an insulating layer of a single layer, but the insulating layer 11 may also be a multilayer wiring substrate. For example, a multilayer wiring substrate may be a structure in which multiple insulating layers and wiring layers are alternately stacked, and the required wiring layers are electrically connected via via wiring that penetrates the insulating layers. In this case, the multilayer wiring substrate may have a substrate serving as a core, or may be a coreless substrate. In addition, the substrate serving as a core may also have a reinforcing material such as glass epoxy resin.

[0088] The semiconductor chip 100 is flip-chip mounted on the wiring substrate 10 in a manner such that the circuit forming surface 110a faces the solder resist layer 14 side (in a face-down state). Specifically, the electrode pads 120 of the semiconductor chip 100 are electrically connected to the wiring layer 12 exposed from the opening 14x of the solder resist layer 14 via the pillar-shaped copper bumps 130. More specifically, the solder layer 136 of the pillar-shaped copper bumps 130 melts and then solidifies, thereby bonding to the wiring layer 12 exposed from the opening 14x of the solder resist layer 14.

[0089] An underfill resin 200 is filled between the circuit formation surface 110a of the semiconductor chip 100 and the upper surface of the solder resist layer 14 of the wiring substrate 10. The underfill resin 200 may cover a portion or all of the side surfaces of the semiconductor chip 100. The underfill resin 200 exposes the back surface of the semiconductor chip 100. A mold resin may also be provided on the wiring substrate 10 to cover the semiconductor chip 100 and the underfill resin 200.

[0090] As described above, the electrode pads 120 of the semiconductor chip 100 are electrically connected to the wiring layer 12 exposed from the openings 14x of the solder resist layer 14 via the pillar-shaped copper bumps 130. Furthermore, as described above, in pillar-shaped copper bumps 130, the outer periphery of the nickel layer 133 protrudes in a ring-shaped manner outside the side surfaces of the copper layer 132, and the outer periphery of the nickel layer 135 protrudes in a ring-shaped manner outside the side surfaces of the copper layer 134. Thus, when the solder layer 136 of the pillar-shaped copper bumps 130 is melted to connect the electrode pads 120 and the wiring layer 12, excess solder is blocked by the protruding portions of the nickel layer 133 and prevented from reaching the circuit forming surface 110a of the semiconductor chip 100. As a result, the occurrence of faults such as circuit shorts caused by solder contact with the circuit forming surface 110a of the semiconductor chip 100 can be suppressed.

[0091] It should be noted that, after the electrode pads 120 and the wiring layer 12 are connected, the underfill resin 200 can be filled by flowing the resin between the circuit forming surface 110a of the semiconductor chip 100 and the upper surface of the solder resist layer 14 of the wiring substrate 10. Therefore, when the underfill resin 200 contains a filler, it is preferable that the filler contain an average particle size smaller than the distance between the protrusions of the nickel layer 133 and the protrusions of the nickel layer 135 (the thickness of the copper layer 134).

[0092] This prevents the filler from being caught between the protrusions of nickel layer 133 and nickel layer 135. Furthermore, since underfill resin 200 containing the filler covers the entirety of pillar-shaped copper bump 130, including the space between the protrusions of nickel layer 133 and nickel layer 135, stress can be dispersed.

[0093] It should be noted that the method for supplying the underfill resin 200 is not limited to the above-described method. For example, a film of underfill resin may be pre-placed on the wiring substrate 10, and the pillar-shaped copper bumps 130 of the semiconductor chip 100 may be bonded to the wiring substrate 10 while penetrating the underfill resin.

[0094] However, in the method described above where resin is flowed between the circuit forming surface 110a of the semiconductor chip 100 and the upper surface of the solder resist layer 14 of the wiring substrate 10 for filling, air is present around the pillar-shaped copper bump 130 when the electrode pad 120 and the wiring layer 12 are connected. Therefore, compared to the method using a film-like underfill resin, the solder is more likely to crawl up the sides of the pillar-shaped copper bump 130 when the resin is flowed for filling, so the effect of providing the raised portion on the nickel layer (anti-crawling effect) is more significant.

[0095] It should be noted that the structure of the semiconductor device 1 described above is merely an example. The semiconductor chip 100 having the pillar-shaped copper bumps 130 can be mounted on a wiring substrate having various structures. Furthermore, the semiconductor chip 100 having the pillar-shaped copper bumps 130 can also be embedded within a wiring substrate. Furthermore, pillar-shaped copper bumps 130A or 130B can be used in place of pillar-shaped copper bumps 130.

[0096] Based on the above, a pillar-shaped copper bump can be provided, which is formed on an electrode pad of a semiconductor chip and comprises: a first copper layer; a first metal layer formed directly above the first copper layer; a second copper layer formed directly above the first metal layer; and a second metal layer formed directly above the second copper layer. The first and second metal layers are formed of metals having different etching rates than copper, and the outer periphery of the first metal layer forms a ring-shaped protrusion outside the side surface of the first copper layer, and the outer periphery of the second metal layer forms a ring-shaped protrusion outside the side surface of the second copper layer.

[0097] A seed layer is formed directly below the first copper layer. An amount by which the outer periphery of the first metal layer protrudes outside the side surface of the first copper layer and an amount by which the outer periphery of the second metal layer protrudes outside the side surface of the second copper layer are greater than a thickness of the seed layer.

[0098] The material of the first metal layer and the second metal layer may be any one of Ni, Cr, Ti, Ta, Co, Au, Ag, Pt, and Pd.

[0099] The material of the first metal layer and the second metal layer is preferably any one of Ni, Cr, Ti, Ta and Co.

[0100] A laminated film is formed between the first metal layer and the second copper layer, wherein the laminated film is formed by sequentially laminating a copper layer and a metal layer formed of a metal having a different etching rate from that of copper. The outer peripheral side of the metal layer is annularly protruding outside the side surface of the copper layer.

[0101] A solder layer is formed directly on the second metal layer.

[0102] A metal layer made of a material having better solder wettability than the second metal layer is formed directly above the second metal layer.

[0103] A copper layer and a solder layer are sequentially stacked directly on the second metal layer.

[0104] In addition, a semiconductor chip may also be provided, wherein the pillar-shaped copper bumps are formed on electrode pads.

[0105] Furthermore, there is provided a semiconductor device including a wiring board and the semiconductor chip, wherein the wiring board and the semiconductor chip are electrically connected via the pillar-shaped copper bumps.

[0106] While preferred embodiments have been described in detail above, the present invention is not limited to the above embodiments and various modifications and substitutions may be made to the above embodiments without departing from the technical scope described in the claims.

Claims

1. A pillar-shaped copper bump formed on an electrode pad of a semiconductor chip and having: 1st copper layer; a first metal layer formed directly above the first copper layer; a second copper layer formed directly above the first metal layer; and A second metal layer is formed directly above the second copper layer. in, The first metal layer and the second metal layer are made of the same material, which includes a metal having an etching rate lower than that of copper. The outer peripheral side of the first metal layer is annularly protruding outside the side surface of the first copper layer. The outer peripheral side of the second metal layer is annularly protruding outside the side surface of the second copper layer. The material of the first metal layer and the second metal layer is any one of Ni, Cr, Ti, Ta, Co, Au, Ag, Pt and Pd.

2. The pillar-shaped copper bump according to claim 1, wherein: A seed layer is formed directly below the first copper layer. The amount by which the outer periphery of the first metal layer protrudes outside the side surface of the first copper layer and the amount by which the outer periphery of the second metal layer protrudes outside the side surface of the second copper layer are greater than the thickness of the seed layer.

3. The pillar-shaped copper bump according to claim 1 or 2, wherein: The material of the first metal layer and the second metal layer is any one of Ni, Cr, Ti, Ta and Co.

4. The pillar-shaped copper bump according to claim 1 or 2, wherein: At least one layer of laminated film is formed between the first metal layer and the second copper layer, the laminated film is formed by sequentially laminating a copper layer and a metal layer, and the metal layer is formed of a metal having a different etching rate from copper. The outer peripheral side of the metal layer is annularly protruded outside the side surface of the copper layer.

5. The pillar-shaped copper bump according to claim 1 or 2, wherein: The solder layer is formed directly on the second metal layer.

6. The pillar-shaped copper bump according to claim 1 or 2, wherein: A metal layer is formed directly on the second metal layer, and the metal layer is made of a material having better solder wettability than the second metal layer.

7. The pillar-shaped copper bump according to claim 1 or 2, wherein: A copper layer and a solder layer are sequentially stacked directly on the second metal layer.

8. A semiconductor chip, wherein: The pillar-shaped copper bump according to any one of claims 1 to 7 is formed on an electrode pad.

9. A semiconductor device comprising: wiring substrate; and The semiconductor chip according to claim 8, in, The wiring substrate and the semiconductor chip are electrically connected via the pillar-shaped copper bumps.

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