Method and apparatus for controlling parallel power devices

Abstract

A system (100) includes a first transistor (102) coupled in parallel to a second transistor (108). A pulse width modulation generator (122) is coupled to the first transistor (102). The pulse width modulation generator (122) generates a first signal (124). A first switch timing controller (128) is coupled to the pulse width modulation generator (122). The first switch timing controller (128) compares a first peak current (144) of the first transistor (102) to a second peak current (152) and generates a second signal (164) based on the comparison. A gate driver is coupled to the first switch timing controller (128). The gate driver controls the first transistor (102) in response to the second signal (164).

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to power devices, and more particularly to methods and apparatus to control parallel power devices. BACKGROUND

[0002] In certain applications, a transistor (e.g., a field effect transistor (FET) or a metal oxide semiconductor field effect transistor (MOSFET)) is connected in parallel with another transistor. The parallel coupled transistors can be controlled to provide current to a load by a pulse width modulation (PWM) signal provided to the gates of the transistors. SUMMARY

[0003] An example system includes a first transistor coupled in parallel to a second transistor, a pulse width modulation generator coupled to the first transistor. The pulse width modulation generator is to generate a first signal. The example system further includes a first switch timing controller coupled to the pulse width modulation generator. The first switch timing controller is to compare a first peak current of the first transistor to a second peak current and generate a second signal based on the comparison of the first peak current to the second peak current. The example system further includes a gate driver coupled to the first switch timing controller, and the gate driver is to control the first transistor in response to the second signal. BRIEF DESCRIPTION OF DRAWINGS

[0004] Figure 1 is a schematic diagram of an example circuit including a transistor, where a peak current passing through the transistor is controlled.

[0005] Figure 2 is a schematic diagram of an example circuit including Figure 1 two parallel coupled transistors of and additional details of an example switch timing controller.

[0006] Figure 3 is a block diagram illustrating additional details of an example implementation of one of the switch timing controllers of Figure 2

[0007] Figure 4 is a block diagram illustrating additional details of an example implementation of one of the switch timing controllers of including temperature sensing capabilities. Figure 2

[0008] Figure 5 is a schematic diagram illustrating additional details of an example implementation of one of the switch timing controllers of Figure 2

[0009] Figure 6 is a representation of code that can be executed to implement​​​Figures 1 to 5 a flowchart of example machine-readable instructions of an example switch timing controller.

[0010] Figure 7A is a graphical illustration of example initial peak current versus time through parallel coupled transistors of Figures 1 to 2

[0011] Figure 7B is a graphical illustration of example initial peak current versus time through parallel coupled transistors of Figures 1 to 2

[0012] Figure 8 is a graphical illustration of different data sets of example initial peak current through parallel coupled transistors of Figures 1 to 2

[0013] Figure 9 is a block diagram of an example processing platform structured to execute machine-readable instructions represented in Figure 6 to implement a switch timing controller of Figures 1 to 5 DETAILED DESCRIPTION

[0014] The drawings are not to scale. In general, throughout the drawings and the accompanying written description, use will be made of the same reference number to refer to the same or similar components. While circuits and blocks are shown in the drawings with clearly defined lines and boundaries, some or all of these lines and / or boundaries can be idealized in reality. In reality, the boundaries and / or lines can be difficult to observe, hazy, and / or irregular.

[0015] Power stages are used, for example, in power conversion circuits, power factor correction circuits, discontinuous current mode power switching circuits, continuous current mode power switching circuits, adapters, or electric vehicle charging units. A technique to provide power and / or current in a power stage is to couple transistors in parallel. When coupled in parallel, the transistors are connected to a common voltage source and load and are driven by a PWM gate driver signal (e.g., a PWM signal). Coupling transistors that receive the same PWM signal in parallel increases the ability of the power stage to supply output current because the parallel coupled transistors share the current load.

[0016] ​​​​In some applications, parallel coupled transistors receiving the same PWM signal turn on and / or off precisely at the same time. When parallel coupled transistors turn on precisely at the same time, load current is equally shared across the parallel coupled transistors and inrush current is shared. In practice, however, even though parallel coupled transistors can be driven by the same PWM signal, each transistor can turn on at slightly different times. When using parallel coupled transistors, the first transistor in the parallel coupled transistors to turn on in response to the PWM signal will experience higher inrush current than the other transistors. For example, the first transistor to turn on will conduct the total load current for a short period of time rather than sharing the load current across the other parallel coupled transistors. The single parallel coupled transistor conducting the total load current experiences high safe operating area (SOA) stress and, as a result, the transistor operates under conditions that stress the transistor and cause faster degradation.

[0017] Prior art to avoid subjecting one transistor in a parallel arrangement to increased SOA stress includes attempting to synchronize parallel coupled transistors based on device temperature. For example, if a first transistor coupled in parallel with a second transistor is to be turned on first (even if for a small period of time (e.g., 1 millisecond)), the first transistor will exhibit a higher temperature than the second transistor. Thus, in prior art, a delay will be generated in response to the higher transistor temperature and, as a result, the signal to turn on the first transistor is adjusted so that the turn on time of the first transistor more closely matches the turn on time of the second transistor.

[0018] Examples described herein include controlling parallel coupled transistors based on initial peak current. Examples described herein include transistors generated using gallium nitride (GaN). Also, examples described herein include parallel coupled GaN transistors and include methods and apparatus to control parallel coupled transistors based on initial peak current conducted through the parallel coupled transistors (e.g., from transistor drain to transistor source). Examples described herein include sensing initial peak current of individual ones of parallel coupled transistors. The transistors used in examples described herein can be power transistors. Alternatively, in some examples described herein, the transistors used can be generated using silicon (Si) or any suitable semiconductor substrate.

[0019] In examples described herein, the turn-on time of a transistor that experiences a higher initial peak current than other parallel coupled transistors (e.g., the transistor that turns on first in response to a PWM signal) can be adjusted (e.g., by delaying the PWM signal) to match the turn-on time of the other parallel coupled transistors. The turn-on time of the first to turn on transistor can be adjusted to reduce the initial peak current conducted through the transistor. Also, the turn-on time of the first to turn on transistor can be adjusted until the initial peak current conducted through the transistor meets a threshold value. In some examples, the threshold value can be an average initial peak current (e.g., a normal average initial peak current of all parallel coupled transistors), a predetermined initial peak current, or any other initial peak current value. In other examples described herein, if more than two transistors are coupled in parallel, the turn-on time of at least two of the parallel coupled transistors can be adjusted to match the turn-on time of one or more of the other parallel coupled transistors.

[0020] Also, examples described herein include methods and apparatus to control parallel coupled transistors based on an initial peak current conducted through the parallel coupled transistors (e.g., from transistor drain to transistor source), a transistor temperature, or any other transistor parameter.

[0021] Figure 1 is a schematic diagram of an example circuit 100 that includes transistors 102, 105, 108, and 111, where the peak current passing through transistors 102, 105, 108, and 111 is controlled. Transistors 102, 105, 108, and 111 each include two current terminals (103 and 104, 106 and 107, 109 and 110, 112 and 113), respectively. Transistors 102, 105, 108, and 111 can be formed on respective dies 114, 116, 118, and 120. Dies 114, 116, 118, and 120 can be thermally coupled to at least one heat sink.

[0022] In Figure 1 the example illustrated in FIG. 1, a pulse width modulation generator 122 (PWM generator 122) generates PWM signals 124 and 126 (e.g., PWM-HS and PWM-LS) for parallel coupled high side transistors 102, 108 and parallel coupled low side transistors 105, 111, respectively. An example switch timing controller 128 is coupled to PWM generator 122 and high side transistor 102, and an example switch timing controller 132 is coupled to PWM generator 122 and high side transistor 108. Likewise, an example switch timing controller 130 is coupled to PWM generator 122 and low side transistor 105, and an example switch timing controller 134 is coupled to PWM generator 122 and low side transistor 111. In Figure 1In the example of FIG. 1, PWM generator 122 generates PWM signals 124 and 126 (e.g., PWM-HS and PWM-LS); however, PWM generator 122 is not limited to generating two PWM signals 124 and 126 (e.g., PWM-HS and PWM-LS). For example, four PWM signals can be generated for four transistors (102, 105, 108, and 111), and thus, the delay can be implemented individually for each transistor by PWM generator 122.

[0023] Transistors 102 and 108 form a pair of high-side transistors coupled in parallel. Transistors 105 and 111 form a pair of low-side transistors also coupled in parallel. High-side transistors 102 and 108 are coupled between an example positive voltage bus PVDD 115 and an example switching circuit node SW 117, and example low-side transistors 105 and 111 are coupled between switching circuit node SW 117 and an example local circuit ground PGND 119. The high-side and low-side transistors (102, 105, 108, and 111) can include gallium nitride (GaN) layers formed epitaxially on a silicon substrate. Electrons in a GaN channel (e.g., 2DEG channel) migrate more quickly than electrons in a silicon (Si) channel (e.g., inversion channel), and thus, GaN transistors (e.g., high electron mobility transistors (HEMTs)) turn on and / or off more quickly in response to PWM signals than Si transistors. Also, transistors generated with GaN layers include lower capacitance between drain and source terminals than transistors generated with Si. Thus, when GaN transistors (e.g., high electron mobility transistors (HEMTs)) are subjected to hard switching, the time during which the amplitude of the drain-to-source voltage is high and the amplitude of the drain current is high (e.g., the amplitude of the drain-to-source voltage and the amplitude of the drain current overlap) is reduced. The reduction in the time during which the amplitude of the drain-to-source voltage is high and the amplitude of the drain current is high allows GaN transistors (e.g., high electron mobility transistors (HEMTs)) to operate safely during hard switching. In some examples described herein, transistors 102, 105, 108, and 111 can be generated using a Si substrate or any other transistor substrate.

[0024] In examples described herein, current terminals 103 and 104 (e.g., source and drain terminals) of high-side transistor 102 can each be coupled (e.g., connected) to respective current terminals 109 and 110 of high-side transistor 108, with no intervening passive components (e.g., inductors, capacitors) coupled therebetween. The respective current terminals 103, 104, 109, and 110 of example high-side transistors 102 and 108 are coupled in parallel, such that a greater amount of power and / or current is switchable than would be possible if switching were to occur through only one example high-side transistor.

[0025] Likewise, in some examples described herein, the current terminals 106 and 107 (e.g., source and drain terminals) of the low-side transistor 105 can each be coupled (e.g., connected) to respective current terminals 112 and 113 of the low-side transistor 111 without intervening passive components (e.g., inductors, capacitors) coupled therebetween. The respective current terminals 106, 107, 112, 113 of the example low-side transistors 105 and 111 are coupled in parallel such that a greater amount of power and / or current is switchable than would otherwise be possible with switching through only one example low-side transistor.

[0026] Although the example high-side and low-side transistors (102, 105, 108, and 111) are coupled in pairs, respectively, each of the example high-side and low-side transistors (102, 105, 108, and 111) can be controlled individually in response to a peak current associated with the individual transistor. For example, if the high-side transistor 102 conducts a greater initial peak current than the high-side transistor 108, the high-side transistor 102 can be switched in response to the local initial peak current of the high-side transistor 108. Likewise, if the low-side transistor 105 conducts a greater initial peak current than the low-side transistor 111, the low-side transistor 105 can be switched in response to the local peak current of the low-side transistor 111.

[0027] The example PWM generator 122 is arranged to generate an example pulse width modulated high-side signal 124 for controlling the example high-side transistors 102 and 108 in response to the example circuit node SW 117. The example PWM generator 122 can alternatively be arranged to control the example high-side transistors 102 and 108 (and / or low-side transistors 105 and 111) in response to a system operating parameter, such as an output voltage of a resistive, inductive, or capacitive load powered by the circuit 100. The example PWM generator 122 is arranged to generate an example pulse width modulated low-side signal 126 for controlling the example low-side transistors 105 and 111 in response to the example circuit node SW 117. The example PWM generator 122 can be powered by the example power rails PVDD 115 and PGND 119. In various examples, the PWM generator 122 can be a processor, such as a microcontroller or a digital signal processor (DSP).

[0028] The example pulse width modulated high-side signal 124 (e.g., PWM-HS) is coupled to a first switch timing controller 128 and a second switch timing controller 132. The example pulse width modulated low-side signal 126 (e.g., PWM-LS) is coupled to a third switch timing controller 130 and a fourth switch timing controller 134.

[0029] An example switch timing controller (e.g., one of 128, 130, 132, and 134) each include a current sensor (e.g., 136, 138, 140, and 142, respectively), an operational amplifier (e.g., 156, 158, 160, and 162, respectively), and a power switch delay circuit (e.g., 172, 174, 176, and 178, respectively). A switch timing controller (e.g., one of 128, 130, 132, and 134) can be included on the same die (e.g., 114, 116, 118, and 120, respectively) as the high side or low side transistor (e.g., 102, 105, 108, and 111, respectively) being controlled. Alternatively, a switch timing controller (e.g., one of 128, 130, 132, and 134) can be included on a separate die (e.g., 114, 116, 118, and 120, respectively) from the high side or low side transistor (e.g., 102, 105, 108, and 111, respectively) being controlled.

[0030] Example current sensors 136, 138, 140, and 142 are coupled to example high side and low side transistors (102, 105, 108, and 111), respectively. Example current sensors 136, 138, 140, and 142 can be disposed on a multi-chip module in proximity to components (e.g., chips including the high side or low side transistors to be monitored) mounted on the multi-chip module. Example current sensors can be located virtually anywhere on a die or multi-chip module where the current sensor is coupled to an example respective metal oxide semiconductor field effect transistor.

[0031] In one example, current sensors 136, 138, 140, and 142 are disposed on the same die on which each respective high side and low side transistor (102, 105, 108, and 111) is disposed. In another example, current sensors 136, 138, 140, and 142 can be disposed on a multi-chip module on which each respective high side and low side transistor (102, 105, 108, and 111) is carried. Example current sensors 136, 138, 140, and 142 are coupled to respective example high side and low side transistors (102, 105, 108, and 111). For example, current sensors 136, 138, 140, and 142 can be coupled to respective high side and low side transistors (102, 105, 108, and 111) by being disposed on the same die (e.g., 114, 116, 118, 120).

[0032] Example current sensors 136, 138, 140, and 142 are arranged (e.g., placed) to generate respective local sensed transistor peak currents 144, 146, 148, and 150, such that each signal indicates a sensed transistor peak current of a respective example high-side and low-side transistor (102, 105, 108, 111). Also, each signal indicating a sensed transistor peak current 144, 146, 148, 150 can also be a voltage signal. The sensed transistor peak currents 144, 146, 148, 150 are coupled to the non-inverting input terminals of example operational amplifiers 156, 158, 160, 162. Example global peak current signals 152, 154 are generated for each of the high-side and low-side circuits, respectively, such that a global current signal 152, 154 is generated in response to current indications of at least two transistors in each of the high-side and low-side. In some examples described herein, each respective global current signal 152, 154 is a signal representing a respective average peak current (e.g., global current high 152 represents an average peak current of sensed transistor peak currents 144 and 148).

[0033] Each respective global current signal 152, 154 is coupled to the non-inverting input terminals of example operational amplifiers 156, 158, 160, 162. For example, global current high (GLOBAL CUR HS) signal 152 is coupled to operational amplifiers 156 and 160, and global current low (GLOBAL CUR LS) signal 154 is coupled to operational amplifiers 158 and 162. Also, each signal indicating a global current signal (152 or 154) can also be a voltage signal. Alternatively, example global current signals (152 or 154) can be coupled to the inverting input terminals of operational amplifiers 156, 158, 160, 162. Likewise, example local current signals (144, 146, 148, and 150) can be coupled to the non-inverting input terminals of operational amplifiers 156, 158, 160, and 162, respectively. Also, respective global current signals 152, 154 can be coupled to resistors (R120, R125).

[0034] Each of example operational amplifiers 156, 158, 160, and 162 is arranged to generate a respective local current differential reference signal 164, 166, 168, and 170 in response to respective global current signals 152 and 154 and local current signals 144, 146, 148, and 150. Each respective local current differential reference signal 164, 166, 168, and 170 is coupled to a respective input terminal of power switch delay circuits 172, 174, 176, and 178.

[0035] The example power switch delay circuits 172, 174, 176, and 178 can be analog circuits, with each example power switch delay circuit configured to delay a respective pulse width modulated signal (124 or 126) in response to a respective local current delta reference signal 164, 166, 168, and 170.

[0036] The first power switch delay circuit 172 and the second power switch delay circuit 176 generate respective delayed PWM signals coupled to respective gate (e.g., control) terminals of the high-side transistors 102 and 108. The pulse width modulated low-side (PWM-LS) signal 126 is coupled to the third power switch delay circuit 174 and the fourth power switch delay circuit 178. The third power switch delay circuit 174 and the fourth power switch delay circuit 178 generate respective delayed PWM signals coupled to respective gate terminals of the low-side transistors 105 and 111.

[0037] The example high-side transistors 102 and 108 are activated (e.g., by establishing a conduction channel) in response to assertion of the example pulse width modulated high-side signal 124. At least one of the example transistors 102 and 108 is also activated in response to the respective example power switch delay circuits 172, 176. The example low-side transistors 105 and 111 are activated in a similar manner, albeit in response to the pulse width modulated low-side signal 126 and arrangement.

[0038] Figure 2 is an example circuit that includes two parallel coupled transistors and additional details of the example switch timing controller Figure 1 is an example circuit that includes two parallel coupled transistors and additional details of the example switch timing controller

[0039] The transistors 202, 204 can be high electron mobility transistors (HEMTs) and can be implemented in a discrete fashion as a semiconductor substrate or can be implemented using any other method. A HEMT is a three-terminal device having a drain terminal, a source terminal, and a gate terminal. The transistors 202, 204 can be formed on a substrate (e.g., a printed circuit board or an integrated circuit), with the substrate formed of a semiconductor material (e.g., silicon or gallium nitride). Example implementations include gallium nitride (GaN) power stages.

[0040] Example switch timing controllers 206, 208 are coupled to PWM generator 212. Switch timing controller 206 receives and / or distributes PWM signals to gate driver 214. Likewise, switch timing controller 208 receives and / or distributes separate PWM signals to gate driver 216. In this way, the PWM signals sent by switch timing controllers 206, 208 are individually adjusted to synchronize the on-time of transistors 202, 204 (e.g., to turn on and / or off at the same time). Switch timing controller 206 is coupled to transistor 202. Switch timing controller 206 senses the peak current passing through transistor 202. Likewise, switch timing controller 208 is coupled to transistor 204, and switch timing controller 208 senses the peak current passing through transistor 204. In other examples described herein, switch timing controllers 206, 208 can be implemented in a network of devices, where the network includes a variable number of switch timing controllers 206, 208 or other electronic devices.

[0041] Example averager 210 is coupled to switch timing controller 206 and switch timing controller 208. Averager 210 receives the peak current passing through transistors 202, 204. Averager 210 can receive a metric from at least one current sensor and generate another metric representing all metrics from all coupled current sensors. For example, if there are two parallel coupled transistors, averager 210 receives a current metric (e.g., sensed peak current 144, 146, 148, and / or 150) representing each individual parallel coupled transistor. Averager 210 generates an additional metric (e.g., average, maximum, minimum, etc.) representing all parallel coupled transistors. Figure 1 Figure 1 ​In other examples described herein, the average 210 can generate a metric that is a representation of a temperature and / or current value generated by the at least one switch timing controller 206 or 208. Other implementations include the average 210 where the metric generated by the average 210 is an initial peak current of a single transistor (e.g., a main transistor). In this case, the initial peak current of the main transistor would serve as a target peak current for modeling all other parallel coupled transistors. Another example includes a single transistor that is a main transistor (e.g., a transistor with an initial peak current as a standard initial peak current for all other parallel coupled transistors). Alternatively, other examples can include a dynamic main transistor (e.g., a transistor that is a main transistor can change). In other implementations, the average 210 can be implemented in a network of devices where the network can include a variable number of electronic devices.

[0042] In other examples described herein, the average 210 can generate a metric that is a representation of a temperature and / or current value generated by the at least one switch timing controller 206 or 208. Other implementations include the average 210 where the metric generated by the average 210 is an initial peak current of a single transistor (e.g., a main transistor). In this case, the initial peak current of the main transistor would serve as a target peak current for modeling all other parallel coupled transistors. Another example includes a single transistor that is a main transistor (e.g., a transistor with an initial peak current as a standard initial peak current for all other parallel coupled transistors). Alternatively, other examples can include a dynamic main transistor (e.g., a transistor that is a main transistor can change). In other implementations, the average 210 can be implemented in a network of devices where the network can include a variable number of electronic devices.

[0043] The example PWM generator 212 is coupled to the switch timing controller 206 and the switch timing controller 208. From the PWM generator 212, a PWM signal is sent through the switch timing controller 206 to command when the transistor 202 is turned on and / or off. Likewise, from the PWM generator 212, a PWM signal is sent through the switch timing controller 208 to command when the transistor 204 is turned on and / or off. The signals sent to the switch timing controllers 206, 208 can differ in amplitude, duty cycle, frequency, etc.

[0044] Example gate drivers 214, 216 receive low-power inputs from switch timing controllers 206, 208. In this example, gate driver 214 generates a high-current drive input for the gate terminal of transistor 202. Similarly, gate driver 216 generates a high-current drive input for the gate terminal of transistor 204. Alternatively, gate driver 214 and / or gate driver 216 may generate low-current drive inputs for the gate terminals of transistor 202 and / or transistor 204. Gate drivers 214, 216 may be implemented using discrete components, on-chip, on-chip integrated CMOS devices, or any other method of implementing gate drivers not directly described herein.

[0045] Figure 3 It is a diagrammatic explanation. Figure 2 Block diagram 300 provides additional details of an example implementation of one of the switching timing controllers. (See diagram 300.) Figure 3 The example block diagram of the switching timing controller shown can be used for switching timing controllers 206 and / or 208. Furthermore, a single switching timing controller can be used for all parallel-coupled transistors present in the circuit, one parallel-coupled transistor present in the circuit, or several parallel-coupled transistors present in the circuit. Switching timing controller 206 receives at least three inputs and sends at least two outputs. Alternatively, the number of inputs received by switching timing controller 206 and / or the number of outputs sent by switching timing controller 206 may differ in other examples. Current sensor 302 is coupled to averager 210 and transistor 202. Alternatively, current sensor 302 may be coupled to averager 210 and transistor 204. Delay controller 304 is coupled to averager 210. Delay controller 304 receives a metric representing at least one transistor in the circuit. Delay controller 304 receives a signal (e.g., a PWM signal) from PWM generator 212. The signal from the PWM generator interacts with a series of devices (e.g., buffers, amplifiers, multiplexers, etc.) to form a new signal that is sent to gate driver 214 and / or gate driver 216.

[0046] Example current sensor 302 includes electronic components such as resistors, capacitors, inductors, transistors (e.g., FETs, diodes, etc.), amplifiers, buffers, multiplexers, or any electrical components. Current sensor 302 can measure, sense, receive, etc., current measurements from at least one transistor. Current sensor 302 can be implemented using a sensing FET, a current sensing integrated circuit (current sensing IC), a shunt resistor, a current converter, etc. The current measurement generated by current sensor 302 is a current and / or voltage value representing the peak input current witnessed by transistor 202 and / or transistor 204.

[0047] The example delay controller 304 includes electronic components such as resistors, capacitors, inductors, transistors (e.g., FETs, diodes, etc.), amplifiers, buffers, multiplexers, or any electronic component not directly described herein. The delay controller 304 is coupled to the PWM generator 212 such that the incoming switching signal (e.g., PWM signal) to the transistor 202 and / or the transistor 204 can be altered and / or adjusted.

[0048] Figure 4 is a block diagram 400 illustrating additional details of an example implementation of one of the switch timing controllers 206 that includes temperature sensing capabilities. Figure 2 The example block diagram of a switch timing controller as shown in Figure 4 may be used for the switch timing controller 208. More specifically, the switch timing controller can be replicated for each parallel coupled transistor. In this example, a temperature sensor 404 is coupled to the output of the current sensor 402 to provide peak temperature information from the individual transistor 202. The switch timing controller 206 receives at least three inputs and sends at least two outputs. Alternatively, the number of inputs received by the switch timing controller 206 and / or the number of outputs sent by the switch timing controller 206 can vary in other examples. The current sensor 402 is coupled to the averager 210 and the transistor 202. Alternatively, a second switch timing controller can include a second current sensor, where the second current sensor is coupled to the averager 210 and the transistor 204. Also, the temperature sensor 404 is coupled to a delay controller 406. The delay controller 406 is coupled to the averager 210. The delay controller 406 receives a metric representative of at least one transistor (e.g., 202 or 204) in the circuit. This metric can be in the form of a current, voltage, and / or temperature. The delay controller 406 receives a signal (e.g., PWM signal) from the PWM generator 212. The signal (e.g., PWM signal) from the PWM generator interacts with a series of devices (e.g., buffers, amplifiers, multiplexers, etc.) to form a new signal that is sent to the gate driver 214 and / or the gate driver 216.

[0049] The example current sensor 402 includes electronic components such as resistors, capacitors, inductors, transistors (e.g., FETs, diodes, etc.), amplifiers, buffers, multiplexers, or any electronic component. The current sensor 402 can measure, sense, and / or receive a current metric from at least one transistor. The current metric generated by the current sensor 402 is a current and / or voltage value representative of the peak input current witnessed by the transistor 202 and / or the transistor 204.

[0050] An example temperature sensor 404 is coupled to internal and / or external temperature sensing circuitry. The temperature sensor 404 is coupled to a temperature sensing device, such as a thermistor. The temperature sensor senses the junction temperature of the transistors 202, 204. A predetermined percentage of the temperature information is coupled to the peak current information from the current sensor 402 (e.g., the predetermined percentage is a temperature value that is proportional to the actual transistor 202, 204 temperature value). The information from the temperature sensor 404 and the current sensor 402 can then be sent to the delay controller 406. The delay controller 406 adjusts the parameters of the PWM signal to delay the turn on and / or turn off time of the parallel coupled transistor (e.g., 202 or 204).

[0051] The delay controller 406 includes electronic components, such as resistors, capacitors, inductors, transistors (e.g., FETs, diodes, etc.), amplifiers, buffers, multiplexers, or any electrical component. The delay controller 406 uses the metrics generated by the current sensor 402 and / or the temperature sensor 404 to modify the PWM signal from the PWM generator 212. The delay controller 406 is coupled to the PWM generator 212 so that the incoming switching signal (e.g., PWM signal) to the transistor 202 and / or the transistor 204 can be altered or adjusted.

[0052] Figure 5 is a schematic diagram 500 illustrating additional details of an example implementation of one of the switch timing controllers (206 or 208) of Figure 2 In this example implementation, the turn on and / or turn off time for the example low side transistor 506 is adjusted. Thus, Figure 5 depicts a switch timing controller (e.g., the switch timing controller 206 or 208 of Figure 2 In this example, the switch timing controller includes a current sensor 508, a temperature sensor 532, and a delay controller 534. In other examples described herein, the order of the current sensor 508, the temperature sensor 532, the delay controller 534, the averager 526, and the power conversion circuit 502 interactions can be rearranged. When multiple transistors are coupled in parallel, there will be additional replicated switch timing controllers (e.g., current sensor 508, temperature sensor 532, and delay controller 534) for all of the parallel coupled transistors. The averager 526 is coupled to all of the existing switch timing controllers (e.g., 206 or 208).

[0053] An example power conversion circuit 502 can be any circuit used in a power stage. For example, a buck converter uses transistors to convert a high DC input voltage to a low DC output voltage. In other examples, the power conversion circuit 502 is employed in power stages such as automotive applications, personal electronics, integrated chips, etc. Also, other examples described herein include power conversion circuits for GaN power stages (e.g., power stages using GaN transistors).

[0054] An example PWM generator 504 generates a PWM signal (e.g., turn-on and / or turn-off signal) for the low-side transistor 506. Example implementations of the PWM generator 504 include using an integrated circuit such as a timing chip, a comparator, etc. Regardless of the implementation, the PWM generator 504 is coupled to a switch timing controller (e.g., 206 or 208) for each individually coupled transistor. The switch timing controller (e.g., 206 or 208) provides an individually adjusted PWM signal for each coupled transistor.

[0055] An example low-side transistor 506 is a three-terminal switching device (e.g., HEMT). Examples described herein include a low-side transistor 506 generated from a gallium nitride (GaN) substrate. Examples described herein include GaN transistors for use in power stage applications. Other example power stage applications include power factor correction circuits, discontinuous current mode power switching circuits, continuous current mode power switching circuits, adapters, electric vehicle charging units, etc. Also, examples described herein include coupled GaN transistors in parallel. Other examples include a low-side transistor 506 and / or coupled transistors generated using another substrate such as silicon (Si), silicon carbide (SiC), or any other substrate.

[0056] An example current sensor 508 includes a trimming resistor 510. The trimming resistor 510 helps measure current by creating a voltage drop. The created voltage drop is proportional to a peak current witnessed by the low-side transistor 506. For example, as a peak current from the low-side transistor 506 travels through the trimming resistor 510, a voltage drop is created across the trimming resistor 510. The peak voltage measured across the voltage drop is proportional to the peak current flowing through the low-side transistor 506. An example current measured via the example trimming resistor 510 represents the current flowing through the low-side transistor 506 in a proportional amount (e.g., can be larger or smaller by several orders of magnitude than the actual peak current flowing through the transistor).

[0057] The example amplifier 512 is a low offset voltage, high bandwidth amplifier that amplifies the voltage on the trimmed resistor 510. Alternatively, the amplifier 512 can be any device that outputs a value proportional to the input. Due to the amplifier 512, the voltage captured on the trimmed resistor 510 is imposed on the resistor 514. The trimmed resistor 510 is coupled to the positive terminal of the amplifier 512 and the resistor 514 is coupled to the negative terminal of the amplifier 512. In other examples, the trimmed resistor 510 can be coupled to the negative terminal of the amplifier 512 and / or the resistor 514 can be coupled to the positive terminal of the amplifier 512.

[0058] The example resistor 514 is coupled to an amplification resistor 516. The voltage on the resistor 514 can be increased and / or decreased across the voltage drop on the amplification resistor 516. The amplification resistor 516 is coupled to an example voltage capture capacitor 518. For example, the peak current flowing through the trimmed resistor 510 is transferred as a peak voltage on the resistor 514 due to the voltage drop. The amplification resistor 516 forms a scaled peak voltage to be captured by the voltage capture capacitor 518.

[0059] The example voltage capture capacitor 518 is coupled to a series of example voltage buffers 520, 522. In other examples, only one voltage buffer 520 or 522 can be coupled to the voltage capture capacitor 518 or multiple voltage buffers 520, 522 can be coupled to the voltage capture capacitor 518.

[0060] The example voltage buffers 520, 522 ensure that the peak voltage value from the voltage capture capacitor 518 is transferred across a capture trimmed resistor 524. Further, the capture trimmed resistor 524 is coupled to a parallel feedback pin 528 and an additional averaging trimmed resistor 530. In some examples described herein, the averaging trimmed resistor 530 includes a resistance equal to the capture trimmed resistor 524. Likewise, the parallel feedback pin 528 includes a resistor that is equivalent in resistance to the averaging trimmed resistor 530. The parallel feedback pin 528 is implemented on an external circuit. Other examples described herein include the parallel feedback pin 528 implemented on the same circuit and / or die as the switch timing controller (e.g., the switch timing controller 206 or 208 of Figure 2 FIG. 1). The parallel feedback pin 528 is coupled to the averager 526. A number of trimmed resistors equal to the total number of parallel coupled transistors are coupled to the parallel feedback pin 528. For example, for three transistors coupled in parallel, three resistors can be coupled to the same external parallel feedback pin 528. Alternatively, a single resistor can be coupled to the parallel feedback pin 528 that has a resistance equivalent to the parallel resistance value of all existing parallel coupled transistors.

[0061] The averager 526 can include a set of parallel coupled resistors where the averager 526 generates a measure across the set of parallel coupled resistors. In this example, the averager is implemented on an external circuit coupled to at least one switch timing controller. Alternatively, the averager 526 can be implemented internally on the same circuit and / or die as the switch timing controller (e.g., 206 or 208 of the switch timing controller 208). In other examples, the averager 526 can receive a single transistor initial peak current, which single transistor is considered the master transistor. In this context, the output of the averager 526 is the initial peak current of the master transistor. In the master transistor scenario, the turn on and / or turn off times of the parallel coupled transistors are adjusted until their initial peak currents match the master transistor peak current. Figure 2

[0062] The example temperature sensor 532 is coupled to the output of the current sensor 508. The temperature sensing network 532 includes a sense resistor (e.g., a thermistor) that obtains a temperature value of the low side transistor 506. The temperature sensing network 532 receives at least two voltage values: a bandgap temperature voltage 546 and a temperature voltage 548. The bandgap temperature voltage is a temperature independent reference voltage. The bandgap temperature voltage 546 can be in the range from 0 to 1.25V; however, the bandgap temperature voltage 546 is not limited to the above range. The temperature voltage 548 is dependent on the thermistor temperature. The temperature voltage 548 can also be in the range from 0 to 1.2V; however, the temperature voltage is not limited to the above defined range. The thermistor includes a variable resistor where the resistance changes in response to a change in temperature. For example, a constant current is forced through the thermistor. As the transistor heats up, the voltage across the resistor changes, thus allowing the temperature value to be measured. This value is then sent through a series of buffers and amplifiers to send the percentage of the transistor temperature value to the current sensor 508 output and the averager 526. Alternatively, the value sent to the delay controller 534 can be a weighted average of each individual transistor peak current plus the percentage of individual transistor temperature information.

[0063] The example delay controller 534 is coupled to the averager 526, the temperature sensor 532, and the current sensor 508. The peak current and peak temperature values of the individual low side transistors 506 are received at the delay controller 534 in the form of a voltage. Alternatively, the peak current and peak temperature values of the individual low side transistors 506 can be received at the delay controller 534 in the form of a current, temperature, voltage, etc. Also, the average peak current and / or junction temperature values obtained from the averager 526 are sent to the delay controller 534.

[0064] The delay controller 534 includes buffers 536, 538, a differential amplifier 540, and a delay generator 542. Alternatively to the buffers 536, 538, there can be a series of buffers.​

[0065] In Figure 5 the examples described in this document, a positive input of the differential amplifier 540 is coupled to an output of the buffer 536. Also, a negative input of the differential amplifier 540 is coupled to an output of the buffer 538. In other examples described in this document, the negative input of the differential amplifier 540 can be coupled to the output of the buffer 536. Likewise, the positive input of the differential amplifier 540 can be coupled to the output of the buffer 538. The differential amplifier 540 generates a signal based on a comparison between the individual transistor peak current and the average transistor peak current. In other examples described in this document, the differential amplifier 540 can generate a signal based on a comparison between the individual transistor temperature value and the average transistor temperature value.

[0066] The example delay generator 542 is coupled to the pulse width modulation generator 504 (PWM generator 504) and an output of the differential amplifier 540. The delay generator 542 can receive current, voltage, and / or temperature values from the differential amplifier 540. The delay generator 542 applies a delay (e.g., a time and / or frequency shift) to the signal from the PWM generator 504. The delay generator 542 can use the information received from the differential amplifier 540 and the PWM generator 504 to adjust the turn-on and / or turn-off times of the parallel coupled transistors using an adjustment loop (e.g., a servo loop, etc.). The delay generator 542 sends the information received from the differential amplifier 540 through an example servo loop. For example, the servo loop uses error sensing feedback to control the operation of the parallel coupled transistors. The servo loop generates a second signal that is an adjusted version of the pulse width modulated signal. Also, there can be an additional servo loop for each individual transistor. Alternatively, the delay generator 542 can modify the signal from the PWM generator 504 in any manner not directly described herein. The output of the delay generator 542 is coupled to the gate driver 544.

[0067] While Figures 2 to 5 an example manner of implementing a switch timing controller of Figure 1 the elements, processes and / or devices illustrated in Figures 2 to 5 may be combined, divided, re-arranged, omitted, eliminated and / or implemented in any other way. Further, the example current sensor (136, 138, 140, 142, 302, 402, or 508), the example temperature sensor (404 or 532), the example delay controller (304, 406, or 534), the example averager (210 or 526), the example PWM generator (122, 212, or 504), the example delay generator (542), the example delay circuit (172, 174, 176, 178), and / or (more generally) any of the elements, processes and / or devices illustrated in Figures 1 to 5The example switch timing controllers of Figures 1 to 5 Any of the example switch timing controllers of Figures 1 to 5 When reading any of the device or system claims of this patent to cover a purely software and / or firmware implementation, at least one of the example current sensors (136, 138, 140, 142, 302, 402, or 508), example temperature sensors (404 or 532), example delay controllers (304, 406, or 534), example averagers (210 or 526), example PWM generators (122, 212, or 504), example delay generators (542), example delay circuits (172, 174, 176, 178), and / or (more generally) Figures 1 to 5 Any of the example switch timing controllers of Figures 1 to 5 may include more than one of any of the illustrated elements, processes, and devices. As used herein, the phrase “in communication,” including variations thereof, encompasses direct communication and / or indirect communication by way of one or more intermediary components, and does not require direct physical (e.g., wired) communication and / or constant communication, but also includes selective communication at periodic intervals, scheduled intervals, non-periodic intervals, and / or one-time events. Figures 1 to 5

[0068] Figure 6 Figure 1 ​​flowchart of example hardware logic, machine-readable instructions, hardware-implemented state machines, and / or any combination thereof, of a switch timing controller. The machine-readable instructions can be portions of or entire executable programs executed by a computer processor (e.g., processor 912 shown in the example processor platform 900 discussed below in connection with FIG. 9) or portions of or entire executable programs. The programs can be embodied in software stored on non-transitory computer-readable storage media such as CD-ROMs, floppy disks, hard drives, DVDs, Blu-ray discs, or memory associated with the processor 912, but the entire program (s) and / or portions thereof can alternatively be executed by devices other than the processors 912 and / or embodied in firmware or dedicated hardware. Also, although the flowcharts discuss the example switch timing controller, the flowcharts can alternatively be used to describe a number of other methods that implement the example switch timing controller. For example, the order of execution of the blocks can be changed, and / or some of the blocks described can be changed, eliminated, or combined. Additionally or alternatively, any one or all of the blocks can be implemented by one or more hardware circuits (e.g., discrete and / or integrated analog and / or digital circuitry, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) structured to perform the corresponding operation without executing software or firmware. Figure 9 The programs discussed above, such as the example process of a switch timing controller, can be implemented using executable instructions, such as computer and / or machine- readable instructions, stored on a non-transitory computer and / or machine-readable medium (e.g., a hard disk drive, a flash memory, a read-only memory, an optical disk, a digital versatile disc, a cache, a random access memory, and / or any other storage device or storage disk) in which the instructions are stored for any duration (e.g., for a short time, for an entire Figure 6 The flowcharts discussed above describe example processes of a switch timing controller, but a number of other methods that implement the example switch timing controller can alternatively be used. For example, the order of execution of the blocks can be changed, and / or some of the blocks described can be changed, eliminated, or combined. Additionally or alternatively, any one or all of the blocks can be implemented by one or more hardware circuits (e.g., discrete and / or integrated analog and / or digital circuitry, FPGAs, ASICs, comparators, operational amplifiers (op-amps), logic circuits, etc.) structured to perform the corresponding operation without executing software or firmware.

[0069] As described above, Figure 6 The example processes of a switch timing controller can be implemented using executable instructions, such as computer and / or machine-readable instructions, stored on a non-transitory computer and / or machine-readable medium (e.g., a hard disk drive, a flash memory, a read-only memory, an optical disk, a digital versatile disc, a cache, a random access memory, and / or any other storage device or storage disk) in which the instructions are stored for any duration (e.g., for a short time, for an entire The example processes of a switch timing controller can be implemented using executable instructions, such as computer and / or machine-readable instructions, stored on a non-transitory computer and / or machine-readable medium (e.g., a hard disk drive, a flash memory, a read-only memory, an optical disk, a digital versatile disc, a cache, a random access memory, and / or any other storage device or storage disk) in which the instructions are stored for any duration (e.g., for a short time, for an entire

[0070] In this description, the term "and / or," in its various forms, when used in a description of examples, is used to mean any one of the items in the several categories of items, for example: (a) A, B, and / or C; (b) A and B and / or C; (c) A, B, or C; (d) A, B, and C; (e) A and B or C; (f) A and B or C; (g) A and B, and C; and (h) A and B, or C. Also, as used in this description, the phrases "at least one of A or B" or "at least one of A and B" mean that an implementation include any one of the following: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B. The example processes of a switch timing controller can be implemented using executable instructions, such as computer and / or machine-readable instructions, stored on a non-transitory computer and / or machine-readable medium (e.g., a hard disk drive, a flash memory, a read-only memory, an optical disk, a digital versatile disc, a cache, a random access memory, and / or any other storage device or storage disk) in which the instructions are stored for any duration (e.g., for a short time, for an entire

[0071] The example processes of a switch timing controller can be implemented using executable instructions, such as computer and / or machine-readable instructions, stored on a non-transitory computer and / or machine-readable medium (e.g., a hard disk drive, a flash memory, a read-only memory, an optical disk, a digital versatile disc, a cache, a random access memory, and / or any other storage device or storage disk) in which the instructions are stored for any duration (e.g., for a short time, for an entire Figure 6 are representative of executable programs that can be executed to implementFigures 1 to 5 FIG. 6 is a flowchart 600 of example machine-readable instructions of an example switch timing controller (206 or 208). The examples described herein include the gate driver 544 receiving a PWM signal from the delay generator 542 (block 602). Once the PWM signal is received, the gate driver 544 sends an on and / or off signal to the low side transistor 506 (block 604). The low side transistor 506 can experience a peak current when it is initially turned on (e.g., conducting). The peak current value generated by the low side transistor 506 is then sent to the switch timing controller (block 606). The switch timing controller (206) incorporates a current sensor 508. The current sensor senses the peak current through the low side transistor 506 and replicates the peak current (block 606). The peak current is replicated at least twice, the first time to be sent to the delay controller 534 (block 608) and the second time to be sent to the averager 526 (block 610). Figure 2 The current sensor 508 senses the peak current through the low side transistor 506 and replicates the peak current (block 606). The peak current is replicated at least twice, the first time to be sent to the delay controller 534 (block 608) and the second time to be sent to the averager 526 (block 610).

[0072] The averager 526 calculates a metric representative of at least two transistors (block 612). The two transistors are parallel coupled transistors. The metric generated can be a direct average, an estimated average, or any other metric described herein that describes the peak current through a transistor. Once the metric is created, the averager 526 sends the newly created and / or generated metric to the delay controller 534 via a conductive path (e.g., copper bus) (block 612).

[0073] The delay controller 534 receives a metric representative of the low side transistor 506 and a metric representative of all parallel coupled transistors. The delay controller 534 compares the metric representative of the individual low side transistor 506 peak current value to the metric representative of all parallel transistors via a series of buffers 536, 538 and a differential amplifier 540 (block 614). The output of the differential amplifier 540 is a metric proportional to the difference between the individual low side transistor 506 peak current and the metric representative of the peak current of at least two parallel coupled transistors. In other examples, the differential amplifier 540 can be replaced by any network capable of creating a metric proportional to at least two input signals (e.g., summing amplifier).

[0074] If there is a difference between the metric representing the individual low-side transistor 506 peak current value and the metric representing all the parallel transistors, then the difference amplifier 540 generates an indication to be sent to the delay generator 542 (block 616). For example, the delay generator 542 will delay the PWM signal (e.g., the signal from the PWM generator 504) in response to the indication from the difference amplifier 540 (block 618). Another example includes the delay generator 542 creating a delay in the rising edge of the PWM signal. Thus, the delay created by the delay generator 542 can be performed using a processor, microcontroller, discrete components using a tuning loop (e.g., a servo loop), etc.

[0075] If the process is to stop operation (block 620), then the process will stop (block 622). Examples of when the process is to stop operation include a loss of power, a user shutdown, an automatic shutdown, etc.

[0076] Figure 7A is an example initial peak current versus time graphical illustration 702 of parallel coupled transistors of 2 and 5 without using a switch timing controller as described herein Figures 1 to 2 The example graphical illustration 702 of initial peak current versus time of parallel coupled transistors of 2 and 5 Figure 7A The graphical illustration 702 includes two waveforms 704, 706 corresponding to current through two parallel coupled transistors (e.g., 202 and 204). The current through the example transistor 202 corresponds to the waveform 704, and the current through the example transistor 204 corresponds to the waveform 706. It is known that due to device characteristic differences, one of the transistors can turn on slightly faster than the other parallel coupled transistor. In this example 702, the transistor 202 turns on faster than the transistor 204. In Figure 7A It is clear from the graphical illustration 702 that without any delay compensation, the transistor 202 with the current waveform 704 experiences a much higher initial peak current than the transistor 204 with the current waveform 706.

[0077] Figure 7B is an example initial peak current versus time graphical illustration 708 of parallel coupled transistors of 2 and 5 using an example switch timing controller as described herein Figures 1 to 2 The example graphical illustration 708 of initial peak current versus time of parallel coupled transistors of 2 and 5 Figure 7BGraph 708 includes two waveforms 710, 712 corresponding to current through two parallel coupled transistors (e.g., 202 and 204). The current through example transistor 202 corresponds to waveform 710, and the current through example transistor 204 corresponds to waveform 712. It is known that due to device characteristic variances, one of the transistors can turn on slightly faster than the other parallel coupled transistor. By adjusting the turn on and / or turn off time of each transistor (e.g., 202 or 204) depending on the individual transistor peak current, as described herein, a delay can be applied to the transistor PWM signal, effectively synchronizing each transistor. In this example 702, transistor 202 turns on relatively simultaneously with transistor 204. In Figure 7B It is clear from graph 800 that with the addition of delay compensation, transistor 202 with current waveform 710 experiences a similar initial peak current as transistor 204 with current waveform 712.

[0078] Figure 8 is a graphical illustration 800 of different data sets of example initial peak currents through parallel coupled transistors of Figures 1 to 5 and 5 with and without example switch timing controller of Figures 1 to 2 Each data point includes an associated data point, one corresponding to a lack of delay compensation (before delay compensation) and the other corresponding to an inclusion of delay compensation (after delay compensation). Each data point corresponds to a statistically varying process condition used to build the device. For example, example data point 804, which hovers around about 15 amps (802), has a peak current difference (e.g., maximum difference) of about 15 amps (relative to the horizontal axis) before delay compensation and a peak current difference (e.g., maximum difference) of about 2.5 amps (relative to the vertical axis) after delay compensation. Data point 806 is an example data set of a portion of which depicts a peak current difference (e.g., maximum difference) when no delay compensation is applied (e.g., the value after compensation is equal to the value before compensation). Figure 8 Depicts the significance of the improvement to the peak current difference before and after delay compensation.

[0079] Figure 9 is structured to execute the machine readable instructions represented in Figure 6 to implement the method of Figures 1 to 5FIG. 1 is a block diagram of an example processing platform 900 of a switch timing controller. The processor platform 900 can be, for example, an automotive electronic system, an industrial manufacturing device, a server, a personal computer, a workstation, a self-learning machine (e.g., a neural network), a mobile device (e.g., a mobile phone, a smart phone, a tablet computer), a personal digital assistant (PDA), an internet appliance, or a controller.

[0080] The processor platform 900 of the illustrated example includes a processor 912. The processor 912 of the illustrated example is hardware. The processor 912 can be implemented by one or more integrated circuits, logic circuits, microprocessors, GPUs, DSPs, or controllers from any desired family or manufacturer, for example. A hardware processor can be a semiconductor (e.g., silicon) based device. In this example, the processor implements an example current sensor, an example temperature sensor, an example delay controller, an example averager, an example PWM generator, an example delay generator.

[0081] The processor 912 of the illustrated example includes a local memory 913 (e.g., cache). The processor 912 of the illustrated example communicates with a main memory including a volatile memory 914 and a non-volatile memory 916 via a bus 918. The volatile memory 914 can be implemented by synchronous dynamic random access memory (SDRAM), dynamic random access memory (DRAM), and / or any other type of random access memory device. The non-volatile memory 916 can be implemented by flash memory and / or any other desired type of memory device. Access to the main memory 914, 916 is controlled by a memory controller.

[0082] The processor platform 900 of the illustrated example also includes an interface circuit 920. The interface circuit 920 can be implemented by any type of interface standard, such as an Ethernet interface, a universal serial bus (USB), a near field communication (NFC) interface, and / or a PCI express interface.

[0083] In the illustrated example, one or more input devices 922 are connected to the interface circuit 920. The input device(s) 922 permit a user to enter data and / or commands into the processor 912. The input device(s) can be implemented by, for example, audio sensors, microphones, video cameras (still or video), keyboards, buttons, mice, touch screens, track pads, track balls, isopoint, and / or voice recognition systems.

[0084] One or more output devices 924 are also connected to the interface circuit 920 of the illustrated example. The output devices 924 can be implemented, for example, by display devices (e.g., a light emitting diode (LED), an organic light emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube display (CRT), an in-plane switching (IPS) display, a touchscreen, etc.), a tactile output device, a printer and / or speakers. In this regard, the interface circuit 920 of the illustrated example, in one implementation, includes a graphics driver card, a graphics driver chip and / or a graphics driver processor.

[0085] The interface circuit 920 of the illustrated example also includes a communication device such as a transmitter, a receiver, a transceiver, a modem, a residential gateway, a wireless access point, and / or a network interface to facilitate exchange of data with external machines (e.g., computing devices of any kind) via a network 926. The communication can be via, for example, an Ethernet connection, a digital subscriber line (DSL), a telephone line, a coaxial cable, a satellite system, a line-of-site wireless system, a cellular telephone system, etc.

[0086] The processor platform 900 of the illustrated example also includes one or more mass storage devices 928 for storing software and / or data. Examples of such mass storage devices 928 include floppy disk drives, hard drive disks, compact disk drives, Blu-ray disk drives, redundant array of independent disks (RAID) systems, and digital versatile disk (DVD) drives.

[0087] Figure 6 Machine executable instructions 932 of the example of FIG. 1 can be stored in the mass storage device 928, in the volatile memory 914, in the non-volatile memory 916, and / or on a removable non-transitory computer readable storage medium such as a CD or DVD.

[0088] From the foregoing, example methods, apparatus, and articles of manufacture are described that overcome limitations encountered when paralleling transistors based on peak current alone or a percentage of peak current and junction temperature values. The described methods, apparatus, and articles of manufacture improve efficiency of using computing devices by synchronizing two parallel coupled devices to turn on at the same time. Also, limitations included in previous solutions, such as temperature sensing, are no longer evident in the described methods, apparatus, and articles of manufacture. Thus, the described methods, apparatus, and articles of manufacture overcome limitations in transistors due to thermal resistance differences. The described methods, apparatus, and articles of manufacture are thus directed to one or more improvements in functionality of computers.

[0089] Modifications are possible in the described arrangements, and other substitutions besides those already described maybe made in the scope of the claims.

Claims

1. A system for power control, comprising: a switched circuit node; a first transistor having a first current terminal, a second current terminal, and a gate terminal, the second current terminal coupled to the switched circuit node; a second transistor having a first current terminal, a second current terminal, and a gate terminal, the first current terminal of the second transistor coupled to the first current terminal of the first transistor, and the second current terminal of the second transistor coupled to the switched circuit node; a resistor having one terminal coupled to the switched circuit node and having a second terminal; and a switch timing controller having inputs coupled to the first current terminal and the second current terminal of the first transistor, an input coupled to the second terminal of the resistor, a pulse width modulation input, and a gate output coupled to the gate terminal of the first transistor, the switch timing controller including a current sensor having inputs coupled to the first current terminal and the second current terminal of the first transistor and having two sensor outputs coupled to a delay circuit, one sensor output coupled to the second terminal of the resistor.

2. The system of claim 1, wherein the switch timing controller includes the delay circuit coupled between the pulse width modulation input and the gate output.

3. The system of claim 1, wherein the switch timing controller includes a temperature sensor coupled to an output of the current sensor.

4. The system of claim 3, wherein the temperature sensor is coupled to the first transistor.

5. The system of claim 1, wherein the switch timing controller includes an operational amplifier having two inputs coupled to the two sensor outputs and having an output coupled to the gate terminal of the first transistor.

6. The system of claim 5, wherein the switch timing controller includes the delay circuit having an input coupled to the pulse width modulation input, an input coupled to the output of the operational amplifier, and an output coupled to the gate output.

7. The system of claim 1, wherein the switch timing controller is a first switch timing controller, the system including a second switch timing controller having inputs coupled to the first current terminal and the second current terminal of the second transistor, an input coupled to the second terminal of the resistor, a pulse width modulation input coupled to the pulse width modulation input of the first switch timing controller, and a gate output coupled to the gate terminal of the second transistor.

8. The system of claim 1, wherein the first transistor is a gallium nitride transistor and the second transistor is a gallium nitride transistor.

9. A system for power control, comprising: a first transistor coupled in parallel to a second transistor; ​ a pulse width modulation generator coupled to the first transistor, wherein the pulse width modulation generator is to generate a first signal; a first switch timing controller coupled to the pulse width modulation generator, wherein the first switch timing controller is to: compare a first peak current of the first transistor to a second peak current; and generate a second signal based on the comparison of the first peak current to the second peak current; and a gate driver coupled to the first switch timing controller, wherein the gate driver is to control the first transistor in response to the second signal, wherein the first switch timing controller further includes a temperature sensor to generate a third signal in response to a second comparison between a first temperature and a second temperature of the first transistor, and wherein the gate driver is to control the first transistor in response to the second signal and the third signal.

10. The system of claim 9, wherein a first output of the first switch timing controller is coupled to the gate driver.

11. The system of claim 9, wherein the first switch timing controller further includes a current sensor to sense the first peak current.

12. The system of claim 9, wherein the first switch timing controller is to generate the second signal until the first peak current equals the second peak current.

13. The system of claim 12, wherein the second peak current is an average peak current of at least the first transistor and the second transistor.

14. The system of claim 9, wherein the second peak current is conducted through a main transistor.

15. A method for power control, comprising: sensing a first transistor peak current of a first transistor and a second transistor peak current of a second transistor, the first transistor and the second transistor coupled in parallel; in response to sensing the first transistor peak current and the second transistor peak current, generating a metric based on an average operation of the first transistor peak current and the second transistor peak current; comparing the first transistor peak current to the metric; and in response to the comparison, adjusting a first on-time of the first transistor.

16. The method of claim 15, wherein the first on-time of the first transistor is adjusted to match a second on-time of the second transistor.

17. The method of claim 15, further including generating a first signal to be sent through an adjustment loop using a delay controller.

18. The method of claim 17, wherein the adjustment loop adjusts the first on-time until the first transistor peak current is equivalent to the second transistor peak current.

19. The method of claim 15, further including sensing a first transistor temperature and a second transistor temperature using a temperature sensor. ​ 20. The method of claim 19, further comprising adjusting the first on-time based on the first transistor temperature and the second transistor temperature using an adjustment loop.

21. A system for power control, comprising: a switched circuit node; a first transistor having a first current terminal, a second current terminal, and a gate terminal, the second current terminal coupled to the switched circuit node; a second transistor having a first current terminal, a second current terminal, and a gate terminal, the first current terminal of the second transistor coupled to the first current terminal of the first transistor, and the second current terminal of the second transistor coupled to the switched circuit node; a resistor having one terminal coupled to the switched circuit node and having a second terminal a first switch timing controller having inputs coupled to the first current terminal and the second current terminal of the first transistor, an input coupled to the second terminal of the resistor, a pulse width modulation input, and a gate output coupled to the gate terminal of the first transistor; and a second switch timing controller having inputs coupled to the first current terminal and the second current terminal of the second transistor, an input coupled to the second terminal of the resistor, a pulse width modulation input coupled to the pulse width modulation input of the first switch timing controller, and a gate output coupled to the gate terminal of the second transistor.

22. The system of claim 21, wherein the first switch timing controller includes a delay circuit coupled between the pulse width modulation input of the first switch timing controller and the gate output of the first switch timing controller.

23. The system of claim 21, wherein the first switch timing controller includes a current sensor having inputs coupled to the first current terminal and the second current terminal of the first transistor and having two sensor outputs coupled to a delay circuit, one sensor output coupled to the second terminal of the resistor.

24. The system of claim 23, wherein the first switch timing controller includes a temperature sensor coupled to an output of the current sensor.

25. The system of claim 24, wherein the temperature sensor is coupled to the first transistor.

26. The system of claim 23, wherein the first switch timing controller includes an operational amplifier having two inputs coupled to the two sensor outputs and having an output coupled to the gate terminal of the first transistor.

27. The system of claim 26, wherein the first switch timing controller includes the delay circuit having an input coupled to the pulse width modulation input, an input coupled to the output of the operational amplifier, and an output coupled to the gate output. ​ 28. The system of claim 21, wherein the first transistor is a gallium nitride transistor and the second transistor is a gallium nitride transistor.

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