Method, readable storage medium and device for setting tensor hardware configuration

Abstract

The present invention relates to a method, a readable storage medium and a device for setting the hardware configuration of a tensor. First, the requirement for configuring registers for a tensor is obtained. Then, according to the properties of the tensor, it is determined whether the registers have been configured for the tensor, whether the tensor has spatial overlap, and whether there are idle registers. Based on these judgments, appropriate hardware is selected and the identification code of the hardware is responded to, so as to realize a technical solution that can automatically schedule hardware resources and automatically manage the life cycle of tensors.

Description

Technical Field

[0001] The present invention generally relates to the field of computers and more particularly to a method, a readable storage medium and a device for setting a tensor hardware configuration. Background Art

[0002] Deep learning is an important research direction in the field of machine learning today. It enables machines to imitate human activities to solve complex pattern recognition problems and promote the rapid development of artificial intelligence related technologies, especially in search technology, data mining, machine translation, natural language processing, and speech recognition.

[0003] Deep learning needs to be implemented through code. In order to improve programming efficiency, a variety of deep learning frameworks have emerged, such as PaddlePaddle, Tensorflow, Caffe, Theano, MXNet, Torch, and PyTorch. These frameworks provide various components, which are like parts of a model or algorithm. Programmers can reference these components as needed to achieve specific functions. By using a deep learning framework, the programming process can be greatly simplified.

[0004] Tensors are the core components of all deep learning frameworks, because most operations and optimization algorithms are based on tensors. Each deep learning framework provides a specific tensor programming model, and each tensor has a unique identification code that is used to bind its attribute information. However, the existing frameworks have the following problems with the management of tensors: the hardware resources for executing deep learning algorithms are limited and cannot always meet the design of the software side, resulting in poor computing efficiency; the dependencies between tensors require programmers to insert synchronization instructions to ensure the correct execution order; after assigning registers to tensors, it is impossible to know the real-time utilization of tensors that temporarily use hardware resources; programmers need to manually set the life cycle of tensors in registers, etc.

[0005] Therefore, a technical solution that can automatically schedule hardware resources and automatically manage the life cycle of tensors is urgently needed. Summary of the invention

[0006] In order to at least partially solve the technical problems mentioned in the background technology, the solution of the present invention provides a method, a readable storage medium and a device for setting a tensor hardware configuration.

[0007] In one aspect, the present invention discloses a method for setting a tensor hardware configuration, wherein the hardware includes a plurality of registers. The method includes: obtaining a requirement for configuring registers for a tensor; judging whether the tensor has been configured with registers according to the properties of the tensor; judging whether the tensor has spatial overlap; judging whether there are idle registers among the plurality of registers; releasing the least active register among the plurality of registers if the following conditions are met: the tensor has not been configured with registers; the tensor has not spatially overlapped; and there are no idle registers among the plurality of registers; and finally responding with an identification code of the least active register.

[0008] In another aspect, the present invention discloses a computer-readable storage medium having stored thereon a computer program code for setting a tensor hardware configuration. When the computer program code is executed by a processing device, the aforementioned method is executed.

[0009] In another aspect, the present invention discloses a device for setting a hardware configuration of a tensor, wherein the hardware includes a plurality of registers. The device includes an acquisition module, a judgment module, a release module, and a response module. The acquisition module is used to obtain a demand for configuring registers for a tensor. The judgment module is used to: determine whether a register has been configured for a tensor based on the properties of the tensor; determine whether a spatial overlap occurs for a tensor; and determine whether there are idle registers for a plurality of registers. The release module is used to release the least active register among a plurality of registers if the following conditions are met: a register has not been configured for a tensor; a spatial overlap does not occur for a tensor; and there are no idle registers for a plurality of registers. The response module is used to respond to an identification code of the least active register.

[0010] Based on the aforementioned technical means, the present invention can achieve the technical effect of automatically scheduling hardware resources and automatically managing the life cycle of tensors. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood. In the accompanying drawings, several embodiments of the present invention are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0012] Figure 1 is a structural diagram of a board card according to an embodiment of the present invention;

[0013] Figure 2 is a structural diagram showing an integrated circuit device according to an embodiment of the present invention;

[0014] Figure 3 is a schematic diagram showing the internal structure of a computing device according to an embodiment of the present invention;

[0015] Figure 4 is a schematic diagram showing the internal structure of a processor core according to an embodiment of the present invention;

[0016] Figure 5 is a flow chart showing a configuration of registers for setting a tensor according to an embodiment of the present invention;

[0017] Figure 6 is a flow chart showing the determination of the least active register according to an embodiment of the present invention;

[0018] Figure 7 is a flowchart showing another embodiment of the present invention for setting register configuration for a tensor; and

[0019] Figure 8 is a schematic diagram showing another embodiment of the present invention. DETAILED DESCRIPTION

[0020] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0021] It should be understood that the terms "first", "second", "third" and "fourth" etc. in the claims, specifications and drawings of the present invention are used to distinguish different objects rather than to describe a specific order. The terms "include" and "comprise" used in the specification and claims of the present invention indicate the presence of the described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or their collections.

[0022] It should also be understood that the terms used in this specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the specification of the present invention and the claims, the singular forms of "a", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should also be further understood that the term "and / or" used in the specification of the present invention and the claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0023] As used in this specification and claims, the term "if" may be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting," depending on the context.

[0024] The specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0025] Figure 1FIG. 1 is a schematic diagram showing the structure of a board 10 according to an embodiment of the present invention. Figure 1 As shown, the board 10 includes a chip 101, which is a system-on-chip (SoC), or system on chip, integrated with one or more combined processing devices, which are artificial intelligence computing units that support various deep learning and machine learning algorithms to meet the intelligent processing needs in complex scenarios in the fields of computer vision, speech, natural language processing, data mining, etc. In particular, deep learning technology is widely used in the field of cloud intelligence. A notable feature of cloud intelligence applications is the large amount of input data, which places high demands on the storage capacity and computing power of the platform. The board 10 of this embodiment is suitable for cloud intelligence applications and has huge off-chip storage, on-chip storage, and powerful computing power.

[0026] The chip 101 is connected to an external device 103 via an external interface device 102. The external device 103 is, for example, a server, a computer, a camera, a display, a mouse, a keyboard, a network card, or a wifi interface. The data to be processed can be transmitted from the external device 103 to the chip 101 via the external interface device 102. The calculation result of the chip 101 can be transmitted back to the external device 103 via the external interface device 102. According to different application scenarios, the external interface device 102 can have different interface forms, such as a PCIe interface.

[0027] The board 10 also includes a storage device 104 for storing data, which includes one or more storage units 105. The storage device 104 is connected to the control device 106 and the chip 101 through a bus and transmits data. The control device 106 in the board 10 is configured to control the state of the chip 101. To this end, in an application scenario, the control device 106 may include a microcontroller (MCU).

[0028] Figure 2 1 is a block diagram showing the combined processing device in the chip 101 of this embodiment. Figure 2 As shown in , the combined processing device 20 includes a computing device 201 , an interface device 202 , a processing device 203 and a DRAM 204 .

[0029] The computing device 201 is configured to execute user-specified operations, and is mainly implemented as a single-core intelligent processor or a multi-core intelligent processor to perform deep learning or machine learning calculations. It can interact with the processing device 203 through the interface device 202 to jointly complete the user-specified operations.

[0030] The interface device 202 is used to transmit data and control instructions between the computing device 201 and the processing device 203. For example, the computing device 201 can obtain input data from the processing device 203 via the interface device 202 and write it into the storage device on the computing device 201 chip. Further, the computing device 201 can obtain control instructions from the processing device 203 via the interface device 202 and write them into the control cache on the computing device 201 chip. Alternatively or optionally, the interface device 202 can also read data in the storage device of the computing device 201 and transmit it to the processing device 203.

[0031] The processing device 203 is a general processing device that performs basic controls including but not limited to data handling, starting and / or stopping the computing device 201. Depending on the implementation, the processing device 203 can be a central processing unit (CPU), a graphics processing unit (GPU) or one or more types of processors in other general and / or special processors, which include but are not limited to digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc., and their number can be determined according to actual needs. As mentioned above, only with respect to the computing device 201 of the present invention, it can be regarded as having a single-core structure or a homogeneous multi-core structure. However, when the computing device 201 and the processing device 203 are integrated and considered together, the two are regarded as forming a heterogeneous multi-core structure.

[0032] DRAM 204 is used to store data to be processed, and is a DDR memory, which is usually 16G or larger in size and is used to store data of the computing device 201 and / or the processing device 203 .

[0033] Figure 3 The figure shows a schematic diagram of the internal structure of the computing device 201. The computing device 201 is used to process input data such as computer vision, speech, natural language, and data mining. The computing device 201 in the figure adopts a multi-core hierarchical structure design. The computing device 201 is a system on a chip, which includes multiple clusters, and each cluster includes multiple processor cores. In other words, the computing device 201 is composed of a hierarchy of system on a chip-cluster-processor core.

[0034] At the system-on-chip level, Figure 3As shown, the computing device 201 includes an external storage controller 301 , a peripheral communication module 302 , an on-chip interconnect module 303 , a synchronization module 304 , and multiple clusters 305 .

[0035] There may be multiple external storage controllers 301, two of which are shown in the figure as an example, and are used to respond to access requests issued by the processor core and access external storage devices, such as Figure 2 DRAM 204 in the chip, thereby reading data from outside the chip or writing data. The peripheral communication module 302 is used to receive control signals from the processing device 203 through the interface device 202 to start the computing device 201 to perform tasks. The on-chip interconnect module 303 connects the external storage controller 301, the peripheral communication module 302 and multiple clusters 305 to transmit data and control signals between each module. The synchronization module 304 is a global synchronization barrier controller (GBC) used to coordinate the work progress of each cluster and ensure information synchronization. Multiple clusters 305 are the computing cores of the computing device 201. Four are shown as examples in the figure. With the development of hardware, the computing device 201 of the present invention can also include 8, 16, 64, or even more clusters 305. Clusters 305 are used to efficiently execute deep learning algorithms.

[0036] At the cluster level, Figure 3 As shown, each cluster 305 includes a plurality of processor cores (IPU cores) 306 and a memory core (MEM core) 307 .

[0037] The figure shows four processor cores 306 by way of example, but the present invention does not limit the number of processor cores 306. Figure 4 Each processor core 306 includes three modules: a control module 41 , a computing module 42 and a storage module 43 .

[0038] The control module 41 is used to coordinate and control the operation of the computing module 42 and the storage module 43 to complete the deep learning task, and includes an instruction fetch unit (IFU) 411 and an instruction decode unit (IDU) 412. The instruction fetch unit 411 is used to obtain instructions from the processing device 203, and the instruction decode unit 412 decodes the obtained instructions and sends the decoding results to the computing module 42 and the storage module 43 as control information.

[0039] The operation module 42 includes a vector operation unit 421 and a matrix operation unit 422. The vector operation unit 421 is used to perform vector operations and can support complex operations such as vector multiplication, addition, and nonlinear transformation; the matrix operation unit 422 is responsible for the core calculation of the deep learning algorithm, namely matrix multiplication and convolution.

[0040] The storage module 43 is used to store or move related data, including a neuron RAM (NRAM) 431, a weight RAM (WRAM) 432, an input / output direct memory access module (IODMA) 433, and a move direct memory access module (MVDMA) 434. NRAM 431 is used to store feature maps (tensors) for calculation by the processor core 306 and intermediate results after calculation; WRAM 432 is used to store weights (tensors) of the deep learning network; IODMA 433 controls the memory access between NRAM 431 / WRAM 432 and DRAM 204 through the broadcast bus 309; MVDMA 434 is used to control the memory access between NRAM 431 / WRAM 432 and SRAM 308.

[0041] Back to Figure 3 The storage core 307 is mainly used for storage and communication, that is, to store shared data or intermediate results between the processor cores 306, and to perform communication between the cluster 305 and the DRAM 204, communication between the clusters 305, and communication between the processor cores 306. In other embodiments, the storage core 307 has the capability of scalar operation and is used to perform scalar operation.

[0042] The storage core 307 includes a shared memory unit (SRAM) 308, a broadcast bus 309, a cluster direct memory access module (cluster direct memory access, CDMA) 310 and a global direct memory access module (global direct memory access, GDMA) 311. The SRAM 308 plays the role of a high-performance data transfer station. The data reused between different processor cores 306 in the same cluster 305 does not need to be obtained from the DRAM 204 by each processor core 306, but is transferred between the processor cores 306 via the SRAM 308. The storage core 307 only needs to quickly distribute the reused data from the SRAM 308 to multiple processor cores 306, so as to improve the efficiency of inter-core communication and greatly reduce on-chip and off-chip input / output access.

[0043] The broadcast bus 309, CDMA 310 and GDMA 311 are respectively used to perform communication between processor cores 306, communication between clusters 305 and data transmission between clusters 305 and DRAM 204. They will be described below.

[0044] The broadcast bus 309 is used to complete high-speed communication between the processor cores 306 in the cluster 305. The broadcast bus 309 of this embodiment supports inter-core communication modes including unicast, multicast and broadcast. Unicast refers to point-to-point (i.e., single processor core to single processor core) data transmission, multicast is a communication mode of transmitting a copy of data from SRAM 308 to specific processor cores 306, and broadcast is a communication mode of transmitting a copy of data from SRAM 308 to all processor cores 306, which is a special case of multicast.

[0045] The CDMA 310 is used to control the memory access of the SRAM 308 between different clusters 305 in the same computing device 201 .

[0046] GDMA 311 cooperates with external memory controller 301 to control the access of SRAM 308 of cluster 305 to DRAM 204, or reads data from DRAM 204 to SRAM 308. As can be seen from the above, the communication between DRAM 204 and NRAM 431 or WRAM 432 can be realized through two channels. The first channel is to directly connect DRAM 204 and NRAM 431 or WRAM 432 through IODAM 433; the second channel is to first transmit data between DRAM 204 and SRAM 308 through GDMA 311, and then transmit data between SRAM 308 and NRAM 431 or WRAM 432 through MVDMA 434. Although it seems that the second channel requires more components to participate and the data flow is longer, in fact, in some embodiments, the bandwidth of the second channel is much greater than that of the first channel, so the communication between DRAM 204 and NRAM 431 or WRAM 432 may be more efficient through the second channel. The embodiment of the present invention can select a data transmission channel according to its own hardware conditions.

[0047] The processing device 203 can implement a method for setting the tensor hardware configuration during the compilation phase. More specifically, it is a method for configuring registers for tensors in the computing device 201. The registers referred to here can be SRAM 308, NRAM431, WRAM 432 or other storage units used to store tensors in the computing device 201. Figure 5 A flowchart showing setting register configuration for a tensor.

[0048] In step 501, the need to configure registers for a tensor is obtained, that is, the processing device 203 receives an instruction to configure registers for a certain tensor. In this embodiment, the instruction also describes the properties of the tensor, including information such as the address and shape of the tensor. This step obtains the identification code of the tensor through the tensor name stored in the feature map, and obtains the shape information of the tensor through the value of the tensor, thereby realizing hardware resource mapping.

[0049] In step 502, based on the properties of the tensor, it is determined whether the tensor has been configured with registers. In this step, the processing device 203 determines whether the tensor has been configured with any registers, and the basis for the determination is the properties of the tensor. If the properties of the two tensors are the same, they are considered to be the same tensor. The processing device 203 compares the properties of the tensor described in the instruction with the properties of the tensor that has been configured with registers, and then determines whether there is a tensor in the tensor that has been configured with registers that has the same address and shape as the tensor. Through step 502, this embodiment can automatically optimize tensors with the same properties to implement a resource deduplication mechanism.

[0050] If so, it means that the tensor has been configured with registers and does not need to be reconfigured. In this case, step 503 is executed, and the processing device 203 directly responds to the identification code of the configured register. If there is no tensor with the same address and shape as the tensor in the configured registers, it means that the tensor has not been configured with registers. In this case, step 504 is executed to determine whether the tensor has spatial overlap. The so-called spatial overlap means that the tensor at least partially overlaps with other tensors of the previous task. When other tensors participate in the previous task, they will affect the value of the tensor. Therefore, the register must be configured after the previous task is completed. Through step 504, this embodiment is able to determine whether there is a coupling relationship between the currently occupied hardware resources, so as to realize resource coupling judgment.

[0051] If the tensor overlaps with the previous tensor in space, step 505 is executed, and the processing device 203 waits for the task of executing the previous tensor. After the previous task is executed, the previous tensor does not need to occupy the register, so in step 506, the processing device 203 responds with the identification code of the register of the previous tensor, which means that this embodiment directly configures the same register for the tensor, and the tensor covers the previous tensor.

[0052] If the tensors do not overlap in space, step 507 is executed, and the processing device 203 determines whether there are idle registers in the computing device 201. If there are idle registers, step 508 is executed, and the processing device 203 selects any idle register and responds to the identification code of the idle register.

[0053] If the result of step 507 is negative, it means that the tensor has neither a register configured nor a spatial overlap, and there is no idle register in the computing device 201. In this case, step 509 is executed, and the processing device 203 releases the least active register among the multiple registers. The so-called least active register refers to the register that temporarily stores the tensor with the lowest activity. In this step, the processing device 203 needs to determine the least active register. Figure 6 A flow chart showing the process of the processing device 203 determining the least active register.

[0054] In step 601, the activity of the tensors of all configured registers is updated. In more detail, in this embodiment, each tensor of the configured register corresponds to a count value, and the processing device 203 determines the activity based on the count value. This step can be further divided into step 602, step 603, and step 604. In step 602, whenever step 501 is executed, the processing device 203 simultaneously determines whether the tensor of each configured register is in use. If it is in use, step 603 is executed, and the processing device 203 resets the count value corresponding to the tensor being used to zero to indicate that the current activity is high. For those tensors that are not in use, step 604 is executed, and the processing device 203 adds one to the count value corresponding to the unused tensor to indicate that the current activity is low. After step 603 and step 604, step 605 is then executed, where the processing device 203 identifies the tensor with the largest value among all count values. The higher the value, the longer the inactivity. This embodiment identifies the tensor with the largest count value to find the register that temporarily stores the least active tensor (the longest inactivity). Figure 6 This embodiment can record the current hardware resource occupancy in real time during the compilation period to implement resource activity detection.

[0055] Back to Figure 5 In step 509, the processing device 203 passes Figure 6 In step 510, the processing device 203 responds with the identification code of the least active register. Under the premise that there are no idle registers, releasing the least active register is a better choice, so the processing device 203 sets the least active register as the register for temporarily storing the tensor.

[0056] After step 503 , step 506 , step 508 and step 510 , step 511 is executed, and the processing device 203 links the identification code of the aforementioned register to the tensor, and binds the tensor and the register on the software side.

[0057] So far, this embodiment completes the setting of the hardware configuration for Tensor.

[0058] Another embodiment of the present invention is also based on Figures 1 to 4 The method to set the tensor hardware configuration based on the hardware. Figure 7 A flow chart showing the processing device 203 setting register configuration for a tensor.

[0059] In step 701, the need to configure registers for tensors is obtained. In step 702, based on the properties of the tensor, it is determined whether the tensor has been configured with registers. If so, step 703 is executed to directly respond to the identification code of the configured registers. If there is no tensor with the same address and shape as the tensor in the configured registers, step 704 is executed to determine whether the tensor overlaps in space. If the tensor overlaps in space with the previous tensor, step 705 is executed to wait for the task of executing the previous tensor.

[0060] If the tensor does not overlap spatially, or after step 705, step 706 is executed to determine whether there are idle registers in the computing device 201. If there are idle registers, step 707 is executed to select any idle register and respond to the identification code of the idle register. If the result of step 706 is no, it means that the tensor has neither configured registers nor spatial overlap, and there are no idle registers in the computing device 201. In this case, step 708 is executed to release the least active register among the multiple registers. In this embodiment, step 708 can also be divided into the following steps: Figure 6 In step 709, the identification code of the least active register is responded. After step 703, step 707 and step 709, step 710 is executed to link the identification code of the aforementioned register to the tensor, and bind the tensor and the register on the software side.

[0061] The difference between this embodiment and the previous embodiment is that after waiting for the task of executing the previous tensor in step 705, step 706 is executed to directly determine whether there is an idle register, and step 506 of the previous embodiment is not executed. The other steps of this embodiment are the same as the corresponding steps of the previous embodiment, so they are not repeated.

[0062] So far, this embodiment completes the setting of the hardware configuration for Tensor.

[0063] Another embodiment of the present invention is a device for setting a tensor hardware configuration. Figure 1 Only Figure 4 The hardware shown in FIG. 1 is structured as follows: Figure 8 As shown, it includes an acquisition module 801, a judgment module 802, a response module 803, a release module 804, a counting module 805, an identification module 806, an update module 807 and a link module 808, and each module communicates with each other via a bus connection.

[0064] The acquisition module 801 is used to obtain the need to configure registers for a tensor, that is, the acquisition module 801 receives an instruction to configure registers for a certain tensor. In this embodiment, the instruction also describes the properties of the tensor, and the properties include information such as the tensor address and shape.

[0065] The judgment module 802 judges whether the tensor has been configured with registers according to the properties of the tensor. In more detail, the judgment module 802 judges whether the tensor has been configured with any registers, and the basis for judgment is the properties of the tensor. If the properties of two tensors are the same, they are considered to be the same tensor. The judgment module 802 compares the tensor properties described in the instruction with the properties of the tensor that has been configured with registers, and then judges whether there is a tensor in the tensor that has been configured with registers with the same address and shape as the tensor.

[0066] If so, it means that the tensor has been configured with registers and does not need to be reconfigured. The response module 803 directly responds to the identification code of the configured register. If there is no tensor with the same address and shape as the tensor in the configured registers, it means that the tensor has not been configured with registers. At this time, the judgment module 802 further determines whether the tensor has spatial overlap.

[0067] If the tensor overlaps with the previous tensor in space, the device of this embodiment waits for the task of executing the previous tensor. After the previous task is executed, the previous tensor does not need to occupy the register, so the response module 803 responds with the identification code of the register of the previous tensor, which means that this embodiment directly configures the same register to the tensor, and the tensor covers the previous tensor. In another scenario, the response module 803 does not respond after the previous task is executed.

[0068] If the tensors do not overlap spatially, or the response module 803 does not respond in another scenario as described above, the determination module 802 then determines whether there are idle registers in the device. If there are idle registers, the response module 803 selects any idle register and responds with the identification code of the idle register.

[0069] If the tensor has no registers configured, no spatial overlap occurs, and there are no idle registers in the device, the release module 804 releases the least active register among the multiple registers. The so-called least active register refers to the register that temporarily stores the tensor with the lowest activity.

[0070] In this embodiment, each tensor of a configured register also corresponds to a count value. Whenever the acquisition module 801 obtains the need to configure a register for a tensor, the judgment module 802 simultaneously determines whether the tensor of each configured register is being used. If it is being used, the counting module 805 will reset the count value corresponding to the tensor being used to zero to indicate that the current activity is high. For those unused tensors, the counting module 805 will increase the count value corresponding to the unused tensor by one to indicate that the current activity is low. The update module 807 updates these count values ​​in real time, that is, updates the activity of the tensors of all configured registers in real time. The identification module 806 identifies the tensor with the largest value among all count values ​​according to the updated count value. The higher the value, the longer the time of inactivity. The release module 804 finds and releases the register that temporarily stores the least active (longest time inactive) tensor by identifying the tensor with the largest count value.

[0071] Then the response module 803 responds with the identification code of the least active register. After the response module 803 responds with the identification code of the register, the link module 808 links the identification code of the aforementioned register to the tensor, and binds the tensor and the register on the software side. So far, this embodiment completes the setting of the hardware configuration for the tensor.

[0072] Another embodiment of the present invention is a computer-readable storage medium, on which a computer program code for setting a tensor hardware configuration is stored, and when the computer program code is run by a processor, the method of each embodiment described above is executed. In some implementation scenarios, the above-mentioned integrated unit can be implemented in the form of a software program module. If implemented in the form of a software program module and sold or used as an independent product, the integrated unit can be stored in a computer-readable memory. Based on this, when the solution of the present invention is embodied in the form of a software product (such as a computer-readable storage medium), the software product can be stored in a memory, which may include several instructions to enable a computer device (such as a personal computer, a server or a network device, etc.) to perform some or all of the steps of the method described in the embodiment of the present invention. The aforementioned memory may include, but is not limited to, various media that can store program codes, such as a USB flash drive, a flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0073] As shown in the aforementioned multiple embodiments, the present invention simultaneously implements hardware resource mapping, resource activity detection, resource coupling judgment and resource deduplication mechanism, making the programming model more friendly, getting rid of the constraints of limited hardware resources, making the programming model more flexible, and achieving the technical effect of automatic scheduling of hardware resources and automatic management of tensor life cycle.

[0074] According to different application scenarios, the electronic equipment or device of the present invention may include a server, a cloud server, a server cluster, a data processing device, a robot, a computer, a printer, a scanner, a tablet computer, a smart terminal, a PC device, an Internet of Things terminal, a mobile terminal, a mobile phone, a driving recorder, a navigator, a sensor, a camera, a camera, a video camera, a projector, a watch, a headset, a mobile storage, a wearable device, a visual terminal, an automatic driving terminal, a vehicle, a household appliance, and / or a medical device. The vehicle includes an airplane, a ship, and / or a vehicle; the household appliance includes a television, an air conditioner, a microwave oven, a refrigerator, an electric rice cooker, a humidifier, a washing machine, an electric light, a gas stove, and a range hood; the medical device includes a nuclear magnetic resonance apparatus, a B-ultrasound apparatus, and / or an electrocardiograph. The electronic equipment or device of the present invention can also be applied to the Internet, the Internet of Things, a data center, energy, transportation, public administration, manufacturing, education, power grid, telecommunications, finance, retail, construction sites, medical treatment and other fields. Further, the electronic equipment or device of the present invention can also be used in the cloud, edge end, terminal and other application scenarios related to artificial intelligence, big data and / or cloud computing. In one or more embodiments, electronic devices or apparatuses with high computing power according to the solution of the present invention can be applied to cloud devices (such as cloud servers), while electronic devices or apparatuses with low power consumption can be applied to terminal devices and / or edge devices (such as smart phones or cameras). In one or more embodiments, the hardware information of the cloud device and the hardware information of the terminal device and / or edge device are compatible with each other, so that according to the hardware information of the terminal device and / or edge device, appropriate hardware resources can be matched from the hardware resources of the cloud device to simulate the hardware resources of the terminal device and / or edge device, so as to complete the unified management, scheduling and collaborative work of end-to-end or cloud-edge-to-end.

[0075] It should be noted that, for the purpose of simplicity, the present invention describes some methods and embodiments thereof as a series of actions and combinations thereof, but those skilled in the art will appreciate that the scheme of the present invention is not limited by the order of the described actions. Therefore, based on the disclosure or teaching of the present invention, those skilled in the art will appreciate that some of the steps therein may be performed in other orders or simultaneously. Further, those skilled in the art will appreciate that the embodiments described in the present invention may be regarded as optional embodiments, i.e., the actions or modules involved therein are not necessarily necessary for the implementation of one or some schemes of the present invention. In addition, depending on the different schemes, the present invention also has different emphases on the description of some embodiments. In view of this, those skilled in the art will appreciate that the parts not described in detail in a certain embodiment of the present invention may also refer to the relevant descriptions of other embodiments.

[0076] In terms of specific implementation, based on the disclosure and teachings of the present invention, those skilled in the art can understand that several embodiments disclosed in the present invention can also be implemented in other ways not disclosed herein. For example, with respect to the various units in the electronic device or device embodiments described above, this article splits them on the basis of considering the logical functions, and there may be other ways of splitting them in actual implementation. For another example, multiple units or components can be combined or integrated into another system, or some features or functions in the units or components can be selectively disabled. In terms of the connection relationship between different units or components, the connection discussed in the above text in conjunction with the accompanying drawings can be a direct or indirect coupling between units or components. In some scenarios, the aforementioned direct or indirect coupling involves a communication connection using an interface, wherein the communication interface can support electrical, optical, acoustic, magnetic or other forms of signal transmission.

[0077] In the present invention, the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units. The aforementioned components or units may be located at the same location or distributed on multiple network units. In addition, according to actual needs, some or all of the units may be selected to achieve the purpose of the scheme described in the embodiment of the present invention. In addition, in some scenarios, multiple units in the embodiment of the present invention may be integrated into one unit or each unit may exist physically separately.

[0078] The embodiments of the present invention are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A method for setting a tensor hardware configuration, the hardware comprising a plurality of registers, the method comprising: Obtaining a requirement for configuring a register for the tensor; According to the attribute of the tensor, determining whether the tensor has been configured with a register; Determining whether the tensors overlap in space; Determine whether there is an idle register among the multiple registers; If the following conditions are met, the least active register among the plurality of registers is released: The tensor has no registers configured; The tensors do not spatially overlap; and There is no idle register among the plurality of registers; The identifier of the least active register is responded to.

2. The method according to claim 1, wherein the attributes include a tensor address and a shape, and the step of determining whether the tensor has been configured with a register comprises: Determine whether there is a tensor in the tensors configured with the registers that has the same address and shape as the tensor.

3. The method according to claim 1, wherein if the tensor has been configured with a register, the method further comprises: Responds with the identifier of the configured register.

4. The method according to claim 1, wherein if the tensor spatially overlaps with a previous tensor, the method further comprises: Waiting for the task to execute the preceding tensor; as well as After the task is executed, an identification code of the register of the previous tensor is responded.

5. The method according to claim 1, wherein if the tensor spatially overlaps with a previous tensor, the method further comprises: Waiting for the task to execute the preceding tensor; After the task is executed, the step of whether there is an idle register is executed.

6. The method according to claim 1, wherein if there is an idle register among the plurality of registers, the method further comprises: An identification code of at least one of the idle registers is responded to.

7. The method of claim 1, wherein the releasing step comprises: Updates the liveness of all configured registers of the tensor.

8. The method according to claim 7, wherein each tensor of the configured register corresponds to a count value, and the updating step comprises: When the obtaining step is executed, determining whether the tensor of each configured register is being used; If it is being used, the corresponding count value will be reset to zero; as well as If it is not being used, the corresponding count value is increased by one.

9. The method of claim 8, wherein the releasing step further comprises: Identify the tensor with the largest value among all count values; The least active register is the register storing the tensor with the largest count value.

10. The method according to claim 1, 3, 4 or 5, further comprising: The identifier is linked to the tensor.

11. A computer-readable storage medium having stored thereon a computer program code for setting a tensor hardware configuration, wherein when the computer program code is executed by a processing device, the method according to any one of claims 1 to 9 is executed.

12. A device for setting a tensor hardware configuration, the hardware comprising a plurality of registers, the device comprising: An acquisition module, used for acquiring a requirement for configuring a register for the tensor; Judgment module, used to: According to the attribute of the tensor, determining whether the tensor has been configured with a register; Determining whether the tensors overlap in space; Determine whether there is an idle register among the multiple registers; A release module is used to release the least active register among the plurality of registers if the following conditions are met: The tensor has no registers configured; The tensors do not spatially overlap; and There is no idle register among the plurality of registers; The response module is used for responding to the identification code of the least active register.

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