Systems for displays

Abstract

A system for a display is disclosed, which drives pixels using a double rate drive (DRD) method. The system includes a timing controller configured to provide a data packet and a lock signal, and a plurality of drivers, each of which is configured to recover display data and a clock of the data packet, and output a source signal corresponding to the display data using the clock. The lock signal is fed back to the timing controller via a plurality of drivers. Each of the drivers outputs an internal lock signal of the next order obtained by updating the lock signal with information about the recovered clock. Each of the drivers can operate in a low power mode.

Description

Technical Field

[0001] The present disclosure relates to a system for a display, and more particularly, to a driving device for a display that drives pixels using a double rate driving (hereinafter referred to as “DRD”) method. Background Art

[0002] Recently, a technology of driving a screen using a DRD method is applied to a display system.

[0003] In order to drive the screen using the DRD method, the display panel has a reproduction structure in which data is provided through a data line in a time-division manner. Exemplarily, the display panel may have a DRD structure in which a pair of pixels are arranged on the right and left sides with a data line inserted therebetween, and the pair of pixels share the data line arranged between the pixels.

[0004] A display system using the DRD method can reduce the number of data lines of a display panel and achieve high-quality horizontal resolution using a small number of data lines.

[0005] Generally, a display system includes a plurality of drivers to drive a display panel. The drivers are configured to drive source signals corresponding to data lines in a horizontal region assigned thereto.

[0006] If a display panel having a DRD structure is adopted, the number of drivers required to configure a display system is reduced according to a small number of data lines.

[0007] The timing controller needs to determine the sorting order of the display data so that the display data can be presented in the display panel. In addition, the driver needs to be designed to recover the display data in the data packet and distribute the recovered display data to the data lines in a time-division manner according to the sorting order.

[0008] In particular, the driver needs to be designed to have a latch structure for distributing display data in a time-division manner. The latch structure of the driver needs to be designed to reduce the occurrence of EMI and the number of components.

[0009] The display system may represent a screen having various patterns, such as a still image or a moving image. Since the driver realizes high resolution, the driver needs to operate at a high frequency and increases power consumption.

[0010] If a still image maintaining the same pattern is displayed, the driver may repeatedly output a source signal corresponding to horizontal data having the same pattern repeated in units of a horizontal cycle.

[0011] In this case, the driver needs to be designed to reduce power consumption by performing low-power operations that disable unnecessary operations.

[0012] Furthermore, if a screen is displayed in a display panel having a DRD structure, a driver needs to be designed to have a latch structure capable of allocating display data to data lines in a time-division manner using the DRD method while ensuring low-power operation. Summary of the invention

[0013] Various embodiments are directed to providing a system for a display, the system including a driving device having a latch structure for distributing display data in a time-division manner using a DRD method.

[0014] Various embodiments are directed to providing a system for a display, the system including a driving device that can distribute display data using a DRD method and reduce the occurrence of EMI and the number of components.

[0015] Various embodiments are directed to providing a system for a display, the system including a driving device for distributing display data using a DRD method and processing horizontal data having the same pattern, such as a still image, in a low power mode.

[0016] Various embodiments are directed to providing a system for a display, the system including a driving device having a latch structure for distributing display data in a time-division manner according to a display panel having a DRD structure in which one data line is shared by two pixels on the left and two pixels on the right.

[0017] Various embodiments are directed to providing a system for a display, the system including a driving device having a latch structure for allocating display data in a time-division manner according to a display panel having a DRD structure in which one data line is shared by a pair of left and right pixels.

[0018] Various embodiments are directed to providing a low power mode to a driving device for a display, the driving device having a latch structure for allocating display data in a time-division manner using a DRD method, and reducing power consumption of the driving device through the low power mode.

[0019] In an embodiment, a system for a display includes: a timing controller configured to provide a data packet and a lock signal; and a plurality of drivers, each of which is configured to recover display data and a clock of the data packet, and output a source signal corresponding to the display data using the clock. The lock signal is fed back to the timing controller via the plurality of drivers. Each of the plurality of drivers can operate in a low power mode. The first driver entering the low power mode recovers and latches the first horizontal data in the first horizontal cycle, and recovers and latches the second horizontal data in the second horizontal cycle that is one cycle faster than the first horizontal cycle, stops the recovery of the display data and the clock, and bypasses the lock signal instead of the internal lock signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a block diagram illustrating a system for a display to which a driving device according to an embodiment of the present disclosure is applied.

[0021] Figure 2 is a block diagram showing a configuration between a driving device and a display panel in order to describe a low power mode.

[0022] Figure 3 is a waveform diagram depicting a data packet corresponding to a low power mode.

[0023] Figure 4 is a block diagram illustrating a driving device for a display according to an embodiment of the present disclosure.

[0024] Figure 5 It is described based on Figure 4 A waveform diagram showing the operation of the driving device according to the embodiment.

[0025] Figure 6 It is shown by Figure 5 The operation latches the table of the first horizontal data and the second horizontal data.

[0026] Figure 7 It is shown for Figure 5 A table of first selection signals, second selection signals and data updated into a digital-to-analog converter (DAC) operating according to the present invention.

[0027] Figure 8 It is shown by Figure 5 A graphical representation of the results of an operation.

[0028] Fig. 9 It is described based on Figure 4 A waveform diagram of another operation of the driving device according to the embodiment.

[0029] Fig.10 It is shown by Fig. 9 The operation latches the table of the first horizontal data and the second horizontal data.

[0030] Fig.11 It is shown for Fig. 9 A table of the first selection signal, the second selection signal and the data updated into the digital-to-analog converter of the operation.

[0031] Fig.12 It is shown by Fig. 9 A schematic diagram of the results of the operation. DETAILED DESCRIPTION

[0032] The system for display according to the embodiment of the present disclosure can be as follows: Figure 1 In addition, see Figure 2 A state driven in a display panel by a system according to an embodiment of the present disclosure is described.

[0033] A driving device for the system according to an embodiment of the present disclosure may be understood as a driver and will be described as a driver hereinafter.

[0034] Reference Figure 1 and Figure 2 , a system for displaying a screen includes a timing controller 10 and a plurality of drivers 20, 30, and 40. A display panel 50 is configured to receive source signals Sout1 to Sout3 from the plurality of drivers 20, 30, and 40 and display a screen.

[0035] Each of the plurality of drivers 20 , 30 , and 40 implemented by the embodiment of the present disclosure may operate in a normal mode and a low power mode.

[0036] In the normal mode, each of the drivers 20, 30, and 40 restores display data and clocks, and displays a screen with a pattern change like a moving image. In the low power mode, the state of each of the drivers 20, 30, and 40 is set to a low power state in which some operations of restoring display data and clocks are stopped, and each of the drivers 20, 30, and 40 displays a screen in which the same pattern like a still image is repeated in units of horizontal cycles.

[0037] Each of drivers 20, 30 and 40 can display the screen in normal mode with respect to an entire frame, or can display the screen in low power mode with respect to the entire frame, or can display the screen in normal mode with respect to some continuous horizontal lines in a frame and can display the screen in low power mode with respect to the remaining continuous horizontal lines.

[0038] As described above, drivers 20, 30, and 40 may be independently driven in normal mode or low power mode, and each may be operated to display the area of ​​display panel 50 responsible for each driver identically in black or white or a specific color in low power mode.

[0039] exist Figure 2 In the display panel 50 of FIG. 1 , the NP region refers to a region displayed in a normal mode, and the LP region refers to a region displayed in a low power mode.

[0040] Reference Figure 1 and Figure 2 The embodiments of the present disclosure are described in more detail.

[0041] The timing controller 10 configures and outputs a data packet EPI including control data and horizontal data in each horizontal cycle, and includes low power information for enabling a low power mode in the control data in a horizontal cycle for starting the low power mode.

[0042] The timing controller 10 is configured to output the lock signal LK and the control signals L2 , L3 , and L4 through a signal line different from a signal line of the data packet EPI.

[0043] The timing controller 10 is configured to provide the lock signal LK to the driver 20 , and receive the lock signal LK sequentially passing through the drivers 20 , 30 , and 40 from the driver 40 .

[0044] In addition, the timing controller 10 is configured to respectively provide control signals L2, L3 and L4 to the drivers 20, 30 and 40. Each of the control signals L2, L3 and L4 includes a mode control signal, a selection signal and a lock control signal.

[0045] In particular, the control signal L2 includes a mode control signal LPC2, a selection signal SE2, and a lock control signal LS2. The control signal L3 includes a mode control signal LPC3, a selection signal SE3, and a lock control signal LS3. In addition, the control signal L4 includes a mode control signal LPC4, a selection signal SE4, and a lock control signal LS4. Each of the selection signals SE2, SE3, and SE4 includes a signal that will be referred to later. Figure 4 The selection signals SEL1 and SEL2 are described.

[0046] Each of the mode control signals LPC2 to LPC4 is output in such a manner as to be shifted to an enable level at the timing of waking up from the low power mode so as to notify the corresponding driver of the timing at which the low power mode is terminated.

[0047] The selection signals SE2 to SE4 are output in the low power mode and are used to control the distribution of the display data latched in the drivers 20, 30 and 40, respectively. Figure 4 Each of the selection signals SEL1 and SEL2 of each of the described selection signals SE2 to SE4 may have a periodically changing value for determining a position at which specific pixel data is presented in the display panel 50 .

[0048] Each of the locking control signals LS2 to LS4 is used to control the driver operating in the low power mode to bypass the locking signal LK and maintain an enable level in the low power mode.

[0049] The drivers 20 , 30 , and 40 are configured to output source signals Sout1 to Sout3 to pre-assigned areas of the display panel 50 , respectively.

[0050] Each of the drivers 20, 30, and 40 receives the data packet EPI, restores control data, display data, and a clock of the data packet EPI in a normal mode, and outputs a source signal corresponding to the display data using the clock.

[0051] In addition, in the low power mode, each of the drivers 20, 30 and 40 recovers and latches the first horizontal data of the data packet EPI in the first horizontal cycle, and recovers and latches the second horizontal data of the data packet EPI in the second horizontal cycle which is one cycle faster than the first horizontal cycle, stops the recovery of the control data, the display data and the clock, and then outputs the source signal corresponding to the latched first horizontal data and the second horizontal data.

[0052] Each of the drivers 20 , 30 , and 40 may enter a low power mode based on the low power information of the control data.

[0053] In the normal mode and the low power mode, the driver 20 outputs the source signal Sout1 , the driver 30 outputs the source signal Sout2 , and the driver 40 outputs the source signal Sout3 .

[0054] The display panel 50 receives the corresponding source signals Sout1 to Sout3 for each area and displays a screen.

[0055] In addition, the drivers 20, 30, and 40 sequentially transmit the lock signal LK provided by the timing controller 10. The driver 40 in the last sequence is configured to feed back the lock signal LK to the timing controller 10.

[0056] In normal mode, each of the drivers 20, 30 and 40 is configured to generate an internal lock signal LKi by updating a lock signal LK received from the timing controller 10 or a driver in a previous order with information about a clock recovered within each driver, and transmit one of the lock signal LK and the internal lock signal LKi to a driver in a next order.

[0057] Because the driver does not recover the clock signal, the driver belonging to the drivers 20, 30, and 40 and entering the low power mode is configured to bypass the lock signal LK received from the driver in the previous order and provide the lock signal LK to the driver in the next order.

[0058] Driver 20 includes a clock data recovery (CDR) circuit 22, a multiplexer (MUX) 24, and a driver circuit 26. Driver 30 includes a CDR circuit 32, a multiplexer 34, and a driver circuit 36. Driver 40 includes a CDR circuit 42, a multiplexer 44, and a driver circuit 46.

[0059] Each of the drivers 20, 30, and 40 can be understood as having the same structure combining a CDR circuit, a driving circuit, and a multiplexer. Among the signals used for the drivers 20, 30, and 40, the internal lock signal LKi, the clock CLK, and the display data DAT are represented by the same reference numerals in the drivers 20, 30, and 40. The mode control signal, the selection signal, the lock control signal, and the source signal are represented by different reference numerals in the drivers 20, 30, and 40.

[0060] Hereinafter, the configuration and operation of the driver 30 are described. The configuration and operation of the drivers 20 and 40 may be understood with reference to the configuration and operation of the driver 30, and thus redundant description thereof is omitted.

[0061] First, the CDR circuit 32 receives the data packet EPI, the mode control signal LPC3, and the lock signal LK received from the driver 20 in the previous order.

[0062] In the normal mode, the CDR circuit 32 recovers the control data, the display data DAT, and the clock CLK from the data packet EPI in units of horizontal cycles, and supplies the display data DAT and the clock CLK to the driving circuit 36 ​​.

[0063] In addition, the CDR circuit 32 generates information indicating whether the clock CLK internally recovered in units of horizontal cycles is normal, generates an internal lock signal LKi by updating the lock signal LK (i.e., the lock signal LK received from the driver 20 in the previous order) using the information indicating whether the clock CLK is normal, and outputs the generated internal lock signal LKi.

[0064] The CDR circuit 32 determines whether low power information for enabling the low power mode is included in the control data of the display data DAT restored in units of horizontal cycles.

[0065] The restored display data DAT includes: a control data period including control information in each horizontal line period corresponding to each horizontal cycle; a horizontal data period including horizontal data; and a clock training period including clock information. The control information included in the control data period can be configured to use some bits to represent low power information. In this case, the low power information can be configured with 1 bit or 2 bits.

[0066] If low power information for enabling the low power mode is included in the control data, the CDR circuit 32 recognizes entry into the low power mode, recovers horizontal data and clock in a horizontal cycle including the low power information, enters the low power mode, and then stops recovery of the control data, display data DAT, and clock CLK.

[0067] The CDR circuit 32 may recognize entry into the low power mode by calculating some low power information in two horizontal cycles (ie, a first horizontal cycle and a second horizontal cycle which will be described later).

[0068] Reference Figure 3 The structure of the data packet EPI and the low power information are described in more detail.

[0069] The data packet EPI includes a frame period divided by a vertical blank (VB). One frame period includes frame data for displaying one screen (or frame) in the display panel 50.

[0070] exist Figure 3 In the embodiment, the first frame period includes frame data for forming an NP region represented by a normal mode. According to the frame data, all drivers 20, 30, and 40 operate in the normal mode and output source signals Sout1 to Sout3 for representing the NP region. In contrast, the second frame period includes frame data for forming an NP region represented by a normal mode, an LP region represented by a low power mode, and an NP region represented by a normal mode. According to the frame data, drivers 20 and 40 operate in the normal mode and output source signals Sout1 and Sout3 for representing the NP region. Driver 30 operates in the low power mode and outputs source signal Sout2 for representing the LP region. Figure 2 The display panel 50 understands the second frame period.

[0071] One frame includes a plurality of horizontal lines determined according to the resolution of the display panel 50. Therefore, one frame period includes a plurality of horizontal line periods. Data included in each of the horizontal line periods may be referred to as horizontal line data.

[0072] Each of the horizontal line periods includes a control data period CTR including control data, a horizontal data period including horizontal data, and a clock training period CT including clock information. That is, the horizontal line data can be understood as including control data, horizontal data, and clock information.

[0073] exist Figure 3 In the embodiment, the horizontal data period included in the horizontal line period of the NP area can be expressed as RGB.

[0074] The driver receiving the horizontal line data for representing the NP area operates in a normal mode, that is, the driver recovers the control data, the display data DAT and the clock CLK in units of horizontal line periods and outputs a source signal corresponding to the display data DAT using the control data and the clock CLK.

[0075] exist Figure 3 In the embodiment, the horizontal data period included in the horizontal line period of the LP area can be expressed as 1H and 2H.

[0076] The driver receiving the horizontal line data for indicating the LP area operates in the low power mode. That is, the driver recognizes the entry into the low power mode based on the control data of the horizontal line data, latches the horizontal data of the horizontal line data at the timing when the driver enters the low power mode, stops the recovery of the control data, the display data DAT and the clock CLK, and then outputs the source signal corresponding to the latched horizontal data.

[0077] The embodiment of the present disclosure shows that the screen is driven using the DRD method. In order to drive the screen using the DRD method, two horizontal data can be presented in one data line. To this end, when entering the low power mode, the driver implemented by the embodiment of the present disclosure latches the horizontal data included in the horizontal data period 1H and the horizontal data period 2H corresponding to two horizontal cycles, and outputs a source signal in which the latched horizontal data in the two horizontal cycles is presented.

[0078] The low power information for low power mode entry may be included in the control information, which is included in the control data period CTR of each horizontal line. The control information may include one or two bits for indicating the low power information. Therefore, the low power mode may be enabled based on the value of the low power information of the control information.

[0079] Illustratively, the driver internally generates a control signal CTR1 and a control signal CTR2, the control signal CTR1 maintains an enabled level during the low power mode based on the low power information included in the horizontal data period 1H, the control signal CTR2 maintains an enabled level during the low power mode based on the low power information included in the horizontal data period 2H, and the driver recognizes entry into the low power mode by combining the control signal CTR1 and the control signal CTR2.

[0080] Therefore, the CDR circuit 32 recovers the horizontal data included in the horizontal data period 1H of the horizontal cycle of the enable control signal CTR1 and the horizontal data included in the horizontal data period 2H of the horizontal cycle of the enable control signal CTR2, and then stops the recovery of the display data DAT and the clock CLK during the low power mode.

[0081] Since the CDR circuit 32 does not restore control data, display data, and clock information during the low power mode, the CDR circuit 32 cannot receive information for returning from the low power mode to the normal mode through the data packet EPI.

[0082] Therefore, the CDR circuit 32 may return from the low power mode to the normal mode in response to the mode control signal LPC3 provided by the timing controller 10 .

[0083] The CDR circuit 32 responds to the mode control signal LPC3 (corresponding to Figure 3 The LPC in the low power mode) determines a wake-up timing for returning to the normal mode from the low power mode, and operates in the normal mode after the wake-up timing, thereby restarting the recovery of the display data DAT and the clock CLK.

[0084] In addition, the multiplexer 34 receives the lock signal LK from the driver 20 and the internal lock signal LKi from the CDR circuit 32, selects one of the lock signal LK and the internal lock signal LKi, and provides the selected signal as the lock signal LK to the driver 40 in the next order. In order to select and output the lock signal LK to be provided to the driver 40, the multiplexer 34 receives the lock control signal LS3 from the timing controller 10.

[0085] The lock control signal LS3 is used to distinguish between the normal mode and the low power mode, and is set to have an enable level in the low power mode.

[0086] In the normal mode where the lock control signal LS3 has a disable level, the multiplexer 34 selects the internal lock signal LKi of the CDR circuit 32 and outputs the selected internal lock signal LKi as the lock signal LK. In the low power mode where the lock control signal LS3 has an enable level, the multiplexer 34 bypasses the lock signal LK and provides the lock signal LK to the driver 40.

[0087] In the low power mode, the CDR circuit 32 does not need to determine whether the recovered clock is normal because it stops the recovery of the control data, the display data DAT and the clock CLK. Therefore, in the low power mode, the multiplexer 34 bypasses the lock signal LK received from the driver 20 and provides the lock signal LK to the driver 40.

[0088] The driving circuit 36 ​​is configured to receive the display data DAT and the clock CLK from the CDR circuit 32, receive the selection signal SE3 from the timing controller 10, and output the source signal Sout2 to the display panel 50. The selection signal SE3 includes a signal which will be referred to later. Figure 4 The selection signals SEL1 and SEL2 are described.

[0089] In the normal mode, the driving circuit 36 ​​is configured to output a source signal Sout2 corresponding to the display data DAT using the clock CLK.

[0090] In the normal mode, the drive circuit 36 ​​latches the display data DAT in units of horizontal cycles, and outputs the source signal Sout2 as the latched horizontal data is updated in each horizontal cycle. The source signal Sout2 is used to display a screen with a pattern change such as a moving image. In the normal mode, the clock CLK is used for the control of the latch and the output of the source signal Sout. For reference, for ease of description, Figure 4 The clock CLK is not shown.

[0091] When the driver 30 enters the low power mode, the driving circuit 36 ​​latches the first horizontal data in the first horizontal cycle and latches the second horizontal data in the second horizontal cycle which is one cycle faster than the first horizontal cycle. In this case, the first horizontal data in the first horizontal cycle can be understood to correspond to the data included in Figure 3 The second horizontal data in the second horizontal cycle can be understood to correspond to the horizontal data included in Figure 3 The horizontal data in the horizontal data cycle 1H.

[0092] Furthermore, the driving circuit 36 ​​outputs a source signal Sout2 for displaying a screen in which the same pattern is repeated in units of horizontal cycles, such as a still image, using the latched first horizontal data and second horizontal data.

[0093] Please refer to Figure 4 The drive circuit 36 ​​is described.

[0094] The driving circuit 36 ​​includes a shift register SR, a first latch circuit LAT1, a second latch circuit LAT2, a first selection circuit MUX1, a second selection circuit MUX2, a digital-to-analog converter (DAC), and a buffer circuit BUF.

[0095] The shift register SR aligns the serially received display data DAT into horizontal data in units of horizontal cycles and supplies pixel data of the horizontal data to the first latch circuit LAT1 in parallel.

[0096] The first latch circuit LAT1 includes first latches LAT11 , LAT12 , and LAT13 for storing first pixel data.

[0097] In addition, the second latch circuit LAT2 includes second latches LAT21, LAT22 and LAT23 corresponding to the first latches LAT11, LAT12 and LAT13, respectively, and storing the second pixel data. In this case, the second pixel data is updated by the first latches LAT11, LAT12 and LAT13.

[0098] More specifically, the second pixel data is obtained by updating the pixel data stored in the first latches LAT11, LAT12, and LAT13 in the second horizontal cycle before the first latches LAT11, LAT12, and LAT13 are updated with the first pixel data in the first horizontal cycle.

[0099] In the normal mode, each of the first latch circuit LAT1 and the second latch circuit LAT2 updates and latches data stored in each horizontal cycle.

[0100] In contrast, in the low power mode, the first latch circuit LAT1 updates the first horizontal data in the first horizontal cycle and holds the first horizontal data during the low power mode. The second latch circuit LAT2 updates the second horizontal data in the second horizontal cycle and holds the second horizontal data during the low power mode.

[0101] The first selection circuit MUX1 includes first selection units MUX11, MUX12, and MUX13, each of which is configured with a multiplexer. Each of the first selection units MUX11, MUX12, and MUX13 is configured to select one of the first pixel data and the second pixel data and output the selected data. The first selection circuit MUX1 is configured to receive a first selection signal SEL1 from the timing controller 10 in a low power mode, and perform selection and output in response to the first selection signal SEL1.

[0102] More specifically, the first selection unit MUX11 is configured to select one of the first pixel data of the first latch LAT11 and the second pixel data of the second latch LAT21 in response to the first selection signal SEL1, and output the selected data. The first selection unit MUX12 is configured to select one of the first pixel data of the first latch LAT12 and the second pixel data of the second latch LAT22 in response to the first selection signal SEL1, and output the selected data. The first selection unit MUX13 is configured to select one of the first pixel data of the first latch LAT13 and the second pixel data of the second latch LAT23 in response to the first selection signal SEL1, and output the selected data.

[0103] The second selection circuit MUX2 includes second selection units MUX21, MUX22, and MUX23, each of which is configured with a multiplexer. Each of the second selection units MUX21, MUX22, and MUX23 is configured to select one of the selection data of a pair of adjacent first selection units and output the source data. The second selection circuit MUX2 is configured to receive a second selection signal SEL2 from the timing controller 10 in a low power mode, and perform selection and output in response to the second selection signal SEL2.

[0104] exist Figure 4 In the embodiment, the second selection unit MUX21 has a floating input stage, which can be understood as a first selection unit having a virtual connection thereto.

[0105] Therefore, the second selection unit MUX21 is configured to select one of the selection data of the adjacent virtual first selection unit and the first selection unit MUX11 in response to the second selection signal SEL2, and output the source data. The second selection unit MUX22 is configured to select one of the selection data of the adjacent first selection units MUX11 and MUX12 in response to the second selection signal SEL2, and output the source data. The second selection unit MUX23 is configured to select one of the selection data of the adjacent first selection units MUX12 and MUX13 in response to the second selection signal SEL2, and output the source data.

[0106] The digital-to-analog converter DAC includes digital-to-analog converters DAC1, DAC2 and DAC3 corresponding to second selection units MUX21, MUX22 and MUX23 of the second selection circuit MUX2, respectively. Each of the digital-to-analog converters DAC1, DAC2 and DAC3 is configured to output an analog signal corresponding to input source data.

[0107] The buffer circuit BUF includes buffers BUF1, BUF2 and BUF3 corresponding to the digital-to-analog converters DAC1, DAC2 and DAC3 of the digital-to-analog converter DAC, respectively. The buffers BUF1, BUF2 and BUF3 output source signals OUT1 to OUT3 corresponding to the input analog signals, respectively.

[0108] In the driver 30, when entry into the low power mode is recognized based on the low power information, the CDR circuit 32 restores horizontal data and clocks including the low power information in a horizontal cycle, enters the low power mode, and then stops restoration of display data DAT and clock CLK.

[0109] According to the operation of the CDR circuit 32 , the driving circuit 36 ​​receives the first horizontal data in the first horizontal cycle and the second horizontal data in the second horizontal cycle at the timing when the driver 30 enters the low power mode.

[0110] In the low power mode, the first latch circuit LAT1 holds first horizontal data in a first horizontal cycle, and the second latch circuit LAT2 holds second horizontal data updated by the first latch circuit LAT1 in a second horizontal cycle.

[0111] In the low power mode, the first horizontal data of the first latch circuit LAT1 and the second horizontal data of the second latch circuit LAT2 are presented in the display panel 50 using the DRD method according to the embodiment of the present disclosure. Presentation of the first horizontal data and the second horizontal data is controlled by switching the first selection circuit MUX1 and the second selection circuit MUX2.

[0112] Illustratively, the first selection unit MUX11 of the first selection circuit MUX1 selects one of the first latch LAT11 for storing first pixel data of the first horizontal data and the second latch LAT21 for storing second pixel data of the second horizontal data, and outputs the selected pixel data as selection data.

[0113] As described above, each of the first selection units MUX11, MUX12 and MUX13 of the first selection circuit MUX1 is configured to select one of the first latch of the first latch circuit LAT1 connected thereto and the second latch of the second latch circuit LAT2 connected thereto, and output the selected pixel data as selection data.

[0114] Therefore, the first selection circuit MUX1 has a function for selecting pixel data for presentation between the first horizontal data in the first horizontal cycle and the second horizontal data in the second horizontal cycle. The selection of pixel data for presentation may be determined based on the level of the first selection signal SEL1.

[0115] Furthermore, illustratively, the second selection unit MUX22 of the second selection circuit MUX2 is configured to select one of the selection data of the adjacent first selection units MUX11 and MUX12 and output the selected selection data as the source data.

[0116] The first selection circuit MUX1 and the second selection circuit MUX2 may be understood to be configured such that selection data of each of the first selection units MUX11 , MUX12 , and MUX13 of the first selection circuit MUX1 is output as source data through one of the adjacent second selection units of the second selection circuit MUX2 .

[0117] That is, the second selection circuit MUX2 has a function for selecting a channel for presenting the first horizontal data or the second horizontal data. The selection of the channel for presenting can be determined based on the level of the second selection signal SEL2.

[0118] Figure 4 The embodiment can be applied to a DRD structure in which two horizontal data are respectively presented in two pairs of pixels, which share one data line and are arranged on the right and left sides.

[0119] To this end, the first selection signal SEL1 and the second selection signal SEL2 can be as follows in the low power mode. Figure 5 As shown in Figure 5 , Sout shows the output of the source signal.

[0120] exist Figure 5 , the states of the first selection signal SEL1 and the second selection signal SEL2 are changed to a first state (low level (L), high level (H)), a second state (H, H), a third state (L, L) and a fourth state (H, L) in a predetermined order.

[0121] In response to the first selection signal SEL1 and the second selection signal SEL2, the first selection circuit MUX1 and the second selection circuit MUX2 align two first pixel data included in the first horizontal data in a continuous order and two second pixel data included in the second horizontal data in a continuous order, thereby sequentially outputting the first pixel data and the second pixel data as source data for the same data line.

[0122] Reference Figures 6 to 8 , in order to describe the Figure 5 The first selection signal SEL1 and the second selection signal SEL2 are presented. Figure 6 It is shown in Figure 5 A table of first horizontal data LAT1_D latched in a latch of a first latch circuit LAT1 and second horizontal data LAT2_D latched in a latch of a second latch circuit LAT2 in a low power mode of the present invention. Figure 7 It is shown for Figure 5 A table of the first selection signal, the second selection signal and the data updated to the DAC of the operation. Figure 8 It is shown by Figure 5 A graph showing the results of the operation.

[0123] like Figure 6 As shown in FIG. 1 , in the low power mode, the first latch circuit LAT1 and the second latch circuit LAT2 latch the first horizontal data LAT1_D and the second horizontal data LAT2_D. Figure 6 A table corresponding to six channels is shown, but reference may be made to Figure 4 The structures of the first latch circuit LAT1 and the second latch circuit LAT2 for the channel are understood.

[0124] When the first selection signal SEL1 and the second selection signal SEL2 are Figure 7 When the first state (L, H) shown in FIG. 1 is provided to the first selection circuit MUX1 and the second selection circuit MUX2 respectively, the source data in the digital-to-analog converter DAC updated to the digital-to-analog converter DAC is the same as the source data stored in the digital-to-analog converter DAC. Figure 6 The second horizontal data LAT2_D in the second latch circuit LAT2 are identically aligned.

[0125] Thereafter, when the first selection signal SEL1 and the second selection signal SEL2 are Figure 7 When the source data in the digital-to-analog converter DAC updated to the digital-to-analog converter DAC is respectively provided to the first selection circuit MUX1 and the second selection circuit MUX2 in the second state (H, H) shown in FIG. Figure 6 The first horizontal data LAT1_D in the first latch circuit LAT1 are identically aligned.

[0126] The source data updated to the digital-to-analog converter DAC according to the changes of the first selection signal SEL1 and the second selection signal SEL2 having the first state (L, H) and the second state (H, H) respectively can be shown as Sout corresponding to Figure 5 The source signal in 1H-OUT.

[0127] Thereafter, when the first selection signal SEL1 and the second selection signal SEL2 are Figure 7 When the third state (L, L) shown in FIG. 1 is provided to the first selection circuit MUX1 and the second selection circuit MUX2, Figure 6 In a state where the second horizontal data LAT2_D stored in the second latch circuit LAT2 has been shifted to the left, the source data of the digital-to-analog converter DAC updated to the digital-to-analog converter DAC is aligned.

[0128] Thereafter, when the first selection signal SEL1 and the second selection signal SEL2 are Figure 7 When the fourth state (H, L) shown in FIG. 1 is provided to the first selection circuit MUX1 and the second selection circuit MUX2, Figure 6 The source data of the digital-to-analog converter DAC updated to the digital-to-analog converter DAC is aligned in a state where the first horizontal data LAT1_D stored in the first latch circuit LAT1 has been shifted to the left.

[0129] The source data in the digital-to-analog converter DAC updated according to the changes of the first selection signal SEL1 and the second selection signal SEL2 having the third state (L, L) and the fourth state (H, L) can be shown as Sout corresponding to Figure 5 The source signal in 2H-OUT.

[0130] When the first horizontal data LAT1_D and the second horizontal data LAT2_D are aligned in the digital-to-analog converter DAC according to the changes of the first selection signal SEL1 and the second selection signal SEL2, respectively, it can be as follows Figure 8 The presentation of pixel data of the display panel 50 is implemented as shown in .

[0131] Figure 8 is a diagram showing that pixel data has been presented in the display panel 50 having the DRD structure, in which two horizontal data are respectively presented in two pairs of pixels which share one data line and are arranged on the left and right.

[0132] also, Figure 4 The embodiment may be applied to a DRD structure in which two horizontal data are respectively presented in two pixels which share one data line and are arranged on the right and left sides.

[0133] To this end, the first selection signal SEL1 and the second selection signal SEL2 can be as follows in the low power mode. Fig. 9 As shown in Fig. 9 , Sout shows the output of the source signal.

[0134] exist Fig. 9 In the embodiment, the first selection signal SEL1 is provided so that the high level (H) and the low level (L) are changed. The second selection signal SEL2 is maintained at a fixed level (for example, a low level (L)).

[0135] The first and second selection circuits MUX1 and MUX2 align the first and second pixel data in response to the first and second selection signals SEL1 and SEL2 , respectively, thereby alternately outputting the first and second pixel data as source data for the same data line.

[0136] Reference Figures 10 to 12 , in order to describe the Fig. 9 The presentation of the first selection signal SEL1 and the second selection signal SEL2. Fig.10 It is shown in Fig. 9 A table of first horizontal data LAT1_D latched in a latch of a first latch circuit LAT1 and second horizontal data LAT2_D latched in a latch of a second latch circuit LAT2 in a low power mode of the present invention. Fig.11 It is shown for Fig. 9 A table of the first selection signal, the second selection signal and the data updated to the DAC for the operation. Fig.12 It is shown by Fig. 9 A graph showing the results of the operation.

[0137] In low power mode, such as Fig.10 As shown in FIG. 1 , the first latch circuit LAT1 and the second latch circuit LAT2 latch the first horizontal data LAT1_D and the second horizontal data LAT2_D, respectively. Fig.10 A table corresponding to six channels is also shown, but reference may be made to Figure 4 The structures of the first latch circuit LAT1 and the second latch circuit LAT2 for six channels are understood.

[0138] exist Fig. 9 , the second selection signal SEL2 maintains a fixed level (L), and the first selection signal SEL1 shifts to a high level (H) and a low level (L). Therefore, when the first selection signal SEL1 has a low level, the first selection circuit MUX1 outputs the second horizontal data LAT2_D as the selection data, and when the first selection signal SEL1 has a high level, the first selection circuit MUX1 outputs the first horizontal data LAT1_D as the selection data. In addition, since the second selection circuit MUX2 maintains a fixed level, the connection state of the digital-to-analog converter DAC of the digital-to-analog converter DAC that will update the source data is fixed.

[0139] Therefore, the first selection circuit MUX1 and the second selection circuit MUX2 can align the first pixel data of the first horizontal data LAT1_D and the second pixel data of the second horizontal data LAT2_D in response to the first selection signal SEL1 and the second selection signal SEL2, respectively, thereby alternately outputting the first pixel data and the second pixel data as source data for the same data line.

[0140] When the first horizontal data LAT1_D and the second horizontal data LAT2_D are transmitted in the digital-to-analog converter DAC according to the changes of the first selection signal SEL1 and the second selection signal SEL2, Fig.11 When the sample is aligned, Fig.12 The presentation of pixel data of the display panel 50 is realized.

[0141] Fig.12 is a diagram showing that pixel data has been presented in the display panel 50 having the DRD structure in which two horizontal data are presented in two pixels which share one data line and are respectively disposed on the right and the left.

[0142] As described above, the embodiment of the present disclosure has a latch structure in which display data is allocated in a time-division manner using the DRD method. Therefore, it is advantageous in that a display panel having the DRD structure can be driven.

[0143] In addition, according to an embodiment of the present disclosure, when display data is allocated using the DRD method, the update of the horizontal data between the latches occurs once. Therefore, the advantages of the embodiment of the present disclosure are that the number of times the horizontal data is updated can be minimized, which makes it possible to reduce the occurrence of EMI and realize a latch structure with a small number of components.

[0144] In the system for a display according to the present disclosure, the driving device has a latch structure for distributing display data in a time-division manner using the DRD method, and thus can drive a display panel having the DRD structure.

[0145] In addition, in the system for a display according to the present disclosure, the advantage of the driving device for a display according to the present disclosure is that when the display data is latched using the DRD method according to the embodiment of the present disclosure, the number of times the horizontal data is updated can be minimized, which can reduce the occurrence of EMI and realize a latch structure with a small number of components.

[0146] In addition, in the system for a display according to the present disclosure, the driving device for a display according to the present disclosure has an advantage in that it can reduce power consumption by executing a low power mode according to a repeated identical pattern (such as a still image) and allocating display data using horizontal data latched in the low power mode according to the DRD method.

[0147] In addition, in the system for a display according to the present disclosure, the driving device for a display according to the present disclosure is advantageous in that it can provide a low power mode according to a DRD structure in which one data line is shared by two pixels on the left and two pixels on the right, or in a DRD structure in which one data line is shared by a pair of left and right pixels.

[0148] In addition, according to the present disclosure, the driving device for a display according to the present disclosure has an advantage in that it can reduce power consumption by executing a low power mode according to a repeated identical pattern such as a still image, and allocating display data using latched horizontal data according to the DRD method in the low power mode.

Claims

1. A system for a display, comprising: a timing controller configured to provide a data packet and a lock signal; as well as a plurality of drivers, each driver being configured to recover display data and a clock of the data packet and output a source signal corresponding to the display data using the clock; Wherein, the locking signal is fed back to the timing controller via the multiple drivers; Each of the plurality of drivers is capable of operating in a normal mode or a low power mode; each of the plurality of drivers entering the normal mode recovers the display data and the clock of the data packet and outputs an internal lock signal obtained by updating the lock signal using information on the recovered clock, and Each of the multiple drivers entering the low power mode recovers and latches the first horizontal data in a first horizontal cycle and recovers and latches the second horizontal data in a second horizontal cycle that is one cycle faster than the first horizontal cycle, stops recovery of the display data and the clock, and outputs the lock signal instead of the internal lock signal.

2. The system of claim 1, wherein: The timing controller provides a lock control signal in the low power mode; and Each of the plurality of drivers outputs the lock signal in response to the lock control signal.

3. The system according to claim 1, wherein: Each of the plurality of drivers comprises: a clock data recovery (CDR) circuit configured to recover the display data and the clock of the data packet and output the internal lock signal obtained by updating the lock signal using information about the recovered clock; a driving circuit configured to output a source signal corresponding to the display data using the clock; and A multiplexer is configured to select the internal lock signal in response to a lock control signal in a normal mode and output the selected internal lock signal, and to select and output the lock signal in the low power mode.

4. The system according to claim 3, wherein: The CDR circuit: in the normal mode, restoring the display data and the clock, and outputting the internal lock signal obtained by updating the lock signal using information about the restored clock; as well as When first low power information included in the first horizontal data and second low power information included in the second horizontal data have values ​​for enabling the low power mode, restoration of the display data and the clock is stopped after the first horizontal cycle in the low power mode.

5. The system of claim 4, wherein: The CDR circuit receives a mode control signal from the timing controller; The mode control signal is transmitted separately from the data packet; After a wake-up timing set by the mode control signal, the CDR circuit returns to the normal mode.

6. The system according to claim 3, wherein: The driving circuit comprises: A first latch circuit including a first latch storing first pixel data of the first horizontal data; a second latch circuit, comprising second latches respectively corresponding to the first latches and storing second pixel data of the second horizontal data, wherein the second pixel data is updated to the corresponding first latches; A first selection circuit including first selection units, each of which selects one of the first pixel data and the second pixel data and outputs selected data; and The second selection circuit includes second selection units, each of which selects one of the selection data of a pair of adjacent first selection units and outputs the source data to be changed into the source signal.

7. The system according to claim 6, wherein: When first low power information included in the first horizontal data in the first horizontal cycle and second low power information included in the second horizontal data in the second horizontal cycle have values ​​for enabling the low power mode, the first latch circuit stores the first horizontal data and then stops the updating, and the second latch circuit stores the second horizontal data and then stops the updating.

8. The system of claim 7, wherein: After a wake-up timing set by a mode control signal, the first latch circuit and the second latch circuit resume updating of the first pixel data and the second pixel data; and The mode control signal is provided by the timing controller separately from the data packet.

9. The system of claim 6, wherein: In the low power mode, a first selection signal and a second selection signal are received from the timing controller separately from the data packet; The first selection unit of the first selection circuit selects the first pixel data or the second pixel data in response to the first selection signal; as well as The second selection unit of the second selection circuit selects one of the selection data of the pair of adjacent first selection units in response to the second selection signal.

10. The system of claim 9, wherein: The states of the first selection signal and the second selection signal are changed to a first state of a low level and a high level, a second state of a high level and a high level, a third state of a low level and a low level, and a fourth state of a high level and a low level in a predetermined order; and In response to the first selection signal and the second selection signal, the first selection circuit and the second selection circuit align two first pixel data included in the first horizontal data in a consecutive order and two second pixel data included in the second horizontal data in a consecutive order so that the two first pixel data and the two second pixel data are sequentially output as source data for the same data line.

11. The system of claim 9, wherein: The first selection signal is configured to be shifted to a high level and a low level; The second selection signal is set to a fixed level; and In response to the first selection signal and the second selection signal, the first selection circuit and the second selection circuit align the first pixel data and the second pixel data so that the first pixel data and the second pixel data are alternately output as source data for the same data line.

12. The system of claim 3, wherein: each of the plurality of drivers receives the lock control signal for distinguishing between the normal mode and the low power mode separately from the data packet; as well as The multiplexer performs selection and output in response to the lock control signal.

13. The system according to claim 3, wherein: The driving circuit comprises: a 1-1th latch storing first pixel data in the first horizontal cycle; a 2-1st latch storing second pixel data in the second horizontal cycle and being updated with the second pixel data via the 1-1st latch; a 1-1 selection unit, selecting one of the first pixel data and the second pixel data, and outputting first selection data; a 1-2 latch storing third pixel data in the first horizontal cycle; a 2-2 latch storing fourth pixel data in the second horizontal cycle and being updated with the fourth pixel data via the 1-2 latch; a 1-2 selection unit, selecting one of the third pixel data and the fourth pixel data, and outputting second selection data; The second selection unit selects the first selection data or the second selection data and outputs the source data to be converted into the source signal.

14. The system of claim 13, wherein: The first level data includes first control data having first low power information; The second level data includes second control data having second low power information; When the first low power information has a value for enabling the low power mode, the 1-1st latch and the 1-2nd latch store the first pixel data and the third pixel data in the first horizontal cycle and then stop updating; as well as When the second low power information has a value for enabling the low power mode, the 2-1st latch and the 2-2nd latch store the second pixel data and the fourth pixel data in the second horizontal cycle and then stop updating.

15. The system of claim 13, wherein: In the low power mode, the first selection signal and the second selection signal are received from the timing controller separately from the data packet; The selection and output of the 1-1 selection unit and the 1-2 selection unit are controlled by the first selection signal; as well as The selection and output of the second selection unit are controlled by the second selection signal.

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