PCIe encryption card low-power-consumption implementation method and system based on ASPM

Abstract

The embodiment of the invention discloses a PCIe encryption card low-power-consumption implementation method and system based on ASPM, and the method comprises the steps: switching the low-power-consumption and working mode of a PCIe encryption card through alternately employing low-power-consumption state interruption and base address register or address conversion unit matching interruption, namely, when a power management module of a PCIe controller detects that the power management module is in an idle state; the PCIe controller generates a low-power-consumption state interrupt signal to the central processing unit and each algorithm module of the PCIe encryption card, in a low-power-consumption state interrupt service program, the central processing unit and each algorithm module enter a low-power-consumption mode, and when the PCIe interface receives an upper host command, the central processing unit and each algorithm module enter a low-power-consumption mode. The PCIe controller generates a base address register interrupt signal or an address conversion unit matching interrupt signal to the central processing unit and each algorithm module, the central processing unit and each algorithm module are awakened, the low-power-consumption mode is quitted, and firmware carries out encryption and decryption command analysis processing on a host command data packet. According to the scheme, the power consumption of the PCIe encryption card can be controlled to be lower.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of electrical digital data processing, and in particular, to a method and system for low-power implementation of a PCIe encryption card based on ASPM. Background Art

[0002] In PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) technology, with the demands of the application market and the development of various technologies, the improvement of performance and data transfer speed will inevitably lead to higher power consumption of PCIe boards. Therefore, it is particularly important to design a stable and effective method for reducing power consumption. ASPM (Active State Power Management) is a hardware power management function that can switch the power consumption mode of the PCIe link to achieve dynamic power management. ASPM supports two low-power states: the L0s low-power state with a short recovery time and the L1 lower-power state with a longer recovery time.

[0003] A PCIe encryption card is a pluggable input device that provides hardware encryption functions by connecting to the PCI bus slot of a computer. In the related PCIe encryption card technology using ASPM, when the PCIe encryption card enters the L1 state, the PCIe encryption card will negotiate L1 control with the host. Sometimes, for some reason, such as other PCIe devices on the host being in a non-idle state, the host will reject the request of the PCIe encryption card to enter the L1 state. In this case, the PCIe encryption card has a long working time and high power consumption, resulting in an increase in the temperature of the PCIe encryption card chip and causing the functions of the PCIe encryption card to be unstable. Summary of the Invention The embodiments of the present application provide a method and system for low-power implementation of a PCIe encryption card based on ASPM, which solve the problem that in the existing method of using ASPM for PCIe encryption cards, the PCIe encryption card has a long working time and high power consumption, resulting in an increase in the temperature of the PCIe encryption card chip and causing the functions of the PCIe encryption card to be unstable. By alternately using low-power state interrupts and base address register matching interrupts or address translation unit matching interrupts to switch the low-power and working modes of the PCIe encryption card, the power consumption of the PCIe encryption card can be controlled lower, without the need to install a chip heat sink or a fan, reducing the production cost of the PCIe encryption card.

[0004] In a first aspect, the embodiments of the present application provide a method for low-power implementation of a PCIe encryption card based on ASPM, including: When the host detects that the PCIe encryption card is powered on, configure the power management function control register to start the power management function in the PCIe controller of the PCIe encryption card, and perform PCIe link training with the PCIe encryption card; When the PCIe link reaches the normal working state through the PCIe link training, configure the base address register and the address translation unit of the PCIe encryption card; The PCIe encryption card detects the host command data transmission based on the power management function in the PCIe controller. When it detects that there is no host command data transmission, it controls the PCIe controller to enter the low power state, and based on the firmware, controls the PCIe controller to generate a low power state interrupt signal and send it to the central processing unit and each algorithm module of the PCIe encryption card, so that the central processing unit and each algorithm module enter the low power mode; When it detects the host command data transmission, it controls the PCIe controller to enter the normal working state, and based on the firmware, controls the PCIe controller to generate a base address register match interrupt signal or an address translation unit match interrupt signal, and send it to the central processing unit and each algorithm module, so that the central processing unit and each algorithm module exit the low power mode.

[0005] Optionally, the controlling the PCIe controller to generate a low power state interrupt signal based on the firmware and send it to the central processing unit and each algorithm module of the PCIe encryption card, so that the central processing unit and each algorithm module enter the low power mode includes: In the low power state interrupt service program, the PCIe encryption card detects the state of the PCIe link based on the firmware. When it detects that it is in the low power state, it disables the low power state interrupt, enables the base address register match interrupt or the address translation unit match interrupt, and controls the central processing unit and each algorithm module to enter the low power mode.

[0006] Optionally, after the central processing unit and each algorithm module enter the low power mode, it includes: When the PCIe encryption card negotiates the state with the host based on the power management function protocol, the PCIe encryption card controls the central processing unit and each algorithm module to keep the low power mode unchanged.

[0007] Optionally, in the low power mode, it further includes: The PCIe encryption card controls the clock stop of other parts except for the parts of the circuit directly driven by the external clock and the internal oscillator with a lower frequency, and controls multiple analog modules to enter the stop state step by step to turn off the central processing unit and each algorithm module.

[0008] Optionally, after the central processing unit and each algorithm module exit the low power mode, it further includes: The PCIe encryption card encrypts and decrypts the host command data based on the firmware, and controls the PCIe controller to enter the low power state again.

[0009] Optionally, after the PCIe encryption card completes the encryption and decryption processing of the host command data, it further includes: The PCIe encryption card sends a message flag interrupt signal to the host based on the firmware, so that the PCIe controller enters the normal working state.

[0010] Optionally, in the case where it is detected that there is no host command data transmission, it includes: Controlling the low power state interrupt signal to be generated only once; In the case where it is detected that there is host command data transmission, it includes: Controlling the base address register interrupt signal or the address translation unit match interrupt signal to be generated only once.

[0011] In a second aspect, an embodiment of the present application further provides a device for implementing low power consumption of a PCIe encryption card based on ASPM, including: A function startup module, configured to configure a power management function control register to start the power management function in the PCIe controller of the PCIe encryption card when the host detects the power-on of the PCIe encryption card; A link training module, configured to perform PCIe link training with the PCIe encryption card; A configuration module, configured to configure the base address register and the address translation unit of the PCIe encryption card when the PCIe link reaches the normal working state through the PCIe link training; A state control module, configured to detect host command data transmission by the PCIe encryption card based on the power management function in the PCIe controller, and control the PCIe controller to enter the low power state when it is detected that there is no host command data transmission; A mode control module, configured to control the PCIe controller to generate a low power state interrupt signal based on the firmware and send it to the central processing unit and algorithm modules of the PCIe encryption card, so that the central processing unit and algorithm modules enter the low power mode; The state control module is further configured to control the PCIe controller to enter the normal working state when detecting the transmission of the host command data; The mode control module is further configured to control the PCIe controller to generate a base address register matching interrupt signal or an address translation unit matching interrupt signal based on the firmware and send the signal to the central processing unit and the algorithm module, so that the central processing unit and the algorithm module exit the low power consumption mode.

[0012] In a third aspect, an embodiment of the present application further provides a low power consumption implementation device for a PCIe encryption card based on ASPM. The device includes: One or more processors; A storage device for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the low power consumption implementation method for the PCIe encryption card based on ASPM in the embodiment of the present application.

[0013] In a fourth aspect, an embodiment of the present application further provides a storage medium storing computer-executable instructions. The computer-executable instructions are used to execute the low power consumption implementation method for the PCIe encryption card based on ASPM in the embodiment of the present application when executed by a computer processor.

[0014] In the embodiment of the present application, the low power consumption state interrupt and the base address register or the address translation unit matching interrupt are alternately used to switch the low power consumption and the working mode of the PCIe encryption card. That is, when the power management module of the PCIe controller detects an idle state, the PCIe controller generates a low power consumption state interrupt signal to the central processing unit and each algorithm module of the PCIe encryption card. In the low power consumption state interrupt service program, the central processing unit and each algorithm module enter the low power consumption mode. When a host command is received on the PCIe interface, the PCIe controller generates a base address register interrupt signal or an address translation unit matching interrupt signal to the central processing unit and each algorithm module, wakes up the central processing unit and each algorithm module, exits the low power consumption mode, and the firmware performs decryption command parsing processing on the host command data packet. This solution solves the problem that in the existing method of using ASPM for PCIe encryption cards, the working time of the PCIe encryption card is long and the power consumption is high, resulting in an increase in the temperature of the PCIe encryption card chip and causing unstable functions of the PCIe encryption card. By alternately using the low power consumption state interrupt signal and the base address register matching interrupt signal or the address translation unit matching interrupt signal to switch the low power consumption and the working mode of the PCIe encryption card, the power consumption of the PCIe encryption card can be controlled lower, and there is no need to install a chip heat sink or a fan, reducing the production cost of the PCIe encryption card. Description of the Drawings

[0015] Figure 1 A flowchart of a method for implementing low power consumption of a PCIe encryption card based on ASPM provided by an embodiment of the present application; Figure 2 A flowchart of a method for implementing low power consumption of a PCIe encryption card based on ASPM, which includes a way for a central processing unit to enter a low power consumption mode; Figure 3 A flowchart of a method for implementing low power consumption of a PCIe encryption card based on ASPM, which includes an operation mode after a central processing unit enters a low power consumption mode; Figure 4 A block diagram of the module structure of a device for implementing low power consumption of a PCIe encryption card based on ASPM provided by an embodiment of the present application; Figure 5 A schematic structural diagram of a device for implementing low power consumption of a PCIe encryption card based on ASPM provided by an embodiment of the present application. Detailed implementation manners

[0016] The following further elaborates on the embodiments of the present application in conjunction with the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the embodiments of the present application, rather than limiting the embodiments of the present application. Additionally, it should be noted that for the sake of description, only parts related to the embodiments of the present application are shown in the accompanying drawings, rather than all structures.

[0017] Terms such as "first" and "second" in the specification and claims of the present application are used to distinguish similar objects, rather than to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by "first", "second", etc. are generally of the same category, and do not limit the number of objects. For example, the first object can be one or multiple. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character "or" generally represents an "or" relationship between the associated objects before and after.

[0018] A method for implementing low power consumption of a PCIe encryption card based on ASPM provided by an embodiment of the present application can be applied to the usage scenario after the PCIe encryption card is powered on. For example, after the PCIe encryption card enters the working state, the method for implementing low power consumption of a PCIe encryption card based on ASPM provided by an embodiment of the present application can be used for power consumption control.

[0019] Figure 1 A flowchart of a method for implementing low power consumption of a PCIe encryption card based on ASPM provided by an embodiment of the present application, as Figure 1As shown below, specifically including: Step S101: When the host detects that the PCIe encryption card is powered on, configure the power management function control register to activate the power management function in the PCIe controller of the PCIe encryption card, and perform PCIe link training with the PCIe encryption card.

[0020] Among them, the host is used to represent a device with a central processing unit (CPU). The host is connected to the PCIe encryption card through the root complex and the PCIe bus, providing functions such as secure data transmission and storage. The power management function control register is a register used to control the power management function of the PCIe device. By configuring this power management function control register, the host can enable the power management function in the PCIe controller of the PCIe encryption card. Exemplarily, the configuration method can be to modify the value of the power management function control register using a command. The Active State Power Management (ASPM) is a power management mechanism mainly used on the PCIe bus, aiming to reduce power consumption during idle time by dynamically adjusting the link power. It mainly acts on the link layer, automatically detecting the link idle state by hardware without software intervention. Software can only enable or disable it by configuring the register. The PCIe encryption card is a pluggable device that provides hardware encryption functions by connecting to the PCI Express (PCIe bus) slot of the host. PCIe link training refers to a series of initialization processes performed by the PCIe bus when devices are connected to ensure that the devices at both ends of the link can correctly communicate data. Among them, the PCIe link refers to the link for the PCIe encryption card to transmit data with the host. The specific steps of this PCIe link training include the detection phase, polarity determination, rate negotiation, link width negotiation, equalization phase, transition to the L0 state (normal working state), etc. An exemplary example can be that after the PCIe encryption card A connected to the host a is powered on, the host a detects this situation, configures the power management function control register to enable the power management function in the PCIe controller of the connected PCIe encryption card A, and performs PCIe link training with the connected PCIe encryption card A.

[0021] Step S102: When the PCIe link reaches the normal working state through the PCIe link training, configure the base address register and the address translation unit of the PCIe encryption card.

[0022] Among them, the normal working state (L0 state) is used to represent the state during normal operation. In this normal working state, devices at both ends of the PCIe link can normally exchange TLPs (Transaction Layer Packets) and DLLPs (Data Link Layer Packets) to achieve standard data interaction. When the PCIe link reaches this normal working state through PCIe link training, the host can configure the base address register and the address translation unit of the connected PCIe encryption card. The base address register (abbreviated as BAR, Base Address Registers) is a register in the PCle encryption card, which is used to define the physical address range of the device and tell the operating system how to map these physical addresses to the local address space of the device. The address translation unit (abbreviated as ATU, address translation) is a hardware unit used for address translation in the PCIe system. With this address translation unit, the local address (external address) of the device can be converted into the global address (internal address) in the system memory or configuration space. In one embodiment, a method for configuring the base address register and the address translation unit of the PCIe encryption card can be that when the power management function of the PCIe encryption card reaches this normal working state through PCIe link training, the host maps the physical address of each base address register to the local address space of the PCIe encryption card based on the operating system, reads and writes the configuration information stored in the configuration space of the PCIe encryption card to set the parameters of the base address register in the PCIe encryption card, completes the configuration of the base address register, and the PCIe controller of the PCIe encryption card configures the address translation unit to ensure that the host can correctly perform address translation and access the internal resources of the device.

[0023] Step S103: The PCIe encryption card detects the host command data transmission based on the power management function in the PCIe controller. When it detects that there is no host command data transmission, it controls the PCIe controller to enter the low-power state, and based on the firmware, controls the PCIe controller to generate a low-power state interrupt signal and send it to the central processing unit and each algorithm module of the PCIe encryption card, so that the central processing unit and each algorithm module enter the low-power mode.

[0024] Among them, the host command data is used to represent various commands and data to be processed sent by the host to instruct the PCIe encryption card to perform corresponding operations. When the PCIe encryption card detects the absence of the transmission of the host command data based on the power management function in the PCIe controller, it can control the PCIe controller to enter the low-power state. The low-power state (L0s state) is used to represent a power management state defined by the ACPI specification, indicating that the system is in an idle state but still maintains the ability to respond to external devices. In this state, the system reduces power consumption but does not completely turn off the power. The firmware is a program embedded in the PCIe encryption card, responsible for controlling the operation of the PCIe encryption card and providing basic functions. Using this firmware, the PCIe controller can be controlled to generate a low-power state interrupt signal and send it to the central processing unit and each algorithm module of the PCIe encryption card. The low-power state interrupt signal can be a signal for interrupting the low-power state (L0s state) of the power management function. Using this low-power state interrupt signal, the central processing unit and each algorithm module of the PCIe encryption card can enter the low-power mode. The central processing unit and each algorithm module can be all the modules in the PCIe encryption card except the modules in the PCIe controller. The low-power mode is used to represent a mode of reducing its own power consumption.

[0025] In one embodiment, a way for the central processing unit to enter the low-power mode can be that the PCIe encryption card selects an encryption chip with a shutdown mode. When the power management function enters the low-power state, a setting instruction is sent through the PCIe controller to make the central processing unit enter the low-power mode. However, this method cannot accurately control the power consumption of the PCIe encryption card. Optionally, a way for the central processing unit to enter the low-power mode can be that in the low-power state interrupt service program, the PCIe encryption card detects the state of the PCIe link based on the firmware. When it detects that it is in the low-power state, it prohibits the low-power state interrupt, enables the base address register match interrupt or the address translation unit match interrupt, and controls the central processing unit and each algorithm module to enter the low-power mode. By outputting the L0s state interrupt from the power management function of the PCIe encryption card to the central processing unit and each algorithm module, the power consumption of the PCIe encryption card algorithm chip can be made more accurate.

[0026] In one embodiment, in the low-power mode of the central processing unit and each algorithm module of the PCIe encryption card, the PCIe encryption card controls the clocks of other parts except for the parts directly driven by the external clock and the internal oscillator with a lower frequency to stop, and controls multiple analog modules to enter the stop state step by step to turn off the central processing unit and each algorithm module. Among them, the clock refers to an electronic component or circuit that generates a stable and accurate time signal. This clock plays a crucial role in the PCIe encryption card, is used to measure and control time, and ensures that the PCIe encryption card can operate according to a predetermined rule. The clock gating function can be used to control the turning on and off of each module. The oscillator is an electronic component or device that can convert DC electrical energy into AC electrical energy with a certain frequency and generate periodic signals independently. The analog module is used to represent a device that converts analog signals into digital signals, such as analog modules like VR, FLASH, EEPROM, and OSC (frequency oscillator). By replacing the original clock with a gated clock, the clock can be turned off when it is not needed, significantly reducing power consumption. In another embodiment, in the low-power mode of the central processing unit of the PCIe encryption card, the power supply of the pre-set modules that do not need to work is cut off to reduce static power consumption and dynamic power consumption.

[0027] In one embodiment, when the PCIe encryption card detects that there is no host command data transmission, control the low-power state interrupt signal to be generated only once. By controlling the power management function in the PCIe controller to generate only one L0s interrupt signal when there is no host command data transmission, it can enable the PCIe encryption chip to enter the low-power mode to save power when there is no upper host command data transmission, and avoid generating multiple low-power state interrupt signals.

[0028] Step S104, when detecting the host command data transmission, control the PCIe controller to enter the normal working state, and based on the firmware, control the PCIe controller to generate a base address register match interrupt signal or an address translation unit match interrupt signal, and send it to the central processing unit and each algorithm module, so that the central processing unit and each algorithm module exit the low-power mode.

[0029] Among them, the base address register matching interrupt signal is used to represent the signal of the matching of the interrupt base address register. The address translation unit matching interrupt signal is used to represent the signal of the matching of the interrupt address translation unit. Specifically, after the base address register matching or the address translation unit matching is successful, the host commands data to be transmitted to the PCIe encryption card, and at the same time, the firmware of the PCIe encryption card will control the PCIe controller to generate the base address register matching interrupt signal or the address translation unit matching interrupt signal. In one embodiment, when the PCIe encryption card detects the transmission of host command data, it controls the PCIe controller to resume from the low-power state to the normal working state. When the host command data is being transmitted and the base address register matching is successful, the firmware of the PCIe encryption card controls the PCIe controller to generate the base address register matching interrupt signal and send it to the central processing unit and each algorithm module to wake up the central processing unit and each algorithm module so that the central processing unit and each algorithm module can exit the low-power mode.

[0030] Optionally, after the central processing unit and each algorithm module exit the low-power mode, the PCIe encryption card performs encryption and decryption processing on the host command data based on the firmware and controls the PCIe controller to enter the low-power state again. When the central processing unit and each algorithm module of the PCIe encryption card are working, since there is no data packet transmission on the PCIe link, the PCIe controller is controlled to enter the power management function low-power state again, so that the power consumption control of the PCIe interface encryption card algorithm chip is divided into two major categories: the power consumption of the "PCIe controller" and the power consumption of the "central processing unit and each algorithm module". This makes the power consumption control of the PCIe encryption card more accurate, and with the cooperation of the host, it can meet the power consumption indicators required by the PCIe standard.

[0031] In one embodiment, when the PCIe encryption card detects the transmission of host command data, it controls the base address register interrupt signal or the address translation unit matching interrupt signal to be generated only once. By controlling the PCIe controller to generate only one BAR / ATU matching interrupt signal when there is host command data transmission, it can ensure that the PCIe link is in the normal working mode during normal data transmission and avoid generating multiple BAR / ATU matching interrupt signals.

[0032] As described above, the low-power and working modes of the PCIe encryption card are switched by alternately using the low-power state interrupt and the base address register or address translation unit matching interrupt. That is, when the power management module of the PCIe controller detects the idle state, the PCIe controller generates a low-power state interrupt signal to the central processing unit and each algorithm module of the PCIe encryption card. In the low-power state interrupt service program, the central processing unit and each algorithm module enter the low-power mode. When a host command is received on the PCIe interface, the PCIe controller generates a base address register interrupt signal or an address translation unit matching interrupt signal to the central processing unit and each algorithm module, wakes up the central processing unit and each algorithm module, exits the low-power mode, and the firmware parses and processes the encryption and decryption commands of the host command data packet. This solution solves the problem that in the existing method of using ASPM for PCIe encryption cards, the PCIe encryption card has a long working time and high power consumption, resulting in an increase in the temperature of the PCIe encryption card chip and causing unstable functions of the PCIe encryption card. By alternately using the low-power state interrupt signal and the base address register matching interrupt signal or the address translation unit matching interrupt signal to switch the low-power and working modes of the PCIe encryption card, the power consumption of the PCIe encryption card can be controlled lower, without the need to install a chip heat sink or a fan, reducing the production cost of the PCIe encryption card.

[0033] Figure 2 The flowchart of a low-power implementation method of a PCIe encryption card based on ASPM including the method for the central processing unit to enter the low-power mode provided by the embodiment of the present application is as Figure 2 shown, and specifically includes: Step S201: When the host detects that the PCIe encryption card is powered on, configure the power management function control register to start the power management function in the PCIe controller of the PCIe encryption card, and perform PCIe link training with the PCIe encryption card.

[0034] Step S202: When the PCIe link reaches the normal working state through the PCIe link training, configure the base address register and the address translation unit of the PCIe encryption card.

[0035] Step S203: The PCIe encryption card detects the host command data transmission based on the power management function in the PCIe controller. When it detects that there is no host command data transmission, it controls the PCIe controller to enter the low-power state, and based on the firmware, controls the PCIe controller to generate a low-power state interrupt signal and send it to the central processing unit and each algorithm module of the PCIe encryption card.

[0036] Step S204: In the low-power state interrupt service routine, the PCIe encryption card detects the status of the PCIe link based on the firmware. When it detects that the link is in the low-power state, it disables the low-power state interrupt, enables the base address register match interrupt or the address translation unit match interrupt, and controls the central processing unit and each algorithm module to enter the low-power mode.

[0037] Among them, the firmware is a program embedded in the PCIe encryption card, which is responsible for controlling the operation of the PCIe encryption card and providing basic functions. This firmware directly interacts with the PCIe encryption card to ensure the stability and performance of the device. Using this firmware, the status of the PCIe link can be detected. When it detects that the link is in the low-power state, it disables the low-power state interrupt. When performing the base address register match, it enables the base address register match interrupt. When performing the address translation unit match, it enables the address translation unit match interrupt, and controls the central processing unit and each algorithm module to enter the low-power mode. In one embodiment, after the central processing unit and each algorithm module enter the low-power mode, when the PCIe encryption card negotiates the status with the host based on the power management function protocol, the PCIe encryption card controls the central processing unit and each algorithm module to maintain the low-power mode unchanged. Among them, since no host command is received on the PCIe interface, the central processing unit and each algorithm module inside the PCIe encryption chip are still in the low-power mode. Therefore, the power consumption control of the central processing unit and each algorithm module is not affected by the result of the status negotiation between the PCIe encryption card and the host, reducing the working time of the central processing unit and each algorithm module, thereby reducing the overall power consumption of the PCIe interface algorithm chip. The power management function protocol is a power management mechanism of the PCIe bus, which allows PCIe devices to perform power management spontaneously by the PCIe link without the participation of system software. Exemplarily, when the sender finds that there is no data transmission on the link for a long time, it recommends that the receiver enter the L1 state (lower power state) through the power management function. If the receiver "agrees", the link enters the L1 state; if the receiver "disagrees", the link enters the L0s state.

[0038] As an exemplary example, the central processing unit and each algorithm module of the PCIe encryption card have entered the low-power mode. Currently, since there has been no data transmission on the PCIe encryption card for a long time, the PCIe encryption card negotiates the L1 state with the host. The host agrees to enter the L1 state, the PCIe link enters the L1 state, and the central processing unit and each algorithm module of the PCIe encryption card are not affected by the negotiation result and still maintain the low-power mode.

[0039] Step S205: When it is detected that the host command data is being transmitted, control the power management function in the PCIe controller to resume to the normal working state, and control the PCIe controller to generate the base address register and address translation unit matching interrupt signals and send them to the central processing unit, so that the central processing unit exits the low-power mode.

[0040] As can be seen from the above, in the low-power state interrupt service routine, the PCIe encryption card detects the status of the PCIe link based on the firmware. When it is detected that the card is in the low-power state, the low-power state interrupt is prohibited, the base address register matching interrupt or the address translation unit matching interrupt is enabled, and the central processing unit and each algorithm module are controlled to enter the low-power mode. In this solution, the power management function of the PCIe encryption card outputs the L0s state interrupt to the central processing unit and each algorithm module, which can make the power consumption of the PCIe encryption card algorithm chip more accurate.

[0041] Figure 3 The flowchart shows a method for implementing low power consumption of a PCIe encryption card based on ASPM, which includes the operation mode after the central processing unit enters the low power consumption mode. As Figure 3 shown, it specifically includes: Step S301: When the host detects that the PCIe encryption card is powered on, configure the power management function control register to start the power management function in the PCIe controller of the PCIe encryption card, and perform PCIe link training with the PCIe encryption card.

[0042] Step S302: When the PCIe link reaches the normal working state through the PCIe link training, configure the base address register and address translation unit of the PCIe encryption card.

[0043] Step S303: The PCIe encryption card detects the host command data transmission based on the power management function in the PCIe controller. When it is detected that there is no host command data transmission, control the PCIe controller to enter the low-power state, and control the PCIe controller to generate a low-power state interrupt signal based on the firmware and send it to the central processing unit and each algorithm module of the PCIe encryption card, so that the central processing unit and each algorithm module enter the low-power mode.

[0044] Step S304: When it is detected that the host command data is being transmitted, control the PCIe controller to enter the normal working state, and based on the firmware, control the PCIe controller to generate a base address register match interrupt signal or an address translation unit match interrupt signal and send it to the central processing unit and each algorithm module, so that the central processing unit and each algorithm module exit the low-power mode.

[0045] Step S305: The PCIe encryption card encrypts and decrypts the host command data based on the firmware, and controls the PCIe controller to enter the low-power state again.

[0046] Among them, when the central processing unit and each algorithm module of the PCIe encryption card are working, since there is no data packet transmission on the PCIe link at this time, the PCIe encryption card will control the PCIe controller to enter the power management function low-power state again. In one embodiment, after the PCIe encryption card completes the encryption and decryption processing of the host command data, the PCIe encryption card sends a message flag interrupt signal to the host based on the firmware, so that the PCIe controller enters the normal working state. Among them, the message flag interrupt signal (MSI interrupt signal) is a modern interrupt mechanism that notifies the processor that the device needs service through message passing rather than the traditional hardware pin interrupt. Using this message flag interrupt signal can force the PCIe controller at the PCIe encryption card end to exit the low-power state and enter the normal working state, so that the PCIe encryption card can interact with the host normally and prepare for the central processing unit and each algorithm module to enter the low-power mode next time. An exemplary example can be that the PCIe encryption card has currently completed the encryption and decryption processing of the host command data, the PCIe encryption card sends a message flag interrupt signal to the host based on the firmware, the PCIe link returns to the normal working state, and the central processing unit and each algorithm module of the PCIe encryption card wait to enter the low-power mode next time.

[0047] As can be seen from the above, after the central processing unit exits the low-power mode, the PCIe encryption card encrypts and decrypts the host command data based on the firmware, and controls the PCIe controller to enter the low-power state again. In this solution, when the central processing unit and each algorithm module of the PCIe encryption card are working, due to no data packet transmission, the PCIe controller is controlled to enter the power management function low-power state again, so that the power consumption control of the PCIe interface encryption card algorithm chip is divided into two categories: the power consumption of the "PCIe controller" and the power consumption of the "central processing unit and each algorithm module". This makes the power consumption control of the PCIe encryption card more accurate, and with the cooperation of the host, the power consumption index required by the PCIe standard can be achieved.

[0048] Figure 4This is a block diagram of the module structure of a low-power implementation device for a PCIe encryption card based on ASPM provided by an embodiment of the present application. This system is used to execute a low-power implementation method for a PCIe encryption card based on ASPM provided by the above embodiment, and has functional modules and beneficial effects corresponding to the execution method. As Figure 4 shown, this system specifically includes: A function startup module 101, configured to configure a power management function control register to start the power management function in the PCIe controller of the PCIe encryption card when the host detects that the PCIe encryption card is powered on; A link training module 102, configured to perform PCIe link training with the PCIe encryption card; A configuration module 103, configured to configure the base address register and the address translation unit of the PCIe encryption card when the PCIe link reaches the normal working state through the PCIe link training; A status control module 104, configured to detect host command data transmission based on the power management function in the PCIe controller of the PCIe encryption card, and control the PCIe controller to enter the low-power state when it is detected that there is no host command data transmission; A mode control module 105, configured to control the PCIe controller to generate a low-power state interrupt signal based on firmware and send it to the central processing unit and the algorithm module of the PCIe encryption card, so that the central processing unit and the algorithm module enter the low-power mode; The status control module is further configured to control the PCIe controller to enter the normal working state when it is detected that there is host command data transmission; The mode control module is further configured to control the PCIe controller to generate a base address register matching interrupt signal or an address translation unit matching interrupt signal based on the firmware and send it to the central processing unit and the algorithm module, so that the central processing unit and the algorithm module exit the low-power mode.

[0049] As can be seen from the above solution, the low-power state interrupt and the base address register or address translation unit matching interrupt are alternately used to switch the low-power and working modes of the PCIe encryption card. That is, when the power management module of the PCIe controller detects an idle state, the PCIe controller generates a low-power state interrupt signal to the central processing unit and each algorithm module of the PCIe encryption card. In the low-power state interrupt service program, the central processing unit and each algorithm module enter the low-power mode. When a host command is received on the PCIe interface, the PCIe controller generates a base address register interrupt signal or an address translation unit matching interrupt signal to the central processing unit and each algorithm module, wakes up the central processing unit and each algorithm module, exits the low-power mode, and the firmware performs the parsing process of the encryption and decryption commands of the host command data packet. This solution solves the problem that in the existing method of using the ASPM PCIe encryption card, the PCIe encryption card has a long working time and high power consumption, resulting in an increase in the temperature of the PCIe encryption card chip and causing instability in the functions of the PCIe encryption card. By alternately using the low-power state interrupt signal and the base address register matching interrupt signal or the address translation unit matching interrupt signal to switch the low-power and working modes of the PCIe encryption card, the power consumption of the PCIe encryption card can be controlled lower, and there is no need to install a chip heat sink or a fan, reducing the production cost of the PCIe encryption card.

[0050] In a possible embodiment, the mode control module 105 is specifically configured to: In the low-power state interrupt service program, the PCIe encryption card detects the state of the PCIe link based on the firmware. When it is detected that the low-power state is reached, the low-power state interrupt is prohibited, the base address register matching interrupt or the address translation unit matching interrupt is enabled, and the central processing unit and each algorithm module are controlled to enter the low-power mode.

[0051] In a possible embodiment, the mode control module 105 is further configured to: When the PCIe encryption card negotiates the state with the host based on the power management function protocol, the PCIe encryption card controls the central processing unit and the algorithm module to keep the low-power mode unchanged.

[0052] In a possible embodiment, the mode control module 105 is further configured to: The PCIe encryption card controls the clocks of other parts except for the parts directly driven by the external clock and the internal lower-frequency oscillator to stop, and controls multiple analog modules to enter the stop state step by step to turn off the central processing unit and each algorithm module.

[0053] In a possible embodiment, the state control module 104 is specifically configured to: The PCIe encryption card encrypts and decrypts the host command data based on firmware, and controls the PCIe controller to enter the low-power state again.

[0054] In a possible embodiment, the state control module 104 is further configured to: The PCIe encryption card sends a message flag interrupt signal to the host based on firmware, so that the PCIe controller enters the normal working state.

[0055] In a possible embodiment, it further includes a signal generation module, specifically configured to: Control the low-power state interrupt signal to be generated only once; When the host command data transmission is detected, control the base address register interrupt signal or the address translation unit matching interrupt signal to be generated only once.

[0056] Figure 5 The figure is a schematic structural diagram of a low-power implementation device of a PCIe encryption card based on ASPM provided by an embodiment of the present application. As Figure 5 shown, the device includes a processor 201, a memory 202, an input device 203, and an output device 204; the number of processors 201 in the device can be one or more, Figure 5 Taking one processor 201 as an example; the processor 201, memory 202, input device 203, and output device 204 in the device can be connected through a bus or other means, Figure 5 Taking connection through a bus as an example. The memory 202, as a computer-readable storage medium, can be used to store software programs, computer-executable programs, and modules, such as program instructions or modules corresponding to a low-power implementation method of a PCIe encryption card based on ASPM in an embodiment of the present application. The processor 201 executes various functional applications and data processing of the device by running the software programs, instructions, and modules stored in the memory 202, that is, implements the above-mentioned low-power implementation method of the PCIe encryption card based on ASPM. The input device 203 can be used to receive input digital or character information, and generate key signal inputs related to user settings and function control of the device. The output device 204 can include a display device such as a display screen.

[0057] An embodiment of the present application further provides a storage medium containing computer-executable instructions, and the computer-executable instructions are used to execute a low-power implementation method of a PCIe encryption card based on ASPM when executed by a computer processor. The method includes: When the host detects that the PCIe encryption card is powered on, configure the power management function control register to start the power management function in the PCIe controller of the PCIe encryption card, and perform PCIe link training with the PCIe encryption card; When the PCIe link reaches the normal working state through the PCIe link training, configure the base address register and the address translation unit of the PCIe encryption card; The PCIe encryption card detects the host command data transmission based on the power management function in the PCIe controller. When it detects that there is no host command data transmission, it controls the PCIe controller to enter the low power state, and based on the firmware, controls the PCIe controller to generate a low power state interrupt signal and send it to the central processing unit and each algorithm module of the PCIe encryption card, so that the central processing unit and each algorithm module enter the low power mode; When it detects the host command data transmission, it controls the PCIe controller to enter the normal working state, and based on the firmware, controls the PCIe controller to generate a base address register interrupt signal or an address translation unit match interrupt signal, and send it to the central processing unit and each algorithm module, so that the central processing unit and each algorithm module exit the low power mode.

[0058] It should be noted that in the embodiments of the above PCIe encryption card low power implementation method system based on ASPM, the various units and modules included are only divided according to functional logic, but are not limited to the above division, as long as the corresponding functions can be achieved; in addition, the specific names of the functional units are only for the convenience of mutual distinction and do not limit the protection scope of the embodiments of the present application.

[0059] Note that the above is only the preferred embodiment of the embodiments of the present application and the applied technical principles. Those skilled in the art will understand that the embodiments of the present application are not limited to the specific embodiments described here, and various obvious changes, re-adjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the embodiments of the present application. Therefore, although the embodiments of the present application have been described in more detail through the above embodiments, the embodiments of the present application are not limited to the above embodiments only. Without departing from the concept of the embodiments of the present application, more other equivalent embodiments can be included, and the scope of the embodiments of the present application is determined by the scope of the appended claims.

Claims

1. A method for realizing low power consumption of a PCIe encryption card based on ASPM, characterized in that: The method comprises: When the host detects that the PCIe encryption card is powered on, configure the power management function control register to start the power management function in the PCIe controller of the PCIe encryption card, and perform PCIe link training with the PCIe encryption card; When the PCIe link reaches a normal working state through the PCIe link training, configuring a base address register and an address conversion unit of the PCIe encryption card; The PCIe encryption card performs host command data transmission detection based on the power management function in the PCIe controller, and controls the PCIe controller to enter a low power consumption state when detecting that the host command data transmission does not exist, and controls the PCIe controller to generate a low power consumption state interrupt signal based on firmware and sends it to the central processing unit and each algorithm module of the PCIe encryption card, so that the central processing unit and each algorithm module enter a low power consumption mode; When the host command data transmission is detected, the PCIe controller is controlled to enter the normal working state, and based on the firmware, the PCIe controller is controlled to generate a base address register interrupt signal or an address conversion unit match interrupt signal, and sent to the central processing unit and each algorithm module, so that the central processing unit and each algorithm module exit the low power consumption mode.

2. The method for realizing low power consumption of PCIe encryption card based on ASPM according to claim 1, characterized in that: The firmware-based control of the PCIe controller to generate a low power consumption state interrupt signal is sent to the central processing unit and each algorithm module of the PCIe encryption card, so that the central processing unit and each algorithm module enter a low power consumption mode, including: In the low-power state interrupt service program, the PCIe encryption card performs status detection on the PCIe link based on firmware. When detecting that the PCIe link is in the low-power state, the low-power state interrupt is disabled, the base address register match interrupt or the address conversion unit match interrupt is enabled, and the central processing unit and each algorithm module are controlled to enter the low-power mode.

3. The method for realizing low power consumption of PCIe encryption card based on ASPM according to claim 2, characterized in that: After the central processing unit and each algorithm module enter the low power consumption mode, the process includes: When the PCIe encryption card and the host perform status negotiation based on the power management function protocol, the PCIe encryption card controls the central processing unit and each algorithm module to keep the low power consumption mode unchanged.

4. The method for realizing low power consumption of a PCIe encryption card based on ASPM according to any one of claims 1 to 3, characterized in that: In the low power consumption mode, the following steps are included: The PCIe encryption card controls the clocks of other parts except for the circuits directly driven by the external clock and the internal lower frequency oscillator to stop, and controls multiple analog modules to enter the stop state step by step to shut down the central processing unit and each algorithm module.

5. The method for realizing low power consumption of a PCIe encryption card based on ASPM according to any one of claims 1 to 3, characterized in that: After the central processing unit and each algorithm module exit the low power consumption mode, the method further includes: The PCIe encryption card performs encryption and decryption processing on the host command data based on firmware, and controls the PCIe controller to enter a low power consumption state again.

6. The method for realizing low power consumption of PCIe encryption card based on ASPM according to claim 5, characterized in that: After the PCIe encryption card completes the encryption and decryption processing of the host command data, the method further includes: The PCIe encryption card sends a message flag interrupt signal to the host based on firmware, so that the PCIe controller enters the normal working state.

7. The method for realizing low power consumption of a PCIe encryption card based on ASPM according to any one of claims 1 to 3, characterized in that: In the case where the host command data transmission is detected to be absent, the method comprises: Controlling the low power consumption state interrupt signal to be generated only once; In the case where the host command data transmission is detected, the method includes: The base address register interrupt signal or the address conversion unit match interrupt signal is controlled to be generated only once.

8. A low power consumption implementation device for PCIe encryption card based on ASPM, characterized in that: include: A function startup module, used to configure a power management function control register to start the power management function in the PCIe controller of the PCIe encryption card when the host detects that the PCIe encryption card is powered on; A link training module, used for performing PCIe link training with the PCIe encryption card; A configuration module, configured to configure a base address register and an address conversion unit of the PCIe encryption card when the PCIe link reaches a normal working state through the PCIe link training; A state control module, used for the PCIe encryption card to perform host command data transmission detection based on the power management function in the PCIe controller, and control the PCIe controller to enter a low power consumption state when it is detected that there is no host command data transmission; A mode control module, used for controlling the PCIe controller to generate a low power consumption state interrupt signal based on firmware and sending it to the central processing unit and algorithm module of the PCIe encryption card, so that the central processing unit and the algorithm module enter a low power consumption mode; The state control module is further used to control the PCIe controller to enter the normal working state when the host command data transmission is detected; The mode control module is also used to control the PCIe controller to generate a base address register match interrupt signal or an address conversion unit match interrupt signal based on the firmware and send it to the central processing unit and the algorithm module, so that the central processing unit and the algorithm module exit the low power consumption mode.

9. A low-power consumption implementation device for a PCIe encryption card based on ASPM, the device comprising: one or more processors; A storage device for storing one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the low-power consumption implementation method of the ASPM-based PCIe encryption card as described in any one of claims 1-7.

10. A storage medium storing computer executable instructions, wherein the computer executable instructions are used to execute the ASPM-based PCIe encryption card low power consumption implementation method as described in any one of claims 1 to 7 when executed by a computer processor.

Images