Trench Etch Process for Photoresist Line Roughness Improvement

Abstract

The present disclosure relates to a trench etching process for improving the roughness of photoresist lines. A method for forming a semiconductor device structure is provided. The method includes forming a resist structure above a substrate. The resist structure includes an anti-reflective coating (ARC) layer and a photoresist layer above the ARC layer. The method also includes patterning the photoresist layer to form a groove therein. The method also includes performing a hydrogen plasma treatment on the patterned photoresist layer. The hydrogen plasma treatment is configured to smooth the sidewalls of the groove without etching the ARC layer. The method also includes patterning the ARC layer using the patterned photoresist layer as an etching mask.

Description

Technical Field

[0001] The present disclosure generally relates to trench etch processes for photoresist line roughness improvement. Background Art

[0002] Integrated circuits include many devices, such as transistors, diodes, capacitors, and resistors fabricated on and / or in semiconductor substrates. These devices are initially isolated from one another and subsequently interconnected together to form functional circuits at the back end of line (BEOL) process stage. As features in integrated circuits continue to shrink, the impact of interconnect structures on the performance and reliability of integrated circuits increases. Summary of the invention

[0003] According to one embodiment of the present disclosure, a method for forming a semiconductor device structure is provided, comprising: forming a resist structure above a substrate, the resist structure comprising an anti-reflective coating (ARC) layer and a photoresist layer located above the ARC layer; patterning the photoresist layer to form a groove therein; performing hydrogen plasma treatment on the patterned photoresist layer, wherein the hydrogen plasma treatment is configured to smooth the sidewalls of the groove; and patterning the ARC layer using the patterned photoresist layer as an etching mask.

[0004] According to another embodiment of the present disclosure, a method for forming a semiconductor device structure is provided, comprising: receiving a substrate; forming an interlayer dielectric (ILD) layer over the substrate; forming a hard mask layer over the ILD layer; forming a first resist structure over the substrate, the first resist structure comprising a first organic planarization layer (OPL), a first anti-reflective coating (ARC) layer over the first OPL, and a first photoresist layer over the first ARC layer; patterning the first photoresist layer to form a first pattern including a plurality of first trenches therein; performing a first hydrogen plasma treatment on the patterned first photoresist layer, wherein the first hydrogen plasma treatment is configured to smooth the sidewalls of the plurality of first trenches; transferring the first pattern into the first ARC layer and the first OPL; transferring the first pattern into the hard mask layer to form a plurality of second trenches in the hard mask layer ... forming a second resist structure over the mask layer and in the plurality of second grooves, the second resist structure comprising a second OPL, a second ARC layer located over the second OPL, and a second photoresist layer located over the second ARC layer; patterning the second photoresist layer to form a second pattern including a plurality of third grooves therein; performing a second hydrogen plasma treatment on the patterned second photoresist layer, wherein the second hydrogen plasma treatment is configured to smooth the sidewalls of the plurality of third grooves; transferring the second pattern into the second ARC layer and the second OPL; transferring the second pattern into the patterned hard mask layer to form a plurality of fourth grooves in the patterned hard mask layer, wherein each of the plurality of fourth grooves is disposed between two adjacent second grooves in the plurality of second grooves; and patterning the ILD layer using the patterned hard mask layer as an etching mask.

[0005] According to another embodiment of the present disclosure, a method for forming a semiconductor device structure is provided, comprising: receiving a substrate including a plurality of conductive structures; forming an interlayer dielectric (ILD) layer over the substrate; forming a hard mask layer over the ILD layer; forming a first resist structure over the substrate, the first resist structure comprising a first organic planarization layer (OPL), a first anti-reflective coating (ARC) layer over the first OPL, and a first photoresist layer over the first ARC layer; patterning the first photoresist layer to form a first pattern including a plurality of first trenches therein; performing a first hydrogen plasma treatment on the patterned first photoresist layer, wherein the first hydrogen plasma treatment is configured to improve a line width roughness (LWR) of the patterned first photoresist layer; transferring the first pattern into the first ARC layer and the first OPL; transferring the first pattern into the hard mask layer to form a plurality of second trenches in the hard mask layer; forming a second resist over the patterned hard mask layer and in the plurality of second trenches; The invention relates to a method for preparing an ILD layer and a second photoresist layer, wherein the second photoresist structure comprises a second OPL, a second ARC layer located above the second OPL, and a second photoresist layer located above the second ARC layer; patterning the second photoresist layer to form a second pattern including a plurality of third grooves therein; performing a second hydrogen plasma treatment on the patterned second photoresist layer, wherein the second hydrogen plasma treatment is configured to improve the line width roughness of the patterned second photoresist layer; transferring the second pattern into the second ARC layer and the second OPL; transferring the second pattern into the patterned hard mask layer to form a plurality of fourth grooves in the patterned hard mask layer, wherein each of the plurality of fourth grooves is disposed between two adjacent second grooves in the plurality of second grooves; patterning the ILD layer using the patterned hard mask layer as an etching mask to form a plurality of interconnect openings therein; and forming a plurality of interconnect structures in the plurality of interconnect openings, wherein the plurality of interconnect structures are in contact with the plurality of conductive structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not necessarily drawn to scale. Instead, the size and (one or more) spatial relationships of various features may be arbitrarily increased or reduced for clarity. In the specification and drawings, the same reference numerals represent the same features.

[0007] Figure 1 is a flow chart of a method of fabricating a semiconductor device structure according to one or more embodiments.

[0008] Figure 2-Figure 15 are cross-sectional views of semiconductor device structures during various stages of fabrication according to one or more embodiments. DETAILED DESCRIPTION

[0009] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, etc. are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be restrictive. Other components, values, operations, materials, arrangements, etc. are contemplated. For example, in the following description, forming a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0010] Additionally, spatially relative terms (e.g., "below," "beneath," "below," "above," "upper," etc.) may be used herein to facilitate describing the relationship of one element or feature illustrated in the figures relative to another element(s) or feature(s). These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0011] In the manufacture of integrated circuits, techniques such as photolithographic patterning and etching are used to form interconnect structures on semiconductor substrates. In the photolithographic process, a photoresist film is first deposited. The photoresist film is then exposed to radiation and developed in a developer (chemical solution). The developer removes portions of the photoresist film, thereby forming a resist pattern including a line pattern and / or a groove pattern. The resist pattern is used as an etching mask in a subsequent etching process to transfer the pattern to the underlying layers. The morphology of the resist pattern (e.g., the resist sidewall angle and sidewall roughness) directly affects the quality of the features formed in the integrated circuit.

[0012] The lines and / or grooves of the resist pattern are typically formed with randomly entangled edges. The edge irregularity is defined by line edge roughness (LER). The two edges of a line pattern with LER produce line width variation, called line width roughness (LWR). Large LWR is disadvantageous because the etching process replicates the roughness of the resist pattern when transferring the resist pattern to the underlying layer. As the feature size of integrated circuits continues to shrink in advanced technology nodes, larger LWR reduces the metal wire bridge window. Adjacent interconnect structures with larger LWR are susceptible to electrical shorts, which leads to device degradation or failure.

[0013] The present disclosure provides a method for reducing the LWR of a photoresist layer arranged on a substrate; and the resulting semiconductor device. The LWR of the photoresist layer is reduced by performing a hydrogen plasma treatment on the photoresist layer after the resist exposure and development process. The hydrogen radicals in the hydrogen plasma saturate the dangling bonds generated in the photoresist patterning process and reduce the line width roughness of the resist pattern. The improved resist roughness increases the bridge margin of the metal line, which increases the device reliability.

[0014] Figure 1 is a flow chart of a method 100 of forming a semiconductor device structure according to one or more embodiments. Figures 2 to 15 is a cross-sectional view of an exemplary semiconductor device structure 200 during various fabrication stages and fabricated by method 100. Figures 1 to 15 , the method 100 and the exemplary semiconductor device structure 200 are collectively described below. In some embodiments, additional operations are performed before, during, and / or after the method 100, or some of the operations described are replaced and / or eliminated. In some embodiments, additional features are added to the semiconductor device structure 200. In some embodiments, some of the features described in the semiconductor device structure 200 are replaced or eliminated. One of ordinary skill in the art will understand that although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order.

[0015] refer to Figure 1 and Figure 2 According to one or more embodiments, the method 100 includes operation 102, in which a layer group is formed over a substrate 210. In some embodiments, the layer group includes an etch stop layer 220, an interlayer dielectric (ILD) layer 230, a hard mask layer 240, and a first resist structure 250.

[0016] In some embodiments, the substrate 210 includes a semiconductor substrate (not shown separately), including a semiconductor device (e.g., a field effect transistor) therein and at least one dielectric layer (not shown separately) above the semiconductor substrate. The at least one dielectric layer embeds a plurality of conductive structures, for example, a first conductive structure 212A and a second conductive structure 212B. In some embodiments, the plurality of conductive structures (212A, 212B) include gate and source / drain contacts electrically connected to various components in the semiconductor device. In other embodiments, the plurality of conductive structures (212A, 212B) include interconnect structures to provide electrical connections to various types of semiconductor devices in the semiconductor substrate. In some embodiments, each conductive structure (212A, 212B) is a metal line providing lateral electrical connection, a metal via providing vertical electrical connection, or a combination of at least one metal line and at least one metal via.

[0017] In some embodiments, the semiconductor substrate is a bulk semiconductor substrate including silicon. Alternatively or additionally, in some embodiments, the bulk semiconductor substrate includes another basic semiconductor (e.g., germanium), a compound semiconductor (e.g., gallium arsenide, gallium, phosphide, indium phosphide, indium arsenide, and / or indium antimonide), an alloy semiconductor (e.g., SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP); or a combination thereof. In some embodiments, the semiconductor substrate includes an epitaxial layer covering the bulk semiconductor substrate. Furthermore, in some embodiments, the semiconductor substrate is a semiconductor-on-insulator (SOI) substrate including a buried oxide (BOX) layer.

[0018] At least one dielectric layer electrically insulates the plurality of conductive structures (212A, 212B) from each other. In some embodiments, at least one dielectric layer comprises silicon oxide. In some embodiments, at least one dielectric layer comprises a low-k dielectric material having a dielectric constant (k) less than 4. In some embodiments, the dielectric layer has a k value less than 3.5. In some embodiments, at least one dielectric layer has a k value less than 2.5. Suitable low-k dielectric materials include, but are not limited to, tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicate glass (e.g., borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG)), polyimide, and porous dielectric materials.

[0019] The conductive structures 212A, 212B are embedded in the dielectric layer. In some embodiments, the conductive structures 212A, 212B are made of a conductive metal, such as copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), or alloys thereof.

[0020] An etch stop layer 220 is formed over the substrate 210. The etch stop layer 220 may be a single layer or multiple layers. The etch stop layer 220 protects the substrate 210 below from being damaged by a subsequent etching process performed to etch the ILD layer 230. In addition, in some embodiments, the etch stop layer 220 also prevents metal impurities, moisture, or other gaseous impurities from diffusing into the substrate 210. In some embodiments, the etch stop layer 220 includes silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbonitride (SiCN), boron nitride (BN), silicon boron nitride (SiBN), silicon carbon boron nitride (SiCBN), combinations thereof, or other suitable materials. In some embodiments, the etch stop layer 220 is formed by CVD, PECVD, atomic layer deposition (ALD), or other suitable processes. The etch stop layer 220 has a thickness suitable for use as a stop layer to protect the substrate 210 below from damage, and the thickness varies according to the process node for manufacturing the semiconductor device structure 200.

[0021] An ILD layer 230 is formed over the etch stop layer 220. In some embodiments, the etch stop layer 220 is omitted and the ILD layer 230 is directly over the substrate 210. In some embodiments, the ILD layer 230 includes silicon oxide. In some embodiments, the ILD layer 230 includes a low-k dielectric material having a dielectric constant (k) less than 4. In some embodiments, the ILD layer 230 has a k value less than 3.5. In some embodiments, the ILD layer 230 has a k value less than 2.5. Suitable low-k dielectric materials include, but are not limited to, silicon oxide formed using tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicate glass (e.g., borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG)), and porous dielectric materials. In some embodiments, the ILD layer 230 is formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), spin coating, or other suitable deposition processes.

[0022] A hard mask layer 240 is formed over the ILD layer 230. The hard mask layer 240 is configured to provide a high etching selectivity relative to the ILD layer 230 during a subsequent etching process. In some embodiments, the hard mask layer 240 has a single-layer structure including silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the hard mask layer 240 has a multi-layer structure. In some embodiments, the hard mask layer 240 has a three-layer structure including a bottom hard mask layer 242, an intermediate hard mask layer 244 located over the bottom hard mask layer 242, and a top hard mask layer 246 located over the intermediate hard mask layer 244.

[0023] In some embodiments, the bottom hard mask layer 242 includes a dielectric oxide material (eg, silicon oxide), or a high-k dielectric oxide having a dielectric constant greater than 4.0. Exemplary high-k dielectric oxides include, but are not limited to, aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), titanium oxide (TiO 2 ) and zirconium oxide (ZrO 2 In some embodiments, the bottom hard mask layer 242 is formed by CVD, PECVD, ALD, or other suitable deposition processes. In some embodiments, the bottom hard mask layer 242 includes silicon oxide deposited by a CVD or PECVD process using tetraethyl orthosilicate (TEOS) and oxygen as precursors.

[0024] In some embodiments, the intermediate hard mask layer 244 includes a dielectric nitride, such as silicon nitride. In some embodiments, the intermediate hard mask layer 244 includes a metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). In some embodiments, the intermediate hard mask layer 244 is formed by CVD, PEDVD, ALD, or other suitable deposition processes.

[0025] In some embodiments, the top hard mask layer 246 includes a dielectric oxide or a high-k dielectric oxide as described above for the bottom hard mask layer 242. For example, in some embodiments, the top hard mask layer 246 includes silicon oxide, Al 2 O 3 , HfO 2 、ZrO 2 or other suitable high-k dielectric oxide. In some embodiments, the top hard mask layer 246 comprises the same dielectric material as the material of the bottom hard mask layer 242. In some embodiments, the top hard mask layer 246 comprises a dielectric material different from the material of the bottom hard mask. In some embodiments, the top hard mask layer 246 is formed by CVD, PECVD, ALD, or other suitable deposition processes.

[0026] A first resist structure 250 is formed over the hard mask layer 240. In some embodiments, the first resist structure 250 has a three-layer structure including a first organic planarization (OPL) 252, a first anti-reflective coating (ARC) layer 254 over the first OPL 252, and a first photoresist layer 256 over the first ARC layer 254. In some embodiments, the first OPL 252, or both the first OPL 252 and the first ARC layer 254 are omitted.

[0027] The first OPL 252 includes an organic self-planarizing material that can provide a planarized surface on which the first ARC layer 254 is formed. In some embodiments, the first OPL 252 includes spin-on carbon, diamond-like carbon, polyarylene ether, polyimide or other suitable organic planarizing materials. In some embodiments, the first OPL 252 is formed by CVD, spin coating or other suitable deposition processes. The first OPL 252 is formed to have a thickness sufficient to provide a planarized surface. In some embodiments, the thickness of the first OPL 252 is about 50nm to about 300nm. In some embodiments, if the thickness of the first OPL 252 is too small, the first OPL 252 cannot provide a planarized surface. In some embodiments, if the thickness of the first OPL 252 is too large, the production cost is increased due to unnecessary material consumption and the increased process time for patterning the first OPL 252.

[0028] A first ARC layer 254 is formed on the first OPL 252. The first ARC layer 254 reduces the reflection of light from the underlying layer during photolithography, thereby increasing the precision of the pattern formed in the first photoresist layer 256. In some embodiments, the first ARC layer 254 includes a nitrogen-free ARC (NFARC) material, for example, silicon oxide or carbon-doped silicon oxide. In some embodiments, the first ARC layer 254 is formed using CVD, PVD, ALD, spin coating, or other suitable deposition processes. The first ARC layer 254 is formed to have a thickness that provides sufficient anti-reflective properties based on the material and wavelength. In some embodiments, the thickness of the first ARC layer 254 is about 20nm to about 100nm. In some embodiments, if the thickness of the first ARC layer 254 is too small, the first ARC layer 254 cannot sufficiently reduce light reflection, and thus the precision of the pattern formed in the first photoresist layer 256 is compromised. In some embodiments, if the thickness of the first ARC layer 254 is too large, the production cost is increased due to unnecessary material consumption and increased process time for etching the first ARC layer 254.

[0029] A first photoresist layer 256 is formed on the first ARC layer 254. The first photoresist layer 256 is used to define a first pattern, which is transferred to the ILD layer 230 through the first ARC layer 254, the first OPL 252 and the hard mask layer 240. The first photoresist layer 256 includes a positive photoresist material or a negative photoresist material. In some embodiments, the first photoresist layer 256 includes an extreme ultraviolet (EUV) photoresist material. In some embodiments, the first photoresist layer 256 includes a deep ultraviolet (DUV) photoresist material. In some embodiments, the first photoresist layer 256 includes an organic or inorganic polymer having a molecular weight range of 2000 to 20000. In some embodiments, the first photoresist layer 256 is deposited by spin coating or other suitable deposition processes. In some embodiments, the thickness of the first photoresist layer 256 ranges from about 35nm to about 50nm. The thickness of the first photoresist layer 256 is greater than the thickness of the first ARC layer 254. In some embodiments, for example, if the thickness of the first photoresist layer 256 is too small, the first photoresist layer 256 will be removed during the patterning of the first ARC layer 254, which causes the pattern of the first photoresist layer 256 to be inaccurately transferred to the ILD layer 230. In some embodiments, if the thickness of the first photoresist layer 256 is too large, the production cost is increased due to unnecessary material consumption and increased process time for patterning the first photoresist layer 256.

[0030] refer to Figure 1 and Figure 3 , the method 100 proceeds to operation 104, where, according to one or more embodiments, the first photoresist layer 256 is photolithographically patterned to form a first pattern including a plurality of first trenches 260 therein. For simplicity, Figure 3 2. A single first trench 260 is shown in FIG. In some embodiments, the first pattern corresponds to a pattern of metal lines to be transferred to the ILD layer 230 during subsequent processing. The first trench 260 exposes a portion of the first ARC layer 254 under the first photoresist layer 256 that is substantially aligned with one of the plurality of conductive structures (e.g., the first conductive structure 212A).

[0031] In some embodiments, the photolithography process for patterning the first photoresist layer 256 includes exposing the first photoresist layer 256 to a pattern of radiation and developing the exposed or unexposed portions of the first photoresist layer 256 using a resist developer depending on whether a positive resist or a negative resist is used in the first photoresist layer 256. In some embodiments, the photolithography process is a DUV photolithography process, which involves radiation with a wavelength ranging from 193nm to 248nm. In some embodiments, the photolithography process is an EUV photolithography process, which involves radiation with a wavelength of about 13.5nm. The shorter wavelength of EUV radiation enables denser patterning of the first photoresist layer 256 compared to radiation with a longer wavelength. The increased pattern density reduces the critical dimensions of semiconductor devices and promotes technology node shrinkage.

[0032] However, various factors in the photolithography process (e.g., light intensity variations in the exposure process and / or chemical solutions used in the resist development process) lead to poor critical dimension control in the first photoresist layer 256, resulting in LWR along the sidewalls 262 of the first trench 260. The LWR problem becomes more severe as photolithography moves to shorter wavelengths. Larger LWRs lead to inaccurate feature transfer to underlying layers, increasing the risk of electrical shorts between adjacent metal lines, and ultimately leading to device degradation or failure and yield loss.

[0033] refer to Figure 1 and Figure 4 , the method 100 proceeds to operation 106, wherein a first hydrogen plasma treatment is performed on the first photoresist layer 256. The positively charged hydrogen atoms (H + ) saturates dangling bonds on the sidewall surface of the first trench 260, thereby smoothing the sidewall 262 of the first trench 260. As a result, the LER of the groove pattern in the first photoresist layer 256 is reduced. In some embodiments, the hydrogen plasma treatment reduces the LER of the groove pattern formed in the first photoresist layer 256 by approximately 7.5 nanometers (nm) to 7.3 nm. In some embodiments, the LER of the groove pattern in the first photoresist layer 256 is reduced by approximately 43% after the hydrogen plasma treatment. In some embodiments, the LER of the groove pattern in the first photoresist layer 256 before the hydrogen plasma treatment is 7 nm to 8 nm, and after the hydrogen plasma treatment, the LER of the groove pattern in the first photoresist layer 256 is reduced to 3.8 nm to 4.8 nm. Excessive LER and the resulting larger LEW increase the semiconductor device structure 200 ( Fig.15 ) risks of electrical short circuits between adjacent metal lines 296L.

[0034] In some embodiments, the hydrogen plasma is generated by igniting or ionizing a process gas containing hydrogen. In some embodiments, the process gas contains hydrogen and a carrier gas. In some embodiments, the carrier gas includes an inert gas, such as nitrogen, argon, helium, or a mixture thereof. The flow rate of the hydrogen is controlled so that no etching of the first ARC layer 254 occurs during the hydrogen plasma treatment. In some embodiments, the flow rate of the hydrogen is about 20 standard cubic centimeters per minute (sccm) to about 500 sccm, and the flow rate of the nitrogen is about 10 sccm to about 300 sccm. In some embodiments, the process gas also includes a fluorine-containing gas, such as fluoromethane (CH 3 F), difluoromethane (CH 2 F 2 ), or trifluoromethane (CHF 3 ). In some embodiments, the flow rate of the fluorine-containing gas is about 0 sccm to about 100 sccm. In some embodiments, the hydrogen plasma treatment is performed at a temperature of about 200° C. to about 600° C. In some embodiments, the hydrogen plasma treatment is performed at a pressure of about 5 millitorr (mT) to about 20 mT. In some embodiments, the hydrogen plasma treatment is performed with a power ranging from about 400 watts (W) to about 1000 W.

[0035] Thus, the hydrogen plasma treatment helps reduce the LWR of patterned features in the first photoresist layer 256. The improved resist LWR helps provide better critical dimension control for patterning of underlying layers in a subsequent pattern transfer process.

[0036] refer to Figure 1 and Figure 5 , the method 100 proceeds to operation 108, wherein the first pattern in the first photoresist layer 256 is transferred to the first ARC layer 254 and the first OPL 252 by an etching process. The etching process forms a groove 264 extending through the first ARC layer 254 and the first OPL 252, exposing a portion of the top hard mask layer 246. The etching process is a wet etching or a dry etching process. In some embodiments, different etching processes are used to sequentially etch the first ARC layer 254 and the first OPL 252. In some embodiments, a single etching process is used to etch the first ARC layer 254 and the first OPL 252. In some embodiments, a dry etching process is performed, for example, reactive ion etching (RIE). In some embodiments, the etchant used to etch the first ARC layer 254 and the first OPL 252 is CF 4 After the first pattern is transferred into the first ARC layer 254 and the first OPL 252, the first photoresist layer 256 is removed using a suitable process (eg, wet stripping or plasma ashing).

[0037] refer to Figure 1 and Figure 6 , the method 100 proceeds to operation 110, wherein the first pattern of the first ARC layer 254 and the first OPL 252 is transferred into the top hard mask layer 246 by an etching process. The etching process forms a trench 266 extending through the top hard mask layer 246, exposing a portion of the middle hard mask layer 244. The etching process is a wet etching or a dry etching process. In some embodiments, RIE is performed to selectively remove the material of the top hard mask layer 246 relative to the material of the middle hard mask layer 244.

[0038] refer to Figure 1 and Figure 7 , the method 100 proceeds to operation 112, where a second resist structure 270 is formed over the hard mask layer 240 and in the first trench 266. In some embodiments, the second resist structure 270 has a three-layer structure including a second OPL 272, a second ARC layer 274 over the second OPL 272, and a second photoresist layer 276 over the second ARC layer 274. In some embodiments, one or both of the second OPL 272 and the second ARC layer 274 are omitted.

[0039] The second OPL 272 includes an organic self-planarizing material that can provide a planarized surface on which the second ARC layer 274 is formed. In some embodiments, the first OPL 252 includes spin-on carbon, diamond-like carbon, polyarylene ether, polyimide or other suitable organic planarizing materials. In some embodiments, the second OPL 272 includes the same material as the material of the first OPL 252. In some embodiments, the second OPL 272 includes a material different from the material of the first OPL 252. In some embodiments, the second OPL 272 is formed by CVD, spin coating or other suitable deposition processes. The second OPL 272 is formed to have a thickness sufficient to provide a planarized surface. In some embodiments, the thickness of the second OPL 272 is about 50nm to about 300nm. In some embodiments, if the thickness of the second OPL 272 is too small, the second OPL 272 cannot provide a planarized surface. In some embodiments, if the thickness of the second OPL 272 is too large, production costs may increase due to unnecessary material consumption and increased process time for patterning the second OPL 272 .

[0040] A second ARC layer 274 is formed on the second OPL 274. The second ARC layer 274 reduces the reflection of light from the underlying layer during photolithography, thereby increasing the precision of the pattern formed in the second photoresist layer 276. In some embodiments, the second ARC layer 274 includes a NFARC material, for example, silicon oxide or carbon-doped silicon oxide. In some embodiments, the second ARC layer 274 includes the same material as the material of the first ARC layer 254. In some embodiments, the second ARC layer 274 includes a material different from the material of the first ARC layer 254. In some embodiments, the second ARC layer 274 is formed using CVD, PVD, ALD, spin coating, or other suitable deposition processes. The second ARC layer 274 is formed to have a thickness that provides sufficient anti-reflective properties based on the material and wavelength. In some embodiments, the thickness of the second ARC layer 274 is about 20nm to about 100nm. In some embodiments, if the thickness of the second ARC layer 274 is too small, the second ARC layer 274 cannot sufficiently reduce light reflection, and thus the precision of the pattern formed in the second photoresist layer 276 is compromised. In some embodiments, if the thickness of the second ARC layer 274 is too large, production costs may increase due to unnecessary material consumption and increased process time for etching the second ARC layer 274 .

[0041] A second photoresist layer 276 is formed on the second ARC layer 274. The second photoresist layer 276 is used to define a second pattern, which is transferred to the ILD layer 230 through the second ARC layer 274, the second OPL 272, and the hard mask layer 240. The second photoresist layer 276 includes a positive photoresist material or a negative photoresist material. In some embodiments, the second photoresist layer 276 includes an EUV photoresist material. In some embodiments, the second photoresist layer 276 includes a DUV photoresist material. In some embodiments, the second photoresist layer 276 includes an organic or inorganic polymer having a molecular weight range of 2000 to 20000. In some embodiments, the second photoresist layer 276 includes the same material as the first photoresist layer 256. In some embodiments, the second photoresist layer 276 includes a material different from the material of the first photoresist layer 256. In some embodiments, the second photoresist layer 276 is deposited by spin coating or other suitable deposition processes. In some embodiments, the thickness of the second photoresist layer 276 ranges from about 35 nm to about 50 nm. The thickness of the second photoresist layer 276 is greater than the thickness of the second ARC layer 274. In some embodiments, for example, if the thickness of the second photoresist layer 276 is too small, the second photoresist layer 276 will be removed during the patterning of the second ARC layer 274, which causes the pattern of the second photoresist layer 276 to be inaccurately transferred to the ILD layer 230. In some embodiments, if the thickness of the second photoresist layer 276 is too large, the production cost is increased due to unnecessary material consumption and increased process time for patterning the second photoresist layer 276.

[0042] refer to Figure 1 and Figure 8 , the method 100 proceeds to operation 114, where the second photoresist layer 276 is photolithographically patterned to form a second pattern including a plurality of second trenches 280 therein, according to one or more embodiments. For simplicity, a single second trench 280 is shown.

[0043] In some embodiments, the second pattern corresponds to another pattern of metal lines to be transferred to the ILD layer 230 during a subsequent process. The second pattern in the second photoresist layer 276 is configured to form a double patterning structure with the first pattern in the first photoresist layer 256. In some embodiments, the second pattern is formed so that one of the second trenches 280 is inserted into two adjacent first trenches 260 ( Figure 3) between (not shown). Thus, the second pattern is combined with the first pattern to form a final pattern having a pitch smaller than that allowed by a single photolithography process. The pitch corresponds to the distance between adjacent trenches in the final pattern. The second trench 280 exposes a portion of the second ARC layer 274 under the second photoresist layer 276 that is substantially aligned with one of the plurality of conductive structures (e.g., the second conductive structure 212B adjacent to the first conductive structure 212A).

[0044] In some embodiments, the photolithography process used to pattern the second photoresist layer 276 is substantially similar to the photolithography process used to pattern the first photoresist layer 256. For example, the second photoresist layer 276 is exposed to a pattern of radiation, and the exposed or unexposed portions of the second photoresist layer 276 are developed using a resist developer depending on whether a positive resist or a negative resist is used in the second photoresist layer 276. Figure 3 In the first trench 260 described in FIG. 8 , the photolithography process used to pattern the second photoresist layer 276 also results in LWR along the sidewalls 282 of the second trench 280 .

[0045] refer to Figure 1 and Fig. 9 , the method 100 proceeds to operation 116, where a second hydrogen plasma treatment is performed on the second photoresist layer 276. A process substantially similar to that described above in operation 104 in terms of process gas composition for generating hydrogen plasma and hydrogen plasma treatment conditions is performed to smooth the sidewalls 282 of the second trench 280 in the second photoresist layer 276. In some embodiments, the hydrogen plasma treatment reduces the LER of the trench pattern formed in the second photoresist layer 276 by about 7.5 nm to 4.3 nm. In some embodiments, after the hydrogen plasma treatment, the LER of the trench pattern in the second photoresist layer 276 is reduced by about 43%. In some embodiments, the LER of the trench pattern in the second photoresist layer 276 before the hydrogen plasma treatment is 7 nm to 8 nm, and after the hydrogen plasma treatment, the LER of the trench pattern in the second photoresist layer 276 is reduced to 3.8 nm to 4.8 nm. The excessive LER in the second photoresist layer 276 and the resulting large LEW increase the semiconductor device structure 200 ( Fig.15 ) risks of electrical short circuits between adjacent metal lines 296L.

[0046] In some embodiments, the conditions of the second plasma treatment are substantially the same as the conditions of the first plasma treatment for reducing the LWR of the groove pattern in the first photoresist layer 256. In some embodiments, the second plasma treatment is different from the first plasma treatment for reducing the LWR of the groove pattern in the first photoresist layer 256 in at least one parameter in terms of gas composition, flow rate, process temperature, process pressure, and power. In some embodiments, the process gas used in the second plasma treatment comprises hydrogen and a carrier gas. In some embodiments, the carrier gas comprises an inert gas, such as nitrogen, argon, helium, or a mixture thereof. The flow rate of the hydrogen is controlled so that no etching of the first ARC layer 254 occurs during the hydrogen plasma treatment. In some embodiments, the flow rate of the hydrogen is about 20 standard cubic centimeters per minute (sccm) to about 500 sccm, and the flow rate of the nitrogen is about 10 sccm to about 300 sccm. In some embodiments, the process gas further comprises a fluorine-containing gas, such as fluoromethane (CH 3 F), difluoromethane (CH 2 F 2 ), or trifluoromethane (CHF 3 In some embodiments, the flow rate of the fluorine-containing gas is about 0 sccm to about 100 sccm. In some embodiments, the hydrogen plasma treatment is performed at a temperature in the range of about 200° C. to about 600° C. In some embodiments, the hydrogen plasma treatment is performed at a pressure in the range of about 5 millitorr (mT) to about 20 mT. In some embodiments, the hydrogen plasma treatment is performed with a power in the range of about 400 watts (W) to about 1000 W.

[0047] Thus, the hydrogen plasma treatment helps reduce the LWR of patterned features in the second photoresist layer 276. The improved resist LWR helps provide better critical dimension control for patterning of underlying layers in a subsequent pattern transfer process.

[0048] refer to Figure 1 and Fig.10, the method 100 proceeds to operation 118, wherein the second pattern in the second photoresist layer 276 is transferred to the second ARC layer 274 and the second OPL 272 by an etching process. The etching process forms a groove 284 extending through the second ARC layer 274 and the second OPL 272, exposing a portion of the top hard mask layer 246. The etching process is a wet etching or a dry etching process. In some embodiments, different etching processes are used to sequentially etch the second ARC layer 274 and the second OPL 272. In some embodiments, a single etching process is used to etch the second ARC layer 274 and the second OPL 272. In some embodiments, a dry etching process is performed, for example, RIE. In some embodiments, the etchant used to etch the second ARC layer 274 and the second OPL 272 is CF 4 After the second pattern is transferred into the second ARC layer 274 and the second OPL 272, the second photoresist layer 276 is removed using a suitable process (eg, wet stripping or plasma ashing).

[0049] refer to Figure 1 and Fig.11 , the method 100 proceeds to operation 120, wherein the second pattern in the second ARC layer 274 and the second OPL 272 is transferred to the top hard mask layer 246 by an etching process. The etching process forms a trench 286 extending through the top hard mask layer 246, exposing a portion of the middle hard mask layer 244. The etching process is a wet etching or a dry etching process. In some embodiments, RIE is performed to selectively remove the material of the top hard mask layer 246 relative to the material of the middle hard mask layer 244. In some embodiments, the etchant used to etch the top hard mask layer 246 includes CF 4 , CHF 3 , CH 2 F 2 , or a combination thereof. In some embodiments, the spacing (P) between adjacent trenches 266 and 286 is about 30 nm to about 50 nm. After patterning the top hard mask layer 246, the second ARC layer 274 and the second OPL 272 are removed by, for example, a dry etching process or a wet etching process.

[0050] refer to Figure 1 and Fig.12, the method 100 proceeds to operation 122, wherein the combined pattern of the first pattern and the second pattern in the top hard mask layer 246 is transferred to the middle hard mask layer 244 and the bottom hard mask layer 242 by an etching process. The etching process forms a trench 288 extending through the middle hard mask layer 244 and the bottom hard mask layer 242, exposing a portion of the ILD layer 230 covering the conductive structures 212A and 212B. The etching process is a wet etching or a dry etching process. In some embodiments, different etching processes are used to sequentially etch the middle hard mask layer 244 and the bottom hard mask layer 242. In some embodiments, a single etching process is used to etch the middle hard mask layer 244 and the bottom hard mask layer 242. In some embodiments, a dry etching process is performed, for example, RIE. In some embodiments, the etchant used to etch the middle hard mask layer 244 and the bottom hard mask layer 242 includes CF 4 , CHF 3 , CH 2 F 2 After the etching process, the top hard mask layer 246 is removed by a dry etching or a wet etching process that selectively removes material of the top hard mask layer 246 relative to the middle hard mask layer 244 .

[0051] refer to Figure 1 and Fig.13, the method 100 proceeds to operation 124, wherein an interconnect opening 290 is formed, which extends through the ILD layer 230 and the etch stop layer 220, exposing portions of the conductive structures 212A, 212B. The interconnect openings 290 each include a trench 290T and a via opening 290V, and are formed using a dual damascene process. In some embodiments, an etching process is performed to remove a portion of the upper portion of the ILD layer 230 exposed by the trench 288 to define the trench 290T in the upper portion of the ILD layer 230. In some embodiments, the etching process is an anisotropic etch, such as RIE or plasma etching. Next, a photolithography and etching process is performed to define a via opening 290V within the corresponding trench 290T. If present, the via opening 290V extends through the ILD layer 230 and the etch stop layer 220. The photolithography process includes applying a photoresist layer (not shown) over the intermediate hard mask layer 244 to fill the trench 290T and the trench 288. The photoresist layer is then patterned by exposing the photoresist layer to a pattern of radiation and developing the photoresist layer to form a patterned photoresist layer (not shown). Once the patterned photoresist layer is formed, one or more anisotropic etching processes are performed to etch the ILD layer 230 and the etch stop layer 220 using the patterned photoresist layer as an etching mask to form via openings 290V under the corresponding trenches 290T. After the via openings 290V are formed, the patterned photoresist layer is removed, for example, by wet stripping or plasma ashing.

[0052] refer to Figure 1 and Fig.14 , the method 100 proceeds to operation 126, where a conductive liner layer 292 and a conductive material layer 294 are formed. The conductive liner layer 292 is deposited on the sidewalls and bottom of the interconnect opening 290, on the sidewalls of the trench 288, and on the top surface of the ILD layer 230. In some embodiments, the conductive liner layer 292 includes a diffusion barrier material that prevents the metal in the conductive material layer 294 from diffusing into the ILD 30. In some embodiments, the conductive liner layer 292 includes Ti, TiN, Ta, TaN, Ru, RuN, or other suitable diffusion barrier materials. In some embodiments, the conductive liner layer 292 includes a stack of the above diffusion barrier materials, for example, Ti / TiN or Ta / TaN. In some embodiments, the conductive liner layer 292 is deposited using a conformal deposition process such as CVD, PECVD, PVD, or ALD.

[0053] Subsequently, a conductive material layer 294 is deposited over the conductive liner layer 292 to fill the interconnect opening 290 and the trench 288. In some embodiments, the conductive material layer 294 includes Cu, Al, W, Co, and alloys thereof, or other suitable conductive metals. In some embodiments, the conductive material layer 294 is deposited by a suitable deposition process (e.g., CVD, PECVD, sputtering, or electroplating). The deposition process is continued until the conductive material layer 294 fills the interconnect opening 290 and the trench 288 and extends over the ILD layer 230. In some embodiments, when Cu or a Cu alloy is used for the conductive material layer 294, an optional electroplating seed layer (not shown) is formed on the conductive liner layer 293 before forming the conductive material layer 294. In some embodiments, the optional electroplating seed layer is formed by a deposition process including, for example, CVD, PECVD, ALD, and PVD.

[0054] refer to Figure 1 and Fig.15 , the method 100 proceeds to operation 128, wherein the interconnect structures 296A, 296B each include a conductive liner 292L, and a conductive material portion 294P is formed in the interconnect opening 290. In some embodiments, the interconnect structures include a first interconnect structure 296A contacting the first conductive structure 212A and a second interconnect structure 296B contacting the second conductive structure 212B. A portion of each interconnect structure 296A, 296B located in the corresponding trench 290T constitutes a metal line 296L, and another portion of each interconnect structure 296A, 296B located in the corresponding via opening 290V constitutes a via 296V.

[0055] The interconnect structures 296A, 296B are formed by removing portions of the conductive material layer 294 and the conductive liner layer 292 located above the top surface of the ILD layer 230 using a planarization process. In some embodiments, a CMP process is performed to remove the conductive material layer 294 and the conductive liner layer 292 from the top surface of the ILD layer 130. The CMP process also removes the remaining hard mask layer 240, for example, the middle hard mask layer 244 and the bottom hard mask layer 242, from the top surface of the ILD layer 230. After planarization, a portion of the conductive material layer 294 remaining in each interconnect opening 290 constitutes a conductive material portion 294P, and a portion of the conductive liner layer 292 remaining in each interconnect opening 290 constitutes a conductive liner 292L. After the planarization process, the top surface of the interconnect structures 296A, 296B is coplanar with the top surface of the ILD layer 130.

[0056] In some embodiments, the hydrogen plasma treatment helps reduce the LWR of the resist pattern before the pattern in the photoresist layer is transferred to the underlying ILD layer 230 through the hard mask layer 240. As a result, the trench 290T formed in the ILD layer 230 that replicates the profile of the resist pattern has an improved LWR. The improved LWR of the trench 290T in the interconnect opening 290 helps reduce the chance of electrical shorts between adjacent metal lines 296L subsequently formed therein. Therefore, the hydrogen plasma treatment on the patterned photoresist layer helps to expand the bridge margin of the metal line, which improves device reliability. In some embodiments, the final opening of the metal line prepared according to the method 100 has an LER roughness ranging from about 3.3 nm to about 5.3 nm.

[0057] One aspect of the present specification relates to a method for forming a semiconductor device structure. The method includes forming a resist structure above a substrate. The resist structure includes an anti-reflective coating (ARC) layer and a photoresist layer located above the ARC layer. The method also includes patterning the photoresist layer to form a groove therein. The method also includes performing a hydrogen plasma treatment on the patterned photoresist layer. The hydrogen plasma treatment is configured to smooth the sidewalls of the groove without etching the ARC layer. The method also includes using the patterned photoresist layer as an etching mask to pattern the ARC layer. In some embodiments, performing the hydrogen plasma treatment includes: using a process gas including hydrogen and a carrier gas. In some embodiments, the carrier gas includes at least one inert gas selected from a group including nitrogen, argon, and helium. In some embodiments, performing the hydrogen plasma treatment includes supplying hydrogen at a flow rate in the range of about 20 standard cubic centimeters per minute (sccm) to about 500 sccm. In some embodiments, performing the hydrogen plasma treatment includes supplying a carrier gas at a flow rate in the range of about 10 sccm to about 300 sccm. In some embodiments, the process gas further includes fluoromethane (CH 3 F), difluoromethane (CH 2 F 2 ), or trifluoromethane (CHF 3). In some embodiments, forming the resist structure further comprises: forming an organic planarization layer (OPL), wherein the ARC layer is located above the OPL; and patterning the OPL using the patterned photoresist layer as an etching mask. In some embodiments, the method further comprises: forming another resist structure above the substrate, the other resist structure comprising another anti-reflective coating (ARC) layer and another photoresist layer located above the ARC layer, patterning the other photoresist layer to form another trench therein, performing another hydrogen plasma treatment on the patterned other photoresist layer, wherein the another hydrogen plasma treatment is configured to smooth the sidewalls of the other trench without etching the other ARC layer, and patterning the other ARC layer using the patterned other photoresist layer as an etching mask.

[0058] Another aspect of the present specification relates to a method for forming a semiconductor device structure. The method includes receiving a substrate. The method also includes forming an interlayer dielectric (ILD) layer above the substrate. The method also includes forming a hard mask layer above the ILD layer. The method also includes forming a first resist structure above the substrate, the first resist structure including a first organic planarization layer (OPL), a first anti-reflective coating (ARC) layer located above the first OPL, and a first photoresist layer located above the first ARC layer. The method also includes patterning the first photoresist layer to form a first pattern including a plurality of first grooves therein. The method also includes performing a first hydrogen plasma treatment on the patterned first photoresist layer. The first hydrogen plasma treatment is configured to smooth the sidewalls of the plurality of first grooves without etching the first ARC layer. The method also includes transferring the first pattern to the first ARC layer and the first OPL. The method also includes transferring the first pattern to the hard mask layer to form a plurality of second grooves in the hard mask layer. The method also includes forming a second resist structure above the patterned hard mask layer and in a plurality of second grooves, the second resist structure including a second OPL, a second ARC layer located above the second OPL, and a second photoresist layer located above the second ARC layer. The method also includes patterning the second photoresist layer to form a second pattern including a plurality of third grooves therein. The method also includes performing a second hydrogen plasma treatment on the patterned second photoresist layer, wherein the second hydrogen plasma treatment is configured to smooth the sidewalls of the plurality of third grooves without etching the second ARC layer. The method also includes transferring the second pattern to the second ARC layer and the second OPL. The method also includes transferring the second pattern to the patterned hard mask layer to form a plurality of fourth grooves in the patterned hard mask layer. Each fourth groove in the plurality of fourth grooves is disposed between two adjacent second grooves in the plurality of second grooves. The method also includes patterning the ILD layer using the patterned hard mask layer as an etching mask. In some embodiments, performing a first hydrogen plasma treatment and performing a second hydrogen plasma treatment include: using a process gas including hydrogen and a carrier gas. In some embodiments, the carrier gas includes nitrogen, argon, helium, or a mixture thereof. In some embodiments, the first hydrogen plasma treatment and the second hydrogen plasma treatment are independently performed at a temperature in the range of about 200° C. to 600° C. In some embodiments, the first hydrogen plasma treatment and the second hydrogen plasma treatment are independently performed at a pressure in the range of about 5 millitorr (mT) to about 20mT. In some embodiments, the first hydrogen plasma treatment and the second hydrogen plasma treatment are independently performed by a power in the range of about 400W to about 1000W. In some embodiments, the spacing between a second trench in the plurality of second trenches and an adjacent fourth trench in the plurality of fourth trenches is about 30nm to about 50nm.In some embodiments, after performing the first hydrogen plasma treatment, the line width roughness of the plurality of first trenches in the first photoresist layer is 2nm to 5nm. In some embodiments, at least one of the process parameters of performing the second hydrogen plasma treatment is different from the process parameters of performing the first hydrogen plasma treatment.

[0059] Another aspect of the present specification relates to a method for forming a semiconductor device structure. The method includes receiving a substrate including a plurality of conductive structures. The method also includes forming an interlayer dielectric (ILD) layer above the substrate. The method also includes forming a hard mask layer above the ILD layer. The method also includes forming a first resist structure above the substrate, the first resist structure including a first organic planarization layer (OPL), a first anti-reflective coating (ARC) layer located above the first OPL, and a first photoresist layer located above the first ARC layer. The method also includes patterning the first photoresist layer to form a first pattern including a plurality of first grooves therein. The method also includes performing a first hydrogen plasma treatment on the patterned first photoresist layer. The first hydrogen plasma treatment is configured to improve the line width roughness (LWR) of the patterned first photoresist layer without etching the first ARC layer. The method also includes transferring the first pattern to the first ARC layer and the first OPL. The method also includes transferring the first pattern to the hard mask layer to form a plurality of second grooves in the hard mask layer. The method also includes forming a second resist structure above the patterned hard mask layer and in a plurality of second grooves, the second resist structure including a second OPL, a second ARC layer located above the second OPL, and a second photoresist layer located above the second ARC layer. The method also includes patterning the second photoresist layer to form a second pattern including a plurality of third grooves therein. The method also includes performing a second hydrogen plasma treatment on the patterned second photoresist layer. The second hydrogen plasma treatment is configured to improve the line width roughness of the patterned second photoresist layer without etching the second ARC layer. The method also includes transferring the second pattern to the second ARC layer and the second OPL. The method also includes transferring the second pattern to the patterned hard mask layer to form a plurality of fourth grooves in the patterned hard mask layer. Each fourth groove in the plurality of fourth grooves is disposed between two adjacent second grooves in the plurality of second grooves. The method also includes patterning the ILD layer using the patterned hard mask layer as an etching mask to form a plurality of interconnect openings therein. The method also includes forming a plurality of interconnect structures in the plurality of interconnect openings. The plurality of interconnect structures are in contact with the plurality of conductive structures. In some embodiments, performing the first hydrogen plasma treatment and performing the second hydrogen plasma treatment include: using a process gas including hydrogen and a carrier gas. In some embodiments, forming the hard mask layer includes: forming a bottom hard mask layer above the ILD layer, forming an intermediate hard mask layer above the bottom hard mask layer, and forming a top hard mask layer above the intermediate hard mask layer. The plurality of second trenches and the plurality of fourth trenches are formed in the top hard mask layer.

[0060] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose of the embodiments introduced herein and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

[0061] Example 1 is a method for forming a semiconductor device structure, comprising: forming a resist structure above a substrate, the resist structure comprising an anti-reflective coating (ARC) layer and a photoresist layer located above the ARC layer; patterning the photoresist layer to form a groove therein; performing hydrogen plasma treatment on the patterned photoresist layer, wherein the hydrogen plasma treatment is configured to smooth the sidewalls of the groove; and patterning the ARC layer using the patterned photoresist layer as an etching mask.

[0062] Example 2 is the method of Example 1, wherein performing the hydrogen plasma treatment includes using a process gas including hydrogen gas and a carrier gas.

[0063] Example 3 is the method of Example 2, wherein the carrier gas includes at least one inert gas selected from the group consisting of nitrogen, argon, and helium.

[0064] Example 4 is the method of Example 2, wherein performing the hydrogen plasma treatment includes supplying the hydrogen gas at a flow rate in a range of about 20 standard cubic centimeters per minute (sccm) to about 500 sccm.

[0065] Example 5 is the method of Example 2, wherein performing the hydrogen plasma treatment includes supplying the carrier gas at a flow rate in a range of about 10 sccm to about 300 sccm.

[0066] Example 6 is the method described in Example 2, wherein the process gas further includes fluoromethane (CH3F), difluoromethane (CH2F2), or trifluoromethane (CHF3).

[0067] Example 7 is the method described in Example 1, wherein forming the resist structure further includes: forming an organic planarization layer (OPL), wherein the ARC layer is located above the OPL; and patterning the OPL using the patterned photoresist layer as an etching mask.

[0068] Example 8 is the method described in Example 1, further including: forming another resist structure above the substrate, the other resist structure including another anti-reflective coating (ARC) layer and another photoresist layer located above the other ARC layer; patterning the other photoresist layer to form another groove therein; performing another hydrogen plasma treatment on the patterned other photoresist layer, wherein the other hydrogen plasma treatment is configured to smooth the sidewalls of the other groove without etching the other ARC layer; and patterning the other ARC layer using the patterned other photoresist layer as an etching mask.

[0069] Example 9 is a method for forming a semiconductor device structure, comprising: receiving a substrate; forming an interlayer dielectric (ILD) layer above the substrate; forming a hard mask layer above the ILD layer; forming a first resist structure above the substrate, the first resist structure comprising a first organic planarization layer (OPL), a first anti-reflective coating (ARC) layer located above the first OPL, and a first photoresist layer located above the first ARC layer; patterning the first photoresist layer to form a first pattern including a plurality of first grooves therein; performing a first hydrogen plasma treatment on the patterned first photoresist layer, wherein the first hydrogen plasma treatment is configured to smooth the sidewalls of the plurality of first grooves; transferring the first pattern into the first ARC layer and the first OPL; transferring the first pattern into the hard mask layer to form a plurality of second grooves in the hard mask layer; A second resist structure is formed in the plurality of second grooves, the second resist structure comprising a second OPL, a second ARC layer located above the second OPL, and a second photoresist layer located above the second ARC layer; the second photoresist layer is patterned to form a second pattern including a plurality of third grooves therein; a second hydrogen plasma treatment is performed on the patterned second photoresist layer, wherein the second hydrogen plasma treatment is configured to smooth the sidewalls of the plurality of third grooves; the second pattern is transferred to the second ARC layer and the second OPL; the second pattern is transferred to the patterned hard mask layer to form a plurality of fourth grooves in the patterned hard mask layer, wherein each of the plurality of fourth grooves is disposed between two adjacent second grooves in the plurality of second grooves; and the ILD layer is patterned using the patterned hard mask layer as an etching mask.

[0070] Example 10 is the method of Example 9, wherein performing the first hydrogen plasma treatment and performing the second hydrogen plasma treatment include using a process gas including hydrogen gas and a carrier gas.

[0071] Example 11 is the method of Example 10, wherein the carrier gas includes nitrogen, argon, helium, or a mixture thereof.

[0072] Example 12 is the method of Example 9, wherein the first hydrogen plasma treatment and the second hydrogen plasma treatment are independently performed at a temperature in a range of approximately 200° C. to 600° C.

[0073] Example 13 is the method of Example 9, wherein the first hydrogen plasma treatment and the second hydrogen plasma treatment are independently performed at a pressure in a range of about 5 millitorr (mT) to about 20 mT.

[0074] Example 14 is the method of Example 9, wherein the first hydrogen plasma treatment and the second hydrogen plasma treatment are independently performed with a power in a range of about 400 W to about 1000 W.

[0075] Example 15 is the method of Example 9, wherein a spacing between a second trench among the plurality of second trenches and an adjacent fourth trench among the plurality of fourth trenches is about 30 nm to about 50 nm.

[0076] Example 16 is the method of Example 9, wherein after performing the first hydrogen plasma treatment, the line width roughness of the plurality of first trenches in the first photoresist layer is 2 nm to 5 nm.

[0077] Example 17 is the method of Example 9, wherein at least one of the process parameters for performing the second hydrogen plasma treatment is different from the process parameters for performing the first hydrogen plasma treatment.

[0078] Example 18 is a method for forming a semiconductor device structure, comprising: receiving a substrate including a plurality of conductive structures; forming an interlayer dielectric (ILD) layer over the substrate; forming a hard mask layer over the ILD layer; forming a first resist structure over the substrate, the first resist structure comprising a first organic planarization layer (OPL), a first anti-reflective coating (ARC) layer over the first OPL, and a first photoresist layer over the first ARC layer; patterning the first photoresist layer to form a first pattern including a plurality of first grooves therein; performing a first hydrogen plasma treatment on the patterned first photoresist layer, wherein the first hydrogen plasma treatment is configured to improve a line width roughness (LWR) of the patterned first photoresist layer; transferring the first pattern into the first ARC layer and the first OPL; transferring the first pattern into the hard mask layer to form a plurality of second grooves in the hard mask layer; forming a second resist structure over the patterned hard mask layer and in the plurality of second grooves, the first pattern being transferred into the first ARC layer and the first OPL; transferring the first pattern into the hard mask layer to form a plurality of second grooves in the hard mask layer; forming a second resist structure over the patterned hard mask layer and in the plurality of second grooves, the first pattern being transferred into the first ARC layer and the first OPL; The second resist structure includes a second OPL, a second ARC layer located above the second OPL, and a second photoresist layer located above the second ARC layer; the second photoresist layer is patterned to form a second pattern including a plurality of third grooves therein; a second hydrogen plasma treatment is performed on the patterned second photoresist layer, wherein the second hydrogen plasma treatment is configured to improve the line width roughness of the patterned second photoresist layer; the second pattern is transferred to the second ARC layer and the second OPL; the second pattern is transferred to the patterned hard mask layer to form a plurality of fourth grooves in the patterned hard mask layer, wherein each of the plurality of fourth grooves is disposed between two adjacent second grooves in the plurality of second grooves; the ILD layer is patterned using the patterned hard mask layer as an etching mask to form a plurality of interconnect openings therein; and a plurality of interconnect structures are formed in the plurality of interconnect openings, wherein the plurality of interconnect structures are in contact with the plurality of conductive structures.

[0079] Example 19 is the method of Example 18, wherein performing the first hydrogen plasma treatment and performing the second hydrogen plasma treatment include: using a process gas including hydrogen gas and a carrier gas.

[0080] Example 20 is the method described in Example 18, wherein forming the hard mask layer includes: forming a bottom hard mask layer above the ILD layer; forming an intermediate hard mask layer above the bottom hard mask layer; and forming a top hard mask layer above the intermediate hard mask layer, wherein the plurality of second grooves and the plurality of fourth grooves are formed in the top hard mask layer.

Claims

1. A method for forming a semiconductor device structure, comprising: forming a resist structure over the hard mask, the resist structure comprising an anti-reflective coating (ARC) layer and a photoresist layer over the ARC layer; patterning the photoresist layer to form trenches therein; performing a hydrogen plasma treatment on the patterned photoresist layer, wherein the hydrogen plasma treatment is configured to smooth the sidewalls of the trench and the hydrogen plasma treatment is performed at a temperature in a range of 200° C. to 600° C.; patterning the hard mask using the patterned photoresist layer as an etch mask; forming another resist structure over the hard mask, the other resist structure comprising another anti-reflective coating (ARC) layer and another photoresist layer over the other ARC layer; patterning the other photoresist layer to form another trench therein; performing another hydrogen plasma treatment on the patterned another photoresist layer; and The hard mask is patterned using the patterned another photoresist layer as a second etch mask.

2. The method according to claim 1, wherein: Performing the hydrogen plasma treatment includes using a process gas including hydrogen gas and a carrier gas.

3. The method according to claim 1, wherein: Performing the hydrogen plasma treatment includes reducing a line edge roughness (LER) of the sidewall to a range of 3.8 nm to 4.8 nm.

4. The method according to claim 2, wherein: Performing the hydrogen plasma treatment includes supplying the hydrogen gas at a flow rate in a range of 20 sccm to 500 sccm.

5. The method according to claim 2, wherein: Performing the hydrogen plasma treatment includes supplying the carrier gas at a flow rate in a range of 10 sccm to 300 sccm.

6. The method according to claim 2, wherein: The process gas further includes fluoromethane (CH3F), difluoromethane (CH2F2), or trifluoromethane (CHF3).

7. The method according to claim 1, wherein: Forming the resist structure further comprises: forming an organic planarization layer OPL, wherein the ARC layer is located above the OPL; and The OPL is patterned using the patterned photoresist layer as an etching mask.

8. The method according to claim 1, wherein: The further hydrogen plasma treatment is configured to smooth sidewalls of the further trench without etching the further ARC layer.

9. A method for forming a semiconductor device structure, comprising: receiving a substrate; forming an interlayer dielectric ILD layer over the substrate; forming a hard mask layer over the ILD layer; forming a first resist structure over the substrate, the first resist structure comprising a first organic planarization layer (OPL), a first anti-reflective coating (ARC) layer over the first OPL, and a first photoresist layer over the first ARC layer; patterning the first photoresist layer to form a first pattern including a plurality of first trenches therein; performing a first hydrogen plasma treatment on the patterned first photoresist layer, wherein the first hydrogen plasma treatment is configured to smooth sidewalls of the plurality of first trenches; transferring the first pattern into the first ARC layer and the first OPL; transferring the first pattern into the hard mask layer to form a plurality of second trenches in the hard mask layer; forming a second resist structure over the patterned hard mask layer and in the plurality of second trenches, the second resist structure comprising a second OPL, a second ARC layer over the second OPL, and a second photoresist layer over the second ARC layer; patterning the second photoresist layer to form a second pattern including a plurality of third trenches therein; performing a second hydrogen plasma treatment on the patterned second photoresist layer, wherein the second hydrogen plasma treatment is configured to smooth sidewalls of the plurality of third trenches; transferring the second pattern into the second ARC layer and the second OPL; transferring the second pattern into the patterned hard mask layer to form a plurality of fourth trenches in the patterned hard mask layer, wherein each of the plurality of fourth trenches is disposed between two adjacent second trenches of the plurality of second trenches; and The ILD layer is patterned using the patterned hard mask layer as an etch mask.

10. The method according to claim 9, wherein: Performing the first hydrogen plasma treatment and performing the second hydrogen plasma treatment include using a process gas including hydrogen gas and a carrier gas.

11. The method according to claim 10, wherein: The carrier gas includes nitrogen, argon, helium, or a mixture thereof.

12. The method according to claim 9, wherein: The first hydrogen plasma treatment and the second hydrogen plasma treatment are independently performed at a temperature ranging from 200° C. to 600° C.

13. The method according to claim 9, wherein: The first hydrogen plasma treatment and the second hydrogen plasma treatment are independently performed at a pressure ranging from 5 mT to 20 mT.

14. The method according to claim 9, wherein: The first hydrogen plasma treatment and the second hydrogen plasma treatment are independently performed with power ranging from 400W to 1000W.

15. The method according to claim 9, wherein: A distance between one of the plurality of second trenches and an adjacent fourth trench of the plurality of fourth trenches is 30 nm to 50 nm.

16. The method according to claim 9, wherein: After performing the first hydrogen plasma treatment, the line width roughness of the plurality of first trenches in the first photoresist layer is 2 nm to 5 nm.

17. The method according to claim 9, wherein: At least one of the process parameters for performing the second hydrogen plasma treatment is different from the process parameters for performing the first hydrogen plasma treatment.

18. A method for forming a semiconductor device structure, comprising: receiving a substrate including a plurality of conductive structures; forming an interlayer dielectric ILD layer over the substrate; forming a hard mask layer over the ILD layer; forming a first resist structure over the substrate, the first resist structure comprising a first organic planarization layer (OPL), a first anti-reflective coating (ARC) layer over the first OPL, and a first photoresist layer over the first ARC layer; patterning the first photoresist layer to form a first pattern including a plurality of first trenches therein; performing a first hydrogen plasma treatment on the patterned first photoresist layer, wherein the first hydrogen plasma treatment is configured to improve a line width roughness LWR of the patterned first photoresist layer; transferring the first pattern into the first ARC layer and the first OPL; transferring the first pattern into the hard mask layer to form a plurality of second trenches in the hard mask layer; forming a second resist structure over the patterned hard mask layer and in the plurality of second trenches, the second resist structure comprising a second OPL, a second ARC layer over the second OPL, and a second photoresist layer over the second ARC layer; patterning the second photoresist layer to form a second pattern including a plurality of third trenches therein; performing a second hydrogen plasma treatment on the patterned second photoresist layer, wherein the second hydrogen plasma treatment is configured to improve a line width roughness of the patterned second photoresist layer; transferring the second pattern into the second ARC layer and the second OPL; transferring the second pattern into the patterned hard mask layer to form a plurality of fourth trenches in the patterned hard mask layer, wherein each of the plurality of fourth trenches is disposed between two adjacent second trenches in the plurality of second trenches; patterning the ILD layer using the patterned hard mask layer as an etch mask to form a plurality of interconnect openings therein; and A plurality of interconnect structures are formed in the plurality of interconnect openings, wherein the plurality of interconnect structures are in contact with the plurality of conductive structures.

19. The method according to claim 18, wherein: Performing the first hydrogen plasma treatment and performing the second hydrogen plasma treatment include using a process gas including hydrogen gas and a carrier gas.

20. The method according to claim 18, wherein: Forming the hard mask layer includes: forming a bottom hard mask layer over the ILD layer; forming an intermediate hard mask layer over the bottom hard mask layer; and A top hard mask layer is formed over the intermediate hard mask layer, wherein the plurality of second trenches and the plurality of fourth trenches are formed in the top hard mask layer.

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