Semiconductor package

Abstract

A semiconductor package includes a redistribution substrate having a first surface and a second surface, and an insulating member and a plurality of redistribution layers disposed at different levels in the insulating member and electrically connected together; a plurality of under bump metal (UBM) pads located in the insulating member and connected to a redistribution layer among the plurality of redistribution layers adjacent to the first surface, the plurality of UBM pads having lower surfaces exposed to the first surface of the redistribution substrate; a dummy pattern located between the UBM pads in the insulating member, a lower surface of the dummy pattern being located at a level higher than the lower surfaces of the UBM pads; and at least one semiconductor chip located on the second surface of the redistribution substrate and having a plurality of contact pads electrically connected to a redistribution layer among the plurality of redistribution substrates adjacent to the second surface.

Description

[0001] Cross-references to related applications

[0002] The entirety of Korean Patent Application No. 10-2019-0164467, entitled "Semiconductor Package and Method of Manufacturing the Same," filed on December 11, 2019, with the Korean Intellectual Property Office, is incorporated herein by reference. Technical Field

[0003] The embodiments relate to semiconductor packages and methods of manufacturing the same. Background Technology

[0004] Semiconductor packages are used to realize semiconductor chips, such as integrated circuits, in a form suitable for use in electronic products. Semiconductor packages have been developed with the goal of miniaturization, light weight, and reduced manufacturing costs. Summary of the Invention

[0005] The embodiment relates to a semiconductor package comprising: a redistribution substrate having a first surface and a second surface disposed opposite to each other, and including an insulating member and a plurality of redistribution layers disposed in the insulating member at different horizontal levels and electrically connected to each other; a plurality of under-bump metal (UBM) pads disposed in the insulating member and connected to a redistribution layer among the plurality of redistribution layers adjacent to the first surface of the redistribution substrate, the plurality of UBM pads having a lower surface exposed to the first surface of the redistribution substrate; a dummy pattern disposed in the insulating member between the plurality of under-bump metal pads, the lower surface of the dummy pattern being located at a horizontal level higher than the lower surface of the plurality of UBM pads; and at least one semiconductor chip disposed on the second surface of the redistribution substrate and having a plurality of contact pads electrically connected to a redistribution layer among the plurality of redistribution layers adjacent to the second surface of the redistribution substrate.

[0006] Embodiments also relate to a semiconductor package including a redistribution substrate having first and second surfaces disposed opposite each other and including a plurality of insulating layers and a plurality of redistribution layers respectively disposed between the plurality of insulating layers, a plurality of under bump metal (UBM) pads disposed on an adjacent insulating layer among the plurality of insulating layers adjacent to the first surface of the redistribution substrate, the plurality of UBM pads having lower surfaces exposed to the first surface of the redistribution substrate and having recessed upper surfaces, a dummy pattern disposed in the adjacent insulating layer, the dummy pattern having a lower surface located at a higher level than the lower surfaces of the plurality of UBM pads and having a protruding upper surface, and at least one semiconductor chip disposed on the second surface of the redistribution substrate and having contact pads electrically connected to redistribution layers among the plurality of redistribution layers adjacent to the second surface of the redistribution substrate.

[0007] Embodiments also relate to a semiconductor package including a redistribution substrate having first and second surfaces disposed opposite each other and including an insulating member and a plurality of redistribution layers respectively disposed at a plurality of different levels in the insulating member and electrically connected to each other, a plurality of under bump metal (UBM) pads disposed in the insulating member to be exposed to the first surface of the redistribution substrate and connected to redistribution layers among the plurality of redistribution layers adjacent to the first surface of the redistribution substrate, a first dummy pattern spaced apart from the first surface of the redistribution substrate and disposed between the plurality of UBM pads, the first dummy pattern having a thickness smaller than a thickness of each of the plurality of UBM pads, and at least one semiconductor chip disposed on the second surface of the redistribution substrate, the at least one semiconductor chip having a plurality of contact pads electrically connected to redistribution layers among the plurality of redistribution layers adjacent to the second surface of the redistribution substrate.

[0008] Embodiments also relate to a method of manufacturing a semiconductor package, the method including: manufacturing a redistribution substrate; and disposing a semiconductor chip on the redistribution substrate. Manufacturing the redistribution substrate can include: forming a first insulating film having a plurality of first openings; and forming a first photoresist film having openings respectively overlapping the plurality of first openings on the first insulating film; forming a first metal pattern in the plurality of first openings, respectively; removing the first photoresist film, and forming a second photoresist film having a plurality of second openings and a third opening disposed between the second openings on the first insulating film, the first metal pattern being open through the plurality of second openings; forming a second metal pattern in the plurality of second openings and the third opening, respectively; and removing the second photoresist film, and forming a second insulating film on the first insulating film to cover the second metal pattern. The first metal pattern in the plurality of first openings and the second metal pattern in the plurality of second openings can be disposed as a plurality of under bump metal (UBM) pads, and the second metal pattern in the third opening is disposed as a dummy pattern.

[0009] Embodiments also relate to a method of manufacturing a semiconductor package, the method including: manufacturing a redistribution substrate; and disposing a semiconductor chip on the redistribution substrate. The manufacturing redistribution substrate can include: forming a first insulating film having a plurality of first openings; and forming a photoresist film having a plurality of second openings respectively overlapping the plurality of first openings and openings for a dummy pattern disposed between the second openings on the first insulating film, the plurality of overlapping first and second openings providing a plurality of openings for under bump metal (UBM) pads, respectively; forming a plurality of UBM pads and a dummy pattern in the openings for the plurality of UBM and the openings for the dummy pattern, respectively; removing the photoresist film, and forming a second insulating film on the first insulating film to cover the plurality of UBM pads and the dummy pattern. BRIEF DESCRIPTION OF DRAWINGS

[0010] The example embodiments will become more fully understood from the detailed description and the accompanying drawings, wherein:

[0011] Figure 1 is a cross-sectional view illustrating a semiconductor package according to an example embodiment;

[0012] Figure 2 is a cross-sectional view illustrating a semiconductor package according to an example embodiment; Figure 1 is a plan view of the semiconductor package illustrated;

[0013] Figure 3 is a cross-sectional view illustrating a semiconductor package according to an example embodiment; Figure 1 is an enlarged cross-sectional view of a portion "A1" of the semiconductor package illustrated; and

[0014] Figure 4 is a plan view of the connection pads at the level of the horizontal height of the line II1-II1' of the portion "A1" of the semiconductor package shown in FIG. 1; Figure 3

[0015] Figure 5 is a plan view of the connection pads of the line II2-II2' of the portion "A1" of the semiconductor package shown in FIG. 1; Figure 3

[0016] Figure 6 is a schematic diagram for explaining the cause of the undulation and the improvement method;

[0017] Figure 7 is a graph comparing the thickness variation (undulation) of the thickness of the covering insulating layer according to the pattern and the distance;

[0018] Figures 8A-8G are cross-sectional views of stages in a method of manufacturing a redistribution substrate according to an example embodiment;

[0019] Figures 9A-9C are cross-sectional views of stages in a method of manufacturing a semiconductor package according to an example embodiment;

[0020] Figures 10A-10D are cross-sectional views of stages in a method of manufacturing a redistribution substrate according to an example embodiment;

[0021] Figure 11 is a cross-sectional view showing a semiconductor package according to an example embodiment;

[0022] Figure 12 is a cross-sectional view showing a semiconductor package according to an example embodiment;

[0023] Figure 13 is a plan view of the semiconductor package shown in FIG. 1; Figure 12

[0024] is an enlarged cross-sectional view of the portion "A2" of the semiconductor package shown in FIG. 1; and Figure 14 Figure 12

[0025] Figure 15 is a block diagram showing a configuration of a semiconductor package according to an example embodiment. DETAILED DESCRIPTION

[0026] Figure 1 is a cross-sectional view showing a semiconductor package according to an example embodiment, and Figure 2 is a plan view of the semiconductor package shown in FIG. 1 taken along the line I-I'; Figure 1

[0027] Referring to​​​​​Figure 1 and Figure 2 The semiconductor package 100 according to the present example embodiment includes a redistribution substrate 130 having a first surface 130A and a second surface 130B opposite to each other, an under-bump metallurgy (UBM) pad disposed on the first surface 130A of the redistribution substrate 130, and a semiconductor chip 150 disposed on the second surface 130B of the redistribution substrate 130.

[0028] The semiconductor chip 150 can include a semiconductor substrate having an active surface on which various individual elements are formed and an inactive surface opposite to the active surface. The semiconductor substrate can include a single-element semiconductor formed of a material such as silicon (Si) or germanium (Ge), or a compound semiconductor formed of a material such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). In an example embodiment, the semiconductor substrate can have a silicon-on-insulator (SOI) structure. For example, the semiconductor substrate constituting the semiconductor chip 150 can include a buried oxide (BOX) layer. The various individual elements can include, for example, metal oxide semiconductor field effect transistors (MOSFETs) such as complementary metal oxide semiconductor (CMOS) transistors and / or image sensors such as system large-scale integrated circuits (LSIs) or CMOS image sensors (CISs).

[0029] The semiconductor chip 150 can include a plurality of contact pads 150P electrically connected to the individual elements and disposed on the active surface. The semiconductor chip 150 can be a memory chip or a logic chip. For example, the memory chip can be a volatile memory chip such as a dynamic random access memory (DRAM) (e.g., high bandwidth memory (HBM)) or a static random access memory (SRAM) or a phase change random access memory (PRAM), or a non-volatile memory chip such as a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), or a resistive random access memory (RRAM). In addition, the logic chip can be, for example, a microprocessor, an analog device, or a digital signal processor.

[0030] As Figure 1As shown, the redistribution substrate 130 includes the insulating member 110 and the redistribution structures 120 disposed at different horizontal levels in the insulating member 110. The insulating member 110 includes a plurality of insulating layers 111, 112, 113, and 114, and the redistribution structures 120 include a plurality of redistribution layers 121, 122, and 123 disposed at interfaces of the plurality of insulating layers 111, 112, 113, and 114, respectively. The redistribution substrate 130 can be used as an interposer for packaging a semiconductor chip 150 to be mounted on a main board.

[0031] Interfaces of the plurality of insulating layers 111, 112, 113, 114 define formation positions of the redistribution layers 121, 122, and 123, but in a final structure according to an example embodiment (e.g., when the plurality of insulating layers 111, 112, 113, and 114 are formed of the same material), the interfaces of the insulating layers 111, 112, 113, and 114 can not be directly observed visually. Some of the plurality of redistribution layers 121, 122, and 123 can include redistribution vias 121V, 122V, and 123V connecting the redistribution layers 121, 122, and 123 disposed at adjacent horizontal levels. According to a formation direction, lower widths of the redistribution vias 121V, 122V, and 123V are smaller than upper widths. For example, the redistribution vias 121V, 122V, and 123V can have a shape that narrows in a direction from the second surface 130B toward the first surface 130A.

[0032] The plurality of insulating layers 111, 112, 113, and 114 can include a resin such as an epoxy resin or a polyimide. In an example embodiment, the plurality of insulating layers 111, 112, 113, and 114 can be formed of a photoimageable insulating material (PID). The plurality of redistribution layers 121, 122, and 123 can include, for example, copper, nickel, stainless steel, or beryllium copper or other copper alloys.

[0033] The semiconductor chip 150 disposed on the second surface 130B of the redistribution substrate 130 can have a plurality of contact pads 150P electrically connected to the redistribution layer 123 among the plurality of redistribution layers 121, 122, and 123 adjacent to the second surface 130B. The redistribution substrate 130 can include a plurality of bond pads 125 connected to the redistribution layer 123 and disposed on the second surface 130B. The plurality of bond pads 125 can each have a via portion 125V passing through a portion of the insulating member 110, i.e., the insulating layer 114, and connected to the redistribution layer 123 adjacent to the second surface 130B. Similar to the redistribution vias 121V, 122V, 123V, the lower end width of the via portion 125V of the bond pad 125 can be smaller than the upper end width. For example, the via portion 125V can have a shape that narrows in a direction from the second surface 130B toward the first surface 130A. Similar to the redistribution layers 121, 122, and 123, the bond pad 125 can include, for example, copper, nickel, stainless steel, or beryllium copper or other copper alloys.

[0034] The semiconductor chip 150 can be mounted on the second surface 130B of the redistribution substrate 130. The contact pads 150P of the semiconductor chip 150 can be respectively connected to the bond pads 125 using connection bumps SB such as solder, respectively. The semiconductor chip 150 can be electrically connected to the redistribution structure 120. The semiconductor package 100 can further include an underfill resin 161 disposed between the active surface of the semiconductor chip 150 and the second surface 130B of the redistribution substrate 130. The underfill resin 161 can be formed to surround the side surfaces of the connection bumps SB. The underfill resin 161 can include, for example, an epoxy resin.

[0035] The upper surface 150T of the semiconductor chip 150 can be exposed through the upper surface of the molding portion 165, and heat can be easily released through the exposed upper surface of the semiconductor chip 150. The upper surface 150T of the semiconductor chip 150 can be obtained by polishing the upper surface of the molding portion 165. The upper surface 150T of the semiconductor chip 150 can have a surface coplanar with the upper surface of the molding portion 165 and be substantially flat. The molding portion 165 can be made of, for example, a hydrocarbon ring compound containing a filler. The filler can be, for example, SiO2 filler. In an example embodiment, the molding portion 165 can be formed of an Ajinomoto Build-up Film (ABF).

[0036] The UBM pads 140 can be disposed on the insulating layer 111 that is the lowermost portion of the insulating member 110, and can be connected to the redistribution layer 121 adjacent to the first surface 130A among the plurality of redistribution layers 121, 122, and 123. At least one surface (e.g., a lower surface) of the UBM pads 140 can be exposed to the first surface 130A of the redistribution substrate 130. The external connection conductors 180 can be disposed on the exposed lower surfaces, respectively. The external connection conductors 180 can be attached on the UBM layer of the redistribution substrate 130. The external connection conductors 180 can be, for example, solder balls or bumps. The external connection conductors 180 can electrically connect the semiconductor package 100 to an external device (e.g., a motherboard).

[0037] In the present example embodiment, the dummy pattern 145 can be disposed between the UBM pads 140 in the insulating member 110 (e.g., in the lowermost insulating layer 111). A lower surface of the dummy pattern 145 can be disposed at a higher level than a lower surface of the UBM pads 140. The dummy pattern 145 can be disposed in the insulating member 110 (e.g., the lowermost insulating layer 111) without being exposed to the outside of the insulating member 110.

[0038] Referring to Figure 3 The arrangement of the UBM pads and the dummy pattern employed in the present example embodiment will be described in detail.

[0039] Figure 3 is Figure 1 is an enlarged sectional view of a portion "A1" of the semiconductor package shown in Figure 4 and Figure 5 are plan views of the semiconductor package shown in Figure 3 is an enlarged sectional view of a portion "A1" of the semiconductor package shown in Figure 4 and Figure 5 in FIGS. Figure 2 correspond to the region of "B" in the entire plane of the semiconductor package 100 shown in

[0040] Referring to Figure 3 and Figure 4 The dummy pattern 145 can be disposed between the UBM pads 140 to relieve the undulation of the redistribution layer 121 formed in a subsequent process. The dummy pattern 145 employed in the present example embodiment can be disposed in the lowermost insulating layer 111 on which the UBM pads 140 are disposed.

[0041] The undulation refers to as Figure 6The height of the upper surface of the cover insulating layer I formed on the conductor pattern P on the substrate S varies, i.e., the thickness of the cover insulating layer I varies (Δt). When the thickness variation (Δt) is large, it can cause a failure (e.g., short circuit) of a redistribution layer (not shown) to be formed on the cover insulating layer.

[0042] The undulation can occur during a curing shrinkage process of the insulating layer I. Thus, as the shrinkage rate increases, the undulation can become more severe. When the same material is used (under the condition that the shrinkage rate of the material is the same), the shrinkage rate can be determined by the volume of the cover insulating layer I, and specifically, the shrinkage rate can be determined by the width Ws between the patterns P and the thickness of the patterns P.

[0043] Figure 7 is a graph comparing the thickness variation (undulation) of the cover insulating layer as the thickness of the pattern and the distance vary.

[0044] Referring to Figure 7 , the thickness deviation Δt decreases as the thickness (tp) of the pattern P decreases and as the width (Ws) between the patterns P decreases. For example, the thickness tc of the redistribution layer 121 can be about 5 μm or less (e.g., about 2 μm to about 4 μm), while the thickness (ta) of the UBM pad 140 is about 8 μm or more. Thus, since the UBM pad 140 is not only disposed in the lowermost portion but also has a relatively large thickness (ta), the UBM pad 140 is a major cause of the undulation.

[0045] Meanwhile, since the UBM pad 140 should be in contact with an external connection conductor 180 for connecting an external circuit (e.g., a motherboard), the UBM pad 140 can be disposed at a sufficient distance D. For example, the distance D of the UBM pad 140 can be at least about 50 μm, and in some example embodiments, the distance D of the UBM pad 140 can be at least about 100 μm.

[0046] Referring to Figure 3 , for example, when the distance D between the UBM pads 140 is about 50 μm or more and the thickness of the lowermost insulating layer 111 is about 11 μm, a severe undulation of about 3 μm or more can occur. To prevent this, a dummy pattern 145 is disposed between the UBM pads 140.

[0047] According to the width W of the dummy pattern 145, the thickness of the insulating layer 111 is maintained between the patterns (e.g., the UBM pad 140 and the dummy pattern 145), but the distance d can be greatly reduced. In this way, even if the thickness of the lowermost insulating layer 111 is large (e.g., about 11 μm), the distance d between the UBM pad 140 and the dummy pattern 145 is reduced, thereby enabling a significant reduction in the undulation. For example, referring to Figure 3By reducing the distance d between the UBM pad 140 and the dummy pattern 145 to about 30 μm or less, a reduced bump effect can be expected. In particular, when the distance d is about 20 μm or less, the thickness deviation Δt due to the bump can be reduced to less than 2 μm.

[0048] In addition, the dummy pattern 145 can be provided in the lowermost insulating layer 111 so as not to be exposed to the first surface 130A of the redistribution substrate 130. Thus, the lowermost insulating layer 111 associated with the UBM pad 140 can be formed by being divided into a first insulating film 111a and a second insulating film 111b. The first insulating film 111a prevents the dummy pattern 145 from being exposed to the outside, and the thickness (to) of the first insulating film 111a is sufficient to ensure stable insulation. For example, the thickness to of the first insulating film 111a can be about 2 μm or more. The thickness to can define a level difference between a bottom surface of the UBM pad 140 and a bottom surface of the dummy pattern 145.

[0049] In the present example embodiment, the UBM pad 140 and the dummy pattern 145 can each have a substantially flat upper surface. The thickness (tb) of the dummy pattern 145 can almost correspond to the thickness (ta - to), that is, the thickness (ta) of the UBM pad 140 excluding or subtracting the thickness (to) of the first insulating film 111a. Such a structure can be formed by a process according to an example embodiment set forth below in conjunction with Figures 8A-8G a process according to another example embodiment set forth below in conjunction with Figures 10A-10D as compared.

[0050] The UBM pad employed in the present example embodiment includes a planar conductive pattern, and can be connected through a redistribution via 121V of the redistribution layer 121 that penetrates the lowermost insulating layer 111 (e.g., the second insulating film 111b).

[0051] In the present example embodiment, the redistribution layer 121 (i.e., the redistribution layer 121 directly connected to the plurality of UBM pads) of the plurality of redistribution layers 121, 122, and 123 closest to the first surface 130A can be provided as connection pads having the same shape as the plurality of UBM pads 140 to respectively correspond to the plurality of UBM pads 140, as Figure 5 shown. In addition, additional dummy patterns 121D can be provided between the connection pads, and the additional dummy patterns 121D can also have substantially the same shape and area as the dummy patterns provided between the UBM pads 140. In another example embodiment, the redistribution layer 121 closest to the first surface 130A can be part of a general redistribution structure such as a line pattern, rather than a connection pad.

[0052] Figures 8A-8G These are cross-sectional views of various stages in a method for manufacturing a redistributed substrate according to an example embodiment.

[0053] This example embodiment can be used for manufacturing. Figure 1 The redistributed substrate of the semiconductor package, and can be understood as Figure 1 The “A1” part (i.e., corresponding to) Figure 3 (Part of the process diagram).

[0054] Reference Figure 8A It can form a first insulating film with multiple first openings.

[0055] A carrier 210 can be provided as a substrate for establishing the redistribution structure. A first insulating film 111a can be formed on the carrier 210, and a plurality of first openings O1 for UBM pads (e.g., the lower region of the UBM pad) can be formed in the first insulating film 111a. In this example embodiment, the formation process of the UBM pad can use a two-layer plating process. The first openings O1 of the first insulating film 111a can define the lower region of the UBM pad, and the thickness (t0) of the first insulating film 111a can be formed to be less than the desired thickness of the UBM pad. Figure 3 The first insulating film 111a may include a resin such as epoxy resin or polyimide. For example, the first insulating film 111a may include a photosensitive insulating material PID. When PID is used as the first insulating film 111a, a first opening O1 can be formed using a photolithography process.

[0056] Reference Figure 8B A first photoresist film PR1 can be formed on the first insulating film 111a, having openings O2' that overlap with a plurality of first openings O1 respectively.

[0057] Before forming the first photoresist film PR1, a first seed layer S1 for the plating process can be formed on the upper surface of the first insulating film 111a and on the surface exposed to the first opening O1. For example, the first seed layer S1 may include a Ti / Cu layer. In the first photoresist film PR1, an overlapping opening O2' for the first plating area used for the UBM pad can be formed by using a photolithography process. The overlapping opening O2' can be arranged to overlap with the first opening O1.

[0058] Reference Figure 8C The first metal pattern 140a can be formed in multiple first openings O1 respectively.

[0059] The first metal pattern 140a (also referred to as a "lower region of a UBM pad") can be formed by a plating process using the first photoresist film PR1 and the first seed layer S1. The first metal pattern 140a can include, for example, copper. The present plating process can be a primary plating process for a UBM pad. In the present plating process, at least a portion of the plurality of first openings O1 can be filled with the first metal pattern 140a, and at least a portion of the overlapping opening O2' can not be filled. The present plating process can be performed by, for example, dip plating, electroless plating, or electroplating.

[0060] Referring to Figure 8D After the first photoresist film PR1 is removed, a second photoresist film PR2 having a plurality of second openings O2 (openings for exposing the plurality of first metal patterns 140a) and a third opening O3 located between the second openings O2 can be formed on the first insulating film 111a.

[0061] The second photoresist film PR2 can be formed on the first insulating film 111a on which the plurality of first metal patterns 140a are formed and from which the first photoresist film PR1 is removed. A plurality of second openings O2 (opening the plurality of first metal patterns 140a, respectively) and a third opening O3 located between the plurality of second openings O2 can be formed in the second photoresist film PR2 using a photolithography process. The second openings O2 can have a size corresponding to the first openings O1. The third opening O3 can define a region for forming a dummy pattern (145) and some regions of the first seed layer S1 disposed on the first insulating film 111a can be opened by the third opening O3. Figure 3

[0062] Referring to Figure 8E The second metal pattern 140b and 145 can be formed in the plurality of second openings O2 and the third opening O3, respectively.

[0063] The second metal pattern 140b and 145 can be formed by a plating process using the second photoresist film PR2. In the present plating process, not only the region of the seed layer S1 exposed by the third opening O3 can serve as a seed, but also the previously formed first metal pattern 140a can serve as a seed. The present plating process can be a secondary plating process for forming an upper region of a UBM pad (corresponding to "140b" among the second metal patterns). In the present secondary plating process, a dummy pattern (corresponding to 145 among the second metal patterns) can be formed in the third opening O3. Similar to the primary plating process, the present plating process can be performed by, for example, dip plating, electroless plating, or electroplating.

[0064] Referring to Figure 8F ​The second photoresist film PR2 can be removed, and a second insulating film 111b can be formed on the first insulating film 111a to cover the second metal patterns 140b and 145.

[0065] The second insulating film 111b can be disposed as a lowermost insulating layer 111 in relation to the UBM pads 140 together with the first insulating film 111a. For example, the second insulating film 111b can be a PID material similar to the first insulating film 111a. The first metal patterns 140a in the plurality of first openings Ol and the second metal patterns 140b in the plurality of second openings 02 can be disposed as the plurality of UBM pads 140, and the second metal pattern 145 in the third opening 03 can be disposed as the dummy pattern 145.

[0066] Referring to Figure 8G A redistribution layer 121 connected to the UBM pads 140 can be formed on the second insulating film 111b.

[0067] When the second insulating film 111b is a PID, a redistribution layer 121 connected to the UBM pads 140 can be formed using a photolithography process and a plating process. For example, a hole connected to the UBM pads 140 can be formed by a photolithography process, a redistribution via 121V can be formed in the hole using a plating process, and a redistribution layer 121 connected to the redistribution via 121V can be formed on the second insulating film 111b.

[0068] When the second insulating film 111b is not a PID, a process of forming a hole in the second insulating film 111b can be performed by a laser drilling method using, for example, a UV laser or an excimer laser.

[0069] As Figure 8G indicated, a second seed layer S2 for a plating process can be retained in the redistribution layer 121 along a surface in contact with the second insulating film 111b. In the present example embodiment, the first seed layer S1 can not be disposed on a surface of the upper region 140b of the UBM pads 140, but can be disposed only on a surface of the lower region 140a of the UBM pads 140. Accordingly, the first seed layer S1 for the UBM pads 140 according to the present example embodiment can be disposed between the plurality of UBM pads 140 and the first insulating film 111a, but the first seed layer S1 can not exist between the plurality of UBM pads 140 and the second insulating film 111b.

[0070] In addition, a portion of the first seed layer S1 for the dummy pattern 145 can be disposed between the dummy pattern 145 and the first insulating film 111a, but can not exist between the dummy pattern 145 and the second insulating film 111b.

[0071] The insulating layers 112, 113, and 114 and the redistribution layers 122, 123, and 125 can be formed by repeating the formation processes of the insulating layers 112, 113, and 114 and the redistribution layers 122, 123, and 125 as described above. Figure 9A The redistribution substrate 130 shown in FIG. 1A can be manufactured by the process shown in FIG. 1B.

[0072] In the process shown in FIG. 1B, the first photoresist film PR1 and the second photoresist film PR2 used in each plating process are shown as using a negative photoresist. Thus, the first photoresist film PR1 can be cured at the time of exposure, and the first photoresist film PR1 can be peeled off and removed after the first plating process (see Figure 8G ) to perform the additional plating process (see Figure 8C ). Then, the second photoresist film PR2 can be formed. In another example embodiment, when a positive photoresist is used as the first photoresist film PR1, only the exposed portion is developed, so that the first photoresist PR1 can not be peeled off, and the exposure / development process can be applied to the first photoresist PR1 to directly form the third opening (O3) of the redistribution layer 123. Figure 8E Figure 8D

[0073] Figures 9A-9C are cross-sectional views of each stage in a method of manufacturing a semiconductor package according to an example embodiment.

[0074] Figures 9A-9C The redistribution substrate 130 shown in FIG. 1A can be manufactured by the process shown in FIG. 1B. Figures 8A-8G The redistribution substrate shown in FIG. 1A can be manufactured by the process shown in FIG. 1B.

[0075] A plurality of bonding pads 125 connected to the redistribution layer 123 can be formed on the second surface of the redistribution substrate 130. Thereby, the semiconductor chip 150 can be electrically connected to the redistribution structure 120. The formation process of the bonding pads 125 can also be similar to the formation process of the redistribution layer. The bonding pads 125 can be connected to the redistribution layer 123 adjacent to the second surface 130B through via portions 125V penetrating the uppermost insulating layer 114.

[0076] Next, referring to Figure 9B , the semiconductor chip 150 can be mounted on the second surface 130B of the redistribution substrate 130.

[0077] In the present process, the contact pads 150P of the semiconductor chip 150 can be connected to the bonding pads 125 arranged on the second surface 130B of the redistribution substrate 130 through the connection bumps SB. The underfill resin 161 can be filled between the semiconductor chip 150 and the redistribution substrate 130. The underfill resin 161 can be formed to surround the side surfaces of the connection bumps SB. The underfill resin 161 can include, for example, an epoxy resin.

[0078] Next, referring to​​Figure 9C A molding portion 165 that protects the semiconductor chip 150 can be formed, and a polishing process can be used to expose the upper surface of the semiconductor chip 150 from the upper surface of the molding portion 165.

[0079] For example, the molding portion 165 can be formed to cover the semiconductor chip 150 disposed on the redistribution substrate 130, and the upper surface of the molding portion 165 can be polished to expose the upper surface of the semiconductor chip 150 (dotted lines represent portions removed by the polishing process). Through the polishing process, the upper surface 150T of the semiconductor chip 150 can be exposed to improve heat dissipation and reduce the thickness of the semiconductor package. The upper surface of the semiconductor chip 150 can have a flat surface that is substantially coplanar with the upper surface of the molding portion 165. The molding portion 165 can include, for example, ABF.

[0080] Figures 8A-8G The illustrated manufacturing method of the redistribution substrate can include a forming process of the UBM pads using a two-time plating process, but the UBM pads can be formed together with the dummy pattern in a single-time plating process.

[0081] Figures 10A-10D are cross-sectional views of stages in a method of manufacturing a redistribution substrate according to an example embodiment.

[0082] Referring to Figure 10A A first insulating film 111a having a plurality of first openings O1 can be formed. A photoresist film PR having a plurality of second openings O2 respectively overlapping the plurality of first openings O1 and dummy pattern openings Od disposed between the plurality of second openings O2 can be formed on the first insulating film 111a.

[0083] The plurality of overlapping first openings O1 and second openings O2 can respectively provide a plurality of UBM openings Op. Unlike the first photoresist film (PR1) of the above-described example embodiment, the photoresist film PR employed in the present example embodiment forms openings Od for the dummy pattern together with the second openings O2 before applying a plating process (i.e., a first plating process). Figure 8B

[0084] The depth h1 of the plurality of UBM openings Op corresponds to the sum of the thickness of the first insulating film 111a and the thickness of the photoresist film PR. The depth h2 of the dummy pattern openings Od corresponds to the thickness of the photoresist film PR. The depth h1 of the plurality of UBM openings Op can be greater than the depth h2 of the dummy pattern openings Od.

[0085] Next, referring to Figure 10B A plurality of UBM pads 140' and a dummy pattern 145' can be respectively formed in the plurality of UBM openings Op and the dummy pattern openings Od.

[0086] ​The plurality of UBM pads 140' and the dummy pattern 145' can be formed using a plating process. In the present example embodiment, the dummy pattern 145' can be formed together with the UBM pads 140' using a single plating process. The present plating process can be performed by using seed layer S1 regions exposed in the plurality of UBM openings Op and the dummy pattern openings Od, respectively.

[0087] As described above, the depth h1 of the plurality of UBM openings Op can be greater than the depth h2 of the dummy pattern openings Od. Thus, when the plurality of UBM pads 140' and the dummy pattern 145' are formed simultaneously by using a one-time plating process, there can be a slight height deviation. As shown in FIG. 14B, if the plurality of UBM openings Op are not sufficiently filled, the plurality of UBM pads 140' can have a concave upper surface 140T'. In contrast, if the dummy pattern openings Od are slightly overfilled, the dummy pattern 145' can have a convex upper surface 145T'. Figure 10B

[0088] Referring to FIG. 14A, a photoresist film PR can be formed on the first insulating film 111a to cover the plurality of UBM pads 140' and the dummy pattern 145'. Figure 10C The photoresist film PR can be removed, and a second insulating film 111b can be formed on the first insulating film 111a to cover the plurality of UBM pads 140' and the dummy pattern 145'.

[0089] The second insulating film 111b can be disposed together with the first insulating film 111a as the lowermost insulating layer 111 associated with the UBM pads 140. For example, the second insulating film 111b can be a PID material similar to the first insulating film 111a.

[0090] Referring to FIG. 14A, a photoresist film PR can be formed on the first insulating film 111a to cover the plurality of UBM pads 140' and the dummy pattern 145'. Figure 10D A redistribution layer 121 connected to the UBM pads 140' can be formed on the second insulating film 111b.

[0091] When the second insulating film 111b is a PID, the redistribution layer 121 connected to the UBM pads 140' can be formed using a lithography process and a plating process. For example, a hole connected to the UBM pads 140' can be formed by a lithography process, a redistribution via 121V can be formed in the hole using a plating process, and the redistribution layer 121 connected to the redistribution via 121V can be formed on the second insulating film 111b.

[0092] In the present example embodiment, similar to the previous example embodiment, a second seed layer S2 can remain in the redistribution layer 121 along a surface in contact with the second insulating film 111b. A first seed layer S1 for the UBM pads 140' can be disposed between the plurality of UBM pads 140' and the first insulating film 111a, but can not exist between the plurality of UBM pads 140' and the second insulating film 111b.

[0093] ​In addition, a portion of the first seed layer S1 for the dummy pattern 145' can be provided between the dummy pattern 145' and the first insulating film 111a, but can not be present between the dummy pattern 145' and the second insulating film 111b.

[0094] The redistribution substrate 130 illustrated in FIG. 1A can be manufactured by repeating the formation processes of the insulating layers 112, 113, and 114 and the redistribution layers 122, 123, and 125 described above. Figure 11 The redistribution substrate 130 illustrated in FIG. 1A.

[0095] Figure 11 is a cross-sectional view illustrating a semiconductor package according to an example embodiment. Figure 11 The semiconductor package illustrated in FIG. 1A can include a redistribution substrate 130 manufactured by Figures 10A-10D the processes illustrated in FIG. 1A.

[0096] In addition to the semiconductor package 100A according to the present example embodiment, the UBM pads 140' and the dummy pattern 145' have recessed upper surfaces 140T' and convex upper surfaces 145T', respectively, and some lower regions 140e of the UBM pads 140' are exposed, Figure 11 The structure illustrated in FIG. 1A can be Figures 1-3 the structure illustrated in FIG. 1A. Thus, unless otherwise specified, Figures 1-3 The description of the example embodiments illustrated in FIG. 1A can be combined with the description of the present example embodiment.

[0097] In the present example embodiment, the UBM pads 140' and the dummy pattern 145' can have recessed upper surfaces 140T' and convex upper surfaces 145T', respectively. As described in the foregoing processes (see Figure 10B ), if the plurality of UBM openings Op are not sufficiently filled, the plurality of UBM pads 140' can have recessed upper surfaces 140T', and if the openings Od for the dummy pattern are slightly overfilled, the dummy pattern 145' can have convex upper surfaces 145T'.

[0098] A desmear or etching process using plasma or the like can be performed on the first surface 130A of the redistribution substrate 130, and the lowermost insulating layer 111 can be partially etched so that some lower regions 140e of the UBM pads 140' can be exposed. The exposed lower regions 140e of the UBM pads 140' can ensure stable connection with the external connection conductor 180.

[0099] Figure 12 is a cross-sectional view illustrating a semiconductor package according to an example embodiment, Figure 13 is Figure 12 a top view of the semiconductor package illustrated in FIG. 1A, and Figure 14 is Figure 12An enlarged cross-sectional view of a portion "A2" of the semiconductor package shown.

[0100] In addition to the second dummy pattern 145b for reducing the undulation being introduced between some redistribution layers 121 and the insulating layer 112, and including the plurality of semiconductor chips 150A and 150B and the heat sink 195, Figure 12 and Figure 13 The structure shown can be similar to Figures 1-3 the structure shown. Thus, unless otherwise noted, Figures 1-3 the description of the example embodiments shown can be combined with the description of the example embodiments.

[0101] Similar to the dummy pattern 145 of the example embodiments described above, the first dummy pattern 145a can be provided between the plurality of UBM pads 140 in the insulating layer 111 to reduce the undulation due to the UBM pads 140. The first dummy pattern 145a can be spaced apart from the first surface 130A of the redistribution substrate 130, and the thickness of the first dummy pattern 145a can be smaller than the thickness of the plurality of UBM pads 140. For example, the first dummy pattern 145a can be provided between the first insulating film 111a and the second insulating film 111a in the lowermost insulating layer 111.

[0102] Referring to Figure 14 , the second dummy pattern 145b can be provided between the plurality of redistribution layers 121, and the lower surface of the second dummy pattern 145b can be set to be higher than the level of the lower surface of each of the plurality of redistribution layers 121. The second dummy pattern 145b can be spaced apart from the first surface 130A of the redistribution substrate 130, and can have a thickness smaller than the thickness of the redistribution layer 121. For example, the second dummy pattern 145b can be provided between the first insulating film 112a and the second insulating film 112b of the insulating layer 112. The second dummy pattern 145b can be provided to reduce the distance when the redistribution layer 121 has a relatively greater thickness than the other redistribution layers or the distance between the redistribution layers 121 is large, thereby reducing the undulation.

[0103] In the present example embodiment, the first semiconductor chip 150A and the second semiconductor chip 150B can be mounted on the second surface 130B of the redistribution substrate 130. The contact pads 150P of the first semiconductor chip 150A and the second semiconductor chip 150B can be connected to the bonding pads 125 by connection bumps, respectively. A molding portion 165 can be formed to surround some or all of the first semiconductor chip 150A and the second semiconductor chip 150B. The molding portion 165 can include, for example, an epoxy molding compound. Similar to the previous example embodiment, the molding portion 165 can have a flat upper surface that is coplanar with the upper surfaces of the first semiconductor chip 150A and the second semiconductor chip 150B.

[0104] The semiconductor package 100B according to the present example embodiment can further include a thermally conductive material layer 191 and a heat spreader 195 disposed in sequence on the upper surfaces of the first semiconductor chip 150A and the second semiconductor chip 150B. The thermally conductive material layer 191 can be disposed between the heat spreader 195 and the first semiconductor chip 150A, the second semiconductor chip 150B, and the molding portion 165. The thermally conductive material layer 191 can help smoothly discharge heat generated by the first semiconductor chip 150A and the second semiconductor chip 150B to the heat spreader 195. The thermally conductive material layer 191 can be made of, for example, a thermal interface material (TIM).

[0105] The thermally conductive material layer 191 can be made of, for example, an electrically insulating material, or can be made of a material capable of maintaining electrical insulation, including an insulating material. The thermally conductive material layer 191 can include, for example, an epoxy resin. Specific examples of the thermally conductive material layer 191 can include mineral oil, grease, caulk, phase change gel, phase change material pads, or epoxy resin filled with particles.

[0106] The heat spreader 195 can be disposed on the thermally conductive material layer 191. The heat spreader 195 can be, for example, a heat sink, a fin, a heat pipe, or a liquid-cooled cooling plate.

[0107] Figure 15 FIG. 1 is a block diagram illustrating a configuration of a semiconductor package according to an example embodiment.

[0108] Referring to Figure 15 The semiconductor package 1000 can include a micro processing unit (MPU) 1010, a memory 1020, an interface 1030, a graphic processing unit (GPU) 1040, a function block 1050, and a bus 1060 connected thereto. The semiconductor package 1000 can include both the micro processing unit 1010 and the graphic processing unit 1040, or can include only one of the two.

[0109] The micro-processing unit 1010 can include cores and L2 cache memories. For example, the micro-processing unit 1010 can include a multi-core. Each core of the multi-core can have the same or different performance. In addition, each core of the multi-core can be activated at the same time or can be different from each other when activated.

[0110] The memory 1020 can store results processed in the functional blocks 1050, etc., under the control of the micro-processing unit 1010. The interface 1030 can exchange information or signals with external devices. The graphic processing unit 1040 can perform a graphic function. For example, the graphic processing unit 1040 can perform a video codec or process 3D graphics. The functional blocks 1050 can perform various functions. For example, when the semiconductor package 1000 is an application processor (AP) used in a mobile device, some of the functional blocks 1050 can perform a communication function. In this case, the semiconductor package 1000 can include a communication function block described with reference to Figure 12 The semiconductor package 100B described above.

[0111] By summarizing and reviewing, a semiconductor package can be manufactured by forming a redistribution substrate (e.g., an interposer) having redistribution layers, and mounting and molding a semiconductor chip on the redistribution substrate. The redistribution substrate can be formed by repeatedly performing a forming process of an insulating layer and a forming process of a pattern (e.g., a UBM pad and a plurality of redistribution layers) of each layer on each insulating layer.

[0112] As described above, embodiments can provide a semiconductor package having high reliability by improving the undulation generated in a redistribution substrate. Embodiments can provide a method of manufacturing a semiconductor package having high reliability by reducing the undulation in a redistribution substrate.

[0113] As described above, by introducing a dummy pattern that is not exposed to the outside between under bump metal (UBM) pads, the undulation generated in a redistribution layer formed in a subsequent process can be reduced, and the reliability of a semiconductor package can be improved. In addition to the UBM pads, a dummy pattern can be provided between redistribution layers in a layer thinner than the redistribution layers to reduce the undulation.

[0114] Example embodiments have been disclosed herein and, although the specific terms are employed, they are used and interpreted in a generic and descriptive sense, and not for purposes of limitation. In some instances, features, attributes and / or elements described in conjunction with a particular embodiment are likewise applicable and usable in conjunction with other embodiments, to the extent that the described features, attributes, and / or elements do not work in direct contradiction. Thus, the skilled artisan will appreciate that various adaptations and modifications of the embodiments described herein can be accomplished without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor package comprising: a redistribution substrate having a first surface and a second surface disposed opposite to each other, and including an insulating member and a plurality of redistribution layers disposed in the insulating member at different levels, respectively, and electrically connected to each other; a plurality of under bump metal pads disposed in the insulating member and connected to a redistribution layer among the plurality of redistribution layers adjacent to the first surface of the redistribution substrate, the plurality of under bump metal pads having lower surfaces exposed to the first surface of the redistribution substrate; a dummy pattern disposed in the insulating member between the plurality of under bump metal pads, a lower surface of the dummy pattern being located at a level higher than the lower surfaces of the plurality of under bump metal pads, and at least one semiconductor chip disposed on the second surface of the redistribution substrate and having a plurality of contact pads electrically connected to a redistribution layer among the plurality of redistribution layers adjacent to the second surface of the redistribution substrate, wherein the plurality of under bump metal pads and the dummy pattern have upper surfaces substantially coplanar.

2. The semiconductor package of claim 1, wherein, The dummy pattern is spaced apart from adjacent under bump metal pads among the plurality of under bump metal pads by a distance of 30 μm or less.

3. The semiconductor package of claim 1, wherein, The dummy pattern is spaced apart from the first surface of the redistribution substrate by a distance of 2 μm or more.

4. The semiconductor package of claim 1, wherein, The plurality of under bump metal pads each have a thickness greater than a thickness of the redistribution layer connected thereto.

5. The semiconductor package of claim 1, wherein the insulating member includes a plurality of insulating layers, and the plurality of under bump metal pads are disposed on a first insulating layer among the plurality of insulating layers adjacent to the first surface of the redistribution substrate, and the first insulating layer includes a first insulating film and a second insulating film disposed in sequence from the first surface of the redistribution substrate.

6. The semiconductor package of claim 5, wherein, A seed layer for the plurality of under bump metal pads is disposed between the plurality of under bump metal pads and the first insulating film, and is not present between the plurality of under bump metal pads and the second insulating film.

7. The semiconductor package of claim 5, wherein, The dummy pattern is disposed on the first insulating film and is covered by the second insulating film.

8. The semiconductor package of claim 7, wherein, A seed layer for the dummy pattern is disposed between the dummy pattern and the first insulating film, and is not present between the dummy pattern and the second insulating film.

9. The semiconductor package of claim 1, wherein the plurality of redistribution layers include redistribution vias connecting redistribution layers disposed at adjacent levels, and the redistribution vias have a shape that narrows in a direction from the second surface toward the first surface.

10. The semiconductor package of claim 1, wherein, The insulating member includes a photoimageable dielectric material.

11. The semiconductor package of claim 1, wherein, A portion of the under bump metal pads protrudes from the first surface of the redistribution substrate.

12. The semiconductor package of claim 1, further comprising a molding portion disposed on the second surface of the redistribution substrate and surrounding the at least one semiconductor chip.

13. The semiconductor package of claim 12, wherein, An upper surface of the at least one semiconductor chip is substantially coplanar with an upper surface of the molding portion.

14. The semiconductor package of claim 12, further comprising: A heat dissipation member disposed on an upper surface of the at least one semiconductor chip.

15. The semiconductor package of claim 1, wherein, The at least one semiconductor chip comprises a plurality of semiconductor chips.

16. A semiconductor package comprising: a redistribution substrate having a first surface and a second surface disposed opposite to each other, and including a plurality of insulating layers and a plurality of redistribution layers respectively disposed between the plurality of insulating layers; a plurality of under bump metal pads disposed on an adjacent insulating layer among the plurality of insulating layers adjacent to the first surface of the redistribution substrate, the plurality of under bump metal pads having lower surfaces exposed to the first surface of the redistribution substrate and having recessed upper surfaces; a dummy pattern disposed in the adjacent insulating layer, a lower surface of the dummy pattern being located at a higher level than the lower surfaces of the plurality of under bump metal pads and having a protruding upper surface; and at least one semiconductor chip disposed on the second surface of the redistribution substrate and having contact pads electrically connected to redistribution layers among the plurality of redistribution layers adjacent to the second surface of the redistribution substrate, wherein the adjacent insulating layer includes a first insulating film and a second insulating film sequentially disposed from the first surface of the redistribution substrate, a seed layer for the plurality of under bump metal pads is disposed between the plurality of under bump metal pads and the first insulating film and is not present between the plurality of under bump metal pads and the second insulating film, and a seed layer for the dummy pattern is disposed between the lower surface of the dummy pattern and the first insulating film and is not present between the dummy pattern and the second insulating film.

17. A semiconductor package comprising: a redistribution substrate having a first surface and a second surface disposed opposite to each other, and including an insulating member and a plurality of redistribution layers respectively disposed at a plurality of different levels in the insulating member and electrically connected to each other; a plurality of under bump metal pads disposed in the insulating member to be exposed to the first surface of the redistribution substrate and connected to redistribution layers among the plurality of redistribution layers adjacent to the first surface of the redistribution substrate; a first dummy pattern spaced apart from the first surface of the redistribution substrate and disposed between the plurality of under bump metal pads, a thickness of the first dummy pattern being smaller than a respective thickness of the plurality of under bump metal pads; and a second dummy pattern disposed on the second surface of the redistribution substrate and having a thickness greater than a respective thickness of the plurality of under bump metal pads. ​ at least one semiconductor chip disposed on the second surface of the redistribution substrate, the at least one semiconductor chip having a plurality of contact pads electrically connected to a redistribution layer of the plurality of redistribution layers adjacent to the second surface of the redistribution substrate, wherein the insulating member includes a plurality of insulating layers, the plurality of under bump metal pads are disposed on a first insulating layer of the plurality of insulating layers adjacent to the first surface of the redistribution substrate, the first insulating layer includes a first insulating film and a second insulating film disposed sequentially from the first surface of the redistribution substrate, a seed layer for the plurality of under bump metal pads is disposed between the plurality of under bump metal pads and the first insulating film, and is not present between the plurality of under bump metal pads and the second insulating film, and a seed layer for the first dummy pattern is disposed between a lower surface of the first dummy pattern and the first insulating film, and is not present between the first dummy pattern and the second insulating film.

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