A driver control circuit and a driver capable of forming a dead time

Abstract

The present invention provides a driver control circuit and a driver capable of forming a dead time. The driver control circuit includes: a reference voltage operational amplifier, a transistor module, a charging module, a comparison module, and a capacitor; a first input terminal of the reference voltage operational amplifier is connected to an original reference voltage, an output terminal of the reference voltage operational amplifier is connected to a control terminal of the transistor module, a first end of the transistor module is connected to a first power supply, and a second end of the transistor module is connected to a second input terminal of the reference voltage operational amplifier; the output terminal of the reference voltage operational amplifier is connected to the charging module and the comparison module, the charging module is connected to the first power supply, the charging module is connected to a conduction state signal of a currently turned-off switch, the charging module is connected to a first end of the capacitor, the first end of the capacitor is connected to the comparison module, and a second end of the capacitor is grounded; an output terminal of the comparison module is directly or indirectly connected to a currently to-be-conducted switch.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and particularly to a driver control circuit and a driver capable of forming a dead time. Background Art

[0002] Transistor switches connected in a push-pull manner conduct and turn off alternately to change the direction of the current in the coil. To avoid unwanted current surges caused by the simultaneous conduction of two transistors, the control circuit introduces a dead time characteristic during the switching operation. During the dead time, even if the pre-stage system issues a signal to turn on another transistor, the control circuit still maintains the off driving state.

[0003] In the prior art, in the dead time generation circuit, in order to improve the anti-noise ability of the circuit, a capacitor needs to be connected in parallel beside the external resistor. The value of this capacitor will affect the stability of the amplifier feedback network in the dead time generation circuit, and thus affect the dead time. Moreover, the adaptation range of the dead time generation circuit is relatively small. Summary of the Invention

[0004] The present invention provides a driver control circuit and a driver capable of forming a dead time to solve the problems of circuit instability and small adaptation range.

[0005] According to a first aspect of the present invention, there is provided a driver control circuit capable of forming a dead time, including: a reference voltage operational amplifier, a transistor module, a charging module, a comparison module, and a capacitor;

[0006] A first input terminal of the reference voltage operational amplifier is connected to an original reference voltage, an output terminal of the reference voltage operational amplifier is connected to a control terminal of the transistor module, a first terminal of the transistor module is connected to a first power supply, and a second terminal of the transistor module is connected to a second input terminal of the reference voltage operational amplifier;

[0007] The output terminal of the reference voltage operational amplifier is further connected to a first input terminal of the charging module and a first input terminal of the comparison module. The reference voltage operational amplifier is configured to: generate a target reference voltage according to the original reference voltage, and feedback the target reference voltage to the comparison module and the charging module;

[0008] A second input terminal of the charging module is connected to the first power supply, a third input terminal of the charging module is connected to a conduction state signal of the current turn-off switch, the conduction state signal represents the conduction state of the corresponding switch, and the current turn-off switch is the currently turned-off switch among two switches connected in series in the driver;

[0009] The charging module is connected to a first terminal of the capacitor. The charging module is configured to: charge the capacitor according to the target reference voltage and the conduction state signal;

[0010] The first end of the capacitor is connected to the second input terminal of the comparison module, and the second end of the capacitor is grounded;

[0011] The output terminal of the comparison module is directly or indirectly connected to the currently to-be-conducted switch. The comparison module is configured to directly or indirectly control the currently to-be-conducted switch to conduct when the voltage of the capacitor is higher than the target reference voltage, so as to form the dead time, and the dead time is less than the time period after the currently off switch turns off and before the currently to-be-conducted switch turns on. The currently to-be-conducted switch is the currently to-be-conducted switch among the two switches connected in series in the driver.

[0012] Optionally, the charging module includes a first charging unit and a second charging unit; the first charging unit is connected to the first power supply through the second charging unit, the first charging unit is also connected to the conduction signal, the second charging unit is also connected to the target reference voltage, and the first end of the capacitor is connected to the first charging unit and the second charging unit;

[0013] The first charging unit is configured to: charge the capacitor when the currently off switch is in the on state, so that the voltage of the capacitor is at the base voltage, and stop charging the capacitor when the currently off switch is in the off state;

[0014] The second charging unit is configured to: charge the capacitor when the first charging unit stops charging the capacitor, so that the voltage of the capacitor reaches the saturation voltage; the base voltage is lower than the target reference voltage, and the saturation voltage is higher than the target reference voltage.

[0015] Optionally, the capacitor is a gate oxide capacitor, and the base voltage matches the threshold voltage of the gate oxide capacitor.

[0016] Optionally, the first charging unit includes a first charging transistor and a second charging transistor;

[0017] The control electrode of the first charging transistor is connected to the conduction state signal, the first electrode of the first charging transistor is connected to the second electrode of the second charging transistor, and the second electrode of the second charging transistor is grounded;

[0018] The control electrode and the first electrode of the second charging transistor are connected to the first end of the capacitor.

[0019] Optionally, the first charging unit further includes a first specified transistor, and the minimum withstand voltage between the first and second electrodes of the first specified transistor is higher than the maximum withstand voltage between the first and second electrodes of any one of the charging transistors;

[0020] The control electrode of the first designated transistor is connected to the first end of the capacitor, the first pole of the first designated transistor is connected to the first pole of the first charging transistor, and the second pole of the first designated transistor is connected to the second pole of the second charging transistor.

[0021] Optionally, the second charging unit includes a third charging transistor, a fourth charging transistor, and a fifth charging transistor.

[0022] The control electrode of the third charging transistor is connected to the output terminal of the reference voltage operational amplifier, the first pole of the third charging transistor is connected to the control electrode and the first pole of the fourth charging transistor, and the second pole of the third charging transistor is connected to an external resistor.

[0023] The second pole of the fourth charging transistor is connected to the first power supply, and the control electrode of the fourth charging transistor is connected to the control electrode of the fifth charging transistor.

[0024] The first pole of the fifth charging transistor is connected to the first end of the capacitor, and the second pole of the fifth charging transistor is connected to the first power supply.

[0025] Optionally, the second charging unit further includes a sixth charging transistor.

[0026] The control electrode of the sixth charging transistor is connected to the control electrode of the fourth charging transistor, and the first pole of the sixth charging transistor is connected to the first power supply.

[0027] Optionally, the second charging unit further includes a second designated transistor, and the minimum withstand voltage between the first and second poles of the second designated transistor is higher than the maximum withstand voltage between the first and second poles of any one of the charging transistors.

[0028] The control electrode of the second designated transistor is connected to the control electrode of the third charging transistor, the first pole of the second designated transistor is connected to the external resistor, and the second pole of the second designated transistor is connected to the second pole of the third charging transistor.

[0029] Optionally, the driver control circuit further includes a first current source.

[0030] The first end of the first current source is connected to the second input terminal of the reference voltage operational amplifier, and the second end of the first current source is connected to ground.

[0031] Optionally, the transistor module includes a seventh transistor and a third designated transistor, and the minimum withstand voltage between the first and second poles of the third designated transistor is higher than the maximum withstand voltage between the first and second poles of any one of the charging transistors.

[0032] The control electrode of the seventh transistor is connected to the output terminal of the reference voltage operational amplifier. The first electrode of the seventh transistor is connected to the first power supply, and the second electrode of the seventh transistor is connected to the second electrode of the third designated transistor;

[0033] The control electrode of the third designated transistor is connected to the output terminal of the reference voltage operational amplifier. The first electrode of the third designated transistor is connected to the second input terminal of the reference voltage operational amplifier.

[0034] Optionally, the comparison module includes a comparator. The first input terminal of the comparator is connected to the output terminal of the reference voltage operational amplifier. The second input terminal of the voltage comparator is connected to the charging module. The output terminal of the comparator is directly or indirectly connected to the currently to-be-conducted switch.

[0035] Optionally, the driver control circuit further includes a biasing module. The first end of the biasing module is connected to the charging module, and the second end of the biasing module is connected to the comparison module;

[0036] The biasing module is used to adjust the delay time of the comparison module according to the charging speed at which the charging module charges the capacitor.

[0037] Optionally, the biasing module includes a first biasing transistor, a second biasing transistor, and a second current source;

[0038] The first electrode and the control electrode of the first biasing transistor are connected to the charging module. The control electrode of the first biasing transistor is connected to the control electrode of the second biasing transistor. The second electrode of the first biasing transistor is connected to ground;

[0039] The first electrode of the second biasing transistor is connected to the comparison module. The second electrode of the second biasing transistor is connected to ground;

[0040] Both ends of the second current source are respectively connected to the third input terminal of the comparison module and ground.

[0041] According to a second aspect of the present invention, there is provided a driver, including a first driver control circuit, a second driver control circuit, a first switch, and a second switch. Both the first driver control circuit and the second driver control circuit are driver control circuits capable of forming a dead time involved in the first aspect of the present invention and its optional solutions;

[0042] The third input terminal of the charging module in the first driver control circuit accesses the on-state signal of the first switch;

[0043] The output terminal of the comparison module in the first driver control circuit is directly or indirectly connected to the control electrode of the second switch, so as to directly or indirectly control the second switch to conduct according to the conduction state signal of the first switch, and output a first control signal for controlling the conduction of the second switch;

[0044] The third input terminal of the charging module in the second driver control circuit accesses the conduction state signal of the second switch;

[0045] The output terminal of the comparison module in the second driver control circuit is directly or indirectly connected to the control electrode of the first switch, so as to output a second control signal for controlling the conduction of the first switch;

[0046] After the first switch is turned off, the first switch is the currently turned-off switch, and the second switch is the currently to-be-conducted switch; after the second switch is turned off, the second switch is the currently turned-off switch, and the first switch is the currently to-be-conducted switch;

[0047] The first pole of the second switch is connected to the second power supply, the second pole of the second switch is connected to the first pole of the first switch; the second pole of the first switch is connected to the ground.

[0048] Optionally, the driver further includes a first logic circuit and a second logic circuit;

[0049] The first input terminal of the first logic circuit is connected to the output terminal of the first driver control circuit, the second input terminal of the first logic circuit is connected to the conduction state signal of the second switch, and the output terminal of the first logic circuit is directly or indirectly connected to the second switch, so as to control the second switch to conduct according to the conduction state signal of the second switch and the first control signal;

[0050] The first input terminal of the second logic circuit is connected to the output terminal of the second driver control circuit, the second input terminal of the second logic circuit is connected to the conduction state signal of the first switch, and the output terminal of the logic circuit is directly or indirectly connected to the first switch, so as to control the first switch to conduct according to the conduction state signal of the first switch and the second control signal.

[0051] Optionally, the first logic circuit includes a first NOT gate and a first AND gate, and the second logic circuit includes a second NOT gate and a second AND gate;

[0052] The input terminal of the first NOT gate is connected to the output terminal of the comparison module of the first driver control circuit, and the output terminal of the first NOT gate is connected to the first input terminal of the first AND gate, so as to invert the first control signal and feedback it to the first input terminal of the first AND gate;

[0053] The second input terminal of the first AND gate receives the conduction state signal of the second switch, and the output terminal of the first AND gate is directly or indirectly connected to the control electrode of the second switch to output a logic signal for controlling the conduction of the second switch;

[0054] The second NOT gate is connected to the output terminal of the comparison module of the second driver control circuit, and the output terminal of the second NOT gate is connected to the first input terminal of the second AND gate to invert the second control signal and feedback it to the first input terminal of the second AND gate;

[0055] The second input terminal of the second AND gate receives the conduction state signal of the first switch, and the output terminal of the second AND gate is directly or indirectly connected to the control electrode of the first switch to output a logic signal for controlling the conduction of the first switch.

[0056] The driver control circuit and driver capable of forming a dead time provided by the present invention, wherein the charging module is independent of the feedback loop of the reference voltage operational amplifier, making the feedback loop of the reference voltage operational amplifier more stable, and further, the control of the driver is more accurate.

[0057] In an alternative embodiment of the present invention, a gate oxide capacitor is used to reduce the control deviation of the two switches caused by the process deviation of the on-chip integrated capacitor.

[0058] In an alternative embodiment of the present invention, a bias module is added to make the delay time of the comparison module match the charging time of the charging module. For example, when the resistance value of the external resistor is large, the charging module charges the capacitor faster, and then the bias module can shorten the delay time of the comparison module according to the capacitor charging speed.

[0059] In an alternative embodiment of the present invention, multiple high-voltage transistors are used to provide a larger range for the resistance value of the external resistor, and at the same time, it can also prevent the transistor from conducting reversely and having an adverse effect on the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0061] Figure 1 is a schematic structural diagram of a driver control circuit in an embodiment of the present invention Figure 1 ;

[0062] Figure 2 is a schematic structural diagram of a driver control circuit in an embodiment of the present inventionFigure 2 ;

[0063] Figure 3 is the circuit schematic of the driver control circuit in an embodiment of the present invention Figure 1 ;

[0064] Figure 4 is the circuit schematic of the driver control circuit in an embodiment of the present invention Figure 2 ;

[0065] Figure 5 is the circuit schematic of the driver control circuit in an embodiment of the present invention Figure 3 ;

[0066] Figure 6 is the circuit schematic of the driver control circuit in an embodiment of the present invention Figure 4 ;

[0067] Figure 7 is the circuit schematic of the driver control circuit in an embodiment of the present invention Figure 5 ;

[0068] Figure 8 is the structural schematic of the driver control circuit in an embodiment of the present invention Figure 3 ;

[0069] Figure 9 is the signal waveform of the driver control circuit in an embodiment of the present invention Figure 1 ;

[0070] Figure 10 is the signal waveform of the driver control circuit in an embodiment of the present invention Figure 2 ;

[0071] Figure 11 is the circuit schematic of the driver control circuit in an embodiment of the present invention Figure 6 ;

[0072] Figure 12 is the structural schematic of the driver in an embodiment of the present invention Figure 1 ;

[0073] Figure 13 is the structural schematic of the driver in an embodiment of the present invention Figure 2 ;

[0074] Figure 14 is the structural schematic of the driver in an embodiment of the present invention Figure 3 ;

[0075] Figure 15 is the signal waveform diagram of the driver in an embodiment of the present invention. Detailed implementation manners

[0076] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0077] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present invention and the above accompanying drawings are used to distinguish similar objects and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order different from those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily need to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0078] The technical solutions of the present invention will be described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.

[0079] Please refer to Figure 1 , a driver control circuit 11 capable of forming a dead time, comprising: a reference voltage operational amplifier U1, a transistor module 111, a charging module 112, a comparison module 113, and a capacitor Cramp;

[0080] The first input terminal of the reference voltage operational amplifier U1 is connected to the original reference voltage Vr, the output terminal of the reference voltage operational amplifier U1 is connected to the control terminal of the transistor module 111, the first terminal of the transistor module 111 is connected to the first power supply Vcc, and the second terminal of the transistor module 111 is connected to the second input terminal of the reference voltage operational amplifier U1;

[0081] The output terminal of the reference voltage operational amplifier U1 is also connected to the first input terminal of the charging module 112 and the first input terminal of the comparison module 113. The reference voltage operational amplifier U1 is configured to: generate a target reference voltage Vr_ramp according to the original reference voltage Vr, and feedback the target reference voltage Vr_ramp to the comparison module 113 and the charging module 112;

[0082] The second input terminal of the charging module 112 is connected to the first power supply Vcc. The third input terminal of the charging module 112 receives the conduction state signal in of the current turn-off switch. The conduction state signal in represents the conduction state of the corresponding switch. The current turn-off switch is the switch that has been turned off among the two series-connected switches in the driver;

[0083] The charging module 112 is connected to the first end of the capacitor Cramp. The charging module 112 is configured to: charge the capacitor Cramp according to the target reference voltage Vr_ramp and the conduction state signal in;

[0084] The first end of the capacitor Cramp is connected to the second input terminal of the comparison module 113. The second end of the capacitor Cramp is grounded;

[0085] The output terminal of the comparison module 113 is directly or indirectly connected to the current switch to be turned on. The comparison module 113 is configured to directly or indirectly control the current switch to be turned on when the voltage of the capacitor Cramp is higher than the target reference voltage Vr_ramp, so as to form the dead time t DT , the dead time t DT is less than the time period after the current turn-off switch is turned off and before the current switch to be turned on is turned on. The current switch to be turned on is the switch to be turned on among the two series-connected switches in the driver.

[0086] Among them, the conduction state signal in represents the conduction state of the switch (the first switch or the second switch) in the driver. Specifically, the conduction state signal can be a logic signal for controlling the conduction or turn-off of the corresponding switch. For example, it can be a signal directly or indirectly sent by the controller to the control pole of the corresponding switch. Combining Figure 14 , the conduction state signal of the second switch K2 is the conduction state signal in2, and the conduction state signal of the first switch K2 is the conduction state signal in1.

[0087] In an example, the specific working process of the charging module 112 for charging the capacitor Cramp is as follows:

[0088] When the conduction state signal connected to the charging module 112 is at a high level, the charging module 112 charges the capacitor Cramp according to the conduction state signal, so that the voltage of the capacitor Cramp is at the base voltage VTH;

[0089] When the conduction state signal of the charging module 112 is at a low level, the charging module 112 charges the capacitor Cramp according to the target reference voltage Vr_ramp so that the voltage of the capacitor Cramp reaches the saturation voltage Vs; the base voltage VTH is lower than the target reference voltage Vr_ramp, and the saturation voltage Vs is higher than the target reference voltage Vr_ramp;

[0090] During the process that the charging module 112 charges the capacitor Cramp according to the target reference voltage Vr_ramp, when the voltage of the capacitor Cramp is higher than the target reference voltage Vr_ramp, the output result of the comparison module 113 will reverse, and then the currently to-be-conducted switch can be directly or indirectly controlled to conduct.

[0091] Among them, the charging module is independent of the feedback loop of the reference voltage operational amplifier, making the feedback loop of the reference voltage operational amplifier more stable. Furthermore, the control of the driver is more accurate.

[0092] Please refer to Figure 2 In one implementation, the charging module 112 includes a first charging unit 1121 and a second charging unit 1122; the first charging unit 1121 is connected to the first power supply Vcc through the second charging unit 1122. The first charging unit 1121 is also connected to the conduction state signal, and the second charging unit 1122 is also connected to the target reference voltage Vr_ramp. The first end of the capacitor Cramp is connected to the first charging unit 1121 and the second charging unit 1122;

[0093] The first charging unit 1121 is configured to: charge the capacitor Cramp when the current off-switch is in the conduction state so that the voltage of the capacitor Cramp is at the base voltage VTH, and stop charging the capacitor Cramp when the current off-switch is in the off state;

[0094] The second charging unit 1122 is configured to: charge the capacitor Cramp when the first charging unit 1121 stops charging the capacitor Cramp so that the voltage of the capacitor Cramp reaches the saturation voltage Vs; the base voltage VTH is lower than the target reference voltage Vr_ramp, and the saturation voltage Vs is higher than the target reference voltage Vr_ramp.

[0095] It can be understood from the above that when the current turn-off switch is in the on state under the control of the on-state signal, even if the on-state signal of the current switch to be turned on changes to a state where it can control the current switch to be turned on, due to the operation of the driver control circuit 11, the current switch to be turned on will not be immediately turned on, but there will be a delay for a period of time. Therefore, the two switches will not be turned on simultaneously, and thus the two outputs of the driver will not affect each other.

[0096] In one embodiment, the capacitor Cramp is a gate oxide capacitor, and the base voltage VTH matches the threshold voltage of the gate oxide capacitor.

[0097] In the above embodiment, when the voltage across the gate oxide capacitor is below the threshold voltage, the capacitance value of the gate oxide capacitor will change as the voltage across its two ends increases. When the voltage across the gate oxide capacitor reaches the threshold voltage, its capacitance value remains almost unchanged, and the voltage across the gate oxide capacitor will show a linear change, which will not affect the accuracy of the generated dead time.

[0098] In the above embodiment, using a gate oxide capacitor instead of other types of capacitors reduces the control deviation of the two switches caused by the process deviation of the on-chip integrated capacitor.

[0099] Please refer to Figure 3 , in one embodiment, the first charging unit 1121 includes a first charging transistor M1 and a second charging transistor M2;

[0100] The control electrode of the first charging transistor M1 is connected to the on-state signal, the first electrode of the first charging transistor M1 is connected to the second electrode of the second charging transistor M2, and the second electrode of the second charging transistor M2 is connected to the ground;

[0101] The control electrode and the first electrode of the second charging transistor M2 are connected to the first end of the capacitor Cramp.

[0102] The transistor therein can be an NFET, that is, composed of a pair of complementary N-channel MOSFETs. The transistor therein can also be a PFET, that is, composed of a pair of complementary P-channel MOSFETs. Whether it is an NFET or a PFET, the control electrode of the transistor can be understood as the gate of the field-effect transistor, and the first and second electrodes of the transistor can be understood as the source and drain of the field-effect transistor.

[0103] In one embodiment, the first charging unit 1121 further includes a first designated transistor N1, and the minimum breakdown voltage between the first and second electrodes of the first designated transistor is higher than the maximum breakdown voltage between the first and second electrodes of any one of the above charging transistors;

[0104] The control electrode of the first designated transistor N1 is connected to the first end of the capacitor Cramp, the first electrode of the first designated transistor N1 is connected to the first electrode of the first charging transistor M1, and the second electrode of the first designated transistor N1 is connected to the second electrode of the second charging transistor M2.

[0105] The first designated transistor among them can be, for example, a high-voltage transistor with a minimum withstand voltage of not less than 5V between the first and second electrodes of the transistor. Furthermore, it provides a larger voltage change range for the circuit and can also prevent the transistors in the circuit from conducting reversely, which has an adverse impact on the circuit.

[0106] Please refer to Figure 4 , in one embodiment, the second charging unit 1122 includes a third charging transistor M3, a fourth charging transistor M4, and a fifth charging transistor M5.

[0107] The control electrode of the third charging transistor M3 is connected to the output terminal of the reference voltage operational amplifier U1, the first electrode of the third charging transistor M3 is connected to the control electrode and the first electrode of the fourth charging transistor M4, and the second electrode of the third charging transistor M3 is connected to the external resistor R DT ;

[0108] The second electrode of the fourth charging transistor M4 is connected to the first power supply Vcc, and the control electrode of the fourth charging transistor M4 is connected to the control electrode of the fifth charging transistor M5.

[0109] The first electrode of the fifth charging transistor M5 is connected to the first end of the capacitor Cramp, and the second electrode of the fifth charging transistor M5 is connected to the first power supply Vcc.

[0110] The external resistor R among them DT is connected to the second electrode of the third charging transistor M3 through a PIN pin, and its resistance value can be changed.

[0111] In one example, an external capacitor can be connected in parallel at both ends of the external resistor R. Furthermore, it can improve the noise suppression ability of the driver control circuit, and since the external capacitor is independent of the feedback loop of the reference voltage operational amplifier, it provides a hardware basis for a larger value range of the external capacitor. DT

[0112] In one embodiment, the second charging unit 1122 further includes a sixth charging transistor M6.

[0113] The control electrode of the sixth charging transistor M6 is connected to the control electrode of the fourth charging transistor M4, and the first electrode of the sixth charging transistor M6 is connected to the first power supply Vcc.

[0114] In one implementation, the second charging unit 1122 further includes a second designated transistor N2, and the minimum withstand voltage between the first and second poles of the second designated transistor N2 is higher than the maximum withstand voltage between the first and second poles of any one of the above charging transistors;

[0115] The control pole of the second designated transistor N2 is connected to the control pole of the third charging transistor M3, the first pole of the second designated transistor N2 is connected to the external resistor R DT , and the second pole of the second designated transistor N2 is connected to the second pole of the third charging transistor M3.

[0116] The second designated transistor therein may be, for example, a high-voltage transistor with a minimum withstand voltage of not less than 5V between the first and second poles of the transistor.

[0117] In one example, the current amplification factors of the third charging transistor M3 and the second charging transistor M2 may be the same; in another example, the current amplification factors of the third charging transistor and the second charging transistor may be different.

[0118] In one example, the current amplification factors of the fourth charging transistor M4, the fifth charging transistor M5, and the sixth charging transistor M6 may be the same; in another example, the current amplification factors of the fourth charging transistor M4, the fifth charging transistor M5, and the sixth charging transistor M6 may be different.

[0119] In one example, the third charging transistor M3 and the second charging transistor M2 are both PFETs, and the fourth charging transistor M4, the fifth charging transistor M5, and the sixth charging transistor M6 are all NFETs; in another example, the third charging transistor M3 and the second charging transistor M2 are both NFETs, and the fourth charging transistor M4, the fifth charging transistor M5, and the sixth charging transistor M6 are all PFETs; it can be seen that the channel types of the third charging transistor M3 and the second charging transistor M2 are different from those of the fourth charging transistor M4, the fifth charging transistor M5, and the sixth charging transistor M6.

[0120] Please refer to Figure 5 , in one implementation, the driver control circuit 11 further includes a first current source I1,

[0121] The first end of the first current source I1 is connected to the second input end of the reference voltage operational amplifier U1, and the second end of the first current source I1 is connected to the ground.

[0122] Please refer to Figure 6 , in one implementation, the transistor module 111 includes a seventh transistor M7 and a third designated transistor N3;

[0123] The control terminal of the seventh transistor M7 is connected to the output terminal of the reference voltage operational amplifier U1, the first terminal of the seventh transistor M7 is connected to the first power supply Vcc, and the second terminal of the seventh transistor M7 is connected to the second terminal of the third designated transistor N3;

[0124] The control terminal of the third designated transistor N3 is connected to the output terminal of the reference voltage operational amplifier U1, and the first terminal of the third designated transistor N3 is connected to the second input terminal of the reference voltage operational amplifier U1.

[0125] The third designated transistor therein may be, for example, a high-voltage transistor with a minimum withstand voltage between the first and second terminals of the transistor not less than 5V, and the seventh transistor M7 may be, for example, a low-voltage transistor with a maximum withstand voltage between the first and second terminals of the transistor not higher than 5V.

[0126] In one example, both the seventh transistor M7 and the third designated transistor N3 are PFETs. In another example, both the seventh transistor M7 and the third designated transistor N3 are NFETs.

[0127] In one example, the transistor module 111 does not include the third designated transistor N3, and the charging module 112 does not include the first designated transistor N1 and the second designated transistor N2. It can be seen that the first designated transistor N1, the second designated transistor N2, and the third designated transistor N3 can be selectively adopted according to the actual application scenario.

[0128] Please refer to Figure 7 , in one embodiment, the comparison module 113 includes a comparator U2. The first input terminal of the comparator U2 is connected to the output terminal of the reference voltage operational amplifier U1, the second input terminal of the voltage comparator U2 is connected to the charging module 112, and the output terminal of the comparator U2 is directly or indirectly connected to the currently to-be-conducted switch.

[0129] Wherein, when the magnitude relationship between the two input terminals of the comparator U2 changes, the output terminal of the comparator U2 does not immediately change the level, but after a period of delay, the level will change.

[0130] In one example, the delay time of the comparator U2 can be changed by adding a bias current to the comparator U2 or changing the magnitude of the bias current.

[0131] Please refer to Figure 8 , in one embodiment, the driver control circuit 11 further includes a bias module 114. The first end of the bias module 114 is connected to the charging module 112, and the second end of the bias module 114 is connected to the comparison module 113;

[0132] The bias module 114 is configured to adjust the delay time of the comparison module 113 according to the charging speed at which the charging module 112 charges the capacitor Cramp.

[0133] The following describes Figures 9 to 10 , in a specific embodiment, the working principle of the bias module 114:

[0134] Figure 9 and Figure 10 wherein, the signal waveform corresponding to in1_dt is the signal waveform at the output end of the comparator U2, the value corresponding to VTH represents the base voltage value of the capacitor Cramp, the dotted line corresponding to Vs represents the voltage value of the saturation voltage of the capacitor Cramp, the dotted line corresponding to Vr_ramp represents the voltage value of the target reference voltage, and the signal waveform corresponding to in1 is the conduction state signal.

[0135] When in the charging module 112, the external resistor R DT is relatively large, the charging speed at which the charging module 112 charges the capacitor Cramp is relatively slow. Consequently, the bias current provided by the bias module 114 to the comparator U2 is relatively small, and the delay of the comparator U2 will be slightly larger;

[0136] When in the charging module 112, the external resistor R DT is relatively small, the charging speed at which the charging module 112 charges the capacitor Cramp is relatively fast. Consequently, the bias current provided by the bias module 114 to the comparator U2 is relatively large. If the additional current of the comparator U2 still remains small at this time, the delay of the comparator will be relatively large, as shown by the dotted line in Figure 10 , so the relative error introduced by it is large. If the additional current of the comparator changes with the charging current, then when the charging speed of the capacitor Cramp is relatively fast, the delay of the comparator will also decrease, as shown by the dotted line in Figure 10 , and the relative error introduced in this way will also decrease.

[0137] Please refer to Figure 11 , in one embodiment, the bias module 114 includes a first bias transistor M8, a second bias transistor M9, and a second current source I2;

[0138] The first pole and the control pole of the first bias transistor M8 are connected to the charging module 112, the control pole of the first bias transistor M8 is connected to the control pole of the second bias transistor M9, and the second pole of the first bias transistor M8 is connected to ground;

[0139] The first pole of the second bias transistor M9 is connected to the comparison module 113, and the second pole of the second bias transistor M9 is connected to ground;

[0140] Both ends of the second current source I2 are respectively connected to the third input terminal of the comparison module 113 and the ground.

[0141] In one example, the first pole and the control pole of the first bias transistor M8 are connected to the second pole of the sixth charging transistor M6.

[0142] In one example, the current amplification factors of the first bias transistor M8 and the second bias transistor M9 can be the same; in another example, the current amplification factors of the first bias transistor M8 and the second bias transistor M9 can be different.

[0143] In one example, both the first bias transistor M8 and the second bias transistor M9 are PFETs; in another example, both the first bias transistor M8 and the second bias transistor M9 are NFETs.

[0144] Please refer to Figure 12 , a driver, including a first driver control circuit 11, a second driver control circuit 12, a first switch K1 and a second switch K2. The first driver control circuit 11 and the second driver control circuit 12 are both driver control circuits capable of forming a dead time as described above;

[0145] The third input terminal of the charging module in the first driver control circuit 11 accesses the conduction state signal in1 of the first switch.

[0146] The output terminal of the comparison module in the first driver control circuit 11 is directly or indirectly connected to the control pole of the second switch K2 to output a first control signal in1 for controlling the conduction of the second switch K2;

[0147] The third input terminal of the charging module in the second driver control circuit 12 accesses the conduction state signal in2 of the second switch.

[0148] The output terminal of the comparison module in the second driver control circuit 12 is directly or indirectly connected to the control pole of the first switch K1 to output a second control signal for controlling the conduction of the first switch K1;

[0149] After the first switch K1 is turned off, the first switch K1 is the current off switch, and the second switch K2 is the current to-be-conducted switch; after the second switch K2 is turned off, the second switch K2 is the current off switch, and the first switch K1 is the current to-be-conducted switch;

[0150] The first pole of the second switch K2 is connected to the second power supply, the second pole of the second switch K2 is connected to the first pole of the first switch K1; the second pole of the first switch K1 is connected to the ground.

[0151] The first driver control circuit 11 and the second driver control circuit 12 ensure that the first switch K1 and the second switch K2 are not turned on simultaneously, and the interval time between non-simultaneous turn-ons is greater than the above dead time.

[0152] Please refer to Figure 13 , in one embodiment, the driver further includes a first logic circuit 13 and a second logic circuit 14;

[0153] The first input terminal of the first logic circuit 13 is connected to the output terminal of the first driver control circuit 11, the second input terminal of the first logic circuit 13 is connected to the conduction state signal in2 of the second switch, and the output terminal of the first logic circuit 13 is directly or indirectly connected to the second switch K2 to control the second switch K2 to conduct according to the conduction state signal in2 of the second switch and the first control signal in1_dt;

[0154] The first input terminal of the second logic circuit 14 is connected to the output terminal of the second driver control circuit 12, the second input terminal of the second logic circuit 14 is connected to the conduction state signal in1 of the first switch, and the output terminal of the logic circuit 14 is directly or indirectly connected to the first switch K1 to control the first switch K1 to conduct according to the conduction state signal in1 of the first switch and the second control signal in2_dt.

[0155] In an example, the driver further includes a first amplifier U3 and a second amplifier U4. The input terminal of the first driver U3 is connected to the output terminal of the first logic circuit 13 to amplify the signal out1 output by the first logic circuit 13 to drive the second switch K2 to conduct;

[0156] The input terminal of the second driver U4 is connected to the output terminal of the second logic circuit 14 to amplify the signal out2 output by the second logic circuit 14 to drive the first switch K1 to conduct.

[0157] Please refer to Figure 14 , in one embodiment, the first logic circuit 13 includes a first NOT gate U5 and a first AND gate U6, and the second logic circuit includes a second NOT gate U7 and a second AND gate U8;

[0158] The input terminal of the first NOT gate U5 is connected to the output terminal of the comparison module in the first driver control circuit 11, and the output terminal of the first NOT gate U5 is connected to the first input terminal of the first AND gate U6 to invert the first control signal in1_dt output by the first driver control circuit 11 and then feedback it to the first input terminal of the first AND gate U6;

[0159] The second input terminal of the first AND gate U6 is connected to the conduction state signal in2 of the second switch, and the output terminal of the first AND gate is directly or indirectly connected to the control electrode of the second switch to output a logic signal out2 for controlling the conduction of the second switch;

[0160] The second NOT gate U7 is connected to the output terminal of the comparison module in the second driver control circuit 12, and the output terminal of the second NOT gate U7 is connected to the first input terminal of the second AND gate U8 to invert the second control signal in2_dt output by the second driver control circuit 12 and feedback it to the first input terminal of the second AND gate U8;

[0161] The second input terminal of the second AND gate U8 is connected to the conduction state signal in1 of the first switch, and the output terminal of the second AND gate U8 is directly or indirectly connected to the control electrode of the first switch K1 to output a logic signal out1 for controlling the conduction of the first switch.

[0162] Please refer to Figure 15 , in an embodiment of the present invention, the signal waveforms output at several key positions of the driver.

[0163] Among them, the signal waveform corresponding to in1 is the waveform of the conduction state signal of the first switch, and the signal waveform corresponding to in2 is the waveform of the conduction state signal of the second switch;

[0164] The signal waveform corresponding to in1_dt is the waveform of the first control signal output by the comparison module of the first driver control circuit 11, and the signal waveform corresponding to in2_dt is the waveform of the second control signal output by the comparison module of the second driver control circuit 12;

[0165] The signal waveform corresponding to out1 is the signal waveform output by the first logic circuit 13 and can control the conduction of the second switch K2; the signal waveform corresponding to out2 is the signal waveform output by the second logic circuit 14 and can control the conduction of the first switch K1.

[0166] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A driver control circuit capable of forming a dead time, characterized in that, Comprising: A reference voltage operational amplifier, a transistor module, a charging module, a comparison module, and a capacitor; A first input terminal of the reference voltage operational amplifier is connected to an original reference voltage, an output terminal of the reference voltage operational amplifier is connected to a control terminal of the transistor module, a first terminal of the transistor module is connected to a first power supply, and a second terminal of the transistor module is connected to a second input terminal of the reference voltage operational amplifier; The output terminal of the reference voltage operational amplifier is further connected to a first input terminal of the charging module and a first input terminal of the comparison module. The reference voltage operational amplifier is configured to: generate a target reference voltage based on the original reference voltage, and feedback the target reference voltage to the comparison module and the charging module; A second input terminal of the charging module is connected to the first power supply, a third input terminal of the charging module is connected to a conduction state signal of a current turn-off switch, the conduction state signal represents a conduction state of a corresponding switch, and the current turn-off switch is the currently turned-off switch among two switches connected in series in a driver; The charging module is connected to a first terminal of the capacitor. The charging module is configured to: charge the capacitor based on the target reference voltage and the conduction state signal; The first terminal of the capacitor is connected to a second input terminal of the comparison module, and a second terminal of the capacitor is grounded; An output terminal of the comparison module is directly or indirectly connected to a current turn-on switch to be turned on. The comparison module is configured to directly or indirectly control the current turn-on switch to be turned on when a voltage of the capacitor is higher than the target reference voltage, so as to form a dead time, and the dead time is less than a time period after the current turn-off switch is turned off and before the current turn-on switch to be turned on is turned on. The current turn-on switch to be turned on is the currently turn-on switch among two switches connected in series in a driver.

2. The driver control circuit capable of forming a dead time according to claim 1, characterized in that, The charging module includes a first charging unit and a second charging unit; the first charging unit is connected to the first power supply via the second charging unit, the first charging unit is further connected to the conduction state signal, the second charging unit is further connected to the target reference voltage, and the first terminal of the capacitor is connected between the first charging unit and the second charging unit; The first charging unit is configured to: charge the capacitor when the current turn-off switch is in a conduction state, so that the voltage of the capacitor is at a base voltage, and stop charging the capacitor when the current turn-off switch is in a turn-off state; The second charging unit is configured to: charge the capacitor when the first charging unit stops charging the capacitor, so that the voltage of the capacitor reaches a saturation voltage; the base voltage is lower than the target reference voltage, and the saturation voltage is higher than the target reference voltage.

3. The driver control circuit capable of forming a dead time according to claim 2, characterized in that, The capacitor is a gate oxide capacitor, and the base voltage matches a threshold voltage of the gate oxide capacitor.

4. The driver control circuit capable of forming a dead time according to claim 2, characterized in that, The first charging unit includes a first charging transistor and a second charging transistor; A control electrode of the first charging transistor is connected to the conduction state signal, a first electrode of the first charging transistor is connected to a second electrode of the second charging transistor, and the second electrode of the second charging transistor is grounded; The control electrode and the first electrode of the second charging transistor are connected to the first end of the capacitor.

5. The driver control circuit capable of forming a dead time according to claim 4, characterized in that, The first charging unit further includes a first designated transistor, and the minimum withstand voltage between the first electrode and the second electrode of the first designated transistor is higher than the maximum withstand voltage between the first electrode and the second electrode of any one of the charging transistors; The control electrode of the first designated transistor is connected to the first end of the capacitor, the first electrode of the first designated transistor is connected to the first electrode of the first charging transistor, and the second electrode of the first designated transistor is connected to the second electrode of the second charging transistor.

6. The driver control circuit capable of forming a dead time according to claim 2, characterized in that, The second charging unit includes a third charging transistor, a fourth charging transistor, and a fifth charging transistor. The control electrode of the third charging transistor is connected to the output terminal of the reference voltage operational amplifier, the first electrode of the third charging transistor is connected to the control electrode and the first electrode of the fourth charging transistor, and the second electrode of the third charging transistor is connected to an external resistor. The second electrode of the fourth charging transistor is connected to the first power supply, and the control electrode of the fourth charging transistor is connected to the control electrode of the fifth charging transistor. The first electrode of the fifth charging transistor is connected to the first end of the capacitor, and the second electrode of the fifth charging transistor is connected to the first power supply.

7. The driver control circuit capable of forming a dead time according to claim 6, characterized in that, The second charging unit further includes a sixth charging transistor. The control electrode of the sixth charging transistor is connected to the control electrode of the fourth charging transistor, and the first electrode of the sixth charging transistor is connected to the first power supply.

8. The driver control circuit capable of forming a dead time according to claim 6, characterized in that, The second charging unit further includes a second designated transistor, and the minimum withstand voltage between the first electrode and the second electrode of the second designated transistor is higher than the maximum withstand voltage between the first electrode and the second electrode of any one of the charging transistors; The control electrode of the second designated transistor is connected to the control electrode of the third charging transistor, the first electrode of the second designated transistor is connected to the external resistor, and the second electrode of the second designated transistor is connected to the second electrode of the third charging transistor.

9. The driver control circuit capable of forming a dead time according to claim 1, characterized in that, A first current source is further included. The first end of the first current source is connected to the second input terminal of the reference voltage operational amplifier, and the second end of the first current source is connected to ground.

10. The drive control circuit capable of forming a dead time according to claim 1, wherein, The transistor module includes a seventh transistor and a third designated transistor, and the minimum withstand voltage between the first electrode and the second electrode of the third designated transistor is higher than the maximum withstand voltage between the first electrode and the second electrode of any one of the charging transistors; The control electrode of the seventh transistor is connected to the output terminal of the reference voltage operational amplifier, the first electrode of the seventh transistor is connected to the first power supply, and the second electrode of the seventh transistor is connected to the second electrode of the third designated transistor. The control electrode of the third designated transistor is connected to the output terminal of the reference voltage operational amplifier, and the first electrode of the third designated transistor is connected to the second input terminal of the reference voltage operational amplifier.

11. The drive control circuit capable of forming a dead time according to claim 1, wherein, The comparison module includes a comparator. The first input terminal of the comparator is connected to the output terminal of the reference voltage operational amplifier, the second input terminal of the voltage comparator is connected to the charging module, and the output terminal of the comparator is directly or indirectly connected to the currently to-be-conducted switch.

12. The drive control circuit capable of forming a dead time according to any one of claims 1 to 11, wherein, It further includes a bias module, with the first end of the bias module connected to the charging module and the second end of the bias module connected to the comparison module; The bias module is used to adjust the delay time of the comparison module according to the charging speed at which the charging module charges the capacitor.

13. The drive control circuit capable of forming a dead time according to claim 12, wherein, The bias module includes a first bias transistor, a second bias transistor, and a second current source; The first pole and the control pole of the first bias transistor are connected to the charging module, the control pole of the first bias transistor is connected to the control pole of the second bias transistor, and the second pole of the first bias transistor is connected to ground; The first pole of the second bias transistor is connected to the comparison module, and the second pole of the second bias transistor is connected to ground; Both ends of the second current source are respectively connected to the third input terminal of the comparison module and ground.

14. A drive, wherein, It includes a first driver control circuit, a second driver control circuit, a first switch, and a second switch. Both the first driver control circuit and the second driver control circuit are driver control circuits capable of forming a dead time as described in any one of claims 1 to 13; The third input terminal of the charging module in the first driver control circuit accesses the on-state signal of the first switch; the output terminal of the comparison module in the first driver control circuit is directly or indirectly connected to the control pole of the second switch to output a first control signal for controlling the conduction of the second switch; The third input terminal of the charging module in the second driver control circuit accesses the on-state signal of the second switch; The output terminal of the comparison module in the second driver control circuit is directly or indirectly connected to the control pole of the first switch to output a second control signal for controlling the conduction of the first switch; After the first switch is turned off, the first switch is the currently turned-off switch, and the second switch is the currently to-be-conducted switch; after the second switch is turned off, the second switch is the currently turned-off switch, and the first switch is the currently to-be-conducted switch; The first pole of the second switch is connected to the second power supply, the second pole of the second switch is connected to the first pole of the first switch; the second pole of the first switch is connected to ground.

15. The drive according to claim 14, wherein, It further includes a first logic circuit and a second logic circuit; The first input terminal of the first logic circuit is connected to the output terminal of the first driver control circuit, the second input terminal of the first logic circuit is connected to the on-state signal of the second switch, and the output terminal of the first logic circuit is directly or indirectly connected to the second switch to control the conduction of the second switch according to the on-state signal of the second switch and the first control signal; The first input terminal of the second logic circuit is connected to the output terminal of the second driver control circuit, the second input terminal of the second logic circuit is connected to the on-state signal of the first switch, and the output terminal of the logic circuit is directly or indirectly connected to the first switch to control the conduction of the first switch according to the on-state signal of the first switch and the second control signal.

16. The drive according to claim 15, wherein, The first logic circuit includes a first NOT gate and a first AND gate, and the second logic circuit includes a second NOT gate and a second AND gate; The input terminal of the first NOT gate is connected to the output terminal of the comparison module of the first driver control circuit, and the output terminal of the first NOT gate is connected to the first input terminal of the first AND gate to invert the first control signal and feedback it to the first input terminal of the first AND gate; The second input terminal of the first AND gate receives the conduction state signal of the second switch, and the output terminal of the first AND gate is directly or indirectly connected to the control electrode of the second switch to output a logic signal for controlling the conduction of the second switch; The second NOT gate is connected to the output terminal of the comparison module of the second driver control circuit, and the output terminal of the second NOT gate is connected to the first input terminal of the second AND gate to invert the second control signal and feedback it to the first input terminal of the second AND gate; The second input terminal of the second AND gate receives the conduction state signal of the first switch, and the output terminal of the second AND gate is directly or indirectly connected to the control electrode of the first switch to output a logic signal for controlling the conduction of the first switch.

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