Method and device for implementing high-speed parallel signal processing in Galois field encoder

Abstract

The present invention provides a method and device for implementing high-speed parallel signal processing in a Galois field encoder. The method comprises: pre-constructing a parallel structure based on a lookup table corresponding to the Galois field encoder; obtaining input information to be encoded based on the parallel structure; determining a corresponding lookup table based on the type of Galois field channel coding; and performing parallel Galois field coding processing on the information to be encoded based on pre-configured corresponding coding parameters and the lookup table to obtain a corresponding coding result. The method for implementing high-speed parallel signal processing in a Galois field encoder disclosed by the present invention can utilize a general parallel structure, save logic resources, avoid repetitive design work, speed up development progress, and simultaneously calculate the coding results of multiple consecutive input information. Storage resources are exchanged for an increase in coding speed, which greatly shortens the coding time and effectively improves the efficiency of Galois field channel coding.

Description

Technical Field

[0001] The present invention relates to the field of computer applications, and more particularly to a method and apparatus for implementing high-speed parallel signal processing in a Galois field encoder. Furthermore, the present invention also relates to an electronic device and a non-transitory computer-readable storage medium. Background Art

[0002] During data transmission and storage, Galois field (i.e., finite field) channel codes such as CRC (Cyclic Redundancy Check), Gold sequences, M sequences, CC (Convolutional Code) codes, and Turbo codes are widely used in wireless communications. In recent years, with the increasing demand for high-speed data transmission in wireless communications, the need to increase coding speed has led to the adoption of parallel coding. However, 3GPP standards 38.211 and 38.212 define CRC, M sequences, Gold sequences, Turbo codes, and CC convolutional codes as LFSR (Linear Feedback Shift Register) algorithms, which are iterative algorithms that rely on feedback data. According to the standards, each time slot can only process one bit of data, making parallelization impossible. However, with the growing demand for high-speed data transmission, the peak downlink rate for 5G has reached 20 Gbit / s. As a fundamental physical layer technology, channel coding will have both direct and indirect impacts on various performance indicators of 5G systems. Therefore, parallelization of the LFSR problem is imperative, and it is necessary to achieve high parallelization in order to prepare for the more demanding 6G standards in the future.

[0003] Currently, a common parallel coding method uses transforms of generator polynomials to parallelize the calculation of multiple bits of data. However, in this approach, each parallel path uses its own logic resources, resulting in an exponential increase in resources. Furthermore, each code requires its own generator polynomial. Conventional implementation methods require separate design and implementation for each code, increasing design time and reducing channel coding efficiency. Therefore, designing a high-speed parallel signal processing solution for Galois field encoders that conserves logic resources while avoiding repetitive design work has become a key research topic in this field. Summary of the Invention

[0004] To this end, the present invention provides a method and device for implementing high-speed parallel signal processing in a Galois field encoder to solve the problems of high logical resource requirements and repetitive design work in the parallel encoding method in the prior art, which leads to slow coding efficiency and development progress.

[0005] The present invention provides a method for implementing high-speed parallel signal processing in a Galois field encoder, comprising: pre-constructing a parallel structure based on a lookup table corresponding to the Galois field encoder; obtaining input information to be encoded based on the parallel structure; determining a corresponding lookup table based on the type of Galois field channel coding; and performing parallel Galois field coding on the information to be encoded based on pre-configured corresponding coding parameters and the lookup table to obtain a corresponding encoding result.

[0006] Furthermore, the type of the Galois field channel coding includes at least one of cyclic redundancy check coding, GOLD sequence coding, M sequence coding, CC convolutional coding and Turbo coding.

[0007] Furthermore, the method for implementing high-speed parallel signal processing in the Galois field encoder also includes: performing preprocessing of selection and reordering before performing parallel operations on the information to be encoded; and performing post-processing of sorting and selecting output after performing parallel operations on the information to be encoded.

[0008] Furthermore, the method for implementing high-speed parallel signal processing in the Galois field encoder further includes: dividing the corresponding display lookup table in the parallel structure into a preset number of target areas; the target areas are respectively used to represent corresponding single-port memories; and assembling a corresponding number of the lookup tables corresponding to the single-port memories.

[0009] Furthermore, the performing parallel Galois field coding on the information to be coded specifically includes: performing XOR processing on the information to be coded corresponding to corresponding positions of matrix elements in the lookup table to complete parallel Galois field coding operation.

[0010] Correspondingly, the present invention also provides a device for implementing high-speed parallel signal processing in a Galois field encoder, comprising: a parallel structure construction unit, used to pre-construct a parallel structure based on a lookup table corresponding to the Galois field encoder; an information to be encoded acquisition unit, used to obtain input information to be encoded based on the parallel structure; a lookup table determination unit, used to determine the corresponding lookup table based on the type of Galois field channel coding; a parallel coding processing unit, used to perform parallel Galois field coding processing on the information to be encoded based on pre-configured corresponding coding parameters and the lookup table to obtain a corresponding coding result.

[0011] Furthermore, the type of the Galois field channel coding includes at least one of cyclic redundancy check coding, GOLD sequence coding, M sequence coding, CC convolutional coding and Turbo coding.

[0012] Furthermore, the device for implementing high-speed parallel signal processing in the Galois field encoder also includes: a preprocessing unit for performing preprocessing of selection and reordering before parallel operation is performed on the information to be encoded; and a post-processing unit for performing post-processing of sorting and selecting output after parallel operation is performed on the information to be encoded.

[0013] Furthermore, the device for implementing high-speed parallel signal processing in the Galois field encoder further includes: a lookup table storage unit, which is used to divide the corresponding display lookup table in the parallel structure into a preset number of target areas; the target areas are respectively used to represent corresponding single-port memories; and a corresponding number of lookup tables are assembled corresponding to the single-port memories.

[0014] Furthermore, the parallel coding processing unit is specifically configured to perform XOR processing on the information to be coded according to the corresponding positions of the matrix elements in the lookup table, thereby completing a parallel Galois field coding operation.

[0015] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and runnable on the processor, wherein when the processor executes the program, the steps of the method for implementing high-speed parallel signal processing in a Galois field encoder as described in any one of the above items are implemented.

[0016] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method for implementing high-speed parallel signal processing in a Galois field encoder as described in any one of the above.

[0017] The method for implementing high-speed parallel signal processing in a Galois field encoder according to the present invention can utilize a general parallel structure based on a lookup table to complete Galois field coding in parallel calculation in a lookup table manner, thereby saving logic resources, avoiding repetitive design work, and accelerating the development progress; it can use multiple small-scale lookup tables to achieve large-scale parallel calculations based on the characteristics of the generator matrix, and simultaneously calculate the coding results of multiple consecutive input information, using storage resources in exchange for an increase in coding speed, greatly shortening the coding time, and effectively improving the efficiency of Galois field channel coding. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 A schematic flow chart of a method for implementing high-speed parallel signal processing in a Galois field encoder provided by an embodiment of the present invention;

[0020] Figure 2 A schematic diagram of a parallel structure corresponding to a Galois field encoder provided in an embodiment of the present invention;

[0021] Figure 3 A schematic diagram of a calculation process for 60-bit data input in parallel to a member encoder based on a parallel structure according to an embodiment of the present invention;

[0022] Figure 4 A schematic diagram of the structure of a Turbo encoder provided in an embodiment of the present invention;

[0023] Figure 5 A schematic diagram of the structure of a member encoder in a Turbo encoder provided by an embodiment of the present invention;

[0024] Figure 6 A schematic diagram of structure a of a turbo encoder according to an embodiment of the present invention;

[0025] Figure 7 A schematic diagram of structure b of a turbo encoder according to an embodiment of the present invention;

[0026] Figure 8 A schematic structural diagram of a device for implementing high-speed parallel signal processing in a Galois field encoder provided by an embodiment of the present invention;

[0027] Figure 9 A schematic diagram of the physical structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without inventive effort shall fall within the scope of protection of the present invention.

[0029] The following describes in detail the embodiment of the method for implementing high-speed parallel signal processing in the Galois field encoder according to the present invention. Figure 1 As shown in FIG, it is a flow chart of a method for implementing high-speed parallel signal processing in a Galois field encoder provided by an embodiment of the present invention. The specific implementation process includes the following steps:

[0030] Step 101: pre-construct a parallel structure based on a lookup table corresponding to a Galois field encoder.

[0031] like Figure 2 and 3 As shown, in this embodiment of the present invention, a general parallel structure based on a lookup table is pre-built. The serial encoding of the Galois field encoder is converted into a one-dimensional calculation of the bit stream. After extracting the time information, it is converted into a two-dimensional matrix operation. At the same time, based on the characteristics of the generator polynomial, the large matrix operation is converted into a few small matrix operations. In the specific implementation process, it should be noted that, given a two-dimensional matrix, this two-dimensional matrix is ​​multiplied by a one-dimensional vector (input vector). The number of elements in the one-dimensional vector is equal to the number of columns in the two-dimensional matrix. The result is a one-dimensional vector (output vector) with the same number of elements as the number of rows in the two-dimensional matrix. Each input vector corresponds to a resulting output vector. All matching input vectors and output vectors are listed in a table, which is the lookup table. The input vector is used as the RAM address and the output vector as the RAM storage content. The lookup table can be stored in the RAM, and the code is finally quickly calculated in parallel using the lookup table.

[0032] Step 102: Obtain input information to be encoded based on the parallel structure.

[0033] Step 103: Determine a corresponding lookup table based on the type of Galois field channel coding.

[0034] The types of Galois field channel coding include at least one of cyclic redundancy check (CRC), Gold sequence coding, M sequence coding, CC convolutional coding, and Turbo coding. Accordingly, it should be noted that CRC, Gold, and M sequence encoders are recursive structures with feedback lines; CC encoders are forward structures without feedback lines; and Turbo member encoders (recursive systematic convolutional code encoders) have two parts: a recursive structure with feedback and a forward structure without feedback. Both the recursive and forward structures are based on lookup tables and share the same principles. The only requirement is to select the feedback circuit according to the different coding types, and to represent the coding formulas for n consecutive moments in time using a matrix.

[0035] (1) The encoding result of the feedback structure is only related to the current input and the encoding output of the previous h (h is the order of the generator matrix) moments. For the encoding formula at each moment, the input c k+i = equal to the h+1 coded outputs from time k+i forward multiplied by the inverse of the feedback generator polynomial (g0m k+i +g1m k+i-1 +...+g h m k+i-h), express the formula of these n moments in a matrix. When the inverse of the polynomial is known, the polynomial inverse matrix can be obtained. In the specific implementation process, in order to facilitate the calculation, the initial value part of the matrix is ​​expanded by h rows to obtain the matrix A. (n+h)x(n+h) , so the feedback part encoding output is equal to the matrix A (n+h)x(n+h) The inverse of is multiplied by the input code. (2) For the encoding result d of the forward structure k+i With the current input m k+i And the input m at the previous h (h is the order of the generating matrix) moments k+i-1 ,...,m k+i-h Related, expressed as a matrix, the encoding result d k Equal to the forward part generating matrix B nx(n+h) Multiply by the feedback section's coded output m k In the specific implementation process, in order to facilitate the calculation, the initial value part of the matrix is ​​expanded to h rows, and the matrix B is obtained. (n+h)x(n+h) (3) For turbo with both feedback structure and forward structure, the matrix B (n+h)x(n+h) Multiply by matrix A (n+h)x(n+h) The inverse of the member encoder is obtained to obtain the generator matrix G (n+h)x(n+h) .

[0036] Step 104: Based on the pre-configured corresponding coding parameters and the lookup table, parallel Galois field coding is performed on the information to be coded to obtain a corresponding coding result.

[0037] The performing parallel Galois field coding on the information to be coded specifically includes performing XOR processing on the information to be coded corresponding to corresponding positions of matrix elements in the lookup table to complete parallel Galois field coding operations.

[0038] In the embodiment of the present invention, all the encoding results obtained can be expressed as the calculation of generating a matrix multiplied by an input code. The matrix operation is calculated by a lookup table, and the lookup tables corresponding to each matrix can be Table1, Table2...TableX respectively. In the specific implementation process, these lookup tables need to be stored in a group of SRAMs (single-port memories), and each lookup table corresponds to a corresponding area in an SRAM. When applied, the input bit data is used as an SRAM address query to obtain the table output. Each SRAM is equivalent to completing a small matrix multiplication. The addition and XOR of the Galois field operation are equivalent. The result of each lookup table SRAM corresponds to the corresponding position of the matrix element and performs XOR, which can complete the encoder operation.

[0039] The corresponding LUT (i.e., display lookup table) in the parallel structure is divided into a preset number of target areas; each target area is used to represent a corresponding single-port memory; and a corresponding number of lookup tables are installed in each single-port memory. It should be noted that the LUT is essentially a RAM. After the lookup table data is pre-written to the RAM, each input signal is equivalent to entering an address, looking up the table, finding the corresponding content, and then outputting it.

[0040] In addition, various encoders, in addition to lookup table calculations, also include data and initial value input, corresponding preprocessing (such as selection and reordering) before parallel operation of the information to be encoded, and corresponding post-processing (such as sorting, selection output, etc.) after parallel operation of the information to be encoded.

[0041] The following is a specific example of a Turbo encoder. Figure 4 The turbo encoder shown in FIG. 1 includes two identical member encoders and an interleaver, wherein the member encoders are as follows: Figure 5 shown.

[0042] In the specific implementation process, the initial values ​​in the registers can be set to D2, D1, and D0 respectively, and the input is c k . Figure 6 and 7 The encoder shown can be broken down into two parts as follows:

[0043] First, yes Figure 6 The structure of the turbo encoder shown in the figure is discussed in part a, and the output of this part is assumed to be m k , easy to get:

[0044]

[0045] By simple matrix multiplication, we can easily get:

[0046]

[0047] From formula (7-3), it is easy to get:

[0048]

[0049] set up

[0050] Since A is a lower triangular matrix and all diagonal elements are non-zero, the matrix A is invertible. Therefore, we have:

[0051] [D0 D1 D2 m k m k+1 … m k+n ]T =A -1 ×[D0 D1 D2 c k c k+1 … c k+n ] T (7-5)

[0052] In formula (7-5), A is only related to the structure of part a. Therefore, (7-5) shows that when the structure of part a is known, part a can process any bit in parallel and the output is m k sequence.

[0053] Then Figure 7 The structure of the Turbo encoder is discussed in part b, with the input being m k , the output is d k , easy to get:

[0054]

[0055] By simple matrix multiplication, we can easily get:

[0056]

[0057] Therefore, when the structure of part b is known, part b can realize parallel processing of any bits.

[0058] In summary, we can conclude that the structure of the Turbo encoder is known and can realize parallel processing of arbitrary bits.

[0059] Adding redundant parts to the matrix formula of formula (7-7) yields formula (7-8):

[0060] make

[0061] make

[0062] Among them, 0 4×60 Representing a 4-row, 60-column all-zero matrix, we have:

[0063]

[0064] When the degree of parallelism is 60, n=59 in formula (7-5), and formula (7-5) can be written as:

[0065] [D0 D1 D2 m k m k+1 … m k+59 ] T =A -1 ×[D0 D1 D2 c k c k+1 … c k+59 ]T (7-9)

[0066] Substituting formula (7-9) into formula (7-8) yields formula (7-10) as follows:

[0067]

[0068] Pick Divide G into columns:

[0069]

[0070] Among them, H1 to H16 and R1 to R8 are all 32×4 two-dimensional matrices, that is, they represent the corresponding lookup tables. 0 is a 32×4 all-zero matrix.

[0071] [D0 D1 D2 c k c k+1 c k+2 … c k+59 ] T The matrix is ​​divided into 1 3×1 matrix and 15 4×1 matrices by row. According to the matrix decomposition and multiplication principle (7-10), it can be written as follows:

[0072]

[0073] The final form of formula (7-11) is F1 32×4 ×P1 4×1 +F2 32×4 ×P2 4×1 +F3 32×4 ×P3 4×1 +…, the next step is to multiply these 23 two-dimensional matrices into 23 SRAMs, store the mapping relationship, and obtain the corresponding lookup tables: Table1, Table2, ...Table23.

[0074] In addition, the first matrix multiplication in formula (7-11) does not satisfy the form F 32×4 ×P 4×1 , so do the following:

[0075] Let M1′ 32×4 =[M1 32×3 0 32×1 ], M2′ 32×4 =[M2 32×3 0 32×1 ];

[0076] Use M1' and [0 0 0 0] T , [0 0 0 1] T , [0 0 1 0]T , [0 0 1 1] T , [0 1 0 0] T , ······, [1 1 1 1] T Table 24 can be obtained by multiplying these 16 linearly independent column vectors and transposing the results and arranging them in order.

[0077] Use M2' and [0 0 0 0] T , [0 0 0 1] T , [0 0 1 0] T , [0 0 1 1] T , [0 1 0 0] T , ······, [1 1 1 1] T Table 25 can be obtained by multiplying these 16 linearly independent column vectors and transposing the results and arranging them in order.

[0078] It should be noted that the above operations on M1 and M2 are equivalent to Substitute in. The last four digits on the left side of the equal sign (output) of formula (7-10) are m k+57 、m k+58 、m k+59 , 0, where the first three digits correspond to the first three initial values ​​used in the next cycle, and the last digit is fixed to 0. Later, in the structure of 7.3, we can find that m k+57 、m k+58 、m k+59 , 0 enters MUX and is used to query Table24 and Table25 except for the first round. That is to say, in actual use, D3=0 is a fixed value, and a column of all-zero matrices is added to M1 and M2. These two points will ensure and The results are completely consistent.

[0079] The 25 lookup tables are configured to 25 16×32 SRAMs. When applied, the 4-bit state information of the input is used as the SRAM address to query the encoding result output. Each SRAM is equivalent to completing a matrix multiplication in (7-11). The addition and XOR operations of the Galois field are equivalent. Therefore, it is only necessary to map the addition items in (7-11) to the corresponding SRAM results and design the corresponding XOR to complete the operation of (7-11).

[0080] The calculation process is as follows Figure 3As shown, each LUT is divided into eight regions, representing eight SRAMs (single-port memories). Each region table has T1, ..., T25, indicating that the SRAM is equipped with 25 lookup tables, Table1, ..., Table25. "Empty" or blank indicates that the SRAM has no tables (i.e., this SRAM region will not be used during the algorithm encoding process). The MUX module selects an initial value at the beginning (the standard defines the initial value as fixed at 0); otherwise, the output (the last four bits) of the TXOR0 module is selected. The TXOR1 module performs an XOR on the nine 32-bit input data and outputs the XOR result (32 bits). The TXOR0 module performs an XOR on the sixteen 32-bit input data and outputs the first 28 bits of the XOR result (32 bits). The last 4 bits are fed into the MUX module as the initial value for the next iteration.

[0081] The present invention proposes a method for quickly obtaining encoding results through a lookup table. Only multiple small lookup tables with the same 4-bit address are used, and the table is looked up once with 4 bits. All operations in the algorithm are Galois field operations. Through a limited and few steps, the encoding results of multiple consecutive input information (60 bits or more) are calculated simultaneously, which greatly shortens the encoding time and exchanges storage resources for increased encoding speed. It should be noted that the embodiments of the present invention are not limited to small lookup tables with 4-bit addresses and 4-bit lookup, and can also be small lookup tables with 8-bit addresses and 8-bit lookup, etc., which are not specifically limited here.

[0082] In the specific implementation process, the encoding calculation process is represented by a matrix. This matrix is ​​a regular sparse matrix. Each row is obtained by shifting the previous row right by one column, so the valid data of the matrix can be extracted. According to the repetitive characteristics of the matrix data blocks, large matrix operations are completed through the operations of a few small matrices. Finally, a small lookup table is used to quickly implement the calculation.

[0083] The present invention proposes a universal parallel structure based on a lookup table, which is applicable to cyclic redundancy check coding, GOLD sequence coding, M sequence coding, CC convolutional coding and Turbo coding in Galois field channel coding. The lookup table generation principle of these codes is the same. Different codes and parallelism correspond to different lookup tables. The corresponding coding calculation can be achieved by simply configuring the corresponding coding parameters and lookup tables.

[0084] The method for implementing high-speed parallel signal processing in a Galois field encoder described in an embodiment of the present invention can utilize a general parallel structure based on a lookup table to complete Galois field coding in parallel calculation in the form of a lookup table, thereby saving logic resources, avoiding repetitive design work, and accelerating the development progress; it can use multiple small-scale lookup tables according to the characteristics of the generating matrix to achieve large-scale parallel calculations, and simultaneously calculate the encoding results of multiple consecutive input information, using storage resources in exchange for an increase in encoding speed, greatly shortening the encoding time, and effectively improving the efficiency of Galois field channel coding.

[0085] Corresponding to the above-mentioned method for implementing high-speed parallel signal processing in a Galois field encoder, the present invention also provides a device for implementing high-speed parallel signal processing in a Galois field encoder. Since the embodiment of the device is similar to the above-mentioned method embodiment, the description is relatively simple. For relevant details, please refer to the description of the above-mentioned method embodiment. The embodiment of the device for implementing high-speed parallel signal processing in a Galois field encoder described below is only illustrative. Please refer to Figure 2 As shown in FIG, it is a schematic diagram of the structure of a device for implementing high-speed parallel signal processing in a Galois field encoder provided by an embodiment of the present invention. The device for implementing high-speed parallel signal processing in a Galois field encoder according to the present invention specifically includes the following parts:

[0086] A parallel structure construction unit 201 is used to pre-construct a parallel structure based on a lookup table corresponding to a Galois field encoder;

[0087] The to-be-encoded information acquiring unit 202 is configured to acquire input to-be-encoded information based on the parallel structure;

[0088] A lookup table determining unit 203, configured to determine a corresponding lookup table based on the type of Galois field channel coding;

[0089] The parallel coding processing unit 204 is configured to perform parallel Galois field coding on the information to be coded based on pre-configured corresponding coding parameters and the lookup table to obtain a corresponding coding result.

[0090] The high-speed parallel signal processing implementation device for a Galois field encoder described in an embodiment of the present invention can utilize a general parallel structure based on a lookup table to complete Galois field coding in parallel calculation in the form of a lookup table, thereby saving logical resources, avoiding repetitive design work, and accelerating the development progress; it can use multiple small-scale lookup tables to achieve large-scale parallel calculations based on the characteristics of the generating matrix, and simultaneously calculate the encoding results of multiple consecutive input information, using storage resources in exchange for an increase in encoding speed, greatly shortening the encoding time, and effectively improving the efficiency of Galois field channel coding.

[0091] Corresponding to the above-mentioned method for implementing high-speed parallel signal processing in a Galois field encoder, the present invention also provides an electronic device. Since the embodiment of the electronic device is similar to the above-mentioned method embodiment, the description is relatively simple. For relevant details, please refer to the description of the above-mentioned method embodiment. The electronic device described below is only exemplary. Figure 9 As shown, it is a schematic diagram of the physical structure of an electronic device disclosed in an embodiment of the present invention. The electronic device may include: a processor 901, a memory 902, and a communication bus 903, wherein the processor 901 and the memory 902 communicate with each other via the communication bus 903. The processor 901 can call the logic instructions in the memory 902 to execute a method for implementing high-speed parallel signal processing in a Galois field encoder, the method comprising: pre-constructing a parallel structure based on a lookup table corresponding to the Galois field encoder; obtaining input information to be encoded based on the parallel structure; determining a corresponding lookup table based on the type of Galois field channel coding; and performing parallel Galois field coding on the information to be encoded based on pre-configured corresponding coding parameters and the lookup table to obtain a corresponding coding result.

[0092] In addition, the logic instructions in the above-mentioned memory 902 can be implemented in the form of a software functional unit and can be stored in a computer-readable storage medium when sold or used as an independent product. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present invention. The aforementioned storage medium includes: various media that can store program code, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0093] On the other hand, an embodiment of the present invention also provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a computer, the computer can execute the high-speed parallel signal processing implementation method in the Galois field encoder provided by the above-mentioned method embodiments, the method including: pre-constructing a parallel structure based on a lookup table corresponding to the Galois field encoder; obtaining input information to be encoded based on the parallel structure; determining a corresponding lookup table based on the type of Galois field channel coding; and performing parallel Galois field coding processing on the information to be encoded based on the pre-configured corresponding coding parameters and the lookup table to obtain a corresponding coding result.

[0094] On the other hand, an embodiment of the present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, it is implemented to execute the high-speed parallel signal processing implementation method in the Galois field encoder provided by the above-mentioned embodiments. The method includes: pre-constructing a parallel structure based on a lookup table corresponding to the Galois field encoder; obtaining input information to be encoded based on the parallel structure; determining a corresponding lookup table based on the type of Galois field channel coding; and performing parallel Galois field coding processing on the information to be encoded based on the pre-configured corresponding coding parameters and the lookup table to obtain a corresponding coding result.

[0095] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.

[0096] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, or of course, by hardware. Based on this understanding, the essence of the above technical solution or the part that contributes to the existing technology can be embodied in the form of a software product. The computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or certain parts of the embodiments.

[0097] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A method for implementing high-speed parallel signal processing in a Galois field encoder, characterized in that: include: Pre-constructing a parallel structure based on a lookup table corresponding to the Galois field encoder, wherein the Galois field encoder serial encoding is converted into a two-dimensional matrix operation according to the one-dimensional calculation of the bit stream, and then the large matrix operation is converted into a small matrix operation to obtain the lookup table; Acquiring input information to be encoded based on the parallel structure; Determining a corresponding lookup table based on a type of Galois field channel coding; Based on the pre-configured corresponding encoding parameters and the lookup table, parallel Galois field encoding is performed on the information to be encoded to obtain a corresponding encoding result; it also includes: dividing the corresponding display lookup table in the parallel structure into a preset number of target areas; the target areas are respectively used to represent the corresponding single-port memories; and a corresponding number of lookup tables are assembled corresponding to the single-port memories; the parallel Galois field encoding of the information to be encoded specifically includes: performing XOR processing on the information to be encoded corresponding to the corresponding position of the matrix element through the lookup table to complete the parallel Galois field encoding operation.

2. The method for implementing high-speed parallel signal processing in a Galois field encoder according to claim 1, wherein: The type of the Galois field channel coding includes at least one of cyclic redundancy check coding, GOLD sequence coding, M sequence coding, CC convolutional coding and Turbo coding.

3. The method for implementing high-speed parallel signal processing in a Galois field encoder according to claim 1, wherein: Also includes: Performing gating and reordering preprocessing before performing parallel operations on the information to be encoded; Furthermore, after performing parallel operations on the information to be encoded, post-processing of sorting and selecting output is performed.

4. A device for implementing high-speed parallel signal processing in a Galois field encoder, characterized in that: include: A parallel structure construction unit is used to pre-construct a parallel structure based on a lookup table corresponding to the Galois field encoder, wherein the Galois field encoder serial encoding is converted into a two-dimensional matrix operation according to the one-dimensional calculation of the bit stream, and then the large matrix operation is converted into a small matrix operation to obtain the lookup table; An information-to-be-encoded acquiring unit, configured to acquire input information to be encoded based on the parallel structure; A lookup table determining unit, configured to determine a corresponding lookup table based on a type of Galois field channel coding; The parallel coding processing unit is used to perform parallel Galois field coding processing on the information to be encoded based on the pre-configured corresponding coding parameters and the lookup table to obtain a corresponding coding result.

5. The device for implementing high-speed parallel signal processing in a Galois field encoder according to claim 4, characterized in that: The type of the Galois field channel coding includes at least one of cyclic redundancy check coding, GOLD sequence coding, M sequence coding, CC convolutional coding and Turbo coding.

6. The device for implementing high-speed parallel signal processing in a Galois field encoder according to claim 4, characterized in that: Also includes: A pre-processing unit, configured to perform gating and reordering pre-processing before performing parallel operations on the information to be encoded; And, a post-processing unit is used for performing post-processing of sorting and selecting output after parallel operation is performed on the information to be encoded.

7. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the program, the steps of the method for implementing high-speed parallel signal processing in a Galois field encoder according to any one of claims 1 to 3 are implemented.

8. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method for implementing high-speed parallel signal processing in a Galois field encoder according to any one of claims 1 to 3 are implemented.

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