Storage control device, storage device and information processing system

Abstract

The states of the reference cells in the memory device are correctly managed. The first memory cell array includes a first reference cell that generates a reference potential of a sense amplifier. The second memory cell array includes a second reference cell that generates a reference potential of a sense amplifier. The state storage unit stores a state indicating the certainty of a hold value with respect to each of the first reference cell and the second reference cell. When writing to the first reference cell or the second reference cell is instructed, the write control unit controls the instructed writing based on the states with respect to the first reference cell and the second reference cell stored in the state storage unit.

Description

Technical Field

[0001] The present technology relates to a storage device, and more particularly to a storage device provided with a reference unit, a storage control device thereof, and an information processing system. Background Art

[0002] A method is known for determining the storage state of a memory cell using a reference cell that maintains a reference threshold when performing a read from a memory cell in a storage device. For example, in a storage device using a magnetic tunnel junction (MTJ) element, the values ​​of multiple reference cells are supplied to one input of a sense amplifier by generating an intermediate potential of potentials generated corresponding to logic levels "0" and "1" by a reference potential generating circuit. Here, due to thermal fluctuations caused by ambient temperature, the MTJ element has a characteristic of randomly exceeding the threshold, and this is called retention. In addition, the insulating layer forming the MTJ element has a film thickness, and there is a failure mode of dielectric breakdown, which is called durability. In the case where the data value of the reference cell does not match expectations due to the influence of such retention and durability, an incorrect value may be output from the sense amplifier. Therefore, for example, a semiconductor device is proposed that counts the number of times a reference cell is accessed, and checks whether the state of the reference cell falls within a predetermined distribution range when a specified number of times is reached (for example, see patent document 1).

[0003] Citation List

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2004-185745 Summary of the invention

[0006] Problems to be solved by the present invention

[0007] In the above conventional technology, when the number of times a reference cell is accessed reaches a specified number of times, if the state of the reference cell does not fall within a predetermined distribution range, the value is corrected. However, in this case, since only the number of accesses is used as a reference, time-dependent data retention characteristics such as retention cannot be handled. Therefore, there is a possibility that the state of the reference cell cannot be properly managed.

[0008] The present technology has been achieved in view of such circumstances, and an object thereof is to appropriately manage the state of a reference cell in a storage device.

[0009] Solution to the problem

[0010] The present technology is implemented to solve the above-mentioned problems, and its first aspect is a storage control device, a storage device, and an information processing system, which are provided with: a state storage section that stores a state indicating the certainty of a hold value for each of a first reference cell included in a first memory cell array and generating a reference potential of a sense amplifier and a second reference cell included in a second memory cell array and generating a reference potential of a sense amplifier; and a write control section that, when writing to either of the first reference cell and the second reference cell is instructed, controls the instructed writing based on the state about the first reference cell and the second reference cell stored in the state storage section. This brings about the effect of controlling the writing to the first reference cell and the second reference cell based on the state indicating the certainty of the value held in the first reference cell and the second reference cell.

[0011] Furthermore, in the first aspect, the write control section may perform writing of the first reference cell group and the second reference cell group, which respectively include the first reference cell and the second reference cell, as a unit, and the state storage section may store a state for each of the first reference cell group and the second reference cell group. This brings about the effect of controlling writing for each of the first reference cell group and the second reference cell group.

[0012] Furthermore, in the first aspect, when writing is performed on any one of the first reference cell and the second reference cell, the state storage unit can update the state of the reference cell on which the writing has been performed. This brings about the effect of updating the state according to the writing on the first reference cell and the second reference cell.

[0013] In addition, in the first aspect, when writing is performed on any one of the first reference cell and the second reference cell, the state storage unit can update the state of the reference cell according to the time elapsed from the writing. This brings about the effect of updating the state according to the time elapsed from the writing of the first reference cell and the second reference cell.

[0014] Furthermore, in the first aspect, a timer circuit that manages the time elapsed from writing may be further provided. This brings about the effect of updating the state triggered by the notification from the timer circuit.

[0015] Furthermore, in the first aspect, when the state of the first reference cell stored in the state storage unit satisfies a predetermined condition when writing to the first reference cell is instructed, the write control unit can control to avoid writing to the first reference cell. This brings about the effect of controlling to avoid unnecessary writing.

[0016] Furthermore, in the first aspect, when the state of the first reference cell stored in the state storage unit does not satisfy a predetermined condition when writing to the first reference cell is instructed, the write control unit may control writing to the first reference cell based on the state of the second reference cell stored in the state storage unit. This brings about the effect of controlling writing to the first reference cell based on the state of the second reference cell.

[0017] Furthermore, in the first aspect, in the case where the state of the first reference cell does not satisfy a predetermined condition and in the case where the state of the second reference cell satisfies another predetermined condition, the write control section can control the execution of writing to the first reference cell only when the value of the first reference cell read with reference to the reference potential generated from the second reference cell as a reference does not coincide with a predetermined read expected value. This brings about the effect of executing writing to the first reference cell only when the value of the first reference cell does not coincide with the read expected value.

[0018] In addition, in the first aspect, a determination circuit may be further provided, which determines whether the value of the first reference cell read with reference to the reference potential of the sense amplifier generated from the second reference cell is consistent with a predetermined read expected value. This brings about an effect of performing a consistency determination between the value of the first reference cell and the read expected value.

[0019] Furthermore, in the first aspect, when the state of the first reference cell does not satisfy a predetermined condition and when the state of the second reference cell does not satisfy another predetermined condition, the write control section can control to write to the first reference cell. This brings about the effect of controlling the writing to the first reference cell according to the state of the second reference cell.

[0020] Furthermore, in the first aspect, as the first reference unit and the second reference unit, for example, a resistance change memory element, and specifically, a magnetoresistance change memory element is assumed. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is a diagram showing a circuit configuration example of a storage device in an embodiment of the present technology.

[0022] Figure 2 is a diagram showing a configuration example of the memory cell array 110 in the embodiment of the present technology.

[0023] Figure 3 is a diagram showing a configuration example of the memory unit 111 in the embodiment of the present technology.

[0024] Figure 4 is a view showing a structural example of the MTJ element 10 in the embodiment of the present technology.

[0025] Figure 5 is a diagram showing an example of the flow of data in a read operation in the embodiment of the present technology.

[0026] Figure 6 is a diagram showing an example of a data flow in a write operation in the embodiment of the present technology.

[0027] Figure 7 is a diagram showing an example of a data flow in a read-modify-write operation in an embodiment of the present technology.

[0028] Figure 8 is a diagram showing a circuit configuration example of the reference cell write operation control circuit 191 in the embodiment of the present technology.

[0029] Fig. 9 is a diagram showing a process example of the reference cell write operation control circuit 191 in the embodiment of the present technology.

[0030] Fig.10 : is a view of a truth table showing an operation example of the reference cell write operation control circuit 191 in the embodiment of the present technology.

[0031] Fig.11 is a diagram showing an example of state transition of the reference cell write operation control circuit 191 in the embodiment of the present technology.

[0032] Fig.12 is a diagram showing a configuration example of an electronic device 600 to which the storage device in the embodiment of the present technology is applied. DETAILED DESCRIPTION

[0033] Modes for carrying out the present technology (hereinafter, referred to as embodiments) are described below. The description is given in the following order.

[0034] 1. Circuit configuration

[0035] 2. Write control

[0036] 3. Application Examples

[0037] <1. Circuit Configuration>

[0038] [Storage device]

[0039] Figure 1 is a diagram showing a circuit configuration example of a storage device in an embodiment of the present technology.

[0040] The storage device includes two memory cell arrays (#1 and #2) 110, each of which is provided with a row decoder 121, a word line driver 122, a reference potential generating circuit 130, and switches 141 and 142. In addition, the storage device is provided with a data selection circuit 150 corresponding to each column, a write driver 160, a sense amplifier 170, and a determination circuit 180. In addition, the storage device is provided with a control circuit 190 including a reference cell write operation control circuit 191, a timer circuit 192, and a reference cell master data holding section 193.

[0041] The memory cell array 110 is obtained by arranging memory cells in a two-dimensional matrix (array).

[0042] The row decoder 121 decodes the address to the memory cell array 110 to generate a row address in the memory cell array 110. The word line driver 122 is a driver that drives a word line (row) designated by the row decoder 121.

[0043] The reference potential generating circuit 130 is a circuit that generates a reference potential based on the value of a reference cell connected to a reference word line output from the memory cell array 110 .

[0044] The switch 141 is a bidirectional switch for switching the connection between the corresponding memory cell array 110 and the switch 142. The switch 141 selects one of the data value output from the corresponding memory cell array 110 and the data value of the reference potential generated by the corresponding reference potential generating circuit 130, and outputs it to the corresponding switch 142. In addition, the switch 141 supplies the data value output from the switch 142 to the corresponding memory cell array 110. Switch control of the switch 141 is performed based on an instruction from the control circuit 190.

[0045] The switch 142 is a bidirectional switch for switching the connection between the corresponding switch 141 and the corresponding write driver 160 and sense amplifier 170. The switch 142 selects a data value supplied from the corresponding write driver 160 and supplies it to the corresponding switch 141. In addition, the switch 142 selects a data value output from the corresponding switch 141 and supplies it to one input of the corresponding sense amplifier 170. Switch control of the switch 142 is performed based on an instruction from the control circuit 190.

[0046] The data selection circuit 150 selects one of the data value supplied from the outside and the data value of the reference cell main data holding section 193 , and supplies it to the corresponding write driver 160 .

[0047] The write driver (WD) 160 is a driver that drives the data value supplied from the data selection circuit 150 for writing into the memory cell array 110 .

[0048] The sense amplifier (SA) 170 is a sense amplifier that amplifies the data value output from the memory cell array 110 for output. The sense amplifier 170 is provided with two input terminals, the potential to be sensed output from the memory cell array 110 is input to one of the two input terminals, and the reference potential generated by the reference potential input circuit 130 is input to the other of the two input terminals. Therefore, the sense amplifier 170 amplifies the potential to be sensed with reference to the reference potential and outputs read data. The read data output from the sense amplifier 170 is supplied to the outside and input to the determination circuit 180.

[0049] The determination circuit 180 compares the output of the sense amplifier 170 with the data value of the reference cell main data holding section 193 to determine whether they are consistent with each other, so as to verify the data value of the reference cell of the memory cell array 110. The determination result made by the determination circuit 180 is supplied to the reference cell write operation control circuit 191.

[0050] The reference cell write operation control circuit 191 is a circuit that controls the write operation to the reference cell of the memory cell array 110. As described later, the reference cell write operation control circuit 191 stores a state indicating the certainty of the retention value of the reference cell of the memory cell array 110 and controls the write operation to the reference cell based on the state.

[0051] The timer circuit 192 is a timer that manages the elapsed time from writing to the reference cell of the memory cell array 110. When a predetermined elapsed time is detected by the timer circuit 192, the reference cell write operation control circuit 191 is notified of this.

[0052] The reference cell master data holding section 193 holds a master value used as a reference cell of the memory cell array 110. That is, the reference cell master data held in the reference cell master data holding section 193 is a read expected value for verifying the data value of the reference cell of the memory cell array 110 in the determination circuit 180. In addition, in the case where the reference cell of the memory cell array 110 is inappropriate, the reference cell master data is used as a data value when rewriting is performed. The reference cell master data holding section 193 can hold fixed values ​​of a high level and a low level, and can be formed by using a flip-flop, a fixed resistor, or the like.

[0053] [Memory cell array]

[0054] Figure 2is a diagram showing a configuration example of the memory cell array 110 in the embodiment of the present technology.

[0055] The memory cell array 110 is obtained by arranging the memory cells 111 in a two-dimensional matrix. The word line driver 122 drives the memory cells 111 in the memory cell array 110 for each word line in the row direction. In addition, source lines and bit lines are formed in the column direction to be connected in series with the respective memory cells 111.

[0056] The word lines of the memory cell array 110 include data word lines used as a normal data storage area and reference word lines used as reference cells. As described above, the reference cells are used to generate a reference potential when reading data.

[0057] Note that in this example, the reference word line is shown in the highest row of the memory cell array 110, but it may be arranged in any row. For example, it is desirable to arrange the reference word line in the center row of the memory cell array 110 from the viewpoint of parasitic resistance.

[0058] Figure 3 is a diagram showing a configuration example of the memory unit 111 in the embodiment of the present technology.

[0059] Here, a spin transfer torque random access memory (STT-MRAM) is described as an example. The STT-MRAM is a memory that uses a tunnel magnetoresistive element (MTJ element) as a resistance change element as a memory cell and stores logic levels "0" and "1" by utilizing the fact that the resistance value changes due to the tunnel magnetoresistive effect (TMR effect).

[0060] The memory cell 111 has a one-transistor-one-resistor configuration in which the MTJ element 10 and the MOS transistor 20 are connected in series. The MOS transistor 20 may be a negative channel metal oxide semiconductor (NMOS) or a positive channel metal oxide semiconductor (PMOS).

[0061] Figure 4 is a view showing a structural example of the MTJ element 10 in the embodiment of the present technology.

[0062] The MTJ element 10 has a configuration in which two magnetic layers are bonded to the upper and lower sides of an insulating layer 12, one of the two magnetic layers is referred to as a free layer 11, and the other is referred to as a reference layer 13. When the magnetization directions of the free layer 11 and the reference layer 13 are the same, for example, they are in a low resistance state and are associated with a logic level "0" of stored data. In addition, when the magnetization directions of the free layer 11 and the reference layer 13 are opposite to each other, for example, they are in a high resistance state and are associated with a logic level "1" of stored data.

[0063] The storage data of the MTJ element 10 is inverted by applying a current to the MTJ element 10. That is, by determining the magnetization direction of the free layer 11 depending on whether the current I is applied in the direction from the drain terminal D to the source terminal S or the current I is applied in the direction from the source terminal S to the drain terminal D, any one of the logic levels "0" and "1" is stored.

[0064] [operate]

[0065] Figure 5 is a diagram showing an example of the flow of data in a read operation in the embodiment of the present technology.

[0066] In this example, the case where the data of memory cell array #2 is read with reference to the reference cell of memory cell array #1 is described. Note that in the case where the data of memory cell array #1 is read with reference to the reference cell of memory cell array #2, the basic operation is similar except that the relationship between the two is reversed.

[0067] The value of the reference cell of the reference word line of the memory cell array #1 is input to the reference potential generating circuit 130. The reference potential generating circuit 130 generates a reference potential based on the value of the reference cell output from the memory cell array #1. The generated reference potential is supplied to one input terminal of the sense amplifier 170 via switches 141 and 142.

[0068] The data value of the data word line of the memory cell array # 2 is supplied to the other input terminal of the sense amplifier 170 via the switches 141 and 142 .

[0069] The sense amplifier 170 amplifies the data value supplied to one input terminal with reference to the reference potential supplied to the other input terminal, and outputs read data.

[0070] Figure 6 is a diagram showing an example of a data flow in a write operation in the embodiment of the present technology.

[0071] In this example, a case where data is written into memory cell array #2 is described. Write data supplied from the outside is selected by data selection circuit 150 and driven by write driver 160. The output of write driver 160 is supplied to memory cell array #2 via switches 142 and 141, and writing is performed.

[0072] Note that in the case of writing data into the memory cell array #1, the output of the write driver 160 is supplied to the memory cell array #1 by switching the switches 142 and 141.

[0073] Figure 7is a diagram showing an example of a data flow in a read-modify-write operation in an embodiment of the present technology.

[0074] As described later, in this embodiment, reading is performed to verify the data value of the reference cell, and writing is performed when the output of the sense amplifier 170 is inconsistent with the read expected value. This operation is called read modify write (RMW). In this example, the reference cell of the memory cell array #2 is verified under the assumption that the data of the reference cell of the memory cell array #1 is certain. That is, as in the normal reading described above, the data value of the reference cell of the memory cell array #2 is read with the reference cell of the memory cell array #1 as the reference. The output of the sense amplifier 170 at this time is supplied to the corresponding determination circuit 180. In addition, the reference cell master data maintained in the reference cell master data holding unit 193 is supplied to the determination circuit 180. The determination circuit 180 reports the determination result to the reference cell write operation control circuit 191.

[0075] As a result of determination by the determination circuit 180 , when the output of the sense amplifier 170 coincides with the reference cell main data, the reference cell write operation control circuit 191 controls to prevent writing from being performed on the reference cell of the memory cell array # 2 .

[0076] On the other hand, in the case where the output of the sense amplifier 170 does not coincide with the reference cell main data, the reference cell write operation control circuit 191 supplies the reference cell main data to the write driver 160 via the data selection circuit 150. Then, the reference cell write operation control circuit 191 controls to write the reference cell main data into the reference cell of the memory cell array #2 via the switches 142 and 141.

[0077] <2. Write Control>

[0078] [Reference cell write operation control circuit]

[0079] Figure 8 is a diagram showing a circuit configuration example of the reference cell write operation control circuit 191 in the embodiment of the present technology.

[0080] The reference cell write operation control circuit 191 is provided with a write operation control circuit #1 (210) that manages the state of the reference cell of the memory cell array #1 and a write operation control circuit #2 (220) that manages the state of the reference cell of the memory cell array #2. The write operation control circuit #1 is provided with a state storage section 211 and a write control section 212, and the write operation control circuit #2 is provided with a state storage section 221 and a write control section 222.

[0081] The state storage section 211 stores a state indicating the certainty of the value held in the reference cell of the memory cell array #1. The state storage section 221 stores a state indicating the certainty of the value held in the reference cell of the memory cell array #2. The output TIMER of the timer circuit 192 is input to the state storage sections 211 and 221. In addition, the outputs of the write control sections 212 and 222 are input to the state storage sections 211 and 221, respectively. Each of the state storage sections 211 and 221 outputs the values ​​of REG1 and REG2.

[0082] Assuming a 2-bit value obtained by sequentially arranging the values ​​of REG1 and REG2, "00" means that the data value held in the corresponding reference cell is uncertain. In addition, "11" means the hold time from writing to the corresponding reference cell. "01" means an intermediate state.

[0083] The write control section 212 controls the write operation to the reference cell of the memory cell array #1. The write control section 222 controls the write operation to the reference cell of the memory cell array #2. REG1 of the state storage section 211 and REG1 and REG2 of the state storage section 221 are input to the write control section 212. REG1 of the state storage section 221 and REG1 and REG2 of the state storage section 211 are input to the write control section 222. Each of the write control sections 212 and 222 outputs the values ​​of EW and RWM.

[0084] EW indicates whether to perform forced writing on the reference cell of the corresponding memory cell array. For example, when EW is "1", forced writing is performed, and when EW is "0", forced writing is not performed.

[0085] RWM indicates whether to perform read-modify-write on the reference cell of the corresponding memory cell array. For example, when RWM is "1", read-modify-write is performed, and when RWM is "0", read-modify-write is not performed.

[0086] The writing timing to the reference cell may be any timing. In addition, in order to suppress the influence on the system performance, writing may be performed on a reference cell of an array different from the accessed data cell when the writing operation is performed on the data cell. In addition, depending on the array partitioning method, writing may be performed on a reference cell of an array that is not accessed when the reading operation of the data cell is performed.

[0087] [process]

[0088] Fig. 9 is a diagram showing a process example of the reference cell write operation control circuit 191 in the embodiment of the present technology.

[0089] Here, when a write command is issued to a reference cell of the memory cell array 110, the memory cell array is referred to as a local array, and the other memory cell arrays are referred to as other arrays. Note that the write command to the reference cell may be an explicit command from the host computer, or may be an internal command generated in the storage device in response to a data write command from the host computer. That is, writing to the reference cell may also be performed by taking advantage of writing to the data cell. In addition, maintenance (refresh) of data values ​​may be performed at regular timing using an internal timer regardless of the host computer. In addition, in the case of an explicit command issued from the host computer, it may be issued as part of an initial sequence when the power is turned on, for example.

[0090] When a write command is issued to the reference cell of the local array (step S911: Yes), write control is performed by the following determination: If REG1 and REG2 of the state storage unit corresponding to the local array are "11" (step S912: Yes), it is in the retention time of the reference cell, so writing to the reference cell of the local array is avoided (NOP) (step S914).

[0091] If REG1 and REG2 of the state storage unit corresponding to the local array are not "11" (step S912: No), write control is performed based on REG1 and REG2 of the state storage unit corresponding to the other array. If REG1 and REG2 of the state storage unit corresponding to the other array are "00" (step S913: Yes), the data value of the reference cell of the other array is uncertain and is not suitable for the application of generating the reference potential, so forced writing (EW) is performed on the reference cell of the local array without verification (step S915). Then, REG1 and REG2 of the state storage unit corresponding to the local array are set to "11" (step S918).

[0092] On the other hand, if REG1 and REG2 of the state storage unit corresponding to the other array are not "00" (step S913: No), the reference cell of the other array is used to generate the reference potential, and the reference cell of the local array is read to perform a read-modify-write (RMW) operation (step S916). That is, if the read value is consistent with the read expected value, it is controlled to avoid performing writing to the reference cell of the local array. On the other hand, if this is inconsistent with the read expected value, it is controlled to perform writing to the reference cell of the local array. At this time, in the case of performing writing to the reference cell of the local array (step S917: Yes), REG1 and REG2 of the state storage unit corresponding to the local array are set to "11" (step S918).

[0093] [Truth table]

[0094] Fig.10 : is a view of a truth table showing an operation example of the reference cell write operation control circuit 191 in the embodiment of the present technology.

[0095] In this example, operation at the time of reference cell writing is shown for a combination of REG1 and REG2 of the state storage unit 211 corresponding to the memory cell array #1 (ARY1) and REG1 and REG2 of the state storage unit 221 corresponding to the memory cell array #2 (ARY2).

[0096] In case #1, both of them have REG1 and REG2 of "00", and this means that the data values ​​in the reference cells of both memory cell arrays #1 and #2 are uncertain. At this time, when a write command is issued to the reference cell of memory cell array #1, a forced write (EW) operation of the expected value is performed on the reference cell of memory cell array #1 without checking the certainty of the data in the reference cell of memory cell array #2. The same applies to the following case: a write command is issued to the reference cell of memory cell array #2, and a forced write (EW) operation of the expected value is performed on the reference cell of memory cell array #2.

[0097] In case #2, REG1 and REG2 of memory cell array #2 are "01" compared to case #1. Therefore, in the case where a write command is issued to the reference cell of memory cell array #1, a reference potential is generated using the reference cell of memory cell array #2, and the reference cell of memory cell array #1 is read to perform a read-modify-write (RMW) operation. On the other hand, in the case where a write command is issued to the reference cell of memory cell array #2, a forced write (EW) operation of an expected value is performed as in case #1.

[0098] In case #3, compared with case #2, REG1 and REG2 of memory cell array #2 are "11". Therefore, in the case where a write command is issued to the reference cell of memory cell array #2, control is performed to avoid writing (NOP) to the reference cell of memory cell array #2. On the other hand, in the case where a write command is issued to the reference cell of memory cell array #1, a read-modify-write (RMW) operation is performed as in case #2.

[0099] In case #4, compared to case #1, REG1 and REG2 of memory cell array #1 are "01". Therefore, in the case where a write command is issued to the reference cell of memory cell array #2, a reference potential is generated using the reference cell of memory cell array #1, and the reference cell of memory cell array #2 is read to perform a read-modify-write (RMW) operation. On the other hand, in the case where a write command is issued to the reference cell of memory cell array #1, a forced write (EW) operation of an expected value is performed as in case #1.

[0100] In case #5, compared with case #4, REG1 and REG2 of memory cell array #2 are "01". Therefore, in the case where a write command is issued to the reference cell of memory cell array #1, a reference potential is generated using the reference cell of memory cell array #2, and a read-modify-write (RMW) operation is performed by reading the reference cell of memory cell array #1. On the other hand, in the case where a write command is issued to the reference cell of memory cell array #2, a read-modify-write (RMW) operation is performed as in case #4.

[0101] In case #6, compared with case #5, REG1 and REG2 of memory cell array #2 are "11". Therefore, in the case where a write command is issued to the reference cell of memory cell array #2, control is performed to avoid writing (NOP) to the reference cell of memory cell array #2. On the other hand, in the case where a write command is issued to the reference cell of memory cell array #1, a read-modify-write (RMW) operation is performed as in case #5.

[0102] In case #7, compared to case #1, REG1 and REG2 of memory cell array #1 are "11". Therefore, in the case where a write command is issued to the reference cell of memory cell array #1, control is performed to avoid writing (NOP) to the reference cell of memory cell array #1. On the other hand, in the case where a write command is issued to the reference cell of memory cell array #2, the reference cell of memory cell array #1 is used to generate a reference potential, and the reference cell of memory cell array #2 is read to perform a read-modify-write (RMW) operation.

[0103] In case #8, compared to case #7, REG1 and REG2 of memory cell array #2 are "01". Therefore, in the case where a write command is issued to the reference cell of memory cell array #2, the reference cell of memory cell array #1 is used to generate a reference potential, and the reference cell of memory cell array #2 is read to perform a read-modify-write (RMW) operation. On the other hand, in the case where a write command is issued to the reference cell of memory cell array #1, control is performed to avoid writing (NOP) to the reference cell of memory cell array #1 as in case 7.

[0104] In case #9, both of them have REG1 and REG2 "11", which means that the data value in the reference cell of both memory cell arrays #1 and #2 is in the retention time. Therefore, even in the case where a write command is issued to the reference cell of memory cell array #1 or #2, it is controlled to avoid executing write (NOP).

[0105] Note that although nine states are assumed using two registers REG1 and REG2 , the number of registers is not limited, and a required number of registers can be appropriately used.

[0106] [State Transition]

[0107] Fig.11 is a diagram showing an example of state transition of the reference cell write operation control circuit 191 in the embodiment of the present technology.

[0108] In this example, transition examples between the states of the above-mentioned cases #1 to #9 are shown. With regard to the lines between the states, the solid line indicates the case where a write command is issued to the reference cell of the memory cell array #1, and the dotted line indicates the case where a write command is issued to the reference cell of the memory cell array #2. In addition, the dot-dash line indicates a state transition caused by a notification from the timer circuit 192 due to the passage of time.

[0109] In the case of performing writing to the reference cell, the corresponding REG1 and REG2 are set to "11". Then, every time the timer circuit 192 gives a notification of the elapse of a certain time, the state changes from "11" to "01" and from "01" to "00". Writing to the reference cell is controlled according to the state changed in this way.

[0110] <3. Application Examples>

[0111] Fig.12 is a diagram showing a configuration example of an electronic device 600 to which a storage device according to an embodiment of the present technology is applied.

[0112] Electronic device 600 includes system-in-package 601, antenna 632, speaker 642, microphone 643, display device 660, input device 670, sensor 680 and power supply 690. In addition, system-in-package 601 also includes processor 610, wireless communication interface 630 and audio circuit 640.

[0113] The antenna 632 is an antenna for performing mobile communication, wireless LAN or short-distance communication, and is connected to the wireless communication interface 630. The speaker 642 outputs sound and is connected to the audio circuit 640. The microphone 643 collects sound around the electronic device 600 and is connected to the audio circuit 640.

[0114] The display device 660 is configured by using, for example, a liquid crystal display, an organic EL display, a light emitting diode (LED) indicator, etc., and is connected to the processor 610. The input device 670 is configured by using, for example, a keyboard, a button, a touch panel, etc., and is connected to the processor 610.

[0115] The sensor 680 has functions of an optical sensor, a position sensor, an acceleration sensor, a biosensor, a magnetic sensor, a mechanical quantity sensor, a thermal sensor, an electric sensor, a chemical sensor, etc. A storage device according to an embodiment of the present technology may be connected to the sensor 680 as a storage device 681. The power supply 690 supplies power to the electronic device 600, and is, for example, a power supply powered from a battery, an AC adapter, etc.

[0116] The processor 610 is an electronic circuit for controlling the operation of the electronic device 600, and the storage device according to the embodiment of the present technology can be connected to the processor 610 as the storage device 620 inside the system-in-package 601 or the storage device 650 outside the system-in-package 601. In that case, the processor 610 issues a command to perform reading or writing on the storage device 620 or 650. That is, the processor 610 is an example of a host computer described in the claims.

[0117] The wireless communication interface 630 has a function of mobile communication, wireless LAN, or short-distance communication. A storage device according to an embodiment of the present technology can be connected to the wireless communication interface 630 as a storage device 631. The audio circuit 640 has a function of controlling a speaker 642 and a microphone 643, and the audio circuit 640 can be connected to a storage device according to an embodiment of the present technology as a storage device 641.

[0118] As described above, according to the embodiment of the present technology, the state of the deterministic data of the reference cell is stored in the state storage units 211 and 221, and the write control units 212 and 222 perform control based on this so that the state of the reference cell can be properly managed. In addition, this makes it possible to minimize the number of writes to the reference cell, reduce power consumption, and alleviate the durability constraints of the memory cell.

[0119] Note that the above-mentioned embodiments describe examples that embody the present technology, and there is a correspondence between the items in the embodiments and the matters that specify the present invention in the claims. Similarly, there is a correspondence between the matters that specify the present invention in the claims and the matters in the embodiments of the present technology with the same names. However, the present technology is not limited to the embodiments, and can be embodied by making various modifications to the embodiments without departing from the scope of the present invention.

[0120] In addition, the process described in the above embodiment can be considered as a method including a series of processes, and can be considered as a program for allowing a computer to execute the series of processes and a recording medium storing the program. For example, a compact disc (CD), a mini disc (MD), a digital versatile disc (DVD), a memory card, a Blu-ray (trademark) disc, etc. can be used as a recording medium.

[0121] Note that the effects described in this specification are merely illustrative and not restrictive; there may be other effects.

[0122] Note that the present technology may also have the following configurations.

[0123] (1) A storage control device comprising:

[0124] a state storage section storing a state indicating certainty of a held value with respect to each of a first reference cell included in the first memory cell array and generating a reference potential of a sense amplifier and a second reference cell included in the second memory cell array and generating a reference potential of the sense amplifier; and

[0125] The write control unit, when instructed to write to any one of the first reference cell and the second reference cell, controls the instructed writing based on the states of the first reference cell and the second reference cell stored in the state storage unit.

[0126] (2) The storage control device according to (1) above,

[0127] wherein the write control unit performs writing on a first reference cell group and a second reference cell group including the first reference cell and the second reference cell, respectively, as a unit; and

[0128] The state storage section stores a state for each of the first reference cell group and the second reference cell group.

[0129] (3) The storage control device according to (1) or (2) above,

[0130] When writing is performed on any one of the first reference cell and the second reference cell, the state storage unit updates the state of the reference cell to which the writing is performed.

[0131] (4) The storage control device according to any one of (1) to (3) above,

[0132] When writing is performed on any one of the first reference cell and the second reference cell, the state storage unit updates the state of the reference cell according to the time elapsed from the writing.

[0133] (5) The storage control device according to (4) above is further provided with:

[0134] The timer circuit manages the elapsed time from writing.

[0135] (6) The storage control device according to any one of (1) to (5) above,

[0136] Here, when writing to the first reference cell is instructed, when the state of the first reference cell stored in the state storage unit satisfies a predetermined condition, the write control unit performs control to avoid writing to the first reference cell.

[0137] (7) The storage control device according to (6) above,

[0138] In which, when the state of the first reference unit stored in the state storage unit does not satisfy the predetermined condition when writing to the first reference unit is instructed, the write control unit controls the writing to the first reference unit based on the state of the second reference unit stored in the state storage unit.

[0139] (8) The storage control device according to (7) above,

[0140] In which, when the state of the first reference unit does not satisfy the predetermined condition and when the state of the second reference unit satisfies other predetermined conditions, the write control unit controls the writing of the first reference unit only when the value of the first reference unit read based on the reference potential generated from the second reference unit is inconsistent with a predetermined read expected value.

[0141] (9) The storage control device according to (8) above is further provided with:

[0142] The determination circuit determines whether the value of the first reference cell read with reference to the reference potential of the sense amplifier generated from the second reference cell is consistent with the predetermined read expected value.

[0143] (10) The storage control device according to any one of (7) to (9) above,

[0144] When the state of the first reference cell does not satisfy the predetermined condition and when the state of the second reference cell does not satisfy another predetermined condition, the write control unit controls to write to the first reference cell.

[0145] (11) A storage device comprising:

[0146] A first memory cell array including a first reference cell generating a reference potential for a sense amplifier;

[0147] a second memory cell array including a second reference cell generating a reference potential for the sense amplifier;

[0148] a state storage section storing a state indicating certainty of a hold value with respect to each of the first reference unit and the second reference unit; and

[0149] The write control unit, when instructed to write to any one of the first reference cell and the second reference cell, controls the instructed writing based on the states of the first reference cell and the second reference cell stored in the state storage unit.

[0150] (12) The storage device according to (11) above,

[0151] The first reference unit and the second reference unit are resistance variable memory elements.

[0152] (13) The storage device according to (12) above,

[0153] The first reference unit and the second reference unit are magnetoresistive memory elements.

[0154] (14) An information processing system comprising:

[0155] A first memory cell array including a first reference cell generating a reference potential for a sense amplifier;

[0156] a second memory cell array including a second reference cell generating a reference potential for the sense amplifier;

[0157] A host computer issues a command to read or write the first memory cell array and the second memory cell array;

[0158] a state storage section storing a state indicating certainty of a hold value with respect to each of the first reference unit and the second reference unit; and

[0159] The write control unit, when instructed to write to any one of the first reference cell and the second reference cell, controls the instructed writing based on the states of the first reference cell and the second reference cell stored in the state storage unit.

[0160] Reference numerals list

[0161] 10 Magnetic Tunnel Junction (MTJ) Device

[0162] 11 Free Tier

[0163] 12 Insulation layer

[0164] 13 Reference Layer

[0165] 20 MOS transistors

[0166] 110 Memory Cell Array

[0167] 111 Memory Cells

[0168] 121 Line Decoder

[0169] 122 Word line driver

[0170] 130 Reference potential generating circuit

[0171] 141, 142 Switch

[0172] 150 Data selection circuit

[0173] 160 Write to drive

[0174] 170 Sense Amplifier

[0175] 180 Decision circuit

[0176] 190 Control Circuit

[0177] 191 Reference cell write operation control circuit

[0178] 192 Timer Circuit

[0179] 193 Reference unit master data storage unit

[0180] 211, 221 state storage unit

[0181] 212, 222 Write control unit

[0182] 610 processor

[0183] 620, 650 Storage Device

Claims

1. A storage control device, comprising: a state storage section storing a state indicating certainty of a held value held in each of a first reference cell for generating a reference potential of a sense amplifier and a second reference cell for generating a reference potential of the sense amplifier, the first reference cell being included in a first memory cell array and the second reference cell being included in a second memory cell array; and The write control unit, when instructed to write to any one of the first reference cell and the second reference cell, controls the instructed writing based on the states of the first reference cell and the second reference cell stored in the state storage unit.

2. The storage control device according to claim 1, in, The write control section performs writing on a first reference cell group and a second reference cell group including the first reference cell and the second reference cell, respectively, as a unit, and The state storage section stores the state of each of the first reference cell group and the second reference cell group.

3. The storage control device according to claim 1, in, When writing is performed on any one of the first reference cell and the second reference cell, the state storage section updates the state regarding the reference cell on which the writing has been performed.

4. The storage control device according to claim 1, in, When writing is performed on any one of the first reference cell and the second reference cell, the state storage section updates the state regarding the reference cell according to a time elapsed from the writing.

5. The storage control device according to claim 4, further comprising: The timer circuit manages the elapsed time from writing.

6. The storage control device according to claim 1, in, When writing to the first reference cell is instructed, the write control section performs control so as to avoid writing to the first reference cell if the state regarding the first reference cell stored in the state storage section satisfies a predetermined condition.

7. The storage control device according to claim 6, in, When instructed to write to the first reference unit, if the state of the first reference unit stored in the state storage unit does not satisfy the predetermined condition, the write control unit controls to write to the first reference unit based on the state of the second reference unit stored in the state storage unit.

8. The storage control device according to claim 7, in, When the state of the first reference unit does not satisfy the predetermined condition and when the state of the second reference unit satisfies other predetermined conditions, the write control unit controls to perform writing on the first reference unit only when the value of the first reference unit read based on the reference potential generated from the second reference unit is inconsistent with a predetermined read expected value.

9. The storage control device according to claim 8, further comprising: The determination circuit determines whether the value of the first reference cell read with reference to the reference potential of the sense amplifier generated from the second reference cell is consistent with the predetermined read expected value.

10. The storage control device according to claim 7, in, The write control section controls to perform writing on the first reference cell when the state regarding the first reference cell does not satisfy the predetermined condition and when the state regarding the second reference cell does not satisfy other predetermined conditions.

11. A storage device, comprising: A first memory cell array including a first reference cell for generating a reference potential for a sense amplifier; a second memory cell array including a second reference cell for generating a reference potential for the sense amplifier; a state storage section storing a state indicating certainty of a held value held in each of the first reference cell and the second reference cell; and The write control unit, when instructed to write to any one of the first reference cell and the second reference cell, controls the instructed writing based on the states of the first reference cell and the second reference cell stored in the state storage unit.

12. The storage device according to claim 11, in, The first reference cell and the second reference cell are resistance change memory elements.

13. The storage device according to claim 12, in, The first reference cell and the second reference cell are magnetoresistive memory elements.

14. An information processing system comprising: A first memory cell array including a first reference cell for generating a reference potential for a sense amplifier; a second memory cell array including a second reference cell for generating a reference potential for the sense amplifier; A host computer issues a command to read or write the first memory cell array and the second memory cell array; a state storage section storing a state indicating certainty of a held value held in each of the first reference cell and the second reference cell; and The write control unit, when instructed to write to any one of the first reference cell and the second reference cell, controls the instructed writing based on the states of the first reference cell and the second reference cell stored in the state storage unit.

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