Storage device and method of operating a storage device

Abstract

A method of operating a storage device including a non-volatile memory includes storing program and erase counts of the non-volatile memory as metadata in units of super blocks, wherein each of the super blocks includes a predefined number of blocks of the non-volatile memory; performing a read operation on a first block included in a first super block based on a first read level; when the read operation on the first block is successful, storing the first read level as a historical read level of the first super block in a historical buffer; receiving a read request for a second block of the first super block and an address of the second block from a host; and performing a read operation on the second block based on the historical read level stored in the historical buffer. The predefined number is at least 2.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims the benefit of priority from Korean Patent Application No. 10-2019-0158459 filed on December 2, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a memory device, and more particularly, to a memory device including a nonvolatile memory and a method of operating the memory device. Background Art

[0004] Flash memory is a non-volatile memory that retains stored data even if the power supply is interrupted. Flash memory has the ability to be electrically reprogrammed and electrically erased. In recent years, storage devices including flash memory, such as solid-state drives (SSDs) and memory cards, have been widely used. Flash memory includes a plurality of memory cells. Flash memory can store data by changing the threshold voltage of the memory cell. Data can be read from the flash memory by sensing the threshold voltage and comparing the sensed voltage with one or more predetermined read levels. However, the threshold voltage of the memory cell may change due to degradation of the memory cell, and therefore, a read error may occur. Summary of the Invention

[0005] At least one embodiment of the inventive concept provides a memory device and a method of operating the memory device, which may require fewer read retry operations, include a lower-capacity history buffer, and prevent performance degradation.

[0006] According to an exemplary embodiment of the present invention, a method for operating a storage device including a non-volatile memory is provided. The method includes: storing program and erase counts of the non-volatile memory as metadata in units of super blocks, wherein each super block includes a predefined number of blocks of the non-volatile memory; performing a read operation on a first block included in the first super block based on a first read level; when the read operation on the first block is successful, storing the first read level as a history read level of the first super block in a history buffer; receiving a read request for a second block of the first super block and an address of the second block from a host; and performing a read operation on the second block based on the history read levels stored in the history buffer. The predefined number is at least 2.

[0007] According to an exemplary embodiment of the inventive concept, there is provided a storage device including a non-volatile memory including a plurality of physical blocks, and a controller configured to group the plurality of physical blocks into a plurality of groups, store a program and erase count of each of the plurality of groups as metadata, store a read level of each of the plurality of groups in a history buffer, and when a read command and an address are received from a host, control the non-volatile memory to perform a read operation on a selected physical block corresponding to the address among the physical blocks based on a corresponding read level of the plurality of read levels stored in the history buffer.

[0008] According to an exemplary embodiment of the inventive concept, there is provided a method of operating a storage device including a non-volatile memory having a plurality of memory blocks divided into a plurality of memory groups. The method includes performing a read operation on a first block included in a first memory group among the plurality of memory groups based on a first read level, storing the first read level as a read level of the first memory group in a history buffer when the read operation on the first block is successful, receiving a read request for a second block included in the first memory group and an address of the second block from a host, determining a second read level based on the first read level stored in the history buffer and an offset indicating a characteristic difference between the first block and the second block, and performing a read operation on the second block based on the second read level.

[0009] According to an exemplary embodiment of the inventive concept, there is provided a method of operating a storage device including a non-volatile memory. The method includes grouping a plurality of physical blocks of the non-volatile memory into a plurality of memory groups based on characteristic information about each of the plurality of physical blocks, receiving a read request for a first physical block included in a first memory group among the plurality of memory groups from a host, ascertaining whether a read level corresponding to the first memory group is stored in a history buffer, performing a read operation on the first physical block based on a default read level when the read level is not stored in the history buffer, and performing a read operation on the first physical block based on the read level when the read level is stored in the history buffer. A degree of degradation indicating a relative degree of degradation between the memory groups is managed for each of the plurality of memory groups. BRIEF DESCRIPTION OF DRAWINGS

[0010] Embodiments of the inventive concept will become more fully understood from the detailed description given herein below, and the accompanying drawings, wherein:

[0011] Figure 1 is a block diagram of a storage system according to an exemplary embodiment of the inventive concept;

[0012] Figure 2A and Figure 2BAccording to an exemplary embodiment of the present inventive concept, Figure 1 a circuit diagram of an example of a nonvolatile memory block;

[0013] Figure 3A and Figure 3B is a diagram showing an exemplary embodiment according to the present invention. Figure 1 A block diagram of a method for grouping super blocks in a non-volatile memory (NVM);

[0014] Figure 4A and Figure 4B illustrates an example of a metadata table stored in a metadata buffer according to an exemplary embodiment of the present inventive concept;

[0015] Figure 5 is a graph showing an example of changes in threshold voltage distribution with respect to degradation of memory cells included in an NVM;

[0016] Figure 6A 、 Figure 6B and Figure 6C An exemplary embodiment according to the present invention is shown. Figure 5 An example of reading the history table corresponding to the change in distribution;

[0017] Figure 7 According to an exemplary embodiment of the present inventive concept, Figure 1 A block diagram of an example of a controller;

[0018] Figure 8A An address mapping table according to an exemplary embodiment of the present inventive concept is shown;

[0019] Figure 8B A super block mapping table according to an exemplary embodiment of the present inventive concept is shown;

[0020] Figure 9A shows a device offset of a nonvolatile memory according to an exemplary embodiment of the inventive concept;

[0021] Figure 9B shows a block offset according to an exemplary embodiment of the inventive concept;

[0022] Figure 10 is a schematic flowchart of a method of operating a storage device according to an exemplary embodiment of the present inventive concept;

[0023] Figure 11 According to an exemplary embodiment of the present inventive concept Figure 10 Detailed flow chart of the operating method shown in FIG;

[0024] Figure 12is a flowchart of a method of operating a storage device according to exemplary embodiments of the inventive concept;

[0025] Figure 13 is a flowchart of a method of operating a storage device according to exemplary embodiments of the inventive concept;

[0026] Figure 14A and Figure 14B shows operation of a controller of a storage device and a non-volatile memory according to exemplary embodiments of the inventive concept;

[0027] Figure 15 is a flowchart of a method of operating a storage device according to exemplary embodiments of the inventive concept;

[0028] Figure 16 is a flowchart of a method of updating a history buffer of a storage device according to exemplary embodiments of the inventive concept;

[0029] Figure 17 is a flowchart of a method of grouping superblocks of a storage device according to exemplary embodiments of the inventive concept;

[0030] Figure 18 is a flowchart of a method of regrouping superblocks of a storage device according to exemplary embodiments of the inventive concept;

[0031] Figure 19A and Figure 19B shows Figure 18 an example of the regrouping method;

[0032] Figure 20 is a flowchart of a method of operating a storage device according to exemplary embodiments of the inventive concept;

[0033] Figure 21 shows Figure 20 an example of the operation method shown in

[0034] Figure 22 is a block diagram of a solid state drive (SSD) and an SSD system including the same according to exemplary embodiments. DETAILED DESCRIPTION

[0035] Figure 1 is a block diagram of a storage system 10 according to exemplary embodiments of the inventive concept.

[0036] Reference is made to Figure 1The storage system 10 includes a storage device 100 and a host 200 (e.g., a host device). The storage device 100 includes a controller 110 (e.g., a control circuit or a memory controller) and a non-volatile memory (NVM) 120. The controller 110 can output a command CMD, an address ADDR, and / or a control signal CTRL signal to the NVM 120, and can exchange data DATA with the NVM 120. The host 200 can communicate with the storage device 100 through various interfaces, and send read and write requests to the storage device 100. In an embodiment, the host 200 can be implemented as an application processor (AP) or a system on chip (SoC).

[0037] The NVM 120 can include a plurality of memory blocks BLK, which can be grouped into a plurality of super blocks SB. A memory block BLK can refer to a physical block. Each physical block can include a plurality of memory cells. Hereinafter, a memory block BLK can be referred to as a block or a physical block. A super block SB can be a unit of a logical memory area required for the controller 110 to manage the NVM 120, and each of the plurality of super blocks SB can include a plurality of memory blocks BLK. In an exemplary embodiment, each super block SB includes the same number of memory blocks BLK, and the number can be adjusted as needed.

[0038] A memory block BLK can be implemented as an array of memory cells, in which a plurality of memory cells form a two-dimensional (2D) or three-dimensional (3D) array structure. The plurality of memory cells can be single-level cells programmed with one bit or multi-level cells (e.g., dual-level cells, triple-level cells, or quad-level cells) programmed with two or more bits. The memory cells can be NAND flash memory cells. However, the inventive concept is not limited thereto, and the memory cells can be resistive memory cells such as resistive RAM (ReRAM) cells, phase-change RAM (PRAM) cells, or magnetic RAM (MRAM) cells.

[0039] A block BLK can include a plurality of pages. Memory cells connected to the same word line can constitute a page. For example, a block BLK can be a unit of an erase operation, and a page can be a unit of a program and read operation.

[0040] The controller 110 (or a storage controller) can control overall operations of the storage device 100. The controller 110 can control the NVM 120 to read data DATA stored in the NVM 120 in response to a read request from the host 200 or to program data DATA in the NVM 120 in response to a write request from the host 200. In addition, the controller 110 can control the NVM 120 to perform internal management operations or background operations of the storage device 100 regardless of the request of the host 200.

[0041] In the present embodiment, the controller 110 includes a metadata buffer MB and a history buffer HB. The controller 110 manages the metadata buffer MB and the history buffer HB in units of predetermined memory groups (e.g., super blocks SB). In an exemplary embodiment, the controller 110 groups a plurality of blocks BLK into a plurality of super blocks SB based on locations of the blocks BLK in the memory device or groups a plurality of blocks BLK into a plurality of super blocks SB based on electrical characteristics (e.g., threshold voltage distribution characteristics of the plurality of blocks BLK during application of the same test program voltage) of the plurality of blocks BLK.

[0042] Various metadata can be stored in the metadata buffer MB. Here, the metadata can be user data stored in the NVM 120 or data generated by the controller 110 to manage the NVM 120. For example, the metadata can include mapping information for converting a logical address of the host 200 to a physical address of the NVM 120. Alternatively, the metadata can include information (e.g., program and erase (P / E) cycles, program and erase counts, and degree of deterioration information) for managing operations of a storage space of the NVM 120, such as a wear leveling process and a garbage collection process. For example, the wear leveling process can include ensuring that writes are evenly distributed to prolong the life of the memory device. For example, the garbage collection process can include moving valid pages of a first memory block to a second memory block and then erasing the first memory block to free up space. The metadata can be continuously used when the storage device 100 is powered off and then powered on again. Accordingly, the metadata can be stored in the NVM 120 during a run time of the storage device 100 or when the storage device 100 is powered off. For example, the metadata can be maintained even after the storage device 100 is powered off.

[0043] The controller 110 can control the NVM 120 such that a plurality of memory blocks BLK included in a super block SB perform a program and / or erase operation at the same point of time. Also, the controller 110 can manage (or store and update) metadata related to management of a degree of deterioration of the NVM 120 in units of the super block SB. For example, a different degree of deterioration (or a degree of deterioration) can be stored and updated for each of the super blocks SB. The degree of deterioration can indicate how much the super blocks have deteriorated with respect to each other. For example, if a first degree of deterioration of a first super block is higher than a second degree of deterioration of a second super block, the first super block is considered to be more deteriorated than the second super block. For example, the first super block can have been programmed and / or erased more times than the second super block, and thus be considered to have a higher degree of deterioration.

[0044] For example, when converting a logical address received from the host 200 along with a write request into a physical address, the controller 110 can map the physical address to the logical address such that a plurality of blocks BLK of a super block SB perform a program operation simultaneously using an interleaving method. Accordingly, the plurality of blocks BLK of the super block SB can have the same degree of deterioration or a similar degree of deterioration. Here, deterioration of a memory cell can indicate that a physical characteristic of the memory cell changes as a P / E cycle is repeated. As a memory cell deteriorates, endurance and retention characteristics of the memory cell can decrease. Since the plurality of blocks BLK of the super block SB have the same degree of deterioration or a similar degree of deterioration, the controller 110 can manage metadata related to the degree of deterioration in units of the super block SB.

[0045] In an exemplary embodiment, the controller 110 manages P / E cycles in units of the super block SB, and stores a program and erase count for each super block SB in a metadata buffer MB. Alternatively, the controller 110 can detect a degree of deterioration of each super block SB, and store the detected degree of deterioration in the metadata buffer MB. As described above, metadata can be managed in units of the super block SB, and thus, a storage capacity of the metadata buffer MB required to store the metadata can be reduced.

[0046] Also, the controller 110 can store a read level of each super block SB in a history buffer HB during a run time of the storage device 100. For example, the read level can be a certain voltage or current. When a read request is received from the host 200, data can be read from a block BLK requested to be read based on a read level stored in the history buffer HB. As used herein, a read level stored in the history buffer HB will be referred to as a "history read level", and a read operation based on the history read level will be referred to as a "history read operation".

[0047] For example, the controller 110 may perform a read operation on a memory block BLK (e.g., the first block) of the first Super Block based on a first read level. If the read operation is successful, the first read level is stored in the history buffer HB as the history read level of the first Super Block. Thereafter, when a read request for the first block or another block of the first Super Block is received from the host 200, the controller 110 performs a history read operation based on the history read level of the first Super Block stored in the history buffer HB.

[0048] When a read operation fails, the controller 110 may perform a read retry operation. When a previous read operation fails, the read level may be modified. Hereinafter, a read operation performed using a modified read level will be referred to as a "read retry operation." In an exemplary embodiment, performing a read operation includes reading a cell voltage of a memory block, converting the read voltage into a codeword (e.g., data and redundant information), performing an error checking and correction (ECC) operation on the codeword, and the read operation will fail when the ECC operation fails. For example, an ECC operation failure may indicate that the codeword has a certain number of errors that exceed the error correction capability of the ECC operation. The conversion of the read voltage to the codeword may use a read level. If the ECC operation fails, the read level used may be increased or decreased to a modified read level, the codeword may be modified using the previously read cell voltage and the modified read level, and the ECC operation may be performed on the modified codeword. When a historical read operation fails, the controller 110 may execute a recovery code through firmware to derive a modified read level, and perform a read retry operation based on the modified read level. When the read retry operation is successful, the controller 110 may store the modified read level as a history read level in the history buffer HB and update the history read level.

[0049] When a read operation is performed based on a default read level in which the degree of degradation of a block BLK is not detected, the probability that the read operation will fail may be high. However, the storage device 100 according to at least one embodiment of the present invention can manage historical read levels in units of super blocks SB, and perform historical read operations on blocks BLK for which reads have been requested based on the historical read levels of the corresponding super blocks SB. Therefore, the probability that the read operation will succeed can be increased. As described above, when a read operation fails, a recovery code can be executed. However, executing the recovery code may take a considerable amount of time. The storage device 100 according to an exemplary embodiment of the present invention can minimize the execution time of the recovery code, and therefore, the performance of the storage device 100 can be improved.

[0050] Further, when an excessively long time elapses from when the history read level is stored in the history buffer HB, even if the history read operation is performed based on the history read level, the probability that the read operation will fail is high. When the storage device 100 is powered off, the elapsed time until the storage device 100 is powered on again can be unknown, and sometimes is quite long. Therefore, when the storage device 100 is powered off, unlike the metadata, the data stored in the history buffer HB (i.e., the history read level of each super block SB) can not need to be stored in the NVM 120. When the storage device 100 is powered on and a normal read operation (e.g., a read operation performed based on the default read level) is successful, the read level can be stored in the history buffer HB as the history read level, used at the run time of the storage device 100, and also updated. In an exemplary embodiment, the history read level is stored in a volatile memory (not shown) of the storage device, the default read level is initially used after the storage device 100 is powered on, and continues to be used until the corresponding history read level has been newly calculated.

[0051] In an exemplary embodiment, during the history read operation, in order to compensate for a characteristic difference between the plurality of blocks BLK included in the same super block SB or compensate for a characteristic difference between a plurality of memory devices respectively including the plurality of blocks BLK, the controller 110 adds an offset to the history read level to generate an adjusted history read level, calculates an adjusted read level from the adjusted history read level, and performs the history read operation based on the adjusted read level.

[0052] Due to a manufacturing process (i.e., a manufacturing operation), the electrical characteristics of the plurality of blocks BLK included in the same super block SB can be different. For example, the threshold voltage distribution characteristics (e.g., the width of the threshold voltage distribution and the threshold voltage level) of a first block can be different from the threshold voltage distribution characteristics of a second block. Therefore, even if the first block and the second block have the same degree of degradation or a similar degree of degradation, the first block and the second block can have different retention characteristics.

[0053] Therefore, the controller 110 can perform the history read operation based on the adjusted read level obtained by adding an offset reflecting a characteristic difference between the plurality of blocks BLK to the history read level. As a result, the read success rate can be improved, and the recovery code execution time can be reduced.

[0054] In an exemplary embodiment, the controller 110 performs a background read operation in units of a super block SB and updates the history buffer HB. In this case, the "background read operation" can indicate that the controller 110 itself issues a read command CMD and an address ADDR without receiving a read request from the host 200, and reads data DATA from the NVM 120 in response to the read command CMD and the address ADDR. In an embodiment, the "background read operation" performed to update the history buffer HB can be performed on one block (e.g., a representative block) of the super block SB based on the history read level stored in the history buffer HB. For example, the storage device 100 is just powered on, the controller 110 can perform one or more background read operations to update the history buffer HB.

[0055] In an embodiment, the controller 110 performs a background read operation in units of a block BLK, and re-groups the super block SB or replaces a defective block BLK among the blocks BLK included in the super block SB with another block based on characteristics of the blocks BLK, which are detected based on the results of the background read operation. For example, if one of the blocks allocated to the super block is determined to be defective, another block of the memory 120 can be allocated to the super block.

[0056] The storage system 10 can be implemented as, for example, a personal computer (PC), a data server, a network-attached storage (NAS), an Internet of Things (IoT) device, or a portable electronic device. The portable electronic device can include a laptop computer, a mobile phone, a smart phone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, an audio device, a portable multimedia player (PMP), a personal navigation device (PND), an MPEG-1 audio layer 3 (MP3) player, a handheld game console, an electronic book (e-book), and a wearable device.

[0057] In some embodiments, the storage device 100 can be an internal memory embedded in an electronic device. For example, the storage device 100 can be a solid state drive (SSD), an embedded Universal Flash Storage (UFS) memory device, or an embedded Multi-Media Card (eMMC). In some embodiments, the storage device 100 can be an external memory detachably attached to an electronic device. For example, the storage device 100 can include a UFS memory card, a Compact Flash (CF) memory, a Secure Digital (SD) memory, a micro-SD memory, a mini-SD memory, an extreme Digital (xD) memory, or a memory stick.

[0058] Figure 2A and Figure 2B are according to exemplary embodiments of the inventive concept, Figure 1a circuit diagram of an example of a block BLK of the NVM 120.

[0059] Referring to Figure 2A , the block BLKa can be a horizontal NAND flash memory. The block BLKa includes a plurality of NAND strings STR, a plurality of word lines (e.g., first to eighth word lines WL1 to WL8), a plurality of bit lines BL1 to BLd, a ground select line GSL, a string select line SSL, and a common source line CSL. Each NAND string can include a string select transistor SST, a plurality of memory cells MC, and a ground select transistor GST connected in series. Here, according to embodiments, the number of NAND strings, the number of word lines, the number of bit lines, the number of ground select lines, and the number of string select lines can vary variously.

[0060] The memory cells MC connected to one word line (e.g., the fifth word line WL5) can constitute a page PAGE, and programming and reading operations can be performed in units of pages. In this case, Figure 2A The page PAGE illustrated in FIG. 1A can indicate a physical page. When the memory cells MC are multi-level cells, a plurality of logical pages can be programmed to the page PAGE, programming and reading operations can be performed in units of pages corresponding to each of the first to eighth word lines WL1 to WL8, and an erase operation can be performed on the entire block BLKa.

[0061] Referring to Figure 2B , the block BLKb can be a vertical NAND flash memory. The block BLKb can include a plurality of NAND strings (e.g., NS11 to NS33), a plurality of word lines (e.g., first to eighth word lines WL1 to WL8), a plurality of bit lines (e.g., first to third bit lines BL1 to BL3), a plurality of ground select lines (e.g., GSL1 to GSL3), a plurality of string select lines (e.g., first to third SSL1 to SSL3), and a common source line CSL. Here, according to embodiments, the number of NAND strings, the number of word lines, the number of bit lines, the number of ground select lines, and the number of string select lines can vary variously.

[0062] The NAND strings NS11, NS21, and NS31 can be provided between the first bit line BL1 and the common source line CSL, and the NAND strings NS12, NS22, and NS32 can be provided between the second bit line BL2 and the common source line CSL. The NAND strings NS13, NS23, and NS33 can be provided between the third bit line BL3 and the common source line CSL. Each NAND string (e.g., NS11) can include a string select transistor SST, a plurality of memory cells (e.g., MC1 to MC8), and a ground select transistor GST connected in series.

[0063] The string selection transistor SST can be connected to the first to third string selection lines SSL1 to SSL3. The memory cells MC1 to MC8 can be connected to the first to eighth word lines WL1 to WL8, respectively, corresponding thereto. The ground selection transistor GST can be connected to the ground selection lines GSL1, GSL2, and GSL3. The string selection transistor SST can be connected to the bit line BL corresponding thereto, and the ground selection transistor GST can be connected to the common source line CSL.

[0064] The word lines connected to the memory cells located at the same level in the NAND strings NS11 to NS33 can be commonly connected, and the first to third string selection lines SSL1 to SSL3 can be separated from each other. For example, when the memory cells connected to the first word line WL1 and belonging to the NAND strings NS11, NS12, and NS13 are programmed, the first word line WL1 and the first string selection line SSL1 can be selected. As shown in FIG. 1B, the first to third string selection lines SSL1 to SSL3 can be commonly connected. However, the inventive concept is not limited thereto, and the first to third string selection lines SSL1 to SSL3 can be separated from each other. Figure 2B The ground selection lines GSL1, GSL2, and GSL3 can be separated from each other, as shown in FIG. 1C. However, the inventive concept is not limited thereto, and the ground selection lines GSL1, GSL2, and GSL3 can be connected to each other.

[0065] The programming and reading operations can be performed in units of pages PAGE corresponding to the first to eighth word lines WL1 to WL8 and the NAND strings NS11 to NS33, respectively, and the erasing operation can be performed on the entire block BLKb.

[0066] Figure 3A and Figure 3B is a block diagram illustrating a method of grouping super blocks in the NVM 120 according to an exemplary embodiment of the inventive concept. Figure 1

[0067] Referring to Figure 1 and Figure 3A The NVM 120 includes a plurality of memory devices (e.g., first to eighth memory devices D1 to D8). The first to eighth memory devices D1 to D8 can communicate with the controller 110 through at least one channel CH. Each of the first to eighth memory devices D1 to D8 can be a semiconductor chip or a semiconductor die, and include a plurality of blocks BLK. For example, as shown in FIG. 2, the first to eighth memory devices D1 to D8 can include a plurality of blocks BLK1 to BLK8, respectively. Figure 3A ​As illustrated in FIG. 1, the first memory device D1 to the eighth memory device D8 can respectively include n number of blocks B11 to B1n, B21 to B2n, …, and B81 to B8n (n is a natural number greater than or equal to 2). Although not illustrated, each of the first memory device D1 to the eighth memory device D8 can further include a peripheral circuit (e.g., a voltage generator, an address decoder, and an input / output (I / O) circuit) configured to perform programming, reading, and erasing operations.

[0068] Among the first memory device D1 to the eighth memory device D8, blocks BLK arranged at the same position (or blocks BLK allocated with the same number) can be grouped into one super block. For example, as illustrated in FIG. 1, the blocks B11 to B81 can be grouped into a first super block SB1, the blocks B12 to B82 can be grouped into a second super block SB2, and the blocks B1n to B8n can be grouped into a k-th super block SBk (here, k is a natural number greater than or equal to 2 and less than or equal to n). Figure 3A

[0069] Referring to FIG. 1, Figure 3B The plurality of blocks B11 to B8n can be grouped into the plurality of super blocks (i.e., the first k super blocks SB1 to the k-th super block SBk) based on electrical characteristics. For example, the blocks B11, B21, …, and B81 can have the same or similar electrical characteristics and be grouped into the first super block SB1, and the blocks B12, B22, …, and B82 can have the same or similar electrical characteristics and be grouped into the second super block SB2. In addition, the blocks B1n, B2n, …, and B8n can have the same or similar electrical characteristics and be grouped into the k-th super block SBk.

[0070] In addition to the grouping method described above, the plurality of blocks BLK of the NVM 120 can be grouped into the plurality of super blocks based on various conditions. Although Figure 3A Figure 3B In addition to the grouping method described above, the plurality of blocks BLK of the NVM 120 can be grouped into the plurality of super blocks based on various conditions. Although Figure 3A Figure 3B Although an example in which the first memory device D1 to the eighth memory device D8 are connected in parallel to one channel CH and communicate with the controller 110 through the channel CH is illustrated, the inventive concept is not limited thereto. For example, the NVM 120 can include a plurality of channels respectively connected to a plurality of memory devices. In an exemplary embodiment, the first memory device D1 to the eighth memory device D8 connected to the same channel CH perform programming, reading, and erasing operations using an interleaving method.

[0071] Figure 4A Figure 4B An example of a metadata table stored in a metadata buffer according to an exemplary embodiment of the inventive concept is illustrated.

[0072] ​​​​Referring to Figure 4A The P / E cycle of each of the plurality of super blocks (e.g., the first super block SB1 to the nth super block SBn) is stored as a count table CTB in the metadata buffer (refer to Figure 1 ) in the MB.

[0073] For example, each entry of the count table CTB can include a super block number SBN that is a super block address of the NVM 120 and a count value CV that indicates the P / E cycle. The count table CTB can store a plurality of count values (e.g., a first count value CV1 to an nth count value CVn) respectively corresponding to the first super block SB1 to the nth super block SBn. For example, the controller 110 can count the P / E cycle (or the number of repeated programming and erasing operations) of the plurality of memory blocks of the first super block SB1 and store the count result as the first count value CV1 of the count values CV. For example, the super block address can include a physical address assigned to each block of a given super block. For example, each time any of the blocks of the super block is programmed or erased, the count value associated with the super block can be incremented.

[0074] Referring to Figure 4B , a degradation value DV indicating a degree of degradation of each of the plurality of super blocks SB1 to SBn is stored as a degradation degree table DTB in the metadata buffer MB. In this case, the degree of degradation can refer to a degree to which each of the plurality of super blocks SB1 to SBn is degraded due to repetition of programming and erasing operations. For example, the degradation degree table DTB can include a super block number SBN that is a super block address of the NVM 120 and a degradation value DV. The degradation degree table DTB can store a plurality of degradation values DV1 to DVn respectively corresponding to the plurality of super blocks SB1 to SBn. For example, the controller 110 can periodically or aperiodically detect a degree of degradation of each of the plurality of super blocks SB1 to SBn and store the degree of degradation or a processing value calculated based on the degree of degradation as the degradation value DV in the degradation degree table DTB.

[0075] Figure 5 is a graph showing an example of a change in a threshold voltage distribution with respect to degradation of a memory cell included in an NVM.

[0076] Referring to Figure 1 and Figure 5 In the initial distribution 51 and the changed distribution 52, the abscissa axis indicates a threshold voltage Vth, and the ordinate axis indicates the number of memory cells.

[0077] For example, when the memory cell is a multi-level cell programmed with 2 bits, the memory cell can have an erase state E and one of first to third program states P1 to P3. The initial distribution 51 can be a distribution obtained within a predetermined time after completion of a program operation on the memory cell. The storage device 100 can determine the first to third program states P1 to P3 using the first to third default read levels DRL1 to DRL3, respectively.

[0078] The changed distribution 52 can be a distribution obtained after a predetermined time from completion of a program operation on the memory cell. As the retention time increases, the amount of charge trapped in the memory cell can decrease, and thus, the distribution can change and shift. Accordingly, the threshold voltage Vth of the memory cell can change compared to the initial distribution 51. Specifically, as the retention time increases, the charge stored in the charge storage layer of the memory cell can leak to the substrate, and thus, the threshold voltage Vth of the memory cell can decrease. The change and shift of the distribution can be affected not only by the time elapsed after the program operation (i.e., the retention time), but also by program and / or erase iterations (e.g., P / E cycles). For example, even if the same time elapses after completion of the program operations on the first and second word lines, the P / E cycles of the first word line are different from those of the second word line, and the change and shift of the distribution of the first word line can be different from those of the second word line.

[0079] In this case, when a read operation is performed on the memory cell using each of the first to third default read levels DRL1 to DRL3, a read error can occur in some of the memory cells programmed in the first to third program states P1 to P3. Here, the read error can correspond to a case where the number of failed bits among read data is greater than or equal to a reference number that can be corrected using an error correction code (ECC). Accordingly, the read error can be referred to as an uncorrectable ECC (UECC). In order to eliminate the read error, it can be necessary to perform a read retry operation to modify the read level.

[0080] When a read error occurs during a normal read operation using the default read level DRL, the storage device 100 can modify the read level and perform a read retry operation using the modified read level. Accordingly, an appropriate read level at which the read operation is successful, e.g., the modified read levels CRL1 to CRL3, can be obtained. The controller 110 can execute a recovery code to modify the read level by firmware. In this case, since execution of the recovery code can take a large amount of time, the performance of the storage device 100 can be degraded.

[0081] During a history read operation in which the history read level is used, the probability of read error occurrence can be reduced. However, when the history read level is managed (or stored and updated) in units of blocks, a read retry operation can be performed to obtain the history read level of each of the plurality of blocks. In addition, the storage capacity of the history buffer HB required to store the history read level of each of the plurality of blocks can be increased. However, according to at least one embodiment of the inventive concept, since the controller 110 manages the history read level in units of super blocks SB, only a read retry operation is required to obtain the history read level of each of the plurality of super blocks SB, without having to perform a read retry operation for each of the plurality of blocks. Accordingly, the recovery code execution time can be reduced, and the storage capacity of the history buffer HB required to store the history read level can be reduced.

[0082] Figure 6A , Figure 6B and Figure 6C shows an example of a read history table corresponding to a change in distribution of Figure 5 according to an exemplary embodiment of the inventive concept.

[0083] Referring to Figure 1 to Figure 6A , the read history table RHTa can be stored in the history buffer HB. The read history table RHTa stores the history read levels HRL1 to HRL3 corresponding to each of the plurality of super blocks (e.g., the first super block SB1 to the n-th super block SBn). For example, the modified read levels CRL1a, CRL2a, and CRL3a corresponding to the first super block SB1 are stored as the history read levels HRL1 to HRL3. In addition, the modified read levels CRL1b, CRL2b, and CRL3b corresponding to the second super block SB2 are stored as the history read levels HRL1 to HRL3, and the modified read levels CRL1c, CRL2c, and CRL3c corresponding to the n-th super block SBn are stored as the history read levels HRL1 to HRL3. The history read levels HRL1 to HRL3 corresponding to each of the first super block SB1 to the n-th super block SBn can be updated with respect to time. Hereinafter, an operation of generating the read history table RHTa will be described.

[0084] The controller 110 performs a normal read operation on one block in the first super block SB1 (e.g., a first block among the plurality of blocks in the first super block SB1 on which a read operation is initially performed during a runtime of the memory device 100) based on the default read levels DRL1, DRL2, and DRL3. When a read error occurs, the controller 110 performs a read retry operation on the first block using the modified read levels CRL1a, CRL2a, and CRL3a. When no read error occurs, the controller 110 can store the modified read levels CRL1a, CRL2a, and CRL3a as the history read levels HRL1 to HRL3 corresponding to the first super block SB1 in the read history table RHTa. Similarly, the controller 110 can perform the normal read operation and / or the read retry operation on the second super block SB2 to the n-th super block SBn, and store the modified read levels CRL1b, CRL2b, and CRL3b in the read history table RHTa. If the read retry operation fails, the controller 110 can adjust the modified read levels CRL1a, CRL2a, and CRL3a, update the history read levels HRL1 to HRL3 associated with the first super block SB1 in the read history table RHTa to the adjusted read levels, respectively, and re-perform the read retry operation based on the adjusted read levels. If the normal read operation with the default read levels DRL1, DRL2, and DRL3 is successful, the controller 110 can update the history read levels HRL1 to HRL3 associated with the first super block SB1 in the read history table RHTa to the default read levels DRL1, DRL2, and DRL3, respectively.

[0085] In some embodiments, when the memory cells are single-level cells programmed with one bit, the memory cells can have one of an erased state and a programmed state. In this case, the read history table can store the modified read levels corresponding to each of the first super block SB1 to the n-th super block SBn as the history read levels. The operation of generating the read history table can be substantially the same as described above with reference to Figure 6A

[0086] Referring to Figure 6B As described above with reference to Figure 6A The read history table RHTb stores the history read levels HRL1 to HRL3 corresponding to each of the plurality of super blocks (e.g., the first super block SB1 to the n-th super block SBn). In addition, the read history table RHTb stores a device number DN indicating an address of a memory device (hereinafter, referred to as a "device") on which a read operation (or a read retry operation) is performed when the history read levels HRL1 to HRL3 corresponding to the super block are obtained. For example, as described above with reference to FIG. 1, the device number DN can indicate a device including a block on which a read operation (or a read retry operation) is performed when the history read levels HRL1 to HRL3 corresponding to the super block are obtained. Figure 6B ​As shown in FIG. 1, the first super block SB1 can be located on a first memory chip having a device number D2, and the nth super block SBn can be located on a second memory chip having a device number D3. In an exemplary embodiment, the device numbers are stored on each memory chip of the memory 120, or the device numbers of all memory chips are stored within the memory 120 but outside of the memory chips. In an exemplary embodiment, the device numbers can be queried by the controller 110. For example, the controller 110 can send a request for the device numbers of the memory chips to the memory 120, and then the memory 120 can respond to the controller 110 with the corresponding device numbers.

[0087] For example, in Figure 3A When the read retry operation is performed on the block B21 included in the first super block SB1 and the modified read levels CRL1a, CRL2a, and CRL3a are obtained, the device number D2 of the second device including the block B21 can be stored as the device number DN. As described above with reference to Figure 1 the electrical characteristics between devices can differ. The electrical characteristics of each of the first device D1 to the eighth device D8 can be detected during a manufacturing process (e.g., a device test operation), and stored in the corresponding device. For example, the detected electrical characteristics can be stored in one of the plurality of blocks included in the corresponding device or in the peripheral circuit of the corresponding device.

[0088] When the historical read operation is performed on the blocks other than the block B21 (e.g., B11 and B81) based on the modified read levels CRL1a, CRL2a, and CRL3a, the controller 110 can ascertain from which device the modified read levels CRL1a, CRL2a, and CRL3a are obtained (i.e., whether the modified read levels CRL1a, CRL2a, and CRL3a are obtained from the second device D2), adjust the modified read levels CRL1a, CRL2a, and CRL3a based on an offset that reflects the difference in electrical characteristics between the second device D2 and the device including the block on which the historical read operation is to be performed, and perform the historical read operation based on the adjusted read levels. For example, the controller 110 can add the offset to each of the modified read levels CRL1a, CRL2a, and CRL3a, and generate adjusted read levels. For example, if the historical read operation on the block B21 of the device D2 was previously performed, its corresponding entry in the read history table RHTb can be temporarily stored in a buffer of the controller 110; and then, if the historical read operation on a block in the device D3 is next required, the offset can be added to the read levels in the buffer to derive the read levels for that block of the device D3.

[0089] Referring toFigure 6C As described with reference to Figure 6A the read history table RHTc stores a history read level HRL1 to HRL3 corresponding to each of a plurality of super blocks (e.g., a first super block SB1 to an n-th super block SBn), and stores a block number BN corresponding to an address of a block. For example, the block number BN can indicate a block on which a read operation (or a read retry operation) is performed when a history read level HRL1 to HRL3 of a super block is obtained. For example, in Figure 3A when a read retry operation is performed on a block B21 included in the blocks B11 to B81 included in the first super block SB1 and modified read levels CRL1a, CRL2a, and CRL3a are obtained, B21 can be stored as the block number BN.

[0090] For example, an electrical characteristic of each of a plurality of blocks included in each of the first device D1 to the eighth device D8 can be detected during a manufacturing process (e.g., a device test operation), and stored in a corresponding device. For example, a characteristic of each of a plurality of blocks of a corresponding device can be stored in a corresponding block, a specific block, or a peripheral circuit of the corresponding device.

[0091] When a history read operation is performed on blocks (e.g., B11 and B81) other than the block B21 based on the modified read levels CRL1a, CRL2a, and CRL3a, the controller 110 can ascertain from which block the modified read levels CRL1a, CRL2a, and CRL3a are obtained (i.e., whether the modified read levels CRL1a, CRL2a, and CRL3a are obtained from the block B21), adjust the modified read levels CRL1a, CRL2a, and CRL3a based on an offset reflecting a difference in electrical characteristics between the block B21 and the block on which the history read operation is to be performed, and perform the history read operation based on the adjusted read levels.

[0092] Figure 7 is a block diagram of an example of a controller 110 according to an exemplary embodiment of the inventive concept. Figure 1

[0093] With reference to Figure 7 ​, the controller 110a includes a processor 111, a memory 112, a host interface 113 (e.g., an interface circuit), a read-only memory (ROM) 114, an ECC module 115, and an NVM interface 116 (e.g., an interface circuit), which can communicate with each other via a bus 117. The processor 111 may include a central processing unit (CPU) or a microprocessor (MP) and controls the overall operation of the controller 110a. The processor 111 may include at least one processor core that is capable of executing an instruction set of a program code configured to perform specific operations. For example, the processor 112 may execute command codes of firmware stored in the ROM 114.

[0094] The memory 112 can be operated under the control of the processor 111 and can be used as an operating memory, a buffer memory, and / or a cache memory. For example, the memory 112 can be implemented as a volatile memory such as a dynamic random access memory (DRAM) and a static RAM (SRAM); or an NVM such as a phase change RAM (PRAM) and a flash memory.

[0095] The read controller RC of the memory 112 may be implemented as firmware or software and loaded in the memory 112. In an embodiment, the read controller RC is implemented as part of a flash translation layer (FTL) and loaded in the memory 112. However, the inventive concept is not limited thereto, and the read controller RC may be implemented as hardware.

[0096] The history buffer HB of the memory 112 may store, for example Figure 6A 、 Figure 6B and Figure 6C , and is implemented as part of the memory 112. In an embodiment, the read controller RC and the history buffer HB are implemented in the same chip. However, the present invention is not limited thereto, and the read controller RC and the history buffer HB may be implemented in different chips. For example, the history buffer HB may be implemented as part of an additional DRAM chip.

[0097] The metadata buffer MB of the memory 112 may store, for example Figure 4A Count table CTB and / or Figure 4B The degradation table DTB is implemented as part of the memory 112 or as part of an additional DRAM chip. In addition, the metadata buffer MB can store: an address mapping table (refer to Figure 8A AMT in ), including mapping information between logical addresses and physical addresses; and super block mapping table (reference Figure 8B SMBT in , including information about the blocks mapped to the superblock.

[0098] Figure 8A An address mapping table AMT according to an example embodiment of the present inventive concept is shown, Figure 8B A super block mapping table SBMT according to an example embodiment of the present inventive concept is shown.

[0099] Referring to Figure 8A , the address mapping table AMT stores a plurality of mapping data configured to convert a logical address to a physical address. The address mapping table AMT can be loaded in the metadata buffer MB and used. Each mapping data indicates a physical page number PPN corresponding to a logical page number LPN. For example, a third physical page PPN3 corresponding to a third page of the block BLK11 can be mapped to a first logical page LPN1, and a ninth physical page PPN9 corresponding to a first page of the block BLK12 can be mapped to a second logical page LPN2. Figure 7 Referring to

[0100] , the super block mapping table SBMT indicates block numbers BN of a plurality of blocks corresponding to a plurality of super blocks SB1 to SBn (i.e., a plurality of blocks grouped into each of the plurality of super blocks SB1 to SBn). For example, blocks BLK11, BLK21, …, and BLK81 correspond to a first super block SB1. In an embodiment, as shown in Figure 8B , the super block mapping table SBMT includes not only block numbers BN of blocks but also device numbers (e.g., D1, D2, …, and D8) including the blocks. Figure 8B

[0101] When the controller 110a receives a read request and a logical address from the host 200, the controller 110a can refer to the address mapping table AMT to determine a physical address corresponding to the received logical address. Thereafter, the controller 110a can refer to the super block mapping table SBMT to determine a super block corresponding to the physical address, and find out whether a history read level of the super block is stored in the read history table (refer to RHTa of Figure 6A , RHTb of Figure 6B , and RHTc of Figure 6C ).

[0102] For example, when the controller 110a receives a first logical page LPN1 from the host 200, the controller 110a refers to the address mapping table AMT to determine that a third physical page PPN3 corresponds to the first logical page LPN1. Thereafter, the controller 110a can refer to the super block mapping table SBMT to determine that the third physical page PPN3 corresponds to a first super block SB1, and find out whether a history read level corresponding to the first super block SB1 is stored in the history buffer (refer to Figure 1 and Figure 7 ​whether the historical read level corresponding to the second super block SB2 is stored in the read history table (refer to RHTa of Figure 6A , RHTb of Figure 6B , and RHTc of Figure 6C ). Since the historical read level corresponding to the second super block SB2 is not stored in the read history table (refer to RHTb of Figure 6A and RHTc of , a read operation (e.g., a normal read operation) can be performed on the ninth physical page PPN9 using a default read level. When the normal read operation is successful, the default read level can be stored as the historical read level corresponding to the second super block SB2. When the normal read operation fails, a read retry operation can be performed, and a modified read level obtained when the read operation is successful can be stored as the historical read level of the second super block SB2.

[0103] For example, when the controller 110a receives the second logical page LPN2 from the host 200, the controller 110a can refer to the address mapping table AMT and determine that the ninth physical page PPN9 corresponds to the second logical page LPN2. Thereafter, the controller 110a can refer to the super block mapping table SBMT to determine that the ninth physical page PPN9 corresponds to the second super block SB2, and ascertain whether the historical read level corresponding to the second super block SB2 is stored in the history buffer (refer to HB of Figure 1 and 7 , i.e., whether the historical read level corresponding to the second super block SB2 is stored in the read history table (refer to RHTa of Figure 6A , RHTb of Figure 6B , and RHTc of Figure 6C ). Since the historical read level corresponding to the second super block SB2 is not stored in the read history table (refer to RHTb of Figure 6B and RHTc of Figure 6C , a read operation (e.g., a normal read operation) can be performed on the ninth physical page PPN9 using a default read level. When the normal read operation is successful, the default read level can be stored as the historical read level corresponding to the second super block SB2. When the normal read operation fails, a read retry operation can be performed, and a modified read level obtained when the read operation is successful can be stored as the historical read level of the second super block SB2.

[0104] Referring to Figure 7 , the host interface 113 can provide an interface between the host 200 and the controller 110a. For example, the host interface 113 can provide an interface based on Universal Serial Bus (USB), Multimedia Card (MMC), Peripheral Component Interconnect Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Enhanced Small Device Interface (ESDI), and Intelligent Drive Electronics (IDE).

[0105] The ROM 114 may store various information required for the operation of the controller 110a. For example, the ROM 114 may store an algorithm for operating the controller 110a or an algorithm for operating the read controller RC using firmware. For example, the algorithm for operating the controller 110a may be an algorithm for managing the metadata buffer MB or an algorithm for managing the history buffer HB.

[0106] The ECC module 115 may perform an ECC operation on data (e.g., codewords) received from the NVM 120, detect error bits from the data, and correct the detected error bits. In an embodiment, the ECC module 115 is implemented as hardware. In an embodiment, the ECC module 115 is implemented as software or firmware and is loaded into the memory 112.

[0107] The NVM interface 116 may provide an interface between the controller 110 a and the NVM 120 . For example, metadata, write data, and read data may be transmitted and received between the controller 110 a and the NVM 120 through the NVM interface 116 .

[0108] Figure 9A shows a device offset of the NVM 120 according to an exemplary embodiment of the inventive concept; and Figure 9B Block offset according to an exemplary embodiment of the inventive concept is shown.

[0109] refer to Figure 1 to Figure 9A , multiple devices of the NVM 120 (e.g., first device D1 to twenty-first device D21) store corresponding device offsets DO (e.g., first device offset DO1 to twenty-first device offset DO21). During the operation of manufacturing the storage device 100, each of the device offsets DO can be calculated based on the difference in electrical characteristics between the multiple devices and stored in the device corresponding thereto. When the storage device 100 is powered on, the controller 110 can read the first device offset DO1 to the twenty-first device offset DO21 from the first device D1 to the twenty-first device D21, configure and store the first device offset DO1 to the twenty-first device offset DO21 as an offset table OTa, and reference the offset table OTa. For example, the offset table OTa can be stored in the metadata buffer MB.

[0110] refer to Figure 9BEach of the plurality of devices (e.g., the first device D1 to the twenty-first device D21) of the NVM 120 can store an offset (i.e., a block offset BO) of a block included in the device corresponding thereto. During an operation of manufacturing the storage device 100, each of the block offsets BO can be calculated based on a difference in electrical characteristics between the plurality of blocks of the plurality of devices, and stored in the device corresponding thereto. For example, when the first device D1 includes the first block to the eighth block, first block offsets BO11 to eighth block offsets BO18 corresponding to the first block to the eighth block can be stored in the first device D1. When the storage device 100 is powered on, the controller 110 can read the block offsets BO from the first device D1 to the twenty-first device D21, configure and store the block offsets BO as an offset table OTb, and refer to the offset table OTb. For example, the offset table OTb can be stored in the metadata buffer MB. The offset table OTb including the block offsets BO can store the block offsets BO in a device unit. For example, the block offsets BO11 to BO18 corresponding to the first block to the eighth block of the first device D1 can be stored in a block offset BO_D1 entry of the first device D1, and the block offsets BO21 to BO28 corresponding to the blocks of the second device D2 can be stored in a block offset BO_D2 entry of the second device D2.

[0111] The device offset DO or the block offset BO described with reference to Figure 9A and Figure 9B may be used during a history read operation. As described with reference to Figure 1 , in order to compensate for a characteristic difference between the plurality of blocks BLK included in the same super block SB or a characteristic difference between the plurality of memory devices included in each of the plurality of blocks BLK, the controller 110 can add the device offset DO or the block offset BO to a history read level, calculate an adjusted read level, and perform a history read operation according to the adjusted read level.

[0112] Figure 10 is a schematic flowchart of a method of operating the storage device 100 according to an exemplary embodiment of the inventive concept, and Figure 11 is a detailed flowchart of the operating method shown in Figure 10 . Figure 10 and Figure 11 The operating method shown in Figure 1 may be performed by the storage device 100 in a time sequence. The description provided with reference to Figure 1 to Figure 9B may also be applied to the present embodiment.

[0113] With reference to Figure 1 and Figure 10The storage device 100 manages the degradation of the NVM 120 in units of super blocks (S10). In addition, the storage device 100 controls the management of the history buffer HB and the read operation on the NVM 120 in units of super blocks (S20). A super block can include a plurality of memory or memory blocks. For example, the controller 110 can group at least one block included in each of a plurality of memory devices included in the NVM 120 as a super block, or group a plurality of blocks having similar electrical characteristics as a super block in the NVM 120, and control the management of the degradation of the NVM 120, the management of the history buffer HB, and the read operation in units of super blocks. The operations S10 and S20 can be continuously performed during the runtime of the storage device 100.

[0114] Referring to Figure 11 The storage device 100 performs a program and erase operation (S11), and stores and updates a program and erase count of each of a plurality of super blocks (S12). For example, the controller 110 can store a count table (refer to CTB in Figure 4A including a program and erase count corresponding to each of a plurality of super blocks in the metadata buffer MB. As the program and erase operation is continuously performed, the program and erase count can be updated in units of super blocks. As described above, the storage device 100 can manage the degradation of the NVM 120 in units of super blocks.

[0115] The storage device 100 performs a normal read operation on a first block of a super block (S21). For example, the first block can be a block on which a read operation is initially performed among a plurality of blocks of the super block after the storage device 100 is powered on. The storage device 100 can perform a normal read operation on the first block based on a default read level. When the read operation performed based on the default read level fails, the storage device 100 performs a read retry operation based on a modified read level.

[0116] When the read operation on the first block of the super block is successful, the storage device 100 stores the read level as a history read level in the history buffer HB (S22). For example, when the read operation performed based on the default read level is successful, the controller 110 can store the default read level as a history read level of the super block in the history buffer HB. Alternatively, when the read retry operation performed based on the modified read level is successful, the controller 110 can store the modified read level as a history read level of the super block in the history buffer HB.

[0117] The storage device 100 performs a history read operation on the plurality of blocks of the super block based on the history read level stored in the history buffer HB (S23). In operation S22, the history read operation on the super block can be performed after the history read level of the super block is stored in the history buffer HB. For example, when the controller 110 performs a read operation on the first block (hereinafter, referred to as a "host read operation") or performs a host read operation on other blocks of the super block in response to a read request from the host 200, the host read operation can be performed based on the history read level. Alternatively, even when the controller 110 performs a background read operation for updating the history read level, the history read operation can be performed based on the history read level.

[0118] As described above, since the storage device 100 according to an exemplary embodiment manages the program and erase counts of the NVM 120 in units of super blocks, the storage device 100 can manage the degradation of the NVM 120, manage the history read levels stored in the history buffer HB in units of super blocks, and control a read operation. In the storage device 100 according to at least one exemplary embodiment, the endurance and retention characteristics of the plurality of blocks included in the super block can similarly change due to the program and erase operations. Accordingly, the history read levels can be stored and updated in the history buffer HB in units of super blocks, and thus, the recovery code execution time can be minimized, the performance of the storage device 100 can be improved, and the capacity of the history buffer HB can be reduced.

[0119] Figure 12 is a flowchart of a method of operating the storage device 100 according to an exemplary embodiment of the inventive concept. Figure 12 An example of operation S20 of Figure 10 is shown.

[0120] Referring to Figure 1 and Figure 12 , the storage device 100 is powered on (S31). After the storage device 100 is powered on, when the NVM 120 performs a read operation, a history read level can be stored in the history buffer HB and updated.

[0121] The storage device 100 receives a read request for a first block of a first super block from the host 200 (S32). For example, a logical address (e.g., a logical page) received from the host 200 along with a read command can indicate a physical address (e.g., a physical page) corresponding to the first block of the first super block.

[0122] The storage device 100 performs a normal read operation on the first block of the first super block (S33). The storage device 100 can perform the normal read operation based on a default read level set for the first super block. When the read operation fails, the storage device 100 can perform a read retry operation based on a modified read level obtained due to the execution of the recovery code.

[0123] When the read operation on the first block of the first super block is successful, the storage device 100 stores the read level as a history read level of the first super block in the history buffer HB (S34). The default read level or the modified read level can be stored as the history read level. For example, the read level resulting in the successful read operation is stored as the history read level.

[0124] Thereafter, the storage device 100 receives a read request for a second block of the first super block from the host 200 (S35). The storage device 100 performs a history read operation on the second block based on the history read level of the first super block stored in the history buffer HB (S36). Although the history read level of the second block has not been obtained, since the history read level of the super block is managed in units of super blocks and is available during the read operation on the plurality of blocks included in the super block, it is not necessary to perform a read retry operation to obtain the history read level of the second block. Accordingly, the recovery code execution time can be reduced.

[0125] In an embodiment, when the history read operation on the second block fails, the storage device 100 performs a read retry operation on the second block based on the modified read level. When the read operation is successful due to the read retry operation, the modified read level can be stored as the history read level of the first super block in the history buffer HB, and thus, the history read level can be updated.

[0126] Further, although an example has been described in which the storage device 100 performs the normal read operation on the first block in response to the read request received from the host 200 in operations S32 and S33, the inventive concept is not limited thereto. In another embodiment, the storage device 100 performs a background read operation (or a patrol read operation) without receiving a read request from the host 200. When the background read operation on the first block is successful, i.e., when the normal read operation performed based on the default read level or the read retry operation performed based on the modified read level is successful, the storage device 100 can store the read level resulting in the success as the history read level of the first super block in the history buffer HB.

[0127] For example, when the storage device 100 is powered on, the storage device 100 can perform a background read operation on a plurality of blocks of the NVM 120, and store a read level obtained when the read operation on a first block of a first super block is successful as a history read level of the first super block in the history buffer HB. In another example, when the storage device 100 is powered on, the storage device 100 can perform a background read operation on a selected block of each of a plurality of super blocks among a plurality of blocks of the NVM 120. For example, the controller 110 can perform a background read operation on a first block among blocks included in a first super block. When the read operation on the first block is successful, the storage device 100 can store a read level derived in the success as a history read level of the first super block in the history buffer HB.

[0128] Figure 13 is a flowchart of a method of operating the storage device 100 according to an exemplary embodiment of the inventive concept. Figure 13 is Figure 12 is a detailed flowchart of the history read operation (S36), and the history read operation (S36) can be performed by Figure 1 the storage device 100 according to the time sequence.

[0129] Referring to Figure 1 and Figure 13 , the storage device 100 receives a read request for a second block of the first super block from the host 200 (S41). The storage device 100 accesses the history buffer HB to retrieve a history read level of the first super block (S42). For example, the history read level can be a read level stored in operation S34 of Figure 12 .

[0130] The storage device 100 adds an offset indicating a characteristic difference between the first block and the second block to the history read level, and calculates an adjusted read level (S43). For example, when the first block and the second block are included in a first device and a second device, respectively, the controller 110 can refer to an offset table including device offsets (refer to OTa in Figure 9A ), add a difference between a first device offset DO1 and a second device offset DO2 as an offset to the history read level, and calculate the adjusted read level. Alternatively, the controller 110 can refer to an offset table including block offsets (refer to OTb in Figure 9B ), add a difference between an offset of the first block and an offset of the second block as an offset to the history read level, and calculate the adjusted read level.

[0131] The storage device 100 performs a history read operation on the second block based on the adjusted read level (S44).

[0132] Figure 14A and Figure 14B Operation of the controller 110 and the NVM 120 of the storage device according to exemplary embodiments is shown.

[0133] Referring to Figure 14A , the controller 110 issues a read command (S111) and sends the read command to the NVM 120 (S112). The controller 110 can issue the read command in response to a read request from the host (refer to 200 in Figure 1 ). Alternatively, the controller 110 can perform a background read operation and issue the read command by itself. The controller 110 can send, as control signals with the read command, an address of a physical region (e.g., a physical page) in which the read operation is to be performed and a default read level to the NVM 120.

[0134] The NVM 120 performs a normal read operation based on the default read level (S121). The NVM 120 sends the read data to the controller 110 (S122). For example, the data retrieved from the NVM 120 during the normal read operation corresponds to the read data.

[0135] The controller 110 determines whether the normal read operation fails (S113). Specifically, the ECC module (refer to 115 in Figure 7 ) can perform an ECC operation on the received data and determine whether a number of failed bits (e.g., a number of bit errors) detected in the received data exceeds an error correction capability of the ECC module 115. If it is determined that the number of failed bits does not exceed the error correction capability or that the received data does not include failed bits, it is determined that the normal read operation is successful, and the controller 110 stores the read level (e.g., the default read level) as a history read level in the history buffer HB (S118).

[0136] Otherwise, if the number of failed bits exceeds the error correction capability, it is determined that the normal read operation fails, and the controller 110 performs a recovery code (S114). As a result of performing the recovery code, the controller 110 issues a read retry command (S115). In addition, the controller 110 can issue an address of the physical region on which the read operation failed and determine a read retry voltage as a modified read level. The controller 110 sends the read retry command to the NVM 120 (S116). The controller 110 can send the address to the NVM 120 with the read retry command and send the read retry voltage (i.e., the modified read level) as a control signal.

[0137] The NVM 120 performs a read retry operation based on the modified read level (S123), and transmits data read as a result of the read retry operation to the controller 110 (S124).

[0138] The controller 110 determines whether the read operation fails as a result of the read retry operation (S117). As described above in operation S113, the ECC module 115 can perform an ECC operation on the received data, and determine whether the read operation fails based on the result. When the read operation fails, the controller 110 can perform operation S114 again. When the read operation succeeds, the controller 110 stores the read level (i.e., the modified read level) as a history read level in the history buffer HB (S118). Accordingly, the history read level of the super block can be stored in the history buffer HB.

[0139] Figure 14B Operations of the controller 110 and the NVM 120 as a result of the history read operation are illustrated after the operations of Figure 14A

[0140] Referring to Figure 14B The controller 110 receives a read request from the host 200 (S211). The controller 110 can receive the read request and an address from the host 200.

[0141] The controller 110 retrieves a history read level from the history buffer HB (S212). The controller 110 can read the history read level of the super block including the physical page corresponding to the address (i.e., the logical page) from the history buffer HB.

[0142] The controller 110 transmits a read command to the NVM 120 (S213). The controller 110 can transmit the history read level as a control signal to the NVM 120 together with the read command.

[0143] The NVM 120 performs a history read operation based on the history read level (S221). For example, the NVM 120 performs a read operation on the block of the super block using the history read level to retrieve read data. The NVM 120 transmits the read data as a result of performing the history read operation to the controller 110 (S222).

[0144] Subsequently, the controller 110 performs an ECC operation on the received data to determine whether the read operation fails (S214). If the read operation succeeds, the controller 110 transmits the data to the host 200 (S220).

[0145] ​If the read operation fails, the controller 110 executes the recovery code and performs a read retry operation. For example, the execution of the recovery code can adjust the read level, and the read retry operation can compare the voltage representing the read data with the adjusted read level. The subsequent operations S215 to S218 performed by the controller 110 can be the same as the operations S114 to S117 of Figure 14A , and the operations S223 and S224 performed by the NVM 120 can be the same as the operations S123 and S124 of Figure 14A . Thus, the repeated description will be omitted.

[0146] Further, when the read operation is successful in operation S218, the controller 110 updates the history read level of the history buffer HB (S219). The controller 110 can update the history read level based on the modified read level determined due to the execution of the recovery code in operation S215. In addition, the controller 110 transmits the data to the host 200 (S220).

[0147] Figure 15 is a flowchart of a method of operating the storage device 100 according to an exemplary embodiment of the inventive concept. Figure 15 The host read operation performed when a read request is received from the host is illustrated. Figure 15 The operation method of Figure 1 may be performed by the storage device 100 of Figure 15 . Thus, the operation method of Figure 1 will be described with reference to

[0148] The storage device 100 receives a read request and an address from the host 200 (S310). The address can include an address of a logical area (i.e., a logical address), and the storage device 100 can determine a physical area (e.g., a physical page) corresponding to the logical area, and determine a block and a super block including the physical area. For example, the super block includes the determined block.

[0149] The storage device 100 determines whether the history buffer HB is empty (S320). Here, it will be understood that when the history buffer HB is referred to as "empty", no history read level of a super block corresponding to a block to be read is stored in the history buffer HB. For example, when the history read levels of super blocks other than the super block corresponding to the block to be read are stored in the history buffer HB, the history buffer HB can be determined to be empty.

[0150] When the history buffer HB is empty, in other words, when there is no history read level of a super block corresponding to a physical region to be read in the history buffer HB, the storage device 100 performs a normal read operation based on a default read level (S330). In contrast, when the history buffer HB is not empty, in other words, when there is a history read level of a super block corresponding to a physical region to be read in the history buffer HB, the storage device 100 performs a history read operation based on the history read level (S340).

[0151] After performing the normal read operation or the history read operation, the storage device 100 determines whether the read operation failed (S350). If the read operation failed, the storage device 100 performs a read retry operation (S360). The storage device 100 updates the history read level of the history buffer HB based on a modified read level obtained when the read retry operation succeeds (S370). The storage device 100 can transmit the read data to the host 200 (S380).

[0152] In addition, in Figure 15 , the history buffer HB can be updated in operation S370 due to a host read operation. However, the inventive concept is not limited thereto, and as will be described below with reference to Figure 16 , the history buffer HB can be updated due to a background read operation of the storage device 100.

[0153] Figure 16 is a flowchart of a method of updating a history buffer HB of a storage device 100 according to an exemplary embodiment of the inventive concept. Figure 16 The updating method of Figure 1 may be performed by the storage device 100 in a time series.

[0154] Referring to Figure 1 and Figure 16 , the storage device 100 performs a background read operation on a representative block of each of a plurality of super blocks of the NVM 120 (S410). The storage device 100 can previously set one block of each of the plurality of super blocks as a representative block, and sequentially perform the background read operation on the representative blocks. The storage device 100 can periodically or aperiodically perform the background read operation. For example, when a predetermined time elapses after performing a read operation on a super block, the background read operation S410 can be performed based on a history read level previously stored in the history buffer HB. For example, the background read operation can be performed to ensure that each super block has the latest read level stored in the history buffer HB.

[0155] The storage device 100 determines whether the read operation failed (S420). If the read operation failed, the storage device 100 performs a read retry operation (S430). The read retry operation can include modifying the read level applied to the representative block and comparing the voltage representing the data of the representative block with the modified read level to determine a codeword. If the read retry operation is successful, the storage device 100 updates the history buffer HB based on the modified read level (S440). For example, the read retry operation can be successful when the ECC operation performed on the codeword is successful. The storage device 100 can store the modified read level in the history buffer HB as a history read level of the superblock corresponding to the representative block on which the background read operation S410 is performed. Otherwise, if it is determined that the read operation is successful in operation S420, the storage device 100 can end the background read operation without updating the history buffer HB.

[0156] Figure 17 is a flowchart of a method of grouping superblocks of the storage device 100 according to an exemplary embodiment of the inventive concept.

[0157] Referring to Figure 1 and Figure 17 , the storage device 100 is initialized (S510). For example, the storage device 100 can be initialized during use or after a manufacturing operation. For example, initializing the storage device 100 can include setting characteristic information in the storage device.

[0158] The controller 110 of the storage device 100 reads characteristic information about each of a plurality of blocks from the NVM 120 (S520). During a manufacturing operation or a subsequent test operation, characteristics of each of the plurality of blocks can be detected, and the characteristic information can be stored in the device. The controller 110 can read the characteristic information about the blocks from a plurality of devices corresponding to the blocks.

[0159] The controller 110 groups the plurality of blocks into a plurality of superblocks based on the characteristic information (S530). In an exemplary embodiment, the controller 110 groups blocks having similar characteristics into one superblock. Thereafter, as described above, the controller 110 can manage metadata and a history buffer in units of superblocks.

[0160] Figure 18 is a flowchart of a method of regrouping superblocks of the storage device 100 according to an exemplary embodiment of the inventive concept. Figure 19A and Figure 19B shows an example of the regrouping method of Figure 18 .

[0161] Referring to Figure 18The storage device 100 performs a background read operation on each of the plurality of blocks of the NVM 120 (S610). The storage device 100 calculates a characteristic value of each of the plurality of blocks based on a result of the background read operation (S620). For example, the characteristic value can include a width of a threshold voltage distribution and a minimum level of a threshold voltage.

[0162] The storage device 100 re-groups the plurality of blocks based on the characteristic value (S630).

[0163] In an embodiment, as shown in Figure 19A , the storage device 100 re-groups the plurality of blocks such that blocks having equal or similar characteristic values are included in the same super block. In Figure 19A , blocks located in the same position or row among the plurality of devices D1 to D8 are grouped into one super block before the re-grouping process. The storage device 100 can perform the re-grouping process based on the characteristic values of the plurality of blocks detected due to the background read operation, and re-group blocks having equal or similar characteristic values into one super block regardless of the position of each block.

[0164] In an exemplary embodiment, the storage device 100 determines a defective block based on the characteristic value, and replaces the defective block with another block in the super block. For example, referring to Figure 19B , the blocks B12 to B82 are initially grouped into the second super block SB2. When it is determined that there is a defect in the block B82 due to the background read operation, the block B82 is replaced with the block Bd8. Accordingly, the blocks B12, B22, and Bd8 can be subsequently re-grouped into the second super block SB2.

[0165] Referring back to Figure 18 , the storage device 100 manages the metadata and the history buffer in units of the re-grouped super blocks (S640).

[0166] Figure 20 is a flowchart of a method of operating the storage device 100 according to an exemplary embodiment of the inventive concept. Figure 21 An example of the operation method shown in Figure 20 is illustrated.

[0167] Referring to Figure 20 , the storage device 100 manages degradation of the NVM in units of a memory group including a plurality of blocks (S10a). The storage device 100 manages a history buffer and a read operation in units of a sub-group of the memory group (S20a).

[0168] Referring to Figure 21, multiple memory devices (e.g., devices D1 to D8) can constitute NVM 120, and at least one block in devices D1 to D8 can be grouped into a super block. For example, the corresponding first blocks (e.g., blocks B11 to B81) of devices D1 to D8 can be grouped into a first super block SB1. In addition, blocks with similar characteristics in a super block (e.g., first super block SB1) can be grouped into sub-groups. For example, in the first super block SB1, blocks B11, B21, B31, and B51 can be included in a first sub-group SG1, and blocks B41, B61, B71, and B81 with similar electrical characteristics can be included in a second sub-group SG2.

[0169] The storage device 100 can obtain and store the program and erase counts of each of a plurality of Super Blocks (e.g., first Super Block SB1 to kth Super Block SBk), manage degradation of the NVM 120 in units of Super Blocks, and store and update a history read level for each of the sub-groups (e.g., first sub-group SG1 and second sub-group SG2). Therefore, the history buffer and read operations can be managed in units of sub-groups.

[0170] Figure 22 is a block diagram of an SSD 1200 and an SSD system 1000 including the SSD 1200 according to an exemplary embodiment of the inventive concept.

[0171] refer to Figure 22 , the SSD system 1000 includes a host 1100 and an SSD 1200. The SSD 1200 can communicate with the host 1100 and send and receive signals (eg, commands, addresses, and data) to and from the host 1100. The SSD 1200 can receive power from the host 1100 to operate.

[0172] The SSD 1200 includes an SSD controller 1210 (eg, a control circuit), a plurality of NVM devices (eg, 1220, 1230, and 1240), and a buffer memory 1300. Figure 1 to Figure 21The described storage device 100 and controller 110 can be applied to the SSD 1200 and the SSD controller 1210, respectively. For example, the SSD controller 1210 can include the controller 110, the controller 110a, etc. The NVM devices 1220, 1230, and 1240 can be implemented as a plurality of semiconductor chips. The SSD controller 1210 can communicate with the NVM devices 1220, 1230, and 1240 through a plurality of channels CH1, CH2, and CHn. For example, at least one memory block included in each memory chip included in each of the NVM devices 1220, 1230, and 1240 can constitute a super block. The SSD 1200 can manage metadata (e.g., a degree of deterioration and program and erase counts) and a history buffer (e.g., a history read level) in units of super blocks.

[0173] The buffer memory 1300 can be implemented as a volatile memory or a resistive memory. For example, the buffer memory 1300 can include a DRAM. The buffer memory 1300 can temporarily store data received from the host 1100 and to be stored in the NVM devices 1220, 1230, and 1240, or data read from the NVM devices 1220, 1230, and 1240 and to be transmitted to the host 1100. In an exemplary embodiment, the history buffer is implemented as a part of the buffer memory 1300.

[0174] In addition to the SSD system 1000, a storage system according to at least one of the above-described embodiments can be installed or applied to a memory card system, a universal flash storage (UFS), and / or an embedded storage.

[0175] While the present inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details can be made therein without departing from the spirit and scope of the disclosure.

Claims

1. A method of operating a storage device including a non-volatile memory, the method comprising: storing program and erase counts of the non-volatile memory as metadata in units of super blocks, wherein each of the super blocks includes at least two blocks among a plurality of blocks of the non-volatile memory; performing a read operation on a first block included in a first super block of the plurality of super blocks based on a first read level; when the read operation on the first block is successful, storing the first read level as a history read level of the first super block in a history buffer; receiving a read request for a second block of the first super block and an address of the second block from a host; calculating an adjusted read level by adding a characteristic offset indicating a characteristic difference between the first block and the second block to the history read level; and performing a read operation on the second block based on the adjusted read level.

2. The method of claim 1, further comprising: when the read operation on the second block fails, generating a modified read level from the first read level; performing a read retry operation on the second block using the modified read level; and updating the first read level of the first super block stored in the history buffer based on the modified read level.

3. The method of claim 1, further comprising: when the history read level is not present, performing the read operation on the second block based on a default read level.

4. The method of claim 3, further comprising: when the read operation on the second block fails, generating a second modified read level from the history read level or from the default read level; performing a read retry operation on the second block based on the second modified read level; and updating the history buffer by storing the second modified read level as the history read level of the first super block. the non-volatile memory includes a plurality of memory devices, a device offset indicating an electrical characteristic of each of the plurality of memory devices is stored in the memory device corresponding thereto, and the first block and the second block are respectively included in a first memory device and a second memory device of the plurality of memory devices, and the characteristic offset is calculated based on the device offset of the first memory device and the device offset of the second memory device.

5. The method of claim 1, wherein, 6. The method of claim 1, further comprising: grouping the plurality of blocks into the plurality of super blocks based on characteristics of the plurality of blocks.

7. The method of claim 1, further comprising: performing a background read operation on at least one block selected from the first super block based on the history read level; when the background read operation fails, generating a modified read level from the history read level; performing a read retry operation on the selected at least one block based on the modified read level; and updating the history buffer by storing the modified read level as the history read level of the first super block.

8. The method of claim 1, further comprising: performing a background read operation on each of the super blocks; calculating a characteristic value of each block of the super blocks based on the background read operation; detecting a defective block in a selected super block among the super blocks based on the characteristic value; and replacing the detected defective block with another block of the non-volatile memory. ​ ​ ​ ​ 9. The method of claim 1, wherein, In response to a read request received from a host, a read operation on the first block is performed based on a default read level.

10. A storage device comprising: a non-volatile memory comprising a plurality of physical blocks; as well as a controller configured to group a plurality of physical blocks into a plurality of groups, store program and erase counts of each of the plurality of groups as metadata, store a read level of each of the plurality of groups in a history buffer, and, when receiving a read command and an address from a host, control the nonvolatile memory to perform a read operation on a selected physical block among the physical blocks corresponding to the address based on a corresponding read level among the plurality of read levels stored in the history buffer, wherein, when determining a corresponding read level based on another physical block of a selected group including a selected physical block in a group, the controller determines an adjusted read level by adding an offset to the corresponding read level, and sends the adjusted read level to the nonvolatile memory to be used during a read operation on the physical block, wherein the offset is obtained based on a characteristic difference between the selected physical block and the another physical block.

11. The storage device of claim 10, wherein, When it is determined that the read operation performed on the physical block based on the corresponding read level has failed, the controller modifies the corresponding read level and performs a read retry operation on the selected physical block based on the modified read level.

12. The storage device of claim 11, wherein, When it is determined that the read retry operation performed on the selected physical block based on the modified read level is successful, the controller updates the corresponding read level stored in the history buffer to the modified read level.

13. The storage device of claim 10, wherein, The controller controls the nonvolatile memory to perform a background read operation on the plurality of physical blocks and regroup the plurality of physical blocks based on a characteristic value of each of the plurality of physical blocks, the characteristic value being calculated based on the background read operation.

14. A method of operating a storage device including a non-volatile memory, the non-volatile memory including a plurality of memory blocks divided into a plurality of memory groups, the method comprising: performing a read operation on a first block included in a first memory group among the plurality of memory groups based on a first read level; When the read operation on the first block is successful, storing the first read level as the read level of the first memory group in the history buffer; receiving, from a host, a read request for a second block included in the first memory group and an address of the second block; determining a second read level based on the first read level stored in the history buffer and a characteristic offset indicating a characteristic difference between the first block and the second block; as well as A read operation is performed on the second block based on the second read level.

15. The method of claim 14, wherein, The first read level is a default read level previously set for the first memory group.

16. The method according to claim 14, further comprising: obtaining program and erase counts for nonvolatile memory of each of a plurality of memory banks; as well as The program and erase counts are stored as metadata in the storage device.

17. The method of claim 14, wherein, A nonvolatile memory includes a plurality of memory devices, a device offset indicating an electrical characteristic of each of the plurality of memory devices is stored in the memory device corresponding thereto, and The first block and the second block are located in a first memory device and a second memory device, respectively, of the plurality of memory devices, and the characteristic offset is calculated based on a device offset of the first memory device and a device offset of the second memory device.

18. The method of claim 17, wherein, The location of the first block in the first memory device corresponds to the location of the second block in the second memory device.

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