Scan drivers and display devices

Abstract

The present invention relates to a scan driver and a display device. The scan driver includes: a plurality of first stages, the plurality of first stages are configured to sequentially output a plurality of intermediate scan signals based on a scan start signal; a plurality of shielding transistors, the plurality of shielding transistors are respectively connected to a plurality of output terminals of the plurality of first stages, and are configured to selectively transmit a plurality of intermediate scan signals in response to the shielding signals; and a plurality of second stages, the plurality of second stages include a plurality of input terminals respectively connected to the plurality of shielding transistors, and are configured to selectively output a plurality of scan signals based on the plurality of intermediate scan signals selectively transmitted through the plurality of shielding transistors.

Description

Technical Field

[0001] Aspects of some example embodiments relate to a scan driver and a display device. Background Art

[0002] For example, to preserve battery life, reducing power consumption may be desirable in a display device employed in a portable device such as a smart phone, a tablet computer, etc. For example, to reduce power consumption of a display device, a low-frequency driving technique that drives or refreshes a display panel at a frequency lower than a normal driving frequency may be utilized.

[0003] However, in a display device to which the low-frequency driving technology is applied, when a still image is not displayed in the entire area of ​​the display panel, or when a still image is displayed in only a partial area of ​​the display panel, the entire area of ​​the display panel may be driven at a normal driving frequency. Therefore, in this case, the low-frequency driving may not be performed, and the power consumption may not be reduced.

[0004] The above information disclosed in this Background section is only for enhancement of understanding of the background technology, and therefore, the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0005] Aspects of some example embodiments relate to a scan driver and a display device, and, for example, to a scan driver and a display device capable of performing multi-frequency driving (MFD).

[0006] Aspects of some example embodiments include a scan driver capable of providing a plurality of scan signals to a plurality of panel regions at different driving frequencies.

[0007] Aspects of some example embodiments include a display device including a scan driver.

[0008] According to some example embodiments, a scan driver includes: a plurality of first stages, the plurality of first stages being configured to sequentially output a plurality of intermediate scan signals based on a scan start signal; a plurality of shielding transistors, the plurality of shielding transistors being respectively connected to a plurality of output terminals of the plurality of first stages and being configured to respectively selectively transmit the plurality of intermediate scan signals in response to the shielding signals; and a plurality of second stages, the plurality of second stages including a plurality of input terminals respectively connected to the plurality of shielding transistors and being configured to selectively output the plurality of scan signals based on the plurality of intermediate scan signals selectively transmitted through the plurality of shielding transistors.

[0009] According to some example embodiments, the plurality of first stages may sequentially output all of the plurality of intermediate scanning signals in a frame period, and the plurality of second stages may not output at least a portion of the plurality of scanning signals in a holding period of the frame period.

[0010] According to some example embodiments, the shielding signal may be changed to the off level one horizontal time before the start time point of the holding period, and may be changed to the on level one horizontal time before the end time point of the holding period.

[0011] According to some example embodiments, each of the plurality of shielding transistors may not transmit a corresponding one of the plurality of intermediate scanning signals in response to a shielding signal having a cut-off level, and may transmit a corresponding one of the plurality of intermediate scanning signals to a corresponding one of the plurality of second stages in response to a shielding signal having a turn-on level.

[0012] According to some example embodiments, each of the plurality of shielding transistors may include a gate for receiving a shielding signal, a first terminal connected to a corresponding one of a plurality of output terminals of the plurality of first stages, and a second terminal connected to a corresponding one of a plurality of input terminals of the plurality of second stages.

[0013] According to some example embodiments, each of the plurality of scan signals selectively output from the plurality of second stages may be delayed by one horizontal time with respect to a corresponding one of the plurality of intermediate scan signals output from the plurality of first stages.

[0014] According to some example embodiments, a Kth first stage among the plurality of first stages may output a Kth intermediate scanning signal among the plurality of intermediate scanning signals based on a K-1th intermediate scanning signal among the plurality of intermediate scanning signals output from a K-1th first stage among the plurality of first stages, wherein K is an integer greater than 1, and a Kth second stage among the plurality of second stages may selectively output a Kth scanning signal among the plurality of scanning signals based on a Kth intermediate scanning signal among the plurality of intermediate scanning signals selectively transmitted through a Kth shielding transistor among the plurality of shielding transistors.

[0015] According to some example embodiments, each of the plurality of second stages may have a structure substantially the same as a structure of each of the plurality of first stages.

[0016] According to some example embodiments, each of the plurality of first stages and the plurality of second stages may include: an input circuit configured to transmit an input signal to a first node in response to a first clock signal; a stress relief circuit located between the first node and the second node and configured to transmit the input signal from the first node to the second node so that a voltage of the second node is changed to a first conduction level; and a bootstrap circuit configured to change a voltage of the second node from the first conduction level to a second conduction level by bootstrapping the second node based on a second clock signal, wherein the first and second stages are configured to transmit the input signal from the first node to the second node so that a voltage of the second node is changed to a first conduction level. A second conduction level having an absolute value greater than the absolute value of the first conduction level; a scan output circuit, which is configured to output a second clock signal as an output signal in response to a voltage of a second node having a second conduction level; a holding circuit, which is configured to hold a third node at a cut-off level while the output signal is output; and a stabilization circuit, which is configured to periodically apply a gate-on voltage to the third node in response to the second clock signal, and to periodically apply a gate-off voltage to the first node in response to the first clock signal after the output signal is output.

[0017] According to some example embodiments, the input circuit may include a first transistor including a gate for receiving a first clock signal, a first terminal for receiving the input signal, and a second terminal connected to a first node; the bootstrap circuit may include a first capacitor including a first electrode connected to a scan output node at which an output signal is output, and a second electrode connected to a second node; the holding circuit may include a fourth transistor including a gate connected to the first node, a first terminal connected to a third node, and a second terminal for receiving the first clock signal; the stabilization circuit may include a second transistor, a third transistor, a fifth transistor, and a second capacitor, the second transistor including a gate connected to the third node, a second terminal, and a first terminal for receiving a gate-off voltage, the third transistor including a gate for receiving a second clock signal, a first terminal connected to the second transistor, and a second terminal for receiving a gate-off voltage. The first terminal of the second terminal and the second terminal connected to the first node, the fifth transistor includes a gate for receiving a first clock signal, a first terminal connected to the third node and a second terminal for receiving a gate-on voltage, the second capacitor includes a first electrode for receiving a gate-off voltage and a second electrode connected to the third node; the scan output circuit may include a sixth transistor and a seventh transistor, the sixth transistor includes a gate connected to the third node, a first terminal for receiving a gate-off voltage and a second terminal connected to the scan output node, the seventh transistor includes a gate connected to the second node, a first terminal connected to the scan output node and a second terminal for receiving a second clock signal; and the stress relief circuit may include an eighth transistor, the eighth transistor includes a gate for receiving a gate-on voltage, a first terminal connected to the first node and a second terminal connected to the second node.

[0018] According to some example embodiments, a Kth first stage among the plurality of first stages may output a Kth intermediate scanning signal among the plurality of intermediate scanning signals based on a previous carry signal output from a K-1th first stage among the plurality of first stages, wherein K is an integer greater than 1, and a Kth second stage among the plurality of second stages may selectively output a Kth scanning signal among the plurality of scanning signals based on a Kth intermediate scanning signal among the plurality of intermediate scanning signals selectively transmitted through a Kth shielding transistor among the plurality of shielding transistors.

[0019] According to some example embodiments, each of the plurality of first stages may further include a carry output circuit compared to each of the plurality of second stages.

[0020] According to some example embodiments, the carry output circuit may include a ninth transistor and a tenth transistor, the ninth transistor including a gate connected to a third node, a first terminal for receiving a gate-off voltage, and a second terminal connected to a carry output node at which a carry signal is output, and the tenth transistor including a gate connected to a second node, a first terminal connected to the carry output node, and a second terminal for receiving a second clock signal.

[0021] According to some example embodiments, the scan driver may further include a plurality of switching transistors configured to transmit the gate-off voltage to the plurality of input terminals of the plurality of second stages in response to an inverted shielding signal which is an inverted signal of the shielding signal.

[0022] According to some example embodiments, each of the plurality of switch transistors may include a gate for receiving an inverted shielding signal, a first terminal for receiving a gate-off voltage, and a second terminal connected to a corresponding one of a plurality of input terminals of the plurality of second stages.

[0023] According to some example embodiments, a plurality of scan signals may be selectively provided to a plurality of pixels included in a display device including a scan driver, and a plurality of intermediate scan signals may be provided to the plurality of pixels as a plurality of initialization signals.

[0024] According to some example embodiments, a display device includes: a display panel including a plurality of pixel rows; a data driver configured to provide a data signal to each of the plurality of pixel rows; a scan driver configured to provide a plurality of scan signals to the plurality of pixel rows, respectively; and a controller configured to control the data driver and the scan driver, and to provide a scan start signal and a shielding signal to the scan driver. The scan driver includes: a plurality of first stages configured to sequentially output a plurality of intermediate scan signals based on the scan start signal; a plurality of shielding transistors respectively connected to a plurality of output terminals of the plurality of first stages and configured to selectively transmit the plurality of intermediate scan signals in response to the shielding signal; and a plurality of second stages including a plurality of input terminals respectively connected to the plurality of shielding transistors and configured to selectively output a plurality of scan signals based on the plurality of intermediate scan signals selectively transmitted through the plurality of shielding transistors.

[0025] According to some example embodiments, the plurality of first stages may sequentially output all of the plurality of intermediate scanning signals in a frame period, and the plurality of second stages may not output at least a portion of the plurality of scanning signals in a holding period of the frame period.

[0026] According to some example embodiments, the controller may include: a still image detection block configured to divide input image data into a plurality of panel area data of a plurality of panel areas, and determine whether each of the plurality of panel area data represents a still image, each panel area including at least one pixel row of a plurality of pixel rows; a driving frequency determination block configured to determine a plurality of driving frequencies of the plurality of panel areas according to whether each of the plurality of panel area data represents a still image; and a scanning driver control block configured to generate a shielding signal based on the plurality of driving frequencies of the plurality of panel areas.

[0027] According to some example embodiments, the scan driver control block may set at least a portion of one or more frame periods as a holding period, may change the shielding signal to an off level one horizontal time before a starting time point of the holding period, and may change the shielding signal to an on level one horizontal time before an ending time point of the holding period.

[0028] As described above, in the scan driver and the display device according to some example embodiments, the plurality of first stages may sequentially output the plurality of intermediate scan signals, the plurality of shielding transistors may selectively transmit the plurality of intermediate scan signals respectively in response to the shielding signals, and the plurality of second stages may selectively output the plurality of scan signals based on the plurality of intermediate scan signals selectively transmitted through the plurality of shielding transistors. Therefore, the scan driver according to some example embodiments may provide the plurality of scan signals to the plurality of panel regions at different driving frequencies. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0030] Figure 1 is a block diagram illustrating a scan driver according to some example embodiments.

[0031] Figure 2 is a circuit diagram illustrating an example of each first stage or each second stage included in a scan driver according to some example embodiments.

[0032] Figure 3 Is used to describe Figure 2 A timing diagram of an example of the operation of the stage.

[0033] Figure 4 is a timing diagram for describing an example of an operation of a scan driver according to some example embodiments.

[0034] Figure 5is a circuit diagram illustrating another example of each first stage included in a scan driver according to some example embodiments.

[0035] Figure 6 is a block diagram illustrating a scan driver according to some example embodiments.

[0036] Figure 7 is a block diagram illustrating a display device including a scan driver according to some example embodiments.

[0037] Figure 8 is a circuit diagram illustrating an example of a pixel included in a display device according to some example embodiments.

[0038] Fig. 9 is a diagram illustrating an example of a display panel including a plurality of panel areas driven at different driving frequencies in a display device according to some example embodiments.

[0039] Fig.10 is used to describe the scanning signal provided to Fig. 9 FIG. 1 is a timing diagram of an example of the operation of a scan driver of a display panel.

[0040] Fig.11 An electronic device including a display device according to some example embodiments. DETAILED DESCRIPTION

[0041] Hereinafter, aspects of some example embodiments of the inventive concept will be explained in more detail with reference to the accompanying drawings.

[0042] Figure 1 is a block diagram illustrating a scan driver according to some example embodiments, Figure 2 is a circuit diagram illustrating an example of each first stage or each second stage included in a scan driver according to some example embodiments, Figure 3 Is used to describe Figure 2 A timing diagram of an example of the operation of the stage, and Figure 4 is a timing diagram for describing an example of an operation of a scan driver according to some example embodiments.

[0043] refer to Figure 1 , the scan driver 100 according to some example embodiments may include a plurality of first stages 110 , a plurality of shielding transistors MST1 to MSTN, and a plurality of second stages 130 .

[0044] The plurality of first stages 110 may receive a scan start signal FLM, and may sequentially output a plurality of intermediate scan signals ISS1 to ISSN based on the scan start signal FLM. A first first stage 111 of the first stages 110 may receive the scan start signal FLM as an input signal, and may output a first intermediate scan signal ISS1 based on the scan start signal FLM. In some example embodiments, the scan driver 100 includes N first stages 111 to 117, and an input terminal of a Kth first stage of the N first stages 111 to 117 may be connected to an output terminal of a previous stage or an output terminal of a K-1th first stage of the N first stages 111 to 117, wherein N is an integer greater than 1, and K is an integer greater than 1 and less than or equal to N. Therefore, the Kth first stage of the N first stages 111 to 117 may receive a K-1th intermediate scan signal from a K-1th first stage of the N first stages 111 to 117 as an input signal, and may output a Kth intermediate scan signal based on the K-1th intermediate scan signal. For example, the second first stage 112 among the N first stages 111 to 117 may output the second intermediate scanning signal ISS2 based on the first intermediate scanning signal ISS1, the third first stage 113 among the N first stages 111 to 117 may output the third intermediate scanning signal ISS3 based on the second intermediate scanning signal ISS2, the fourth first stage 114 among the N first stages 111 to 117 may output the fourth intermediate scanning signal ISS4 based on the third intermediate scanning signal ISS3, the fifth first stage 115 among the N first stages 111 to 117 may output the fifth intermediate scanning signal ISS5 based on the fourth intermediate scanning signal ISS4, and the Nth first stage 117 among the N first stages 111 to 117 may output the Nth intermediate scanning signal ISSN based on the N-1th intermediate scanning signal ISSN-1.

[0045] The plurality of first stages 110 may further receive a first clock signal CLK1-1 and a second clock signal CLK2-1 having different phases (e.g., opposite phases). In some example embodiments, odd-numbered stages 111, 113, 115, ... among the plurality of first stages 110 may receive an input signal in response to the first clock signal CLK1-1, and may output odd-numbered intermediate scanning signals ISS1, ISS3, ISS5, ... in response to the second clock signal CLK2-1. Further, even-numbered stages 112, 114, ... among the plurality of first stages 110 may receive an input signal in response to the second clock signal CLK2-1, and may output even-numbered intermediate scanning signals ISS2, ISS4, ... in response to the first clock signal CLK1-1.

[0046] In some example embodiments, each of the plurality of first stages 110 may have Figure 2The structure of stage 200 is shown in FIG. Figure 2 An example is shown in which the stage 200 (e.g., odd-numbered stages 111, 113, 115, ... among the plurality of first stages 110) receives an input signal SIN (e.g., a scan start signal FLM or a previous intermediate scan signal) in response to a first clock signal CLK1 (e.g., a first clock signal CLK1-1), and outputs an output signal SOUT (e.g., one of the plurality of intermediate scan signals ISS1 to ISSN) in response to a second clock signal CLK2 (e.g., a second clock signal CLK2-1). In some example embodiments, as Figure 2 As shown in FIG. 2 , each stage 200 may include an input circuit 210 , a stress relaxation circuit 220 , a bootstrap circuit 230 , a scan output circuit 240 , a holding circuit 250 , and a stabilization circuit 260 .

[0047] The input circuit 210 may transmit the input signal SIN to the first node NQ' in response to the first clock signal CLK1. In some example embodiments, the stress relief circuit 220 may be located at the Q node, and thus, the Q node may be divided into the first node NQ' and the second node NQ by the stress relief circuit 220. The input circuit 210 may be connected to the first node NQ'. In some example embodiments, the input circuit 210 may include a first transistor T1 including a gate for receiving the first clock signal CLK1, a first terminal for receiving the input signal SIN, and a second terminal connected to the first node NQ'. Further, in some example embodiments, as Figure 2 As illustrated in FIG. 1 , the first transistor T1 may be implemented using, but not limited to, a double transistor including two transistors connected in series.

[0048] The stress relief circuit 220 may be located between the first node NQ' and the second node NQ, and may transmit the input signal SIN from the first node NQ' to the second node NQ. The voltage of the second node NQ may be changed to a first conduction level by the input signal SIN transmitted to the second node NQ. In some example embodiments, the stress relief circuit 220 may include an eighth transistor T8 including a gate for receiving a gate-on voltage VGL (e.g., a low gate voltage), a first terminal connected to the first node NQ', and a second terminal connected to the second node NQ. When the voltage of the second node NQ has a second conduction level having an absolute value greater than the absolute value of the first conduction level, the stress relief circuit 220 or the eighth transistor T8 may not transmit the voltage of the second node NQ having the second conduction level to the first node NQ', thereby reducing the voltage stress applied to the transistors T1, T3, and T4 connected to the first node NQ'.

[0049] The bootstrap circuit 230 may change the voltage of the second node NQ from the first conduction level to the second conduction level by bootstrapping the second node NQ based on the second clock signal CLK2. In some example embodiments, the first conduction level may be a first low level, and the second conduction level may be a second low level lower than the first low level. Further, the voltage level difference between the first conduction level (e.g., the first low level) and the second conduction level (e.g., the second low level) may correspond to, but is not limited to, the voltage level difference between the cut-off level (e.g., the high level) and the first conduction level (e.g., the first low level). In some example embodiments, the bootstrap circuit 230 may include a first capacitor C1, the first capacitor C1 including a first electrode connected to the scan output node NSO where the output signal SOUT is output and a second electrode connected to the second node NQ.

[0050] The scan output circuit 240 may output the second clock signal CLK2 as the output signal SOUT in response to the voltage of the bootstrapped second node NQ or the voltage of the second node NQ having the second conduction level. In some example embodiments, the scan output circuit 240 may include a sixth transistor T6 and a seventh transistor T7, the sixth transistor T6 including a gate connected to the third node NQB, a first terminal for receiving a gate-off voltage VGH (e.g., a high gate voltage), and a second terminal connected to the scan output node NSO, and the seventh transistor T7 including a gate connected to the second node NQ, a first terminal connected to the scan output node NSO, and a second terminal for receiving the second clock signal CLK2.

[0051] The holding circuit 250 may hold the third node NQB at a cut-off level (e.g., a high level) while the output signal SOUT is output. In some example embodiments, the holding circuit 250 may include a fourth transistor T4 including a gate connected to the first node NQ', a first terminal connected to the third node NQB, and a second terminal for receiving the first clock signal CLK1.

[0052] After the output signal SOUT is output, the stabilization circuit 260 may periodically apply the gate-on voltage VGL to the third node NQB in response to the second clock signal CLK2, and may periodically apply the gate-off voltage VGH to the first node NQ' in response to the first clock signal CLK1. The gate-off voltage VGH applied to the first node NQ' may be transmitted to the second node NQ through the eighth transistor T8, and thus, the gate-off voltage VGH may also be periodically applied to the second node NQ. In some example embodiments, the stabilization circuit 260 may include a second transistor T2, a third transistor T3, a fifth transistor T5, and a second capacitor C2, the second transistor T2 including a gate connected to a third node NQB, a second terminal, and a first terminal for receiving a gate-off voltage VGH, the third transistor T3 including a gate for receiving a second clock signal CLK2, a first terminal connected to the second terminal of the second transistor T2, and a second terminal connected to the first node NQ', the fifth transistor T5 including a gate for receiving a first clock signal CLK1, a first terminal connected to the third node NQB, and a second terminal for receiving a gate-on voltage VGL, and the second capacitor C2 including a first electrode for receiving the gate-off voltage VGH and a second electrode connected to the third node NQB.

[0053] In the following, reference will be made to Figure 2 and Figure 3 An example of the operation of stage 200 is described.

[0054] refer to Figure 2 and Figure 3 Each stage 200 may receive an input signal SIN, a first clock signal CLK1, and a second clock signal CLK2. Figure 3 As illustrated in , the on period of each of the first clock signal CLK1 and the second clock signal CLK2 may be shorter than the off period of each of the first clock signal CLK1 and the second clock signal CLK2. For example, each of the first clock signal CLK1 and the second clock signal CLK2 may have a duty cycle ranging from, but not limited to, about 20% to about 40%. In other example embodiments, the on period of each of the first clock signal CLK1 and the second clock signal CLK2 may be longer than or equal to the off period of each of the first clock signal CLK1 and the second clock signal CLK2. Figure 2 and Figure 3 An example is shown, in which transistors T1 to T8 are PMOS transistors, the first on-level is a first low level L, the second on-level is a second low level 2L, the off-level is a high level H, the gate on-voltage is a low gate voltage VGL, and the gate off-voltage is a high gate voltage VGH.

[0055] In a period from the first time point TP1 to the second time point TP2, an input signal SIN having a first low level L may be applied, and a first clock signal CLK1 having a first low level L may be applied. The first transistor T1 may transmit the input signal SIN to the first node NQ', and thus, a voltage V_NQ' of the first node NQ' may be changed from a high level H to a first low level L. Further, the eighth transistor T8 may transmit the input signal SIN from the first node NQ' to the second node NQ in response to the low gate voltage VGL having a first low level L, and thus, a voltage V_NQ of the second node NQ may be changed from a high level H to a first low level L.

[0056] The first clock signal CLK1 may be changed from the first low level L to the high level H at the second time point TP2, and the first clock signal CLK1 having the high level H may be applied in a period from the second time point TP2 to the third time point TP3. The fourth transistor T4 may transmit the first clock signal CLK1 having the high level H to the third node NQB in response to the voltage V_NQ' of the first node NQ' having the first low level L, and the voltage V_NQB of the third node NQB may be changed from the first low level L to the high level H.

[0057] The second clock signal CLK2 may be changed from the high level H to the first low level L at the third time point TP3, and the second clock signal CLK2 having the first low level L may be applied in a period from the third time point TP3 to the fourth time point TP4. The seventh transistor T7 may transmit the second clock signal CLK2 having the first low level L to the scan output node NSO in response to the voltage V_NQ of the second node NQ, and the second clock signal CLK2 may be output as the output signal SOUT at the scan output node NSO. In this case, the voltage of the scan output node NSO or the voltage of the first electrode of the first capacitor C1 may be changed from the high level H to the first low level L, and therefore, the voltage of the second electrode of the first capacitor C1 or the voltage V_NQ of the second node NQ may be changed from the first low level L to the second low level 2L lower than the first low level L. In some example embodiments, the voltage level difference between the first low level L and the second low level 2L may correspond to, but is not limited to, the voltage level difference between the high level H and the first low level L. Here, the operation of changing the voltage V_NQ of the second node NQ from the first low level L to the second low level 2L may be referred to as a bootstrap operation, and the first capacitor C1 may be referred to as a bootstrap capacitor. The eighth transistor T8 may not transmit the voltage V_NQ of the second node NQ having the second low level 2L to the first node NQ', thereby reducing the voltage stress applied to the transistors T1, T3 and T4 connected to the first node NQ'. Therefore, the eighth transistor T8 may be referred to as a stress relaxation (or relief) transistor. While the output signal SOUT is output, the fourth transistor T4 having a gate for receiving the voltage V_NQ' of the first node NQ' having the first low level L may be turned on, and the voltage V_NQB of the third node NQB may be maintained or maintained as a high level H by the turned-on fourth transistor T4. While the output signal SOUT is output, the sixth transistor T6 may not be turned on based on the voltage V_NQB of the third node NQB having the high level H.

[0058] If the second clock signal CLK2 is changed to the high level H at the fourth time point TP4, the output signal SOUT at the scan output node NSO may be changed to the high level H. If the voltage of the scan output node NSO or the voltage of the first electrode of the first capacitor C1 is changed from the first low level L to the high level H, the voltage of the second electrode of the first capacitor C1 or the voltage V_NQ of the second node NQ may be changed from the second low level 2L to the first low level L.

[0059] The first clock signal CLK1 may be changed from a high level H to a first low level L at a fifth time point TP5, and the first clock signal CLK1 having the first low level L may be applied in a period from the fifth time point TP5 to the sixth time point TP6. The first transistor T1 may change a voltage V_NQ' of the first node NQ' from a first low level L to a high level H in response to the first clock signal CLK1 having the first low level L, and the eighth transistor T8 may change a voltage V_NQ of the second node NQ from a first low level L to a high level H in response to the low gate voltage VGL. The fifth transistor T5 may change a voltage V_NQB of the third node NQB from a high level H to a first low level L in response to the first clock signal CLK1 having the first low level L. The fifth transistor T5 may be turned on every time the first clock signal CLK1 has the first low level L, and thus, the low gate voltage VGL may be periodically applied to the third node NQB. The sixth transistor T6 may apply the high gate voltage VGH to the scan output node NSO in response to the voltage V_NQB of the third node NQB having the first low level L.

[0060] The second clock signal CLK2 may be changed from the high level H to the first low level L at the seventh time point TP7, and the second clock signal CLK2 having the first low level L may be applied in the period from the seventh time point TP7 to the eighth time point TP8. The second transistor T2 may be turned on in response to the voltage V_NQB of the third node NQB having the first low level L, the third transistor T3 may be turned on in response to the second clock signal CLK2 having the first low level L, the high gate voltage VGH may be applied to the first node NQ' through the turned-on second transistor T2 and the turned-on third transistor T3, and thus, the voltage V_NQ' of the first node NQ' may be stabilized to the high level H. Further, by the eighth transistor T8 turned on in response to the gate-on voltage VGL having the first low level L, the voltage V_NQ of the second node NQ may also be stabilized to the high level H. The third transistor T3 may be turned on every time the second clock signal CLK2 has the first low level L, and thus, the high gate voltage VGH may be periodically applied to the first node NQ′ and the second node NQ.

[0061] In this manner, the stage 200 (eg, odd-numbered stages 111 , 113 , 115 , . . . ) may receive the input signal SIN in response to the first clock signal CLK1 , and may output the output signal SOUT in response to the second clock signal CLK2 .

[0062] Reference again Figure 1, the plurality of shielding transistors MST1 to MSTN may be respectively connected to the plurality of output terminals of the plurality of first stages 110, and may selectively transmit the plurality of intermediate scanning signals ISS1 to ISSN, respectively, in response to the shielding signal MSS. For example, the first shielding transistor MST1 may selectively transmit the first intermediate scanning signal ISS1 output from the first first stage 111 in the first stage 110 to the first second stage 131 in the second stage 130 in response to the shielding signal MSS, the second shielding transistor MST2 may selectively transmit the second intermediate scanning signal ISS2 output from the second first stage 112 in the first stage 110 to the second second stage 132 in the second stage 130 in response to the shielding signal MSS, and the Nth shielding transistor MSTN may selectively transmit the Nth intermediate scanning signal ISSN output from the Nth first stage 117 in the first stage 110 to the Nth second stage 137 in the second stage 130 in response to the shielding signal MSS.

[0063] Further, each of the plurality of shielding transistors MST1 to MSTN may not transmit a corresponding one of the plurality of intermediate scanning signals ISS1 to ISSN in response to the shielding signal MSS having an off level (e.g., a high level), and may transmit a corresponding one of the plurality of intermediate scanning signals ISS1 to ISSN to a corresponding one of the plurality of second stages 130 in response to the shielding signal MSS having an on level (e.g., a low level). In some example embodiments, as Figure 1 As illustrated in FIG. 1 , each of the plurality of shielding transistors MST1 to MSTN may include a gate for receiving a shielding signal MSS, a first terminal connected to an output terminal of a corresponding one of the plurality of first stages 110 , and a second terminal connected to an input terminal of a corresponding one of the plurality of second stages 130 .

[0064] A plurality of input terminals of the plurality of second stages 130 may be respectively connected to the plurality of shielding transistors MST1 to MSTN, and the plurality of second stages 130 may selectively output a plurality of scan signals SS1 to SSN based on a plurality of intermediate scan signals ISS1 to ISSN selectively transmitted through the plurality of shielding transistors MST1 to MSTN. In some example embodiments, the scan driver 100 includes N second stages 131 to 137, and an input terminal of an Mth second stage among the N second stages 131 to 137 may be connected to an Mth shielding transistor among the plurality of shielding transistors MST1 to MSTN, where M is an integer greater than 0 and less than or equal to N. Therefore, the Mth second stage among the N second stages 131 to 137 may selectively output an Mth scan signal based on the Mth intermediate scan signal selectively transmitted through the Mth shielding transistor.

[0065] For example, a first second stage 131 among the N second stages 131 to 137 may selectively output a first scanning signal SS1 based on a first intermediate scanning signal ISS1 selectively transmitted through the first shielding transistor MST1, a second second stage 132 among the N second stages 131 to 137 may selectively output a second scanning signal SS2 based on a second intermediate scanning signal ISS2 selectively transmitted through the second shielding transistor MST2, and a third second stage 133 among the N second stages 131 to 137 may selectively output a third scanning signal SS3 based on a third intermediate scanning signal ISS3 selectively transmitted through the third shielding transistor MST3. , the fourth second stage 134 among the N second stages 131 to 137 can selectively output the fourth scanning signal SS4 based on the fourth intermediate scanning signal ISS4 selectively transmitted through the fourth shielding transistor MST4, the fifth second stage 135 among the N second stages 131 to 137 can selectively output the fifth scanning signal SS5 based on the fifth intermediate scanning signal ISS5 selectively transmitted through the fifth shielding transistor MST5, and the Nth second stage 137 among the N second stages 131 to 137 can selectively output the Nth scanning signal SSN based on the Nth intermediate scanning signal ISSN selectively transmitted through the Nth shielding transistor MSTN.

[0066] The plurality of second stages 130 may further receive first clock signals CLK1-2 and second clock signals CLK2-2 having different phases (e.g., opposite phases). In some example embodiments, odd-numbered stages 131, 133, 135, ... among the plurality of second stages 130 may receive odd-numbered intermediate scanning signals ISS1, ISS3, ISS5, ... in response to the second clock signal CLK2-2, and may output odd-numbered scanning signals SS1, SS3, SS5, ... in response to the first clock signal CLK1-2. Further, even-numbered stages 132, 134, ... among the plurality of second stages 130 may receive even-numbered intermediate scanning signals ISS2, ISS4, ... in response to the first clock signal CLK1-2, and may output even-numbered scanning signals SS2, SS4, ... in response to the second clock signal CLK2-2.

[0067] Further, in some example embodiments, the first clock signal CLK1-2 applied to the plurality of second stages 130 may have a phase and / or pulse width substantially the same as those of the first clock signal CLK1-1 applied to the plurality of first stages 110, and the second clock signal CLK2-2 applied to the plurality of second stages 130 may have a phase and / or pulse width substantially the same as those of the second clock signal CLK2-1 applied to the plurality of first stages 110. In other example embodiments, the first clock signal CLK1-2 and the second clock signal CLK2-2 applied to the plurality of second stages 130 may have a pulse width greater than the pulse widths of the first clock signal CLK1-1 and the second clock signal CLK2-1 applied to the plurality of first stages 110.

[0068] In some example embodiments, each of the plurality of second stages 130 may have a structure substantially the same as that of each of the plurality of first stages 110. For example, similar to each of the plurality of first stages 110, each of the plurality of second stages 130 may have Figure 2 The structure of stage 200 is shown in FIG. Figure 2 An example is shown in which the stage 200 (e.g., the even-numbered stages 132, 134, ... among the plurality of second stages 130) receives an input signal SIN (e.g., a corresponding intermediate scan signal) in response to a first clock signal CLK1 (e.g., the first clock signal CLK1-2), and outputs an output signal SOUT (e.g., a corresponding scan signal) in response to a second clock signal CLK2 (e.g., the second clock signal CLK2-2). For example, each of the plurality of second stages 130 may include an input circuit 210, a stress relaxation circuit 220, a bootstrap circuit 230, a scan output circuit 240, a holding circuit 250, and a stabilization circuit 260. Further, in some example embodiments, each of the plurality of second stages 130 may use Figure 3 For example, the stage 200 (eg, the even-numbered stages 132, 134, ...) may receive an input signal SIN in response to a first clock signal CLK1, and may output an output signal SOUT in response to a second clock signal CLK2.

[0069] The plurality of scan signals SS1 to SSN selectively generated by the plurality of second stages 130 may be provided to a plurality of pixels included in a display device including the scan driver 100. In some example embodiments, the plurality of intermediate scan signals ISS1 to ISSN generated by the plurality of first stages 110 may be selectively provided to the plurality of second stages 130 through the plurality of shielding transistors MST1 to MSTN, and may not be provided to the outside of the scan driver 100. In other example embodiments, the plurality of intermediate scan signals ISS1 to ISSN generated by the plurality of first stages 110 may be provided to the plurality of pixels as a plurality of initialization signals. In this case, the plurality of intermediate scan signals ISS1 to ISSN may be used as a plurality of initialization signals.

[0070] A display device including a scan driver 100 according to some example embodiments may perform a multi-frequency drive (MFD) that drives a plurality of panel areas at a plurality of driving frequencies, each panel area including at least one pixel row. In some example embodiments, among the plurality of panel areas, a panel area displaying a moving image may be driven at a normal driving frequency (e.g., about 60 Hz or about 120 Hz), while a panel area displaying a still image may be driven at a low frequency lower than the normal driving frequency. In this case, in at least one frame period among a plurality of continuous frame periods, a portion of the frame period corresponding to the panel area driven at a low frequency may be set as a holding period in which the panel is not driven (e.g., in which a data signal and / or a scan signal may not be applied to a plurality of pixels of the panel area). For example, in a case where the first panel area is driven at a normal driving frequency of about 60 Hz and the second panel area is driven at a low frequency of about 30 Hz, among two frame periods, a portion of a frame period corresponding to the second panel area may be set as a holding period.

[0071] In the case where at least one frame period among the plurality of consecutive frame periods includes a holding period, the plurality of first stages 110 may sequentially output all of the plurality of intermediate scanning signals ISS1 to ISSN in each of the plurality of consecutive frame periods. However, the plurality of second stages 130 may sequentially output all of the plurality of scanning signals SS1 to SSN in each frame period not including the holding period, and may output only a portion of the plurality of scanning signals SS1 to SSN in each frame period including the holding period. For example, Figure 4As illustrated in the figure, in a case where a first panel area including a first pixel row and a second pixel row applied with a first scan signal SS1 and a second scan signal SS2 is driven at a normal driving frequency of about 60 Hz, a second panel area including a third pixel row and a fourth pixel row applied with a third scan signal SS3 and a fourth scan signal SS4 is driven at a low frequency of about 30 Hz, and a third panel area including a fifth pixel row to an Nth pixel row applied with a fifth scan signal to an Nth scan signal SS5, ..., SSN is driven at a normal driving frequency of about 60 Hz, within a first frame period FP1 and a second frame period FP2, a portion of the second frame period FP2 can be set as a holding period HP.

[0072] In the first frame period FP1, the plurality of first stages 110 may sequentially output the plurality of intermediate scanning signals ISS1 to ISSN based on the scanning start signal FLM. The shielding signal MSS may have an on level or a low level L in the first frame period FP1, and the plurality of shielding transistors MST1 to MSTN may transmit the plurality of intermediate scanning signals ISS1 to ISSN to the plurality of second stages 130, respectively, in response to the shielding signal MSS having the low level L. Therefore, in the first frame period FP1, the plurality of second stages 130 may respectively output the plurality of scanning signals SS1 to SSN based on the plurality of intermediate scanning signals ISS1 to ISSN transmitted through the plurality of shielding transistors MST1 to MSTN.

[0073] In some example embodiments, since each of the plurality of second stages 130 receives a corresponding one of the plurality of intermediate scanning signals ISS1 to ISSN in response to one of the first clock signal CLK1 and the second clock signal CLK2, and outputs a corresponding one of the plurality of scanning signals SS1 to SSN in response to the other of the first clock signal CLK1 and the second clock signal CLK2, each of the plurality of scanning signals SS1 to SSN output from the plurality of second stages 130 may be delayed by a horizontal time 1H relative to a corresponding one of the plurality of intermediate scanning signals ISS1 to ISSN output from the plurality of first stages 110.

[0074] For example, Figure 4As illustrated in FIG. 1 , the first second stage 131 in the second stage 130 can output the first scanning signal SS1 delayed by one horizontal time 1H from the first intermediate scanning signal ISS1, the second second stage 132 in the second stage 130 can output the second scanning signal SS2 delayed by one horizontal time 1H from the second intermediate scanning signal ISS2, the third second stage 133 in the second stage 130 can output the third scanning signal SS3 delayed by one horizontal time 1H from the third intermediate scanning signal ISS3, the fourth second stage 134 in the second stage 130 can output the fourth scanning signal SS4 delayed by one horizontal time 1H from the fourth intermediate scanning signal ISS4, the fifth second stage 135 in the second stage 130 can output the fifth scanning signal SS5 delayed by one horizontal time 1H from the fifth intermediate scanning signal ISS5, and the Nth second stage 137 in the second stage 130 can output the Nth scanning signal SSN delayed by one horizontal time 1H from the Nth intermediate scanning signal ISSN.

[0075] In the second frame period FP2, the plurality of first stages 110 may sequentially output the plurality of intermediate scanning signals ISS1 to ISSN based on the scanning start signal FLM. In some example embodiments, the shielding signal MSS may be changed to a cut-off level or a high level H at a time point TPH one horizontal time 1H before a start time point SP of the holding period HP, and may be changed to a turn-on level or a low level L at a time point TPL one horizontal time 1H before an end time point EP of the holding period HP.

[0076] For example, Figure 4 As illustrated in the figure, in the case where a part of the second frame period FP2 in which the third scanning signal SS3 and the fourth scanning signal SS4 are output is set as the holding period HP, the time point TPH one horizontal time 1H before the start time point SP of the holding period HP or the time point TPH when the shielding signal MSS is changed to the high level H can be after the second intermediate scanning signal ISS2 is output and before the third intermediate scanning signal ISS3 is output, and the time point TPL one horizontal time 1H before the end time point EP of the holding period HP or the time point TPL when the shielding signal MSS is changed to the low level L can be after the fourth intermediate scanning signal ISS4 is output and before the fifth intermediate scanning signal ISS5 is output.

[0077] Therefore, in response to the shielding signal MSS, the first shielding transistor MST1 and the second shielding transistor MST2 may transmit the first intermediate scanning signal ISS1 and the second intermediate scanning signal ISS2 to the first second stage 131 and the second second stage 132 in the second stage 130, the third shielding transistor MST3 and the fourth shielding transistor MST4 may not transmit the third intermediate scanning signal ISS3 and the fourth intermediate scanning signal ISS4, and the fifth to N-th shielding transistors MST5, …, MSTN may transmit the fifth to N-th intermediate scanning signals ISS5, …, ISSN to the fifth to N-th second stages 135, …, 137 in the second stage 130. Therefore, in the second frame period FP2, the first second stage 131 and the second second stage 132 in the second stage 130 may output the first scan signal SS1 and the second scan signal SS2, the third second stage 133 and the fourth second stage 134 in the second stage 130 may not output the third scan signal SS3 and the fourth scan signal SS4, and the fifth second stage to the N-th second stage 135, ..., 137 in the second stage 130 may output the fifth scan signal to the N-th scan signal SS5, ..., SSN.

[0078] As described above, in the scan driver 100 according to some example embodiments, the plurality of first stages 110 may sequentially output the plurality of intermediate scan signals ISS1 to ISSN, the plurality of shielding transistors MST1 to MSTN may selectively transmit the plurality of intermediate scan signals ISS1 to ISSN, respectively, in response to the shielding signal MSS, and the plurality of second stages 130 may selectively output the plurality of scan signals SS1 to SSN based on the plurality of intermediate scan signals ISS1 to ISSN selectively transmitted through the plurality of shielding transistors MST1 to MSTN. Therefore, the scan driver 100 according to some example embodiments may provide the plurality of scan signals SS1 to SSN to the plurality of panel regions at different driving frequencies.

[0079] Figure 5 is a circuit diagram illustrating another example of each first stage included in a scan driver according to some example embodiments.

[0080] refer to Figure 1 , Figure 2 and Figure 5 In some example embodiments, each of the plurality of second stages 130 may have Figure 2 The structure of the stage 200 shown in FIG. 1 and each of the plurality of first stages 110 may have Figure 5 Thus, each of the plurality of second stages 130 or Figure 2Compared to the stage 200 shown in FIG. 1 , each of the plurality of first stages 110 or Figure 5 The stage 300 illustrated in may further include a carry-out circuit 370 .

[0081] like Figure 5 As shown in FIG. 3 , each stage 300 may include an input circuit 310 , a stress relaxation circuit 320 , a bootstrap circuit 330 , a scan output circuit 340 , a holding circuit 350 , a stabilization circuit 360 , and a carry output circuit 370 . Figure 5 The input circuit 310, stress relaxation circuit 320, bootstrap circuit 330, scan output circuit 340, holding circuit 350 and stabilization circuit 360 shown in FIG. Figure 2 The input circuit 210, stress relaxation circuit 220, bootstrap circuit 230, scan output circuit 240, holding circuit 250 and stabilization circuit 260 shown in FIG. 2 are basically the same.

[0082] The scan output circuit 340 may output the intermediate scan signal ISS in response to the voltage of the bootstrapped second node NQ, and the carry output circuit 370 may output the carry signal CR applied to the next stage as the input signal SIN in response to the voltage of the bootstrapped second node NQ. In some example embodiments, the carry output circuit 370 may include a ninth transistor T9 and a tenth transistor T10, the ninth transistor T9 including a gate connected to the third node NQB, a first terminal for receiving the gate-off voltage VGH, and a second terminal connected to the carry output node NCO to which the carry signal CR is output, and the tenth transistor T10 including a gate connected to the second node NQ, a first terminal connected to the carry output node NCO, and a second terminal for receiving the second clock signal CLK2. Although Figure 5 An example in which the bootstrap circuit 330 or the first electrode of the first capacitor C1 is connected to the carry output node NCO is illustrated, but in some example embodiments, the first electrode of the first capacitor C1 may be connected to the scan output node NSO.

[0083] Each of the plurality of first stages 110 has Figure 5In the case of the structure of the stage 300 illustrated in FIG. 1 , the plurality of first stages 110 may selectively provide the plurality of intermediate scanning signals ISS1 to ISSN to the plurality of second stages 130 through the plurality of shielding transistors MST1 to MSTN, and may provide the carry signal CR as the input signal SIN to the next first stage 110. Therefore, the first first stage 111 of the first stages 110 may output the first intermediate scanning signal ISS1 based on the scan start signal FLM. And the Kth first stage of the first stages 110 may output the Kth intermediate scanning signal based on the previous carry signal CR output from the K-1th first stage of the first stages 110, where K is an integer greater than 1.

[0084] For example, the second first stage 112 in the first stage 110 may output the second intermediate scanning signal ISS2 based on the carry signal CR output from the first first stage 111 in the first stage 110, the third first stage 113 in the first stage 110 may output the third intermediate scanning signal ISS3 based on the carry signal CR output from the second first stage 112 in the first stage 110, the fourth first stage 114 in the first stage 110 may output the fourth intermediate scanning signal ISS4 based on the carry signal CR output from the third first stage 113 in the first stage 110, the fifth first stage 115 in the first stage 110 may output the fifth intermediate scanning signal ISS5 based on the carry signal CR output from the fourth first stage 114 in the first stage 110, and the Nth first stage 117 in the first stage 110 may output the Nth intermediate scanning signal ISSN based on the carry signal CR output from the N-1th first stage in the first stage 110. The Kth second stage among the plurality of second stages 130 may selectively output the Kth scan signal among the plurality of scan signals SS1 to SSN based on the Kth intermediate scan signal selectively transmitted through the Kth shielding transistor. Therefore, the scan driver 100 according to some example embodiments may provide the plurality of scan signals SS1 to SSN to the plurality of panel regions at different driving frequencies.

[0085] Figure 6 is a block diagram illustrating a scan driver according to some example embodiments.

[0086] refer to Figure 6 , the scan driver 400 according to some example embodiments may include a plurality of first stages 110 , a plurality of shielding transistors MST1 to MSTN, a plurality of second stages 130 , and a plurality of switching transistors SWT1 to SWTN. Figure 6 The scan driver 400 may further include a plurality of switching transistors SWT1 to SWTN, Figure 6 The scan driver 400 may have Figure 1The configuration and operation of the scan driver 100 are substantially the same as the configuration and operation of FIG.

[0087] The plurality of switch transistors SWT1 to SWTN may transmit a gate-off voltage VGH (e.g., a high gate voltage) to the plurality of input terminals of the plurality of second stages 130 in response to an inverted shielding signal / MSS that is an inverted signal of the shielding signal MSS. In some example embodiments, each of the plurality of switch transistors SWT1 to SWTN may include a gate for receiving the inverted shielding signal / MSS, a first terminal for receiving the gate-off voltage VGH, and a second terminal connected to a corresponding one of the plurality of input terminals of the plurality of second stages 130.

[0088] When the shielding signal MSS has a turn-on level and the inverted shielding signal / MSS has a turn-off level, the plurality of intermediate scanning signals ISS1 to ISSN may be transmitted to the input terminals of the plurality of second stages 130 through the plurality of shielding transistors MST1 to MSTN. Alternatively, when the shielding signal MSS has a turn-off level and the inverted shielding signal / MSS has a turn-on level, the gate-off voltage VGH may be transmitted to the input terminals of the plurality of second stages 130 through the plurality of switching transistors SWT1 to SWTN. Therefore, while the plurality of shielding transistors MST1 to MSTN are turned off, the situation in which the input terminals of the plurality of second stages 130 are floated may be prevented or reduced.

[0089] As described above, in the scan driver 400 according to some example embodiments, the plurality of first stages 110 may sequentially output the plurality of intermediate scan signals ISS1 to ISSN, the plurality of shielding transistors MST1 to MSTN may selectively transmit the plurality of intermediate scan signals ISS1 to ISSN respectively in response to the shielding signal MSS, and the plurality of second stages 130 may selectively output the plurality of scan signals SS1 to SSN based on the plurality of intermediate scan signals ISS1 to ISSN selectively transmitted through the plurality of shielding transistors MST1 to MSTN. Therefore, the scan driver 400 according to some example embodiments may provide the plurality of scan signals SS1 to SSN to the plurality of panel regions at different driving frequencies. Further, in the scan driver 400 according to some example embodiments, the plurality of switching transistors SWT1 to SWTN may prevent or reduce the situation where the input terminals of the plurality of second stages 130 are floated.

[0090] Figure 7 is a block diagram illustrating a display device including a scan driver according to some example embodiments, Figure 8 is a circuit diagram illustrating an example of a pixel included in a display device according to some example embodiments, Fig. 9is a diagram illustrating an example of a display panel including a plurality of panel areas driven at different driving frequencies in a display device according to some example embodiments, and Fig.10 is used to describe the scanning signal provided to Fig. 9 FIG. 1 is a timing diagram of an example of the operation of a scan driver of a display panel.

[0091] refer to Figure 7 , a display device 500 according to some example embodiments may include a display panel 510 including a plurality of pixel rows, a data driver 520 that provides a data signal DS to each of the plurality of pixel rows, a scan driver 530 that provides a plurality of scan signals SS to the plurality of pixel rows, respectively, and a controller 550 that controls the data driver 520 and the scan driver 530. In some example embodiments, the display device 500 may further include an emission driver 540 that provides an emission signal SEM to the plurality of pixel rows.

[0092] The display panel 510 may include a plurality of scan lines, a plurality of data lines, and a plurality of pixel rows respectively connected to the plurality of scan lines. Here, each pixel row may mean a row of pixels PX connected to a single scan line. In some example embodiments, each pixel PX may include at least one capacitor, at least two transistors, and an organic light emitting diode (OLED), and the display panel 510 may be an OLED display panel.

[0093] For example, Figure 8As shown in FIG. 1 , each pixel PX may include a driving transistor PXT1 that generates a driving current, a switching transistor PXT2 that transmits a data signal DS from a data driver 520 to a source of the driving transistor PXT1 in response to a scanning signal SS from a scanning driver 530, a compensation transistor PXT3 that diode-connects the driving transistor PXT1 in response to a scanning signal SS from the scanning driver 530, a storage capacitor CST that stores the data signal DS transmitted through the switching transistor PXT2 and the diode-connected driving transistor PXT1, and a gate electrode that supplies an initialization voltage VINIT to the storage capacitor CST and the driving transistor PXT1 in response to an initialization signal SI (or an intermediate scanning signal ISS) from the scanning driver 530. The organic light emitting diode EL includes a first initialization transistor PXT4 for connecting the line of the first power supply voltage ELVDD to the source electrode of the driving transistor PXT1 in response to the emission signal SEM from the emission driver 540, a second emission transistor PXT6 for connecting the drain electrode of the driving transistor PXT1 to the organic light emitting diode EL in response to the emission signal SEM from the emission driver 540, a second initialization transistor PXT7 for providing the initialization voltage VINIT to the organic light emitting diode EL in response to the initialization signal SI (or the intermediate scanning signal ISS) from the scan driver 530, and an organic light emitting diode EL that emits light based on the driving current from the line of the first power supply voltage ELVDD to the line of the second power supply voltage ELVSS.

[0094] In some example embodiments, each pixel PX may include: Figure 8 . In other example embodiments, each pixel PX may include an NMOS transistor. In other example embodiments, each pixel PX may include different types of transistors suitable for low-frequency driving capable of reducing power consumption. For example, each pixel PX may include at least one low-temperature polysilicon (LTPS) PMOS transistor and at least one oxide NMOS transistor. For example, the compensation transistor PXT3 and the first initialization transistor PXT4 may be implemented using NMOS transistors, and the other transistors PXT1, PXT2, PXT5, PXT6, and PXT7 may be implemented using PMOS transistors. In this case, since the transistors PXT3 and PXT4 directly connected to the storage capacitor CST are implemented using NMOS transistors, the leakage current from the storage capacitor CST can be reduced, and therefore, the pixel PX may be suitable for low-frequency driving. In other example embodiments, the display panel 510 may be a liquid crystal display (LCD) panel, etc.

[0095] The data driver 520 may generate a data signal DS based on the output image data ODAT and the data control signal DCTRL received from the controller 550, and may provide the data signal DS to each of the plurality of pixel rows through a plurality of data lines. In some example embodiments, the data control signal DCTRL may include, but is not limited to, an output data enable signal, a horizontal start signal, and a load signal. In some example embodiments, the data driver 520 and the controller 550 may be implemented using a single integrated circuit, and the single integrated circuit may be referred to as a timing controller embedded data driver (TED). In other example embodiments, the data driver 520 and the controller 550 may be implemented using separate integrated circuits.

[0096] The scan driver 530 may generate a plurality of scan signals SS based on a scan control signal received from the controller 550, and may provide the plurality of scan signals SS to a plurality of pixel rows respectively through a plurality of scan lines. In some example embodiments, the scan control signal may include, but is not limited to, a scan start signal FLM, a first clock signal CLK1, a second clock signal CLK2, and a shielding signal MSS. In some example embodiments, the scan driver 530 may further provide a plurality of initialization signals SI to a plurality of pixel rows. Further, in some example embodiments, a plurality of intermediate scan signals ISS generated by a plurality of first stages 532 of the scan driver 530 may be provided to a plurality of pixel rows as a plurality of initialization signals SI. In some example embodiments, the scan driver 530 may be integrated or formed in a peripheral portion of the display panel 510. In other example embodiments, the scan driver 530 may be implemented using one or more integrated circuits.

[0097] In some example embodiments, the scan driver 530 may be Figure 1 The scanning driver 100, Figure 4The scan driver 530 may include a plurality of first stages 532, a plurality of shielding transistors MST, and a plurality of second stages 534, the plurality of first stages 532 sequentially outputting a plurality of intermediate scanning signals ISS based on the scan start signal FLM, the plurality of shielding transistors MST respectively connected to a plurality of output terminals of the plurality of first stages 532 and selectively transmitting the plurality of intermediate scanning signals ISS in response to the shielding signal MSS, and the plurality of second stages 534 including a plurality of input terminals respectively connected to the plurality of shielding transistors MST and selectively outputting a plurality of scanning signals SS based on the plurality of intermediate scanning signals ISS selectively transmitted through the plurality of shielding transistors MST. In the scan driver 530, the plurality of first stages 532 may sequentially output all of the plurality of intermediate scanning signals ISS in a frame period, and the plurality of second stages 534 may not output at least a portion of the plurality of scanning signals SS in a holding period of the frame period. Therefore, the scan driver 530 may provide the plurality of scanning signals SS to the plurality of panel areas at different driving frequencies.

[0098] The emission driver 540 may generate an emission signal SEM based on an emission control signal EMCTRL received from the controller 550, and may provide the emission signal SEM to a plurality of pixel rows through a plurality of emission lines. In some example embodiments, the emission signal SEM may be provided sequentially to a plurality of pixel rows. In other example embodiments, the emission signal SEM may be a global signal that is substantially concurrently (e.g., simultaneously) provided to a plurality of pixel rows. In some example embodiments, the emission driver 540 may be integrated or formed in a peripheral portion of the display panel 510. In other example embodiments, the emission driver 540 may be implemented using one or more integrated circuits.

[0099] The controller 550 (e.g., a timing controller (TCON)) may receive input image data IDAT and a control signal CTRL from an external host (e.g., a graphics processing unit (GPU) or a graphics card). In some example embodiments, the control signal CTRL may include, but is not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a main clock signal, etc. The controller 550 may generate output image data ODAT, a data control signal DCTRL, a scan control signal, and an emission control signal EMCTRL based on the input image data IDAT and the control signal CTRL. The controller 550 may control the operation of the data driver 520 by providing the output image data ODAT and the data control signal DCTRL to the data driver 520, may control the operation of the scan driver 530 by providing the scan control signal to the scan driver 530, and may control the operation of the emission driver 540 by providing the emission control signal EMCTRL to the emission driver 540.

[0100] The display device 500 according to some example embodiments may perform multi-frequency driving (MFD) to drive a plurality of panel regions of the display panel 510 at a plurality of (different) driving frequencies. In order to perform the MFD, Figure 7 As illustrated in , the controller 550 may include a still image detection block 560 , a driving frequency decision block 570 , and a scan driver control block 580 .

[0101] The still image detection block 560 may divide the input image data IDAT into a plurality of panel area data of a plurality of panel areas, and may determine whether each of the plurality of panel area data represents a still image, each panel area including at least one pixel row of a plurality of pixel rows. In some example embodiments, each panel area may include only one pixel row, and the still image detection block 560 may divide the input image data IDAT into a plurality of panel area data (each panel area data is used for one pixel row), and may determine whether each panel area data for one pixel row represents a still image. In other example embodiments, each panel area may include two or more pixel rows, and the still image detection block 560 may divide the input image data IDAT into a plurality of panel area data (each panel area data is used for two or more pixel rows), and may determine whether each panel area data for two or more pixel rows represents a still image.

[0102] For example, Fig. 9 As shown in FIG. 5 , the still image detection block 560 may divide the input image data IDAT for the display panel 510a into first panel area data for a first panel area PZ1 including a first pixel row and a second pixel row receiving a first scan signal SS1 and a second scan signal SS2, second panel area data for a second panel area PZ2 including a third pixel row and a fourth pixel row receiving a third scan signal SS3 and a fourth scan signal SS4, and third panel area data for a third panel area PZ3 including a fifth pixel row and a sixth pixel row receiving a fifth scan signal SS5 and a sixth scan signal SS6. Although Fig. 9 The example of the display panel 510a including the first to sixth pixel rows receiving the first to sixth scan signals SS1 to SS6 is shown, but the number of pixel rows of the display panel 510a is not limited to Fig. 9 Further, although Fig. 9 The illustrated example shows that the display panel 510a is divided into first to third panel areas PZ1, PZ2, and PZ3, but the number of the panel areas PZ1, PZ2, and PZ3 is not limited to Fig. 9 .

[0103] In some example embodiments, with respect to each panel area data, the still image detection block 560 may determine whether the panel area data represents a still image by comparing the panel area data in the previous frame period with the panel area data in the current frame period. For example, the still image detection block 560 may determine that the panel area data represents a still image when the panel area data in the current frame period is substantially the same as the panel area data in the previous frame period, and may determine that the panel area data does not represent a still image or represents a moving image when the panel area data in the current frame period is different from the panel area data in the previous frame period.

[0104] In other example embodiments, with respect to each panel area data, the still image detection block 560 may determine whether the panel area data represents a still image by comparing a previous representative value (e.g., an average value or a checksum) of the panel area data in a previous frame period with a current representative value of the panel area data in a current frame period. Fig. 9 As illustrated in the figure, the still image detection block 560 can determine that the first panel area data of the first panel area PZ1 represents a still image when the current representation value of the first panel area data is the same as the previous representation value of the first panel area data, can determine that the second panel area data of the second panel area PZ2 represents a moving image when the current representation value of the second panel area data is different from the previous representation value of the second panel area data, and can determine that the third panel area data of the third panel area PZ3 represents a still image when the current representation value of the third panel area data is the same as the previous representation value of the third panel area data.

[0105] The driving frequency decision block 570 may determine a plurality of driving frequencies of a plurality of panel areas according to whether each of the plurality of panel area data represents a still image. In some example embodiments, in the case where each of the panel area data represents a moving image, the driving frequency decision block 570 may determine the driving frequency of the panel area corresponding to the panel area data as a normal driving frequency. Here, the normal driving frequency may be a driving frequency under normal driving of the display device 500. In some example embodiments, the normal driving frequency may be the same as the input frame frequency (e.g., about 60 Hz or about 120 Hz) of the input image data IDAT. Further, in the case where each of the panel area data represents a still image, the driving frequency decision block 570 may determine the driving frequency of the panel area corresponding to the panel area data as a low frequency lower than the normal driving frequency. Here, the low frequency may be any frequency lower than the normal driving frequency. In some example embodiments, in the case where each of the panel area data represents a still image, the driving frequency decision block 570 may determine the flicker value corresponding to the grayscale (or brightness) of the panel area data by using a flicker lookup table, and may determine the driving frequency of the panel area corresponding to the panel area data based on the flicker value. For example, the flicker lookup table may store flicker values ​​corresponding to the gray levels of the image data, for example, 256 gray levels from 0 gray level to 255 gray level. Here, the flicker value may represent the level of flicker perceived by the user. According to some example embodiments, determining the flicker value and the driving frequency may be performed on a pixel-by-pixel basis, on a segment-by-segment basis, or on a panel-by-panel-area basis. For example, each panel area data may be divided into a plurality of segment data of a plurality of segments, the flicker value of the corresponding segment may be determined by using the flicker lookup table, the segment driving frequency of the corresponding segment may be determined, and the driving frequency of the panel area may be determined as the maximum segment driving frequency among the segment driving frequencies.

[0106] For example, Fig. 9 As illustrated in FIG. 5 , in a case where each of the first panel area data of the first panel area PZ1 and the third panel area data of the third panel area PZ3 represents a moving image, the driving frequency decision block 570 may determine the first driving frequency DF1 of the first panel area PZ1 and the third driving frequency DF3 of the third panel area PZ3 as a normal driving frequency, for example, about 60 Hz. Further, in a case where the second panel area data of the second panel area PZ2 represents a still image, the driving frequency decision block 570 may determine the second driving frequency DF2 of the second panel area PZ2 as a low frequency lower than the normal driving frequency. For example, the driving frequency decision block 570 may determine a flicker value based on the grayscale (or brightness) of the second panel area data, and may determine the second driving frequency DF2 of the second panel area PZ2 to be about 20 Hz lower than the normal driving frequency based on the flicker value.

[0107] The scan driver control block 580 may generate the shielding signal MSS based on the plurality of driving frequencies of the plurality of panel regions. In some example embodiments, the scan driver control block 580 may set at least a portion of one or more frame periods as a holding period, may change the shielding signal MSS to an off level one horizontal time before a start time point of the holding period, and may change the shielding signal MSS to an on level one horizontal time before an end time point of the holding period.

[0108] For example, Figure 7 , Fig. 9 and Fig.10 As shown, the plurality of first stages 532 may sequentially generate a plurality of intermediate scanning signals ISS1 to ISS6 in each frame period FP1 to FP4. The scanning driver control block 580 may set at least a portion of one or more frame periods FP2 and FP3 as a holding period HP according to a plurality of driving frequencies DF1, DF2, and DF3 of the plurality of panel regions PZ1, PZ2, and PZ3. For example, in the case where the second driving frequency DF2 of the second panel region PZ2 is a low frequency of about 20 Hz, two frame periods FP2 and FP3 among the three frame periods FP1, FP2, and FP3 may include a holding period HP in a partial period in which the third scanning signal SS3 and the fourth scanning signal SS4 are provided to the second panel region PZ2. Further, the scanning driver control block 580 may change the shielding signal MSS to a cut-off level one horizontal time before the start time point of the holding period HP, and may change the shielding signal MSS to a turn-on level one horizontal time before the end time point of the holding period HP. In response to the shielding signal MSS, the plurality of shielding transistors MST may transmit the first to sixth intermediate scanning signals ISS1 to ISS6 to the plurality of second stages 534 in the first frame period FP1, and may transmit only the first to sixth intermediate scanning signals ISS1, ISS2, ISS5 and ISS6 to the plurality of second stages 534 in each of the second frame period FP2 and the third frame period FP3 without transmitting the third intermediate scanning signal ISS3 and the fourth intermediate scanning signal ISS4.

[0109] Therefore, the plurality of second stages 534 may provide the first to sixth scan signals SS1 to SS6 to the first to third panel regions PZ1, PZ2, and PZ3 in the first frame period FP1, and may provide only the first to sixth scan signals SS1, SS2, SS5, and SS6 to the first and third panel regions PZ1 and PZ3 in each of the second and third frame periods FP2 and FP3, without providing the third to fourth scan signals SS3 and SS4 to the second panel region PZ2. Further, the controller 550 may provide the first panel area data to the third panel area data PD1, PD2, and PD3 of the first to third panel areas PZ1, PZ2, and PZ3 to the data driver 520 in the first frame period FP1, and may provide only the first panel area data PD1 of the first panel area PZ1 and the third panel area data PD3 of the third panel area PZ3 to the data driver 520 in each of the second frame period FP2 and the third frame period FP3 without providing the second panel area data PD2 of the second panel area PZ2 to the data driver 520. Therefore, the first panel area PZ1 and the third panel area PZ3 may be driven at a normal driving frequency of about 60 Hz, and the second panel area PZ2 may be driven at a low frequency of about 20 Hz.

[0110] As described above, in the display device 500 according to some example embodiments, the plurality of first stages 532 may sequentially output a plurality of intermediate scanning signals ISS, the plurality of shielding transistors MST may selectively transmit the plurality of intermediate scanning signals ISS, respectively, in response to the shielding signals MSS, and the plurality of second stages 534 may selectively output a plurality of scanning signals SS based on the plurality of intermediate scanning signals ISS selectively transmitted through the plurality of shielding transistors MST. Therefore, the display device 500 according to some example embodiments may perform multi-frequency driving of driving the plurality of panel zones PZ1, PZ2, and PZ3 at different driving frequencies DF1, DF2, and DF3.

[0111] Fig.11 An electronic device including a display device according to some example embodiments.

[0112] refer to Fig.11 , the electronic device 1100 may include a processor 1110, a memory device 1120, a storage device 1130, an input / output (I / O) device 1140, a power supply 1150, and a display device 1160. The electronic device 1100 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, and other electronic devices.

[0113] The processor 1110 may perform various computing functions or tasks. The processor 1110 may be an application processor (AP), a microprocessor, a central processing unit (CPU), etc. The processor 1110 may be connected to other components via an address bus, a control bus, a data bus, etc. Further, in some example embodiments, the processor 1110 may be further connected to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0114] The memory device 1120 may store data used for the operation of the electronic device 1100. For example, the memory device 1120 may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc., and / or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.

[0115] The storage device 1130 may be a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 1140 may be an input device such as a keyboard, a keypad, a mouse, a touch screen, etc. and an output device such as a printer, a speaker, etc. The power supply 1150 may supply power for the operation of the electronic device 1100. The display device 1160 may be connected to other components through a bus or other communication links.

[0116] In the display device 1160, a plurality of first stages of the scan driver may sequentially output a plurality of intermediate scan signals, a plurality of shielding transistors of the scan driver may selectively transmit the plurality of intermediate scan signals respectively in response to the shielding signals, and a plurality of second stages of the scan driver may selectively output a plurality of scan signals based on the plurality of intermediate scan signals selectively transmitted through the plurality of shielding transistors. Thus, the scan driver may provide a plurality of scan signals to a plurality of panel regions at different driving frequencies, and the display device 1160 may perform multi-frequency driving that drives the plurality of panel regions at different driving frequencies.

[0117] The inventive concept may be applied to any display device 1160 and any electronic device 1100 including the display device 1160. For example, the inventive concept may be applied to mobile phones, smart phones, wearable electronic devices, tablet computers, televisions (TVs), digital TVs, 3D TVs, personal computers (PCs), home appliances, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, music players, portable game consoles, navigation devices, and the like.

[0118] The foregoing is an illustration of example embodiments and should not be construed as limiting the example embodiments. Although some example embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications in the example embodiments are possible without departing substantially from the novel teachings and features of the embodiments conceived in accordance with the present invention. Therefore, all of these modifications are intended to be included within the scope of the embodiments conceived in accordance with the claims and their equivalents. Therefore, it is to be understood that the foregoing is an illustration of various example embodiments and should not be construed as being limited to the specific example embodiments disclosed, and modifications to the disclosed example embodiments as well as other example embodiments are intended to be included within the scope of the appended claims and their equivalents.

Claims

1. A scanning driver, comprising: a plurality of first stages configured to sequentially output a plurality of intermediate scanning signals based on a scanning start signal; a plurality of shielding transistors connected to the plurality of output terminals of the plurality of first stages, respectively, and configured to selectively transmit the plurality of intermediate scanning signals, respectively, in response to shielding signals; as well as a plurality of second stages including a plurality of input terminals respectively connected to the plurality of shielding transistors and configured to selectively output a plurality of scanning signals based on the plurality of intermediate scanning signals selectively transmitted through the plurality of shielding transistors, In which, the output terminal of the first stage among the multiple first stages is electrically connected to the input terminal of the next stage of the first stage among the multiple first stages without passing through the corresponding shielding transistor among the multiple shielding transistors, so that the signal from the output terminal of the first stage among the multiple first stages can be transmitted to the input terminal of the next stage.

2. The scan driver according to claim 1, wherein: The plurality of first stages are configured to sequentially output all of the plurality of intermediate scanning signals in a frame period, and The plurality of second stages are configured not to output at least a portion of the plurality of scan signals during a holding period of the frame period.

3. The scan driver according to claim 2, wherein: The shielding signal is changed to an off level one horizontal time before a start time point of the holding period, and is changed to an on level one horizontal time before an end time point of the holding period.

4. The scan driver according to claim 3, wherein: Each of the plurality of shielding transistors is configured to not transmit a corresponding one of the plurality of intermediate scanning signals in response to the shielding signal having the cut-off level, and is configured to transmit the corresponding one of the plurality of intermediate scanning signals to a corresponding one of the plurality of second stages in response to the shielding signal having the on-level.

5. The scan driver according to claim 1, wherein: Each of the plurality of shielding transistors includes a gate configured to receive the shielding signal, a first terminal connected to a corresponding one of the plurality of output terminals of the plurality of first stages, and a second terminal connected to a corresponding one of the plurality of input terminals of the plurality of second stages.

6. The scan driver according to claim 1, wherein: Each of the plurality of scan signals selectively output from the plurality of second stages is delayed by one horizontal time with respect to a corresponding one of the plurality of intermediate scan signals output from the plurality of first stages.

7. The scan driver according to claim 1, wherein: A Kth first stage among the plurality of first stages is configured to output a Kth intermediate scanning signal among the plurality of intermediate scanning signals based on a K-1th intermediate scanning signal among the plurality of intermediate scanning signals output from a K-1th first stage among the plurality of first stages, wherein K is an integer greater than 1, and The Kth second stage among the plurality of second stages is configured to selectively output a Kth scan signal among the plurality of scan signals based on a Kth intermediate scan signal among the plurality of intermediate scan signals selectively transmitted through a Kth shielding transistor among the plurality of shielding transistors.

8. The scan driver according to claim 1, wherein: Each of the plurality of second stages has the same structure as that of each of the plurality of first stages.

9. The scan driver according to claim 1, wherein: Each of the plurality of first stages and the plurality of second stages comprises: an input circuit configured to transmit an input signal to the first node in response to a first clock signal; a stress relaxation circuit between the first node and a second node and configured to transmit the input signal from the first node to the second node so that a voltage of the second node is changed to a first conduction level; a bootstrap circuit configured to change the voltage of the second node from the first conduction level to a second conduction level having an absolute value greater than an absolute value of the first conduction level by bootstrapping the second node based on a second clock signal; a scan output circuit configured to output the second clock signal as an output signal in response to the voltage of the second node having the second conduction level; a holding circuit configured to hold the third node at an off level while the output signal is output; and A stabilization circuit is configured to periodically apply a gate-on voltage to the third node in response to the second clock signal, and to periodically apply a gate-off voltage to the first node in response to the first clock signal after the output signal is output.

10. A display device, comprising: A display panel comprising a plurality of pixel rows; a data driver configured to provide a data signal to each of the plurality of pixel rows; a scan driver configured to provide a plurality of scan signals to the plurality of pixel rows respectively; as well as a controller configured to control the data driver and the scan driver and to provide a scan start signal and a shield signal to the scan driver, Wherein, the scanning driver comprises: a plurality of first stages configured to sequentially output a plurality of intermediate scanning signals based on the scanning start signal; a plurality of shielding transistors connected to the plurality of output terminals of the plurality of first stages, respectively, and configured to selectively transmit the plurality of intermediate scanning signals, respectively, in response to the shielding signal; and a plurality of second stages including a plurality of input terminals respectively connected to the plurality of shielding transistors and configured to selectively output a plurality of scanning signals based on the plurality of intermediate scanning signals selectively transmitted through the plurality of shielding transistors, In which, the output terminal of the first stage among the multiple first stages is electrically connected to the input terminal of the next stage of the first stage among the multiple first stages without passing through the corresponding shielding transistor among the multiple shielding transistors, so that the signal from the output terminal of the first stage among the multiple first stages can be transmitted to the input terminal of the next stage.

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