Bottom-pinned SOT-MRAM bit structure and manufacturing method

Abstract

Embodiments of the present disclosure generally relate to data storage and computer storage systems, and more specifically to a SOT-MRAM chip structure. The SOT-MRAM chip structure includes a plurality of leads, a plurality of memory cells, and a plurality of transistors. The leads may be made of a material having a large spin-orbit coupling strength and a high resistivity. Each individual lead may include a plurality of first portions and a plurality of second portions distinguished from the first portions. The resistivity of the second portion is less than the resistivity of the first portion, so the total resistivity of the lead is reduced, resulting in improved power efficiency and signal-to-noise ratio.

Description

[0001] This application is a divisional application of the invention patent application with application number 201610939473.7 filed on October 24, 2016 and invention name “Bottom Pinned SOT-MRAM Bit Structure and Manufacturing Method”. Technical Field

[0002] Embodiments of the present disclosure relate generally to data storage and computer memory systems, and more particularly to a spin-orbit torque magnetoresistive random access memory (SOT-MRAM) chip structure. Background Art

[0003] At the heart of a computer is a magnetic recording device, which may typically include rotating magnetic media or solid-state media devices. There are many different storage technologies today to store information used in computing systems. In general, these different storage technologies can be divided into two main categories: volatile memory and non-volatile memory. Volatile memory generally refers to a type of computer memory that requires electrical energy to retain stored data. On the other hand, non-volatile memory generally refers to a type of computer memory that does not require electrical energy to retain stored data. Examples of volatile memory may include certain types of random access memory (RAM), such as dynamic RAM (DRAM) and static RAM (SRAM). Examples of non-volatile memory may include read-only memory (ROM), magnetoresistive RAM (MRAM), and flash memory (such as NOR and NAND flash memory), etc.

[0004] In recent years, there has been a need for higher density devices in mass storage and memory applications that maintain a relatively low cost per bit. Today, the memory technologies that generally dominate the computing industry are DRAM and NAND flash memory, however, these memory technologies are unable to address the current and future capacity requirements of next generation computing systems.

[0005] Recently, a number of emerging technologies have received continued attention as potential contenders for the next generation of memory. One such storage technology is magnetoresistive random access memory (MRAM). MRAM offers fast write times, nearly unlimited read / write endurance, radiation resistance, and high storage density. Unlike conventional RAM chip technology, MRAM data is not stored as an electric charge, but instead uses the magnetic polarization state of magnetic elements to store data bits. These elements are formed by two magnetically polarized layers (separated by a thin insulating layer), each of which can maintain a magnetic polarization field, which together form a magnetic tunnel junction (MTJ) structure. MRAM cells including MTJ storage elements can be designed for in-plane or perpendicular polarization of the MTJ layer structure relative to the film surface. The magnetization of one of the two layers (referred to as the fixed or reference layer) is fixed and set to a specific polarity, for example by coupling the layer to an antiferromagnet; the polarization of the second layer (referred to as the free layer) is freely rotated under the influence of an external write mechanism (such as a strong magnetic field or a spin-polarized current) (which is used as spin torque transfer or STT-MRAM in the form of MRAM).

[0006] However, the MTJ storage element in an STT-MRAM device is subject to wear due to driving sufficient amounts of current to switch through the MTJ (including through the barrier layer). Typically, a large amount of current is required to switch the state of the cell. Over time, due to the large amount of current, the barrier layer breaks down, causing the MTJ to fail.

[0007] Therefore, there is a need in the art for an improved MRAM device. Summary of the invention

[0008] Embodiments of the present disclosure generally relate to data storage and computer storage systems, and more specifically to a SOT-MRAM chip structure. The SOT-MRAM chip structure includes a plurality of leads, a plurality of memory cells, and a plurality of transistors. The leads may be made of a material having a large spin-orbit coupling strength and a high resistivity. Each individual lead may include a plurality of first portions and a plurality of second portions distinguished from the first portions. The resistivity of the second portion is less than the resistivity of the first portion, so the total resistivity of the lead is reduced, resulting in improved power efficiency and signal-to-noise ratio.

[0009] In one embodiment, the SOT-MRAM chip structure includes a plurality of leads made of a material including Pt, Ta, W, Hf, Ir, CuBi, CuIr, or AuW, a plurality of memory cells coupled to each of the plurality of leads, and a plurality of transistors, each transistor being coupled to a corresponding memory cell of the plurality of memory cells.

[0010] In another embodiment, the SOT-MRAM chip structure includes a plurality of leads, each lead having a plurality of first portions and a plurality of second portions distinguished from the first portions. Each of the plurality of first portions has a first width, and each of the plurality of second portions has a second width, the first width being less than the second width. The SOT-MRAM chip structure also includes a plurality of memory cells coupled to the first portion of each lead and a plurality of transistors. Each transistor is coupled to a corresponding memory cell of the plurality of memory cells.

[0011] In another embodiment, the SOT-MRAM chip structure includes a plurality of leads, each lead having a plurality of first portions and a plurality of second portions distinguished from the first portions. Each of the plurality of first portions is made of a first material, and each of the plurality of second portions is made of a second material, the first material being different from the second material. The SOT-MRAM chip structure also includes a plurality of memory cells coupled to the first portion of each lead and a plurality of transistors. Each transistor is coupled to a corresponding memory cell of the plurality of memory cells. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The present disclosure briefly described above will be described in more detail with reference to embodiments so that the above-mentioned features of the present disclosure can be understood in more detail, and some embodiments are shown in the accompanying drawings. However, it should be noted that the accompanying drawings only show typical embodiments of the present disclosure and are therefore not to be construed as limiting the scope of the present invention, as the present disclosure may be applied to other equivalent embodiments.

[0013] Figure 1 is a schematic perspective view of a single lead, multiple memory cells, and multiple transistors according to one embodiment described herein.

[0014] Figure 2 is a schematic perspective view of a single lead, multiple memory cells, and multiple transistors according to another embodiment described herein.

[0015] Figure 3 is a schematic perspective view of a single lead, multiple memory cells, and multiple transistors according to yet another embodiment described herein.

[0016] Figures 4A-4J The process steps for forming leads and memory cells according to one embodiment described herein are schematically shown.

[0017] Figures 5A-5E The process steps for forming leads and memory cells according to another embodiment described herein are schematically shown.

[0018] Figures 6A-6D The process steps for forming a memory cell having leads according to yet another embodiment described herein are schematically shown.

[0019] To facilitate understanding, like reference numerals have been used, where necessary, to designate like elements that are common to the figures. It is contemplated that elements disclosed in one embodiment may be beneficially utilized in other embodiments without specific recitation. DETAILED DESCRIPTION

[0020] Below, reference is made to embodiments of the present disclosure. However, it should be understood that the present disclosure is not limited to the specifically described embodiments. Specifically, it is foreseeable that any combination of the following features and elements (whether or not related to different embodiments) implements and practices the present disclosure. Moreover, although the embodiments of the present disclosure can achieve advantages better than other possible schemes and / or the prior art, whether a specific advantage is achieved by a given embodiment does not limit the present disclosure. Therefore, the following aspects, features, embodiments and advantages are merely illustrative and are not considered to be elements or limiting features of the appended claims unless explicitly cited in the claims. Similarly, reference to "the present disclosure" should not be understood as a summary of any creative subject matter disclosed herein, and should not be understood as elements or limiting features of the appended claims unless explicitly cited in the claims.

[0021] Embodiments of the present disclosure generally relate to data storage and computer storage systems, and more specifically to a SOT-MRAM chip structure. The SOT-MRAM chip structure includes a plurality of leads, a plurality of memory cells, and a plurality of transistors. The leads may be made of a material having a large spin-orbit coupling strength and a high resistivity. Each lead of the plurality of leads may include a plurality of first portions and a plurality of second portions distinguished from the first portions. The resistivity of the second portion is less than the resistivity of the first portion, so the total resistivity of the lead is reduced, resulting in improved power efficiency and signal-to-noise ratio.

[0022] Figure 11 is a schematic perspective view of a single lead 102, a plurality of memory cells 104, and a plurality of transistors 106 according to one embodiment described herein. The lead 102, the plurality of memory cells 104, and the plurality of transistors 106 may be part of a SOT-MRAM chip structure. The SOT-MRAM chip structure may include a plurality of leads 102, each of which may be attached to a plurality of memory cells 104. The lead 102 may be made of a material having a large spin-orbit coupling strength, such as Pt, Ta, W, Hf, Ir, CuBi, CuIr, or AuW. The material having a large spin-orbit coupling strength may have a high resistivity, such as from about 150 μΩcm to about 250 μΩcm. The material having a large spin-orbit coupling strength is referred to herein as a spin-orbit torque (SOT) material. The resistivity of the SOT material is much greater than the resistivity of a conductive metal (such as copper). In one embodiment, the lead 102 may have a constant width W of about the size of one memory cell 104 of the plurality of memory cells 104. The width W may be in a range of about 10 nm to about 500 nm. A plurality of memory cells 104 may be electrically coupled to the lead 102 . Figure 1 104, but more than three memory cells 104 may be electrically coupled to the lead 102. Each memory cell 104 includes an MTJ element 114 having a reference layer 108, a barrier layer 110, and a free layer 112. The free layer 112 may be in contact with the lead 102. Alternatively, an in-stack layer (not shown) may be located between the free layer 112 and the lead 102. The free layer 112 may include one of Ni, Fe, Co, B, Ge, Mn and / or an alloy of Ni, Fe, Co, B, Ge or Mn, and / or a combination and mixture thereof, such as NiFe, CoFe or CoFeB. The magnetic moment of the free layer 112 may be in the layer plane or perpendicular to the layer plane. The barrier layer 110 may be made of a non-magnetic metal (such as Cu or Ag) or an insulating material (such as alumina, MgO or HfO). Reference layer 108 may include one of Ni, Fe, Co, B, Ge, Mn and / or alloys of Ni, Fe, Co, B, Ge or Mn, and / or combinations and mixtures thereof, such as NiFe, CoFe or CoFeB, and / or Co / Pt, Co / Pd or Co / Ni superlattices. The magnetic moment of reference layer 108 may be in the plane of the layer or perpendicular to the plane of the layer. Reference layer 108 may be simply pinned or antiparallel (AP) pinned. Each transistor 106 of multiple transistors 106 may be electrically coupled to a corresponding memory cell 104, such as Figure 1 Transistor 106 may be any semiconductor device capable of switching electrical power, such as a complementary metal oxide semiconductor (CMOS) transistor.

[0023] During operation, writing is accomplished by a semi-selection mechanism that includes a combination of passing a current through the lead 102 and biasing a single memory cell 104 via a transistor 106 electrically coupled to the memory cell 104. Spin-orbit torque (SOT) may be derived from a spin Hall or Rashba effect generated by the current passing through the lead 102. Passing a current through the lead 102 alone is not sufficient to switch the state of the memory cell 104. In one embodiment, the current passing through the lead 102 is half of the current that causes the memory cell 104 to switch. In order to select a particular memory cell 104 for a write process, a voltage is applied to the memory cell 104 to produce a voltage controlled magnetic anisotropy (VCMA) effect. The VCMA effect can be explained in terms of an electric field-induced change in the occupancy of atomic orbitals at the interface in the MTJ of the memory cell 104, which cooperates with the spin-orbit coupling to produce a change in anisotropy. For example, a reduction in the electron density at the interface can increase the perpendicular anisotropy. Since the magnetoelectric coupling is not strain mediated, it is not endurance limited, making it compatible with logic and storage applications. The combination of SOT and VCMA selects a specific memory cell 104 for the write process. Here, the impedance of the barrier layer 110 is tuned to be large enough so that the current flowing through the lead 102 is relatively small. Reading is accomplished by passing current through the lead 102 and using transistor 106 to select a specific memory cell 104.

[0024] In another embodiment, the barrier layer 110 impedance can be made low enough so that the current across the MTJ of a particular memory cell 104 is half the current that causes the memory cell 104 to switch. Here, the combination of SOT and direct spin torque transfer from the current selects a particular memory cell 104 for the write process.

[0025] In order to increase the torque acting on the memory cell 104, the thickness of the lead 102 can be about the spin diffusion length of the SOT material used, which is generally about 5-10 nm, and the width W of the lead 102 can be about the size of the memory cell 104 (to increase the current density). Since the lead 102 is made of a SOT material with a high resistivity, the lead 102 has a relatively small thickness and width, so problems such as heat generation or low power efficiency (due to the large voltage applied by the high resistivity) may occur. In order to improve power efficiency and reduce heat generation in the lead 102, the lead 102 can be modified to reduce the resistance of the lead 102.

[0026] Figure 2 1 is a schematic perspective view of a lead 102, a plurality of memory cells 104, and a plurality of transistors 106 according to another embodiment described herein. Figure 2As shown, the lead 102 may include a plurality of first portions 202 and a plurality of second portions 204 distinguished from the first portions. The first portion 202 and the second portion 204 may be made of the same material, such as a SOT material. Each first portion 202 of the plurality of first portions 202 has a width W and each second portion 204 of the plurality of second portions 204 has a width W1. The widths W and W1 may be in the range of about 10 nm to about 500 nm, and the width W1 is greater than the width W. Each first portion 202 may be electrically coupled to the memory cell 104, and each second portion 204 may be located between two first portions 202. Each second portion 204 is spaced apart from the memory cell 104 and does not contact the memory cell 104. In other words, each second portion 204 may be located between adjacent memory cells 104. The smaller width W of the first portion 202 coupled to the memory cell 104 may increase the torque acting on the memory cell 104 (due to the increased current density). The larger width W1 of second portion 204 reduces the resistivity of second portion 204, which results in an overall reduced resistivity of lead 102. Since lead 102 has second portion 204 that is wider than first portion 202, power efficiency is increased due to a smaller voltage applied to lead 102.

[0027] Figure 3 1 is a schematic perspective view of a lead 102, a plurality of memory cells 104, and a plurality of transistors 106 of another embodiment described herein. Figure 3As shown, the lead 102 may include a plurality of first portions 302 and a plurality of second portions 304 distinguished from the first portions 302. Each first portion 302 of the plurality of first portions 302 has a width W, and each second portion 304 of the plurality of second portions 304 has the same width W. Each first portion 302 may be electrically coupled to the memory cell 104, and each second portion 304 may be located between two first portions 302. Each second portion 304 does not contact the memory cell 104. In other words, each second portion 304 is located between adjacent memory cells 104. The first portion 302 of the lead 102 may be made of a SOT material, such as Pt, Ta, W, Hf, Ir, CuBi, CuIr, or AuW. The second portion 304 of the lead 102 may be made of a material having a lower resistivity than the first portion 302. In one embodiment, the second portion 304 of the lead 102 may be made of one or more layers, at least one layer being made of a material having a lower resistivity than the first portion 302. In one embodiment, the second portion 304 is made of a single layer of a conductive metal (such as copper or aluminum) or a double layer of a conductive metal / SOT material, which can be the same material as the first portion 302. In another embodiment, the second portion 304 is made of a doped material, such as Ta doped with nitrogen. The doped material of the second portion 304 may include a substrate and a dopant. The substrate may be the same material as the first portion 302. By doping the substrate with a dopant, the resistivity of the second portion 304 is less than the resistivity of the first portion 302. In some embodiments, the first portion 302 is made of a doped material including a substrate and a dopant. The substrate may be the same material as the second portion 304. By doping the substrate with a dopant, the resistivity of the first portion 302 is higher than the resistivity of the second portion 304. Making the second portion 304 of a material having a resistivity less than the first portion 302 results in an overall reduced resistivity of the lead 102. Since the lead 102 has a second portion 304 made of a material having a resistivity less than the first portion 302, the power efficiency is increased due to the less voltage applied to the lead 102.

[0028] Return to see Figure 2 The overall resistivity of the lead 102 can also be reduced by using a more conductive material for the second portion 204. In one embodiment, the first portion 202 can be made of a SOT material, such as Pt, Ta, W, Hf, Ir, CuBi, CuIr, AuW, and the second portion 204 can be made of a conductive material similar to the second portion 304 ( Figure 3 ) In one embodiment, the second portion 204 may be made of one or more layers, at least one layer being made of a material having a lower resistivity than the first portion 202. The combination of the wider width W1 and the more conductive material of the second portion 204 results in an overall reduced resistivity of the lead 102.

[0029] Figures 4A-4J Schematically illustrates the process steps for forming leads 102 and a memory cell 104 of a plurality of memory cells according to one embodiment described herein. Figure 4A As shown, a substrate 402 including a metal pad 404 can be electrically coupled to the transistor 106. A lower layer 406 can be formed on the substrate 402. The lower layer 406 can include multiple layers, such as a grain layer for promoting the growth of the MTJ and an AFM layer for pinning the reference layer. A first ferromagnetic layer 408 can be formed on the lower layer 406 and in contact with the lower layer, a barrier layer 410 can be formed on the first ferromagnetic layer 408 and in contact with the first ferromagnetic layer, and a second ferromagnetic layer 412 can be formed on the barrier layer 410 and in contact with the barrier layer. The first ferromagnetic layer 408 can be formed by contacting the reference layer 108 ( Figure 1 ) is made of the same material as the barrier layer 110 ( Figure 1 ) is made of the same material as the free layer ( Figure 1 ) is made of the same material. The first SOT layer 414 can be formed on the second ferromagnetic layer 412 and in contact with the second ferromagnetic layer. The first SOT layer 414 can be made of SOT material and have a thickness of about 2nm to about 5nm. A sacrificial layer 416 can be formed on the first SOT layer 414 and in contact with the first SOT layer. The sacrificial layer 416 can be made of a material that is easy to etch, such as copper, aluminum or silver. The thickness of the sacrificial layer 416 can be about 2nm to about 10nm. A hard mask 418 can be formed on the sacrificial layer 416 and in contact with the sacrificial layer. The hard mask 418 can be made of a material with a low etching rate, such as diamond-like carbon, aluminum oxide, TaN or W. Layers 406-418 can be formed by any suitable method, such as physical vapor deposition, chemical vapor deposition or plasma chemical vapor deposition, and can be formed in the same processing chamber.

[0030] Next, a photoresist 422 is formed and patterned on the hard mask 418, and the pattern is transferred to the hard mask 418 to form a hard mask 420 using reactive ion etching or wet etching, such as Figure 4B As shown. To better illustrate the stack, transistor 106 may be omitted. Next, as Figure 4C As shown, the pattern is transferred to all layers on the substrate 402. A portion of the lower layer 406 is removed to form a lower layer 424, a portion of the first ferromagnetic layer 408 is removed to form a reference layer 426, a portion of the barrier layer 410 is removed to form a barrier layer 428, a portion of the second ferromagnetic layer 412 is removed to form a free layer 430, a portion of the first SOT layer 414 is removed to form a second SOT layer 432, and a portion of the sacrificial layer 416 is removed to form a sacrificial layer 434. The reference layer 426 can be the reference layer 108 ( Figure 1 ), the barrier layer 428 may be the barrier layer 110 ( Figure 1 ), the free layer 430 may be the free layer 112 ( Figure 1 ). The reference layer 426, the barrier layer 428, and the free layer 430 may form the memory cell 104. The removal process may be any suitable removal process, such as ion milling or RIE. The dielectric material 425 may be deposited on the substrate 402 and the layer stack. The dielectric material 425 may be aluminum oxide, SiO2, TaO x or other suitable dielectric material. The dielectric material 425 may be deposited using any suitable deposition method, such as ion beam deposition, plasma enhanced chemical vapor deposition, physical gas deposition, atomic layer deposition, or spin coating. In some embodiments, the dielectric material 425 does not have a flat top surface 436, such as Figure 4C As shown, a chemical mechanical polishing (CMP) process may be performed to planarize the top surface 436 of the dielectric material 425. Figure 4D As shown, after the planarization process, the top surface 436 of the dielectric material 425 is planar. In one embodiment, the dielectric material 425 is deposited as spin-on-glass, and the top surface 436 is substantially planar without performing a CMP process.

[0031] Next, if Figure 4E As shown, a portion of dielectric material 425 is removed so that a remaining portion 438 of dielectric material is flush with sacrificial layer 434. A portion of dielectric material 425 is removed by ion milling or RIE. Hard mask 420 may be removed by RIE, such as Figure 4F Next, the sacrificial layer 434 and a portion of the remaining portion 438 of the dielectric material 425 are removed to expose the second SOT layer 432, as shown in FIG. Figure 4G In one embodiment, the sacrificial layer 434 and the remaining portion 438 of the dielectric material 425 have the same etch rate, and the top surface 440 is flat after the removal process. The removal process can be ion milling or RIE.

[0032] The third SOT layer 442 is formed on the top surface 440, such as Figure 4H The third SOT layer 442 may be made of the same material as the lead 102. A photoresist 444 may be formed on the third SOT layer 442, as shown. Fig. 4I As shown. The photoresist 444 may be patterned into stripes having a constant width W or into a plurality of regions with a narrower width W and a plurality of regions with a wider width W1. By removing the portion of the third SOT layer 442 not covered by the photoresist 444, the pattern of the photoresist 444 is transferred to the third SOT layer 442, thereby forming the lead 446, as shown. Figure 4J The removal process may be ion milling or RIE. Lead 446 may be Figure 1The lead 102 shown has a constant width W or can be as shown Figure 2 Lead 102 is shown having a plurality of first portions (having width W) and a plurality of second portions (having width W1). Reference layer 426, barrier layer 428, and free layer 430 may form memory cell 104.

[0033] Figures 5A-5E Schematically illustrates the process steps for forming the lead 102 and the memory cell 104 according to another embodiment described herein. Figure 5A As shown, the starting structure is similar to Fig. 4I The memory cell 104 may include a reference layer 426, a barrier layer 428, and a free layer 430. Next, the pattern of the photoresist 444 is transferred to the third SOT layer 442 to form a SOT layer 502, as shown in FIG. Figure 5B As shown. A conductive layer 504 is deposited in the region where a portion of the SOT layer 442 is removed, forming a flat top surface 506 having the SOT layer 502 and the conductive layer 504. Alternatively, instead of removing a portion of the SOT layer 442 to form the SOT layer 502, the portion of the SOT layer 442 not covered by the photoresist 444 is doped with a dopant (such as nitrogen) to reduce the resistivity. Therefore, the portion of the SOT layer 442 covered by the photoresist 444 is the SOT layer 502, and the doped portion of the SOT layer 442 is the conductive layer 504. Alternatively, instead of doping the portion of the SOT layer 442 not covered by the photoresist 444, a material with a lower resistivity may be deposited on the portion of the SOT layer 442 not covered by the photoresist 444. The material with a lower resistivity may be a conductive metal. Therefore, the conductive layer 504 may be a double layer including a SOT layer and a conductive metal layer. The conductive layer 504 may be formed by contacting the second portion 304 ( Figure 3 ) are made of the same material. Figure 5C yes Figure 5B A top view of the top surface 506 is shown. Figure 5C As shown, top surface 506 includes alternating stripes of SOT layer 502 and conductive layer 504. Each stripe of SOT layer 502 may be over a plurality of memory cells 104 (represented by dashed lines).

[0034] Next, a photoresist may be deposited on the top surface 506 and patterned to form a plurality of photoresists 508, such as Figure 5D Each photoresist stripe 508 may be aligned with a plurality of memory cells 104 and may be perpendicular to the stripes of the SOT layer 502 and the conductive layer 504. Portions of the SOT layer 502 and the conductive layer 504 not covered by the photoresist stripe 508 are removed to form a plurality of leads 510, as shown in FIG. Figure 5EAs shown. The photoresist stripe 508 can be removed by a stripping process. Each lead 510 may include a plurality of first portions 512 and a plurality of second portions 514 distinguished from the first portions 512. The first portion 512 may be a remaining portion of the SOT layer 502, and the second portion 514 may be a remaining portion of the conductive layer 504. The lead 510 may be the lead 102, and the first portion 512 may be the first portion 302 ( Figure 3 ), the second portion 514 may be the second portion 304 ( Figure 3 ).

[0035] Figures 6A-6D Schematically illustrates the process steps for forming the lead 102 and the memory cell 104 according to another embodiment described herein. Fig. 6A As shown, the super-initial structure is similar to Figure 4J The structure shown is the same, and the memory cell 104 may include a reference layer 426 , a barrier layer 428 , and a free layer 430 . Figure 6B yes Fig. 6A A top view of the structure shown. Figure 6B As shown, a plurality of leads 446 are formed on the remaining portion 438 of the dielectric material 425. Next, a photoresist may be deposited on the plurality of leads 446 and the remaining portion 438 of the dielectric 425. The photoresist may be patterned to form a plurality of photoresist stripes 602, such as Figure 6C As shown. Each photoresist stripe 602 can be aligned with a plurality of memory cells 104 and can be perpendicular to lead 446. Portions of lead 446 not covered by photoresist stripes 602 can be doped with dopants to reduce resistivity. Next, photoresist stripes 602 can be removed by a stripping process, and a plurality of leads 604 are formed on remaining portions 438 of dielectric material 425. Each lead 604 may include a plurality of first portions 606 and a plurality of second portions 608 distinguished from the first portions 606. First portion 512 may be a portion of lead 446 covered by photoresist stripe 602, and second portion 514 may be a doped portion of lead 446. Lead 604 may be lead 102, and first portion 606 may be first portion 302 ( Figure 3 ), the second portion 608 may be the second portion 304 ( Figure 3 ).

[0036] In summary, a SOT-MRAM chip structure including multiple leads, multiple memory cells and multiple transistors is disclosed. The leads may include a first portion coupled to the memory cell and a second portion not coupled to the memory cell. The first portion is made of a SOT material having a large spin-orbit coupling strength, and the first portion is relatively thin and narrow. The second portion is wider than the first portion and / or is made of a more conductive material. Having the second portion reduces the total resistivity of the leads, thereby resulting in increased power efficiency.

[0037] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments may be made without departing from the basic scope of the invention, which is determined by the following claims.

Claims

1. A spin-orbit torque magnetoresistive random access memory (SOT-MRAM) chip structure, comprising: a plurality of memory cells, wherein each memory cell comprises a reference layer, a barrier layer, and a free layer; a plurality of leads, wherein each of the plurality of leads comprises a plurality of first portions and a plurality of second portions distinguished from the first portions, wherein each of the plurality of first portions is made of a first material, and each of the plurality of second portions is made of a second material, wherein a resistivity of the second material is less than a resistivity of the first material, and wherein the first material is selected from the group consisting of Pt, Ta, W, Hf, Ir, CuBi, CuIr, and AuW, and the second material comprises a material selected from the group consisting of Pt, Ta, W, Hf, Ir, CuBi, CuIr, and AuW doped with a dopant, and wherein each of the plurality of first portions is coupled to a corresponding memory cell of the plurality of memory cells, and the plurality of second portions do not contact the plurality of memory cells; and a plurality of transistors, wherein each transistor is coupled to a corresponding memory cell of the plurality of memory cells, wherein each memory cell further comprises a spin-orbit torque layer disposed on the free layer, wherein each of the plurality of first portions contacts the spin-orbit torque layer of a memory cell of the plurality of memory cells, and each of the plurality of second portions is separated from a memory cell of the plurality of memory cells, Wherein, the thickness of the lead is 5-10nm, Wherein, the thickness of the spin-orbit torque layer is 2-5 nm.

2. The (SOT-MRAM) chip structure as claimed in claim 1, wherein: The write process is performed by a half selection mechanism including a combination of flowing a current along a lead among a plurality of leads and applying a voltage to a memory cell among a plurality of memory cells.

3. The (SOT-MRAM) chip structure as claimed in claim 1, wherein: The second material includes one or more layers including at least one layer including copper, aluminum, or a material selected from the group consisting of Pt, Ta, W, Hf, Ir, CuBi, CuIr, and AuW doped with a dopant.

4. The (SOT-MRAM) chip structure as claimed in claim 3, wherein: The one or more layers include a first layer and a second layer, the first layer includes copper and aluminum, and the second layer includes a material selected from the group consisting of Pt, Ta, W, Hf, Ir, CuBi, CuIr and AuW.

5. The (SOT-MRAM) chip structure as claimed in claim 1, wherein: Each of the plurality of first portions has a first width, and each of the plurality of second portions has a second width, wherein the first width is smaller than the second width.

6. The (SOT-MRAM) chip structure as claimed in claim 1, wherein: The second material includes the first material doped with a dopant.

7. The (SOT-MRAM) chip structure as claimed in claim 6, wherein: The first material is tantalum and the second material is tantalum doped with nitrogen.

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