Method of manufacturing a mosfet and intermediate structure manufactured thereby

Abstract

The present disclosure relates to a method of manufacturing a field effect transistor, the method comprising: providing a substrate comprising a semiconductor layer, a layer of a first high-k dielectric material overlying a channel layer, and a channel layer overlying the semiconductor layer, performing a patterning process such that at least the first high-k dielectric material layer is removed from a first region for forming a source electrode and a second region for forming a drain electrode, such that a third region for forming a gate electrode comprising a patterned layer of the first high-k dielectric material is formed between the first region in which the source electrode is formed and the second region in which the drain electrode is formed, wherein the source electrode and the drain electrode have exposed extremities and comprise a material susceptible to self-limiting oxidation, placing the source electrode and the drain electrode in an oxidizing medium, thereby converting the exposed extremities of the source electrode and the drain electrode into a conformal layer of oxide, and providing a gate electrode only over the patterned layer of the first high-k dielectric material in the third region.

Description

Technical Field

[0001] This invention relates to a method for manufacturing a field-effect transistor (FET). More specifically, it relates to manufacturing a metal-oxide-semiconductor field-effect transistor (MOSFET) and intermediate structures manufactured therefrom. Background Technology

[0002] Reducing parasitic resistance and capacitance, which limit device performance, is an important consideration in the design and manufacture of electronic devices.

[0003] In the context of MOSFETs, the two main parasitic properties of the device—access resistance and gate-source / drain capacitance—can be minimized by forming the source and drain regions in a self-aligned manner with the gate. This is possible in MOSFETs fabricated based on silicon and other mainstream semiconductor materials, according to techniques that utilize self-aligned source and drain contact regions with the gate. However, for MOSFETs that fabricate the channel layer using different materials, this capability is absent due to the lack of suitable doping techniques in these materials, such as 2D materials, or because the source / drain electrodes are placed directly on the channel. This means that the source and drain electrodes are not separate doped contact regions as in Si MOSFETs, such as those using III-V materials or carbon nanotubes. Therefore, the device performance of such MOSFETs is limited by access resistance and gate-source / drain capacitance.

[0004] Therefore, there is a need in the art for a method to realize a MOSFET in which the source and drain regions are self-aligned with the gate. Summary of the Invention

[0005] One object of this disclosure is to provide a method for manufacturing a field-effect transistor (FET) having a gate electrode that is self-aligned with the source / drain region; thus, the source / drain electrodes.

[0006] The above objectives are achieved by the method according to the present invention.

[0007] One advantage of embodiments of this disclosure is that the method allows the fabrication of FETs with minimal access resistance and gate-source / drain capacitance.

[0008] One advantage of embodiments of this disclosure is that the method allows the fabrication of FETs with a gate dielectric thickness of less than 10 nm, thereby electrically isolating the gate electrode from the source / drain electrodes. Another advantage of embodiments of this disclosure is that the method allows the fabrication of FETs with a gate dielectric thickness of less than 2 nm.

[0009] One advantage of embodiments of this disclosure is that the method allows for the provision of a gate electrode that is self-aligned with the source / drain electrodes of a FET, the FET comprising a 2D material layer as a channel layer.

[0010] One advantage of embodiments of this disclosure is that the method allows for the provision of a gate electrode that is self-aligned with the source / drain electrodes of a FET, the FET comprising a layer of III-V material as a channel layer.

[0011] One advantage of embodiments of this disclosure is that the method allows for the provision of a gate electrode that is self-aligned with the source / drain electrodes of a FET having a gate dielectric thickness of less than 10 nm and including a III-V material layer, carbon nanotube, or 2D material layer as a channel layer, wherein the gate electrode is electrically isolated from the source / drain electrodes.

[0012] In a first aspect, this disclosure relates to a method of manufacturing a field-effect transistor, the field-effect transistor including a source electrode and a drain electrode in contact with a channel layer. The method includes:

[0013] - A substrate is provided, comprising a semiconductor layer, a first high-k dielectric material layer covering a channel layer, and a channel layer covering the semiconductor layer.

[0014] - A patterning process is performed such that at least a first high-k dielectric material layer is removed from a first region for forming a source electrode and a second region for forming a drain electrode, such that a third region for forming a gate electrode, comprising a patterned layer of the first high-k dielectric material, is formed between the first and second regions.

[0015] - A source electrode is formed in a first region and a drain electrode is formed in a second region, wherein the source electrode and the drain electrode have exposed ends and include materials susceptible to self-limiting oxidation.

[0016] - By placing the source and drain electrodes in an oxide medium, the exposed ends of the source and drain electrodes are transformed into a conformal layer of oxide.

[0017] - Gate electrodes are provided only on the patterned layer of the first high-k dielectric material in the third region.

[0018] In a second aspect, this disclosure relates to an intermediate structure for manufacturing field-effect transistors. The intermediate structure includes:

[0019] - A substrate, the substrate including a first region spatially separated from a second region by a third region, the third region including a semiconductor layer, a channel layer covering the semiconductor layer, and a first high-k dielectric material layer covering the channel layer.

[0020] - A source electrode in a first region and a drain electrode in a second region, wherein the source electrode and the drain electrode are in contact with the channel layer and comprise a material susceptible to self-limiting oxidation, and have a conformal layer of oxides at their exposed ends, and

[0021] - The first gate electrode on the first high-k dielectric material layer in the third region.

[0022] Specific and preferred aspects of the invention are set forth in the appended independent and dependent claims. Features from the dependent claims may be suitably combined with features of the independent claims and other dependent claims, and not merely as expressly set forth in the claims.

[0023] Although devices in the field are constantly being improved, changed, and developed, it is believed that the concepts of this invention represent a sufficiently novel and original advancement, including deviations from prior practice, thereby providing devices with this property that are more efficient, stable, and reliable.

[0024] The above and other features, characteristics, and advantages of the present invention will become apparent from the following detailed description taken in conjunction with the accompanying drawings, which illustrate the principles of the invention by way of example. This description is given for illustrative purposes only and does not limit the scope of the invention. The accompanying drawings are referenced below. Attached Figure Description

[0025] Figures 1a to 1f : This shows a schematic representation of the processing steps used as in an embodiment of the first aspect of the invention.

[0026] Figure 2 : This shows a schematic representation of an intermediate structure obtained during an embodiment according to a first aspect of the invention, wherein the source electrode and the drain electrode have upper and lower portions, and the ends of the source electrode and the drain electrode are oxidized.

[0027] Figures 3a to 3b : This shows a schematic representation of an intermediate structure in an embodiment according to a first aspect of the invention, wherein a gap is formed between the gate electrode and the source electrode and between the gate electrode and the drain electrode.

[0028] Figure 3c : This shows a schematic representation of an intermediate structure obtained during an embodiment according to a first aspect of the invention, wherein a conformal layer of dielectric material is provided at the ends of the source and drain electrodes.

[0029] Figures 4a to 4c : This illustrates a schematic representation of the steps performed during an embodiment of the first aspect of the invention, wherein the substrate further includes a second high-k dielectric material layer.

[0030] Figures 5a to 5b : This shows a schematic representation of the steps performed during an embodiment of the first aspect of the invention, illustrating the creation of the bottom gate electrode.

[0031] Figures 6a to 6e: This illustrates a schematic representation of the steps performed during an embodiment of the first aspect of the invention, showing an alternative example of the creation of the bottom gate electrode.

[0032] Figure 7 : A schematic representation of an intermediate structure for manufacturing a field-effect transistor according to a second aspect of the present invention.

[0033] Figures 8a to 8b : This shows a schematic representation of an embodiment according to the second aspect of the invention. Detailed Implementation

[0034] The invention will be described with reference to specific embodiments and certain accompanying drawings, but the invention is not limited thereto, but is defined only by the claims. The described drawings are merely illustrative and not restrictive. In the drawings, some elements may be enlarged and not drawn to scale for illustrative purposes. Scale and relative scale do not correspond to a true reduction in scale for the practice of the invention.

[0035] Furthermore, the terms first, second, and third, etc., used in the specification and claims are used to distinguish similar elements and are not necessarily used to describe a temporal, spatial, arrangement, or any other chronological order. It should be understood that the terms thus used are interchangeable where appropriate, and the embodiments of the invention described herein can be operated in a different order than those described or illustrated herein.

[0036] Furthermore, the terms top, above, below, etc., used in the specification and claims are for descriptive purposes and not necessarily for describing relative positions. It should be understood that these terms, as used so, can be interchanged with their antonyms where appropriate, and the embodiments of the invention described herein can operate in orientations other than those described or illustrated herein.

[0037] It should be noted that the term "comprising" as used in the claims should not be construed as limiting itself to the means listed thereafter; it does not exclude other elements or steps. Therefore, the term should be interpreted as specifying the presence of the stated features, integers, steps, or components as mentioned, but does not exclude the presence or addition of one or more other features, integers, steps, or components, or groups thereof. Thus, the term "comprising" covers both the presence of only the stated feature and the presence of these features along with one or more other features. Therefore, the scope of a device comprising "A and B" should not be construed as limited to a device consisting only of components A and B. This means that for the purposes of this invention, the only relevant components of the device are A and B.

[0038] Throughout this specification, the reference to "an embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. Therefore, the phrase "in an embodiment" or "in an embodiment" appearing in various places throughout this specification does not necessarily refer to the same embodiment, but may refer to the same embodiment. Furthermore, in one or more embodiments, as will be obvious to those skilled in the art from this disclosure, particular features, structures, or characteristics can be combined in any suitable manner.

[0039] Similarly, it should be understood that in the description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, drawing, or description for the purpose of simplifying the disclosure and aiding in the understanding of one or more inventive aspects. However, this method of disclosure should not be construed as reflecting an intention to claim more features than are expressly recited in each claim. Rather, as reflected in the appended claims, inventive aspects exist in fewer features than all the features of a single foregoing disclosed embodiment. Therefore, the claims appended following the detailed description are thus explicitly incorporated into this detailed description, wherein each claim itself represents a separate embodiment of the invention.

[0040] Furthermore, while some embodiments described herein include features that are included in other embodiments but not others, it will be understood by those skilled in the art that combinations of features from different embodiments are intended to fall within the scope of the invention and form different embodiments. For example, any embodiment of the claimed embodiments in the appended claims can be used in any combination.

[0041] Numerous specific details are set forth in the description provided herein. However, it should be understood that embodiments of the invention may be practiced without these specific details. In other instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this description.

[0042] The following items are provided separately to facilitate understanding of the invention.

[0043] As used herein and unless otherwise specified, the term “access resistance” refers to the resistance caused by the channel region between the edge of the source or drain contact electrode and the edge of the gate electrode.

[0044] As used herein and unless otherwise specified, the term “gate-source / drain capacitance” refers to the capacitance resulting from the lateral or vertical overlap of the gate electrode with the source and drain electrodes.

[0045] As used herein and unless otherwise specified, the term “DC performance” refers to performance characteristics such as total device resistance or on-state current.

[0046] As used herein and unless otherwise specified, the term "high-frequency performance" refers to current and power gain, and the maximum current and power gain cutoff frequency. High frequency as used herein refers to frequency values ​​above 1 GHz.

[0047] As used herein and unless otherwise specified, the term "two-dimensional structure" refers to a crystalline material whose crystal structure is a two-dimensional array of atoms or molecules.

[0048] As used herein and unless otherwise specified, the term "self-limiting oxidation" refers to the process by which the oxidation rate of a material decreases to an infinitesimal value after a certain thickness of the material has been oxidized, under given temperature and conditions.

[0049] This disclosure will now be described in detail through several embodiments thereof. It will be apparent that other embodiments of this disclosure can be configured based on the knowledge of those skilled in the art without departing from the technical teachings of this disclosure, which is limited only by the provisions of the appended claims.

[0050] Referring now to FIG1, a schematic representation of the processing steps used in an embodiment of the first aspect of the invention is shown.

[0051] The method includes providing a substrate (25). The substrate includes a semiconductor layer (10). In various embodiments, the semiconductor layer may be a Si layer. In various embodiments, the Si layer may be... <111> An oriented Si layer. In an alternative embodiment, the semiconductor layer (10) may also be a Ge layer, a SiC layer, or a III-V semiconductor layer. The substrate (25) further includes a first high-k dielectric layer (40). The first high-k dielectric layer (40) covers the channel layer (30).

[0052] In various embodiments, the first high-k dielectric material layer (40) may be in direct contact with the channel layer (30).

[0053] In other embodiments, an intermediate layer may be present between the first high-k dielectric material layer (40) and the channel layer (30) to enhance or promote adhesion, for example.

[0054] In various embodiments, the first high-k dielectric layer (40) can be any type of high-k dielectric material known in the art suitable for manufacturing field-effect transistors. A channel layer (30) covers the semiconductor layer (10). In various embodiments, the substrate may include a dielectric layer (20) located between the semiconductor layer (10) and the channel layer (30). This dielectric layer isolates the channel layer (30) from the semiconductor layer (10). This prevents the semiconductor layer (10) from operating as a parasitic parallel channel.

[0055] In various embodiments, when the semiconductor layer is a silicon layer, the dielectric layer (20) may be silicon oxide. In alternative embodiments, when the semiconductor layer is a III-V semiconductor layer, the dielectric layer (20) may be a high bandgap material such as AlA or AlN. Regarding the thickness of the dielectric layer (20), the lower limit is determined by the leakage current and parasitic capacitance caused by the dielectric; thus, a thickness value of less than 5 nm is generally preferred. On the other hand, there is no upper limit to the thickness, except for feasibility and compatibility limitations with other manufacturing methods.

[0056] In various embodiments, the channel layer (30) may comprise a two-dimensional (2D) material. This 2D material may be a transition metal dichalcogenide, represented by the chemical formula MX2, where M represents a transition metal, such as W or Mo, and X represents a chalcogenide, such as an oxy-based nonmetal, such as S, Se, or Te. Graphene is another 2D material. However, its lack of a band gap and the fact that opening the band gap degrades its mobility pose challenges to its use as a channel layer.

[0057] In an alternative embodiment, the channel layer (30) may include a III-V material.

[0058] In further alternative embodiments, the channel layer (30) may include a II-VI material.

[0059] In various embodiments, the thickness of the channel layer (30) may be less than 2 nm. This thickness is typically achieved by constraints imposed by the material synthesis method. In practice, the upper limit for the channel layer thickness is less than 50 nm.

[0060] In a further embodiment, the channel layer (30) may be made of carbon nanotubes. In these embodiments, the thickness of the channel layer may range from 0.3 nm to 40 nm.

[0061] The method also includes performing a patterning process. As a result of this patterning process, at least a first high-k dielectric material layer (40) is removed from the first region (I) and the second region (II), as... Figure 1b As shown. This results in the formation of a patterned layer (41) of a first high-k dielectric material. The first region (I) is suitable for forming a source electrode, while the second region (II) is suitable for forming a drain electrode. Therefore, the patterning process results in the formation of a third region (III) with a width of “x”, which is suitable for forming a gate electrode. This third region (III) spatially separates the first region (I) from the second region (II).

[0062] In various embodiments, both the first high-k dielectric material layer (40) and the channel layer (30) can be removed from the first region (I) and the second region (II), such as Figure 1c As shown.

[0063] In this case, the third region (III) with a width “x” includes a patterned layer (41) of a first high-k dielectric material and a patterned channel layer (31). The method also includes forming a source electrode (50) in the first region (I) and a drain electrode (51) in the second region (II), as... Figure 1d As shown. The source electrode (50) and drain electrode (51) have exposed ends and comprise a material susceptible to self-limiting oxidation. In various embodiments, such a material may be a metal, such as aluminum, titanium, or copper. In alternative embodiments, such a material may also be a semiconductor material, such as silicon. The source electrode (50) and drain electrode (51) are placed in an oxidizing medium. Due to the self-limiting oxidation properties, the source electrode and drain electrode are not completely oxidized, and exposure converts the exposed ends of the source electrode (50) and drain electrode (51) into a conformal layer (60) of oxide, as shown. Figure 1e As shown. In this way, the width of the third region, which is the distance (x) between the source and drain regions, is maintained because the thickness of the conformal oxide layer does not extend into the third region. Thus, the gate length remains equal to the distance (x) between the source (I) and drain (II).

[0064] In various embodiments, the thickness of the conformal layer of the oxide can be configured to provide electrical isolation, thereby achieving leakage current and breakdown voltage comparable to those of typical dielectrics used in the same devices / technologies.

[0065] In various embodiments, the oxidation medium can be a gaseous and / or liquid medium. In a preferred embodiment, the medium is a gaseous medium. In various embodiments, the gaseous medium can be a gaseous environment. In various embodiments, the gaseous environment includes oxygen. The gaseous environment can be an environment in which the source and drain electrodes are exposed, such as, for example, within the cavity of a machining tool or in a machining environment. In various embodiments, the substrate can be integrally placed in the oxidation medium. The method also includes providing a gate electrode (150) on a patterned layer (41) of a first high-k dielectric material in the third region (III), such as Figure 1f As shown.

[0066] In various embodiments, the gate electrode (150) may be provided in different ways.

[0067] In various embodiments, the gate electrode (150) may be a metal or semiconductor doped at a concentration level of dopant to achieve a resistance comparable to that of a metal.

[0068] In various embodiments, after the source / drain electrodes (50, 51) are formed and placed in an oxide medium, a dielectric layer may be deposited on the substrate, thereby converting their ends into a conformal layer (60) of oxide. In various embodiments, this dielectric may be silicon oxide. When photolithography is performed on the gate electrode, a photoresist layer is used to define the gate opening, which includes a third region (III) with a width “x”. After the gate electrode metal is deposited, a planarization process may be performed to form a flat surface, thereby patterning the photoresist features adjacent to the gate electrode metal on a common surface. Etching back the gate electrode metal in the third region (III) results in the formation of the gate electrode (150).

[0069] In an alternative embodiment, the provision of the gate electrode (150) can be facilitated by a stripping process. This involves performing a photolithography process to deposit a photoresist layer on the substrate, followed by gate electrode patterning. Subsequently, gate electrode metal is provided on the substrate at a desired thickness, the gate electrode metal being disposed on the patterned photoresist features resting on the exposed surfaces of the source / drain electrodes (50, 51) and the substrate. After the gate metal stripping process, the patterned photoresist features and the gate electrode metal present thereon are removed.

[0070] The inventors have discovered that, in the fabrication of field-effect transistors, when the source and drain electrodes contain materials susceptible to self-limiting oxidation, the formation of a conformal layer of oxides at the ends of the source and drain electrodes helps to self-align the gate electrode with the first and second regions in which the source and drain electrodes are formed, respectively.

[0071] Furthermore, due to this self-limiting characteristic, no additional space is introduced in the third region providing the gate electrode. Therefore, the gate length in the third region is maintained compared to the design value. This is an advantage compared to conventional practices (where a dielectric spacer layer between the source or drain electrode and the gate electrode can be formed by depositing a dielectric layer followed by anisotropic etching). It reduces the gate length, thereby increasing the access resistance. Thus, the method of the present invention leads to improvements in DC performance and the high-frequency performance of the FET. This is achieved by reducing the access resistance and the gate-source / drain capacitance.

[0072] In addition, due to the self-limiting oxidation of the source electrode (50) and the drain electrode (51), the gate length is not lost, thus allowing it to be as small as photolithography allows.

[0073] The method of the present invention is particularly advantageous when the channel layer is made of a 2D material. Feasible doping techniques for 2D materials do not exist. In a FET with a 2D material channel, where there are no doped source and drain regions, the channel length is equal to the distance between the source and drain electrodes. Therefore, self-aligned gates and source / drain electrodes imply that the length of the gate electrode is equal to the source-drain electrode spacing. This, subsequently, presents the challenge of electrically isolating the gate electrode from the source or drain electrode. This becomes even more challenging as the gate dielectric thickness decreases proportionally.

[0074] Using the method of the present invention, electrical isolation can be achieved without doping a 2D material layer because the source electrode or drain electrode contains a material that is susceptible to self-limiting oxidation (resulting in a conformal layer that is converted into an oxide).

[0075] In various embodiments, both the first high-k dielectric material layer (40) and the channel layer (30) can be removed, such as Figure 1c As shown. The patterning process may include: providing a patterned photoresist layer on a first high-k dielectric material layer (40), and then etching the first high-k dielectric material layer (40) and the channel layer (30) from a first region (I) and from a second region (II), wherein the first high-k dielectric material layer (40) and the channel layer (30) are not actually covered with the patterned photoresist layer. In these embodiments, the duration for which the source electrode (50) and the drain electrode (51) are placed in the oxide medium is configured such that at least a portion of the source electrode (50) and the drain electrode (51) in direct contact with the channel layer (31) remains unoxidized. This provides electrical contact between the at least unoxidized portion and the patterned channel layer (31), allowing the device to still function.

[0076] The thickness of the formed conformal layer (60) can vary depending on the duration the source / drain electrodes (50, 51) are placed in the oxide medium, which depends on the type of material used that is susceptible to self-limiting oxidation. When the thickness of the gate dielectric (41) is proportionally reduced, configuring the duration of this placement becomes crucial to prevent complete oxidation of the portions of the source electrode (50) or drain electrode (51) that are in direct contact with the patterned channel layer (31); otherwise, the device will cease to function because the current path through the source / drain electrodes (50, 51) and the gate electrode (150) will be blocked by the formed conformal layer of oxide. This can occur, for example, when the thickness of the patterned gate dielectric is less than the thickness of the formed conformal layer (60) of oxide. If continued exposure to the oxidizing medium is permitted, for example, until the maximum thickness achievable through the self-limiting oxidation properties of the source electrode (50) or drain electrode (51) is reached, the sidewalls of the source / drain electrodes in contact with the first high-k dielectric material layer and the channel layer can also be oxidized up to that maximum thickness, thereby blocking the electrical connection between the source / drain electrodes (50, 51) and the channel layer (31). This is due to the fact that oxidation also occurs in the downward direction to compensate for the oxidation in the lateral direction. Therefore, in embodiments where the patterning process removes the first high-k dielectric material layer (40) and the channel layer (30) from the first region (I) and from the second region (II), the degree of oxidation in the downward direction should be less than the combined thickness of the patterned layer (41) of the first high-k dielectric material and the patterned channel layer (31) so that the FET device can operate.

[0077] In various embodiments, materials susceptible to self-limiting oxidation may be included in the upper portion (A) of the source electrode (50) and drain electrode (51). The upper portion may be located above and in contact with the lower portion (B). The lower portion may be in contact with the channel layer (31) and may include materials that cannot be oxidized by an oxidizing medium, such as... Figure 2 As shown. In various embodiments, the lower portion (B) may have a thickness at least equal to the thickness of the patterned channel layer (31). Advantageously, the material of the lower portion cannot be oxidized by an oxidizing medium, as oxidation would sever the electrical connection between the source / drain electrodes (50, 51) and the channel layer (31). In these embodiments, even if the lengths of the source and drain electrodes are reduced due to surface oxidation, there is no limitation on how small the electrode lengths can be manufactured.

[0078] In various embodiments, even when the thickness of the lower portion (B) is less than that of the channel layer (31), the functionality of the device remains unaffected even if the entire sidewall of the source / drain electrode in contact with the first high-k dielectric material layer and the channel layer is oxidized. This is because there is always an electrical connection between the source / drain electrodes (50, 51) and the channel layer (31), thanks to the fact that the lower portion (B) contains a material that cannot be oxidized by an oxidizing medium.

[0079] In various embodiments, for example in Figure 1b In the middle, if the channel layer is not patterned (30), then the lower part is in horizontal contact with the channel layer. In these embodiments, the thickness of the lower part (B) needs to be less than the thickness of the patterned layer (41) of the first high-k dielectric material.

[0080] In various embodiments, for example, Figure 1c As shown, when the channel layer is patterned (31), the lower portion will contact the patterned channel layer (31) perpendicularly from the sidewall of the patterned channel layer (31). In these embodiments, the thickness of the lower portion (B) needs to be less than the sum of the thicknesses of the patterned layer (41) of the first high-k dielectric material and the patterned channel layer (31).

[0081] Advantageously, such a lower portion (B) is included in either the source electrode (50) or the drain electrode (51). This makes it possible to... Figure 1c The patterned channel layer (31) shown or as Figure 1b The unpatterned channel layer shown is always in electrical contact with the source electrode (50) or drain electrode (51). In various embodiments, the channel layer (30) is not as... Figure 1b In the case shown by the patterning, it is further advantageous because this makes the thickness of the conformal layer of the oxide independent of the thickness of the patterned layer (41) of the first high-k dielectric material.

[0082] In various embodiments, the thickness of the lower portion may be at least equal to, less than, or greater than the thickness of the patterned channel layer (31). In various embodiments, however, even if the thickness of the lower portion is less than the thickness of the channel layer, the propagation of self-limiting oxidation at the ends of the source / drain electrodes (50, 51) becomes independent of the thickness of the first high-k dielectric material layer (41), such that oxidation along the sidewalls of the source / drain electrodes in contact with the channel layer (31) does not cause problems.

[0083] In various embodiments, the method may further include removing a conformal layer (60) of oxide from the source electrode (50) and from the drain electrode (51) after forming the gate electrode (150). This creates voids (52) between the gate electrode (150) and the source electrode (50) and between the gate electrode (150) and the drain electrode (51), for example as... Figure 3a and 3bAs shown. It is advantageous to remove the oxide layer (60) when the dielectric quality of the oxide (60) causes its resistance, capacitance, and breakdown characteristics to not meet FET device specifications. In various embodiments, the voids form air gaps, thereby providing the FET device with alternatively better resistance, capacitance, and breakdown characteristics. The conformal layer of the oxide can be removed by selectively etching the conformal layer (60) of the oxide relative to the gate electrode (150). Thus, by being selective, it means that the gate electrode (150) is not removed during the removal of the conformal layer of the oxide. Furthermore, the etching process parameters must be configured such that any portion of the substrate exposed as a result of the etching process remains intact and is not further etched to form conformal voids in place of the conformal layer (60) of the oxide.

[0084] In further embodiments, the method may include providing a dielectric material layer (61) on the source electrode (50) and drain electrode (51), the thickness of which is such that the void (52) is completely filled. In various embodiments, the dielectric material layer (61) may be a conformal layer and therefore also covers the gate electrode (150), for example as... Figure 3c As shown in the diagram. Thus, the conformal layer of dielectric material (61) can be provided, for example, by an atomic layer deposition (ALD) process. This dielectric material layer (61) can be selected to provide preferred resistance, capacitance, and breakdown characteristics for the FET device. Selecting this dielectric material layer as a low-k dielectric material has the advantage that it results in a reduction in gate-source / drain capacitance.

[0085] The methods disclosed in the above embodiments make it possible to fabricate a FET device having a top gate electrode (150) self-aligned with the source electrode (50) and the drain electrode (51). Further embodiments of the disclosed methods allow the fabrication of a FET including a dual-gate FET self-aligned with the source electrode (50) and the drain electrode (51).

[0086] Thus, in various embodiments, the substrate (25) may further include a second high-k dielectric material layer (90) sandwiched between the channel layer (30) and the oxidizable conductive material layer (80). The method may then further include, after performing patterning, replacing portions of the oxidizable conductive material layer in the first region (I) and the second region (II) with a dielectric layer (85). A portion (86) of the oxidizable conductive material layer (80) remains in the third region (III). Thus, this portion (86) of the oxidizable conductive material layer (80) retained in the third region (III) forms another gate electrode (86), wherein the thickness of the dielectric layer (85) in the first region (I) and the second region (II) is at least the same as the thickness of this portion (86) of the oxidizable conductive material layer in the third region (III). An advantage in these embodiments is that a bottom gate electrode (86) is formed. This makes it possible to fabricate dual-gate field FETs with self-aligned gate electrodes, thanks to reduced access resistance and gate-source / drain capacitance, which improves DC and high-frequency performance.

[0087] In various embodiments, the oxidizable conductive material layer (80) may be, for example, but not limited to, aluminum, molybdenum or titanium.

[0088] In any embodiment, the patterning process may include providing a layer stack for patterning on a substrate. The layer stack includes at least, for example, […]. Figure 4a The photoresist layer (109) is shown. A patterned layer stack corresponding to the third region (III) is formed on the substrate, for example, as shown. Figure 4b and Figure 6b As shown. The patterned layer stack is used as a mask to further etch the substrate, for example, as... Figure 4c and 6c As shown in the image.

[0089] In various embodiments, the layer stack may further include a sacrificial layer (100) located between the first high-k dielectric material layer (40) and the photoresist layer (109), for example, as Figure 4a As shown in the figure. Performing photolithography results in the formation of a patterned photoresist layer (110), for example, as Figure 4b As shown in the figure. Using a patterned photoresist layer (110) as a mask to etch the sacrificial layer (100) and the first high-k dielectric layer (40) results in the formation of a patterned sacrificial layer (105) and a patterned layer (41) of the first high-k dielectric material.

[0090] In these embodiments, the replacement may include performing oxygen implantation through the channel layer (30) and through a second high-k dielectric material layer (90), for example, as Figure 5aAs shown in the diagram. This implantation process provides region-selective oxidation of the oxidizable conductive material layer (80) in the first region (I) and the second region (II), thereby oxidizing it. However, in the third region (III), it remains unoxidized (86) because it is covered by the patterned layer (41) of the first high-k dielectric material, as well as the patterned sacrificial layer (105) and the patterned photoresist layer (110) (which constitute a stack of patterned layers). In this way, the risk of oxidation of the entire layer of oxidizable conductive material is avoided, which would otherwise cause the bottom gate electrode (86) to disappear.

[0091] In various embodiments, the sacrificial layer (100) can be selectively etched relative to the first high-k dielectric layer (40). In these embodiments, both the patterned photoresist layer (110) and the patterned sacrificial layer (105) can then compensate for the patterned layer stack and can be used as masks to etch the first high-k dielectric layer (40) and / or further layers of the substrate.

[0092] In other embodiments, where selectivity relative to the first layer of high-k dielectric material is not required, the patterned photoresist layer (110) compensates for the patterned layer stack, and a mask can be used to etch the first high-k dielectric material layer (40) and / or more layers of the substrate.

[0093] In various embodiments, the patterning process is performed to remove the first high-k dielectric material layer from the first region (I) and the second region (II), thereby forming a patterned layer of the first high-k dielectric layer (41) in the third region (III), for example, as... Figure 4c As shown.

[0094] After oxygen implantation, annealing can be performed to remedy defects caused by implantation and to better distribute the oxygen dopant. The channel layer (30) can then be removed from the first region (I) and the second region (II), for example, as... Figure 5b As shown in the diagram. This is because the portions of the channel layer that have already undergone implantation in the first region (I) and the second region (II) can no longer be used as the channel layer, as they are damaged by the implantation process. Thus, the unoxidized portion (86) of the oxidizable conductive material layer (80) remains in the third region (III), thereby forming the bottom gate electrode (86).

[0095] In an alternative embodiment, the first high-k dielectric material layer (40), the channel layer (30), the second high-k dielectric material layer (90), and the oxidizable conductive material layer (80) can be removed from the first region (I) and the second region (II) by performing a patterning process, for example, as Figure 6bAs shown in the figure. The patterning process in these embodiments may include providing a layer stack including a sacrificial layer (100) between a first high-k dielectric material layer (40) and the photoresist layer (109), for example, as Figure 6a As shown. Figure 6b As shown, after photolithography, a patterned photoresist layer (110) is formed, for example, as... Figure 6b As shown. Using a patterned photoresist layer (110) as a mask to etch through a first high-k dielectric material layer (40), a channel layer (30), a second high-k dielectric material layer (90), and an oxidizable conductive material layer (80) results in the formation of patterned features (101, 41, 31, 91, 86), for example, as... Figure 6c As shown in the image.

[0096] In these embodiments, the replacement process may include providing a dielectric material layer (120) on the substrate. Performing a planarization process results in the removal of the covering of the dielectric material layer (120), for example, as... Figure 6d As shown, the upper surfaces of the patterned sacrificial layer (101) and the dielectric material layer (120) are adjacent to a common plane. Subsequently, the dielectric material layer (120) can be removed from the first region (I) and the second region (II) to such an extent that the thickness of the remaining dielectric material layer (85) in the first region (I) and the second region (II) is at least the same as the thickness of the portion (86) of the oxidizable conductive material layer in the third region (III) (see...). Figure 6e This removal process can be called an etch-back process, and it may be a time-dependent process. Thus, the oxidizable conductive material layer in the third region (III) forms the bottom gate electrode.

[0097] In various embodiments, the sacrificial layer (100) may be selectively etched relative to the first high-k dielectric layer (40) and the dielectric layer (120). In these embodiments, the sacrificial material may be, for example, W, Ti, TiN, or a material suitable as a hard mask, such as, for example, spin-on carbon. The fact that the sacrificial layer (100) is easier to etch than the first high-k dielectric layer (40) and the dielectric layer (120) is also an advantage.

[0098] In various embodiments, the dielectric material layer (120) may be silicon oxide.

[0099] In various embodiments, the patterned stack includes a photoresist layer (109) located on and in contact with the sacrificial layer (100) to form the source electrode (50), while the drain electrode (51) may include metal provided on the substrate for the source electrode (50) or drain electrode (51). This provision may be performed according to a metal deposition process. In these embodiments, the metal may be provided after the patterned photoresist layer (110) has been removed from the substrate. A planarization process is performed so that the upper surface of the patterned sacrificial layer (101) is coplanar with the upper surface of the source electrode (50) and the upper surface of the drain electrode (51). Removal of the patterned sacrificial layer from the third region (III) exposes the upper surface of a first high-k dielectric material. The metals of the source electrode (50) and drain electrode (51) may be any suitable metal for this purpose. The source electrode and drain electrode may be further doped to reduce contact resistance. If silicon is used as the source / drain electrode (50, 51), doping may be performed.

[0100] In an alternative embodiment, metal can be provided to the source electrode (50) and drain electrode (51) while the patterned photoresist layer remains intact. The metal can then be deposited on the first region (I) and the second region (II), as well as on the patterned photoresist layer (110) located in the third region (III). The provision of the metal can be configured such that the source and drain electrodes achieve the desired thickness. A stripping process can then be performed to remove the patterned photoresist layer (110) and the metal on top of it from the third region (III).

[0101] We now refer to Figure 7 The diagram illustrates a schematic representation of the intermediate structure used in an embodiment of the second aspect of the invention.

[0102] The intermediate structure for manufacturing a field-effect transistor includes a substrate (25). The substrate includes a first region (I) spatially separated from a second region (II) by a third region (III). The third region (III) includes a semiconductor layer (10), a channel layer (31) covering the semiconductor layer, and a first high-k dielectric material layer (41) covering the channel layer (31). It also includes a source electrode (50) in the first region (I) and a drain electrode (51) in the second region (II), wherein the source electrode (50) and drain electrode (51) are in contact with the channel layer (31) and include a material susceptible to self-limiting oxidation, and have a conformal layer of oxides at their exposed ends, such as... Figure 7 As shown. The intermediate structure also includes a first gate electrode (150) on a first high-k dielectric material layer (41) in the third region (III), for example, as Figure 7 As shown.

[0103] This intermediate structure is advantageous because it allows the fabrication of field-effect transistors in which the gate electrode is self-aligned with the source and drain electrodes. Using such an intermediate structure is even more advantageous when a channel layer is to be used, as the source and drain regions associated with that channel layer cannot be doped. The device performance, such as DC performance and high-frequency performance, of FET devices fabricated using this intermediate structure will be limited by the access resistance and gate-source / drain capacitance.

[0104] In various embodiments, the channel layer can be a two-dimensional material. In these embodiments, the intermediate structure is more advantageous because it allows the fabrication of field-effect transistors, whereby the DC and high-frequency performance of the device will not be limited by the access resistance and gate-source / drain capacitance. Without the intermediate structure of this invention, this would create defects in FET fabrication using two-dimensional materials as the channel layer, because the doping capability of the source and drain regions is almost non-existent if unrestricted, which would hinder the self-alignment of the gate electrode with the source and drain electrodes.

[0105] Such two-dimensional materials can be transition metal dichalcogenides, represented by the chemical formula MX2, where M represents a transition metal, such as W or Mo, and X represents a chalcogenide, such as an oxygen-based nonmetal, such as S, Se, or Te. Graphene is another type of two-dimensional material.

[0106] In various embodiments, the conformal layer (60) of the oxide can be an oxide obtainable by oxidation of a material susceptible to self-limiting oxidation, which is contained within the source / drain electrodes (50, 51). This is an advantage that allows the channel length, predicted by the design and defined by the source and drain regions of this intermediate structure, to be maintained. By design, it refers to the original design made on the mask set. Therefore, there is no extra space in the channel of the FET device fabricated using this intermediate structure. Such extra space in the channel reflects itself as a difference between the design and the resulting final device, which will increase the FET's access resistance.

[0107] In various embodiments, the substrate may further include a second high-k dielectric material layer (91). This second high-k dielectric material layer may be sandwiched between the channel layer (31) and a portion (86) of the oxidizable conductive material in the third region (III). This portion (86) of the oxidizable conductive material may be laterally sandwiched by a dielectric layer (121) located in the first region (I) and the second region (II). The dielectric layer (121) may have a thickness at least the same as the thickness of the portion (86) of the oxidizable conductive material layer in the third region (III), for example, as... Figure 8a As shown. In these embodiments, a portion (86) of the oxidizable conductive material in the third region (III) serves as the bottom gate electrode of the FET device to be fabricated using this intermediate structure.

[0108] The dielectric layer (121) serves as an insulating layer between the source / drain electrodes (50, 51) and the bottom gate electrode (86), so that the bottom gate electrode (86) is not short-circuited by the source / drain electrodes (50, 51).

[0109] In various embodiments, the dielectric layer (121) that laterally holds the portion (86) of the oxidizable conductive material can be any type of dielectric material. In a preferred embodiment, the dielectric layer (121) can be a low-k dielectric material. This has the advantage of reducing the parasitic capacitance between the source / drain electrodes and the bottom gate electrode (86). This also reduces leakage current.

[0110] In an alternative embodiment, the dielectric layer (121) may be an oxide of an oxidizable conductive material (86) located in the third region (III). In various embodiments, the oxide (121) may be, for example, an oxide of aluminum, molybdenum, or titanium, which may be used as the oxidizable conductive material (80).

[0111] In various embodiments, materials susceptible to self-limiting oxidation may be included in the upper portion (A) of the source electrode (50) and drain electrode (51). This upper portion (A) may be located on and in contact with the lower portion (B), which contains a non-oxidizable material and contacts the channel layer (31) along its thickness, for example, as... Figure 8b As shown. The fact that the lower portion (B) contacts the channel layer (31) allows the channel to make electrical contact with the source / drain electrodes (50, 51). In these embodiments, the thickness of the dielectric layer (121) can be configured such that it laterally sandwiches both the portion (86) of the oxidizable conductive material in the third region (III) and the second high-k dielectric material layer (91) covering it. In these embodiments, the thickness of the dielectric layer (121) may not be such that it also laterally sandwiches the channel layer (31), because in this case, there would no longer be electrical contact between the source / drain electrodes (50, 51) and the channel layer (31).

Claims

1. A method for manufacturing a field-effect transistor, the field-effect transistor comprising a source electrode and a drain electrode in contact with a channel layer, the method comprising: A substrate (25) is provided, the substrate (25) including a semiconductor layer (10), a first high-k dielectric material layer (40) covering a channel layer (30), and a channel layer (30) covering the semiconductor layer (10). A patterning process is performed such that at least the first high-k dielectric material layer (40) is removed from the first region (I) for forming the source electrode and the second region (II) for forming the drain electrode, such that a third region (III) for forming the gate electrode, comprising the patterned layer (41) of the first high-k dielectric material, is formed between the first region (I) and the second region (II). The source electrode (50) is formed in the first region (I) and the drain electrode (51) is formed in the second region (II), wherein the source electrode (50) and the drain electrode (51) have exposed ends and comprise materials susceptible to self-limiting oxidation. The source electrode (50) and the drain electrode (51) are placed in an oxide medium, thereby transforming the exposed ends of the source electrode and the drain electrode into a conformal layer (60) of oxide. The gate electrode (150) is provided only on the patterned layer (41) of the first high-k dielectric material in the third region (III).

2. The method of claim 1, wherein, The patterning process removes both the first high-k dielectric material layer (40) and the channel layer (30) from the first region (I) and the second region (II), and the duration for which the source electrode and the drain electrode are placed in the oxidizing medium is configured such that at least a portion of the source electrode (50) and the drain electrode (51) that are in direct contact with the patterned channel layer (31) remains unoxidized, such that the unoxidized portion is in electrical contact with the patterned channel layer.

3. The method as described in claim 1 or 2, characterized in that, The material susceptible to self-limiting oxidation is included in the upper part (A) of the source electrode (50) and the drain electrode (51), the upper part (A) being located on and in contact with the lower part (B) of the source electrode (50) and the drain electrode (51), the lower part: a. Electrically contacting the patterned channel layer (31), b. Including materials that cannot be oxidized by oxidizing media.

4. The method as described in claim 1 or 2, characterized in that, The method further includes: After the gate electrode (150) is formed, the conformal layer (60) of the oxide is removed from the source electrode (50) and from the drain electrode (51), thereby forming a void (52) between the gate electrode (150) and the source electrode (50) and between the gate electrode (150) and the drain electrode (51).

5. The method as described in claim 4, characterized in that, The method further includes providing a layer of dielectric material (61) on the source electrode (50) and the drain electrode (51), the thickness of the layer of dielectric material (61) being such that the void (52) is completely filled.

6. The method as described in claim 1 or 2, characterized in that, The substrate (25) further includes a second high-k dielectric material layer (90) sandwiched between the channel layer (30) and the oxidizable conductive material layer (80), wherein the method further includes, after performing the patterning process, replacing portions of the oxidizable conductive material layer in the first region (I) and the second region (II) with dielectric layers (85, 87), thereby retaining a portion (86) of the oxidizable conductive material layer in the third region (III) to form another gate electrode, and wherein the thickness of the dielectric layers (85, 87) in the first region (I) and the second region (II) is at least the same as the thickness of the portion (86) of the oxidizable conductive material layer in the third region (III).

7. The method as described in claim 6, characterized in that, The first high-k dielectric material layer (40) is removed from the first region (I) and the second region (II) by performing the patterning process, and the replacement includes: Oxygen implantation is performed through the channel layer (30) and the second high-k dielectric material layer (90), and then... Perform annealing, and Remove the channel layer (30) from the first region (I) and the second region (II).

8. The method as described in claim 6, characterized in that, The first high-k dielectric material layer (40), the channel layer (30), the second high-k dielectric material layer (90), and the oxidizable conductive material layer (80) are removed from the first region (I) and the second region (II) by performing the patterning process, and the replacement includes: A dielectric material layer (120) is provided on the substrate (25). Perform flattening processing. Remove the dielectric material layer (120) from the first region (I) and the second region (II) to such an extent that the thickness of the remaining dielectric layer (87) in the first region (I) and the second region (II) is at least the same as the thickness of the oxidizable conductive material layer (86) in the third region (III).

9. The method as described in claim 1 or 2, characterized in that, The process of performing the patterning process includes: A layer stack for patterning is provided on the substrate (25), the layer stack including at least one photoresist layer. A patterned stack of layers is formed on the third region (III), and The patterned layer stack is used as a mask to etch the substrate.

10. The method as described in claim 9, characterized in that, The layer stack for patterning includes a photoresist layer (109) located on and in contact with the sacrificial layer (100), and the formation of a source electrode (50) in the first region (I) and a drain electrode (51) in the second region (II) includes: Metal is provided on the substrate for the source electrode or the drain electrode. A planarization process is performed so that the upper surface of the patterned sacrificial layer is coplanar with the upper surfaces of the source electrode and the drain electrode. The patterned sacrificial layer is removed from the third region, thereby exposing the upper surface of the patterned layer (41) of the first high-k dielectric material.

11. The method as described in claim 1 or 2, characterized in that, The channel layer (30) therein comprises a two-dimensional material.

12. An intermediate structure for manufacturing a field-effect transistor, the intermediate structure comprising: The substrate includes a first region (I) spatially separated from a second region (II) by a third region (III), the third region including a semiconductor layer (10), a channel layer (31) covering the semiconductor layer, and a patterned layer (41) of a first high-k dielectric material covering the channel layer. A source electrode (50) in the first region and a drain electrode (51) in the second region, wherein the source electrode and the drain electrode are in contact with the channel layer (31) and comprise a material susceptible to self-limiting oxidation, and have a conformal layer (60) of oxide at their exposed ends, wherein the conformal layer (60) of oxide is obtained by placing the source electrode (50) and the drain electrode (51) in an oxidizing medium, thereby converting the exposed ends of the source electrode (50) and the drain electrode (51). A first gate electrode (150) on the patterned layer (41) of the first high-k dielectric material in the third region (III) is self-aligned with the source electrode (50) and the drain electrode (51).

13. The intermediate structure as described in claim 12, characterized in that, The conformal layer (60) of the oxide is an oxide that can be obtained by oxidizing the material that is susceptible to self-limiting oxidation.

14. The intermediate structure as described in claim 12 or 13, characterized in that, The substrate further includes a second high-k dielectric material layer (91) sandwiched between the channel layer (31) and a portion (86) of oxidizable conductive material in the third region (III), wherein the portion (86) of oxidizable conductive material is laterally sandwiched by a dielectric layer (121) in the first region (I) and the second region (II), wherein the dielectric layer (121) has a thickness at least the same as the thickness of the portion (86) of the oxidizable conductive material layer in the third region (III).

15. The intermediate structure as described in claim 12 or 13, characterized in that, The material susceptible to self-limiting oxidation is included in the upper part (A) of the source electrode (50) and the drain electrode (51), the upper part (A) being above and in contact with the lower part (B), the lower part (B) comprising an oxidizable material and in contact with the channel layer (31) along its thickness.

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