Three-dimensional semiconductor memory device

Abstract

A three-dimensional semiconductor memory device. The semiconductor memory device includes: a cell region, which defines a vertical channel passing through alternately stacked electrode layers and interlayer dielectric layers; a step region, which is disposed adjacent to the cell region in a first direction and defines contacts connected to the electrode layers extending at different lengths; a first opening, which passes through the electrode layer and the interlayer dielectric layer in the step region; a second opening, which passes through the electrode layer and the interlayer dielectric layer in the cell region; a lower wiring connected to a peripheral circuit defined on a substrate; a top wiring, which is disposed above the electrode layer and the interlayer dielectric layer and connected to the contact; and a vertical through hole, which connects the lower wiring and the top wiring, wherein the vertical through hole includes a first vertical through hole passing through the first opening and a second vertical through hole passing through the second opening.

Description

Technical Field

[0001] Various embodiments relate generally to semiconductor memory devices, and particularly to three-dimensional semiconductor memory devices. Background Art

[0002] In order to meet consumer demand for excellent performance and low prices, the integration level in semiconductor devices must be increased. Since the integration level of a two-dimensional or planar semiconductor memory device is mainly determined by the area occupied by a unit memory cell, the integration level is greatly affected by the level of fine pattern forming technology. However, since very expensive equipment is required to form fine patterns, although the integration level of two-dimensional semiconductor memory devices is still increasing, it is still limited. In order to overcome these limitations, an alternative solution has been proposed, including a three-dimensional semiconductor memory device, which includes memory cells arranged in three dimensions.

[0003] In a three-dimensional semiconductor memory device, the integration degree can be increased by increasing the number of stacked rows of row lines. However, since the number of wirings connected to the row lines increases in proportion to the number of row lines, a large number of metal layers are required. Summary of the invention

[0004] Various embodiments relate to a semiconductor memory device that can help reduce the number of metal layers.

[0005] In an embodiment, a semiconductor memory device may include: a cell region, which defines a plurality of vertical channels, the plurality of vertical channels passing through a plurality of electrode layers and a plurality of interlayer dielectric layers alternately stacked on a source plate; a step region, which is disposed adjacent to the cell region in a first direction parallel to a top surface of the source plate and defines a plurality of contacts connected to the plurality of electrode layers extending at different lengths; a first opening, which passes through the plurality of electrode layers and the plurality of interlayer dielectric layers in a vertical direction in the step region; a second opening, which passes through the plurality of electrode layers and the plurality of interlayer dielectric layers in a vertical direction in the cell region; a plurality of lower wirings, which are disposed below the source plate and are connected to a peripheral circuit, the peripheral circuit being defined on a substrate below the source plate; a plurality of top wirings, which are disposed above the plurality of electrode layers and the plurality of interlayer dielectric layers and are connected to the plurality of contacts; and a plurality of vertical through holes, which connect the plurality of lower wirings and the plurality of top wirings. The vertical through holes may include a plurality of first vertical through holes passing through the first opening and a plurality of second vertical through holes passing through the second opening.

[0006] In an embodiment, a semiconductor memory device may include: a cell region having a plurality of vertical channels, the plurality of vertical channels passing through a plurality of electrode layers and a plurality of interlayer dielectric layers alternately stacked on a source plate; a step region adjacent to the cell region in a first direction parallel to a top surface of the source plate and having a plurality of contacts connected to the plurality of electrode layers extending into the step region with different lengths; a first opening passing through the plurality of electrode layers and the plurality of interlayer dielectric layers in a vertical direction in the step region; a second opening and a third opening passing through the plurality of electrode layers and the plurality of interlayer dielectric layers in a vertical direction in the cell region and arranged along the first direction; a plurality of lower wirings disposed below the source plate and connected to a peripheral circuit, the peripheral circuit being defined on a substrate below the source plate; a plurality of top wirings disposed above the plurality of electrode layers and the plurality of interlayer dielectric layers and connected to the plurality of contacts; and a plurality of vertical through holes connecting the plurality of lower wirings and the plurality of top wirings. The plurality of vertical through holes may include a plurality of first vertical through holes passing through the first opening, a plurality of second vertical through holes passing through the second opening, and a plurality of third vertical through holes passing through the third opening.

[0007] In an embodiment, a semiconductor memory device may include: a plurality of pass transistors defined in a substrate, the substrate being defined with a cell region, a step region extending from the cell region in a first direction, and a peripheral region extending from the step region in the first direction; a plurality of electrode layers and a plurality of interlayer dielectric layers alternately stacked on a source plate above the plurality of pass transistors; a vertical channel passing through the plurality of electrode layers and the plurality of interlayer dielectric layers in the cell region; a plurality of lower wirings disposed between the plurality of pass transistors and the source plate and coupled to the plurality of pass transistors; a plurality of top wirings disposed above the electrode layer and the plurality of interlayer dielectric layers and coupled to the plurality of electrode layers in the step region through a plurality of contacts respectively coupled to the plurality of electrode layers; and a plurality of vertical vias coupling the plurality of top wirings and the plurality of lower wirings. The plurality of vertical vias may include a first vertical via passing through a first opening defined in the electrode layer and the interlayer dielectric layer in the step region, and a second vertical via passing through a second opening defined in the plurality of electrode layers and the plurality of interlayer dielectric layers in the cell region. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram illustrating a representative semiconductor memory device according to an embodiment of the present disclosure.

[0009] Figure 2 is an example Figure 1 An equivalent circuit diagram of an example of one of the memory blocks is shown.

[0010] Figure 3 is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0011] Figure 4A is a top view schematically illustrating a semiconductor memory device related to the present disclosure.

[0012] Figure 4B is a top view schematically illustrating a semiconductor memory device related to the present disclosure.

[0013] Figure 5 is a representative cross-sectional view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0014] Figure 6 is an example Figure 5 A top view of an example of a memory structure.

[0015] Figure 7 is an example Figure 5 A top view of an example of a logical structure.

[0016] Figure 8 is a representative cross-sectional view illustrating a semiconductor memory device according to an embodiment of the present disclosure.

[0017] Fig. 9 is an example Figure 8 A top view of an example of a memory structure.

[0018] Fig.10 is an example Figure 8 A top view of an example of a logical structure.

[0019] Fig.11 is a diagram schematically illustrating a memory system including a semiconductor memory device according to an embodiment of the present disclosure.

[0020] Fig.12 is a block diagram schematically illustrating a computing system including a semiconductor memory device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] According to the description of the exemplary embodiments described below with reference to the accompanying drawings, the advantages and features of the present disclosure and the methods for realizing them will become apparent. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but can be implemented in various different ways. The exemplary embodiments of the present disclosure convey the scope of the present disclosure to those skilled in the art.

[0022] The figures, sizes, ratios, angles, and quantities of the elements given in the drawings describing the embodiments of the present disclosure are exemplary and non-restrictive only. Throughout the specification, similar reference numerals refer to similar elements. When describing the present disclosure, when it is determined that the detailed description of the known related art may obscure the gist or clarity of the present disclosure, its detailed description will be omitted. It should be understood that the terms "including", "having", "comprising", etc. used in the specification and claims should not be interpreted as being limited to the devices listed thereafter, unless otherwise expressly stated. When an indefinite article or a definite article is used when referring to a singular noun (e.g., "one", "the"), the article may include the plural form of the noun unless otherwise expressly stated.

[0023] Even if not explicitly stated, elements in the embodiments of the present disclosure should be construed as including error tolerances.

[0024] In addition, when describing the components of the present disclosure, there may be terms such as first, second, A, B, (a) and (b) used. These are only for the purpose of distinguishing one component from another component, and are not meant to imply or teach the essence, sequence, order or quantity of the component. If a component is described as "connected", "connected" or "linked" to another component, this may mean that the component is not only directly "connected", "connected" or "linked", but also indirectly "connected", "connected" or "linked" via a third component. When describing positions such as "element A on element B", "element A above element B", "element A below element B1" and "element A next to element B", unless the term "directly" or "immediately thereafter" is clearly used, another element C may be arranged between element A and element B.

[0025] In addition, the elements in the embodiments of the present disclosure are not limited by these terms. These terms are only used to distinguish one element from another element. Therefore, as used herein, within the technical concept of the present disclosure, the first element may be the second element.

[0026] The features of various exemplary embodiments of the present disclosure may be partially or completely connected, combined or separated. Technically, various interactions and operations are also feasible. Various exemplary embodiments may be implemented individually or in combination.

[0027] Hereinafter, various examples of embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0028] Figure 1 is a block diagram illustrating a representative semiconductor memory device according to an embodiment of the present disclosure.

[0029] Reference Figure 1, the semiconductor memory device 100 according to the embodiment of the present disclosure may include a memory cell array 110 and a logic circuit 120. The logic circuit 120 may include a row decoder (X-DEC) 121, a page buffer circuit 122, and a peripheral circuit (PERI circuit) 123.

[0030] The memory cell array 110 may include a plurality of memory blocks BLK. Although not shown, each memory block BLK may include a plurality of cell strings. Each cell string may include at least one drain select transistor, a plurality of memory cells, and at least one source select transistor connected in series. In the following disclosure, the embodiments may be described as being applied to NAND flash memory, but it should be noted that the present disclosure is not limited thereto.

[0031] The memory cell array 110 may be coupled to the row decoder 121 through a plurality of row lines RL. The row lines RL may include at least one drain selection line, a plurality of word lines, and at least one source selection line. The memory cell array 110 may be coupled to the page buffer circuit 122 through a plurality of bit lines BL.

[0032] The row decoder 121 may select any one of the memory blocks BLK included in the memory cell array 110 in response to the row address X_A provided from the peripheral circuit 123. The row decoder 121 may transmit the operation voltage X_V provided from the peripheral circuit 123 to the row line RL connected to the memory block BLK selected from among the memory blocks BLK included in the memory cell array 110. In order to transmit the operation voltage X_V to the row line RL, the row decoder 121 may include a plurality of pass transistors connected to the row line RL of the memory block BLK. The number of pass transistors included in the row decoder 121 may be proportional to the number of memory blocks BLK and the number of row lines RL included in each memory block BLK.

[0033] The page buffer circuit 122 may include a plurality of page buffers PB respectively connected to the bit lines BL. The page buffer circuit 122 may receive a page buffer control signal PB_C from the peripheral circuit 123, and may send a data signal DATA to and receive a data signal DATA from the peripheral circuit 123. The page buffer circuit 122 may control the bit lines BL arranged in the memory cell array 110 in response to the page buffer control signal PB_C. For example, the page buffer circuit 122 may detect data stored in the memory cells of the memory cell array 110 by sensing the signals of the bit lines BL of the memory cell array 110 in response to the page buffer control signal PB_C, and may send the data signal DATA to the peripheral circuit 123 according to the detected data. The page buffer circuit 122 may apply a signal to the bit lines BL based on the data signal DATA received from the peripheral circuit 123 in response to the page buffer control signal PB_C, so that data may be written into the memory cells of the memory cell array 110. The page buffer circuit 122 may write data in the memory cells connected to the activated word lines or read data from the memory cells connected to the activated word lines.

[0034] The peripheral circuit 123 may receive a command signal CMD, an address signal ADD, and a control signal CTRL from outside the semiconductor memory device 100, and may transmit a data signal DATA to a device outside the semiconductor memory device 100 (such as, for example, a memory controller) and receive a data signal DATA from a device outside the semiconductor memory device 100. The peripheral circuit 123 may output a signal for writing data into or reading data from the memory cell array 110 based on the command signal CMD, the address signal ADD, and the control signal CTRL, such as a row address X_A, a page buffer control signal PB_C, etc. The peripheral circuit 123 may generate various voltages including an operating voltage X_V required in the semiconductor memory device 100.

[0035] Hereinafter, in the accompanying drawings, two directions parallel to the top surface of the substrate or source plate and intersecting each other are defined as a first direction FD and a second direction SD, respectively, and a direction protruding vertically from the top surface of the substrate or source plate is defined as a third direction TD. For example, the first direction FD may correspond to the extension direction of the word line and the arrangement direction of the bit line, and the second direction SD may correspond to the extension direction of the bit line and the arrangement direction of the word line. The first direction FD and the second direction SD may substantially cross each other perpendicularly. The third direction TD may correspond to a direction perpendicular to the first direction FD and the second direction SD. In the following description, the term "vertical" or "vertical direction" will be used as having substantially the same meaning as the third direction TD. In the accompanying drawings, the direction indicated by the arrow and the direction opposite thereto represent the same direction.

[0036] Figure 2 is an example Figure 1 An equivalent circuit diagram of an example of one of the memory blocks BLK is shown.

[0037] Reference Figure 2 , the memory block BLK may include a plurality of cell strings CSTR connected between a plurality of bit lines BL and a common source line CSL. The bit lines BL may extend in a second direction SD and may be arranged in a first direction FD. A plurality of cell strings CSTR may be connected in parallel to each bit line BL. The cell strings CSTR may be commonly connected to a common source line CSL. A plurality of cell strings CSTR may be connected between a plurality of bit lines BL and a common source line CSL.

[0038] Each cell string CSTR may include a drain select transistor DST coupled to a bit line BL, a source select transistor SST coupled to a common source line CSL, and a plurality of memory cells MC coupled between the drain select transistor DST and the source select transistor SST. The drain select transistor DST, the memory cells MC, and the source select transistor SST may be coupled in series in a third direction TD.

[0039] The drain selection line DSL, the plurality of word lines WL, and the source selection line SSL may be stacked between the bit line BL and the common source line CSL in the third direction TD. The drain selection line DSL may be respectively connected to the gates of the corresponding drain selection transistors DST. The word lines WL may be respectively connected to the gates of the corresponding memory cells MC. The source selection line SSL may be connected to the gate of the source selection transistor SST. The memory cells MC commonly connected to one word line WL may constitute one page.

[0040] Figure 3 is a perspective view schematically illustrating a semiconductor memory device according to an embodiment of the present disclosure. Figure 4A is a top view schematically illustrating a semiconductor memory device related to the present disclosure. Figure 4B is a top view schematically illustrating a semiconductor memory device related to the present disclosure.

[0041] Reference Figure 3 The semiconductor memory device 100 according to the embodiment of the present disclosure may have a PUC (Peripheral Under Cell) structure. Figure 1 121), page buffer circuit ( Figure 1 122) and peripheral circuits ( Figure 1 The logic structure P of 123) can be arranged in a memory cell array ( Figure 1 110) below the memory structure C.

[0042] The PUC structure can effectively reduce the layout area by disposing circuits (other than the memory cell array 110 ) below the memory cell array 110 , and thus, can increase the number of semiconductor memory devices 100 manufactured from a single wafer.

[0043] Reference Figure 4A As the integration degree and operation speed of the semiconductor memory device 100 increase, it is necessary to reduce the signal delay provided from the row decoder 121 to the row line RL. To this end, the circuit configuring the row decoder 121 may be disposed adjacent to the memory cell array 110 and disposed along one edge of the memory cell array 110 in the second direction SD, which is the arrangement direction of the row line RL. Therefore, the row decoder 121 may have a shape extending in the second direction SD, and may have a length substantially the same as or similar to the length of the memory cell array 110 in the second direction SD.

[0044] In addition, as the integration degree and operation speed of the semiconductor memory device 100 increase, it is necessary to reduce the delay of the signal applied to the bit line BL from the page buffer circuit 122 or the signal received from the bit line BL in the page buffer circuit 122. To this end, the circuit configuring the page buffer circuit 122 may be disposed adjacent to the memory cell array 110 and disposed along the other edge of the memory cell array 110 in the first direction FD, which is the arrangement direction of the bit line BL. Due to this fact, the page buffer circuit 122 may have a shape extending in the first direction FD, and may have a length substantially the same as or similar to the length of the memory cell array 110 in the first direction FD.

[0045] Since the row decoder 121 and the page buffer circuit 122 have the same or similar length as the memory cell array 110 in a specific direction, in order to overlap both the row decoder 121 and the page buffer circuit 122 with the memory cell array 110 in the third direction TD, a portion of the row decoder 121 and a portion of the page buffer circuit 122 should overlap each other. However, in a structure in which the row decoder 121 and the page buffer circuit 122 are arranged on the same plane, the row decoder 121 and the page buffer circuit 122 cannot overlap each other. Therefore, it may be difficult to make both the row decoder 121 and the page buffer circuit 122 overlap with the memory cell array in the third direction TD. For these reasons, the page buffer circuit 122 can be set to overlap with the memory cell array 110, and the row decoder 121 can be set on the substrate 10 so as not to overlap with the memory cell array 110.

[0046] In addition, if the number of stacked row lines RL is increased to support a larger capacity and a higher integration of the semiconductor memory device 100, it is necessary to increase the number of pass transistors included in the row decoder 121. However, in order to keep the length of the row decoder 121 in the second direction SD substantially the same as or similar to the length of the memory cell array 110, the increased number of pass transistors needs to be arranged in the first direction FD. Therefore, as the length of the row decoder 121 in the first direction FD increases, the length of the semiconductor memory device 100 in the first direction FD may also increase and may cause the device to be larger than a predetermined package size.

[0047] Reference Figure 4B , each of the row decoder 121 and the page buffer circuit 122 may be divided into two or more parts, and the separated parts of the row decoder 121 and the page buffer circuit 122 may be arranged around the periphery of the memory cell array 110. For example, the circuit included in the row decoder 121 may be divided into a first row decoder 121A and a second row decoder 121B, and the circuit included in the page buffer circuit 122 may be divided into a first page buffer circuit 122A and a second page buffer circuit 122B. The first row decoder 121A and the second row decoder 121B may be arranged to overlap with the opposite corners of the memory cell array 110. Similarly, the first page buffer circuit 122A and the second page buffer circuit 122B may be arranged to overlap with the remaining opposite corners of the memory cell array 110. The first row decoder 121A and the second row decoder 121B and the first page buffer circuit 122A and the second page buffer circuit 122B may be arranged to overlap with the memory cell array 110 in the third direction TD. Since the page buffer circuit 122 and the row decoder 121 overlap with the memory cell array 110, the Figure 4B However, because the memory cell array 110 is disposed above the row decoder 121 , a wiring path for connecting the pass transistors of the row decoder 121 with the row lines RL of the memory cell array 110 should be configured to bypass the memory cell array 110 .

[0048] Figure 4BA method for configuring a bypass wiring path is illustrated, in which the top wiring TM connected to the row line RL of the memory cell array 110 and the lower wiring UM connected to the transfer transistor of the row decoder 121 extend to the peripheral region PR outside the memory cell array 110, and are connected to each other in the peripheral region PR using a vertical via V. In this case, the number of top wirings TM and lower wirings UM in the peripheral region PR can be increased, thereby increasing the number of required metal layers. Therefore, the number of manufacturing steps required to form the metal layer can be increased, so that the manufacturing time and manufacturing cost increase, and the probability of failure during the manufacturing process increases.

[0049] If the number of memory blocks is reduced, the number of row lines RL and the number of transfer transistors are also reduced, and the number of wirings connecting the row lines RL and the transfer transistors can be reduced, and the number of metal layers does not need to be increased. However, if the number of memory blocks is reduced while the capacity of the semiconductor memory device 100 is kept as it is, the number of cell strings included in each memory block increases, and in this case, the parasitic capacitance between the cell strings and the row lines RL increases, so that the operating characteristics of the semiconductor memory device are deteriorated.

[0050] Embodiments of the present disclosure may provide a semiconductor memory device capable of reducing the number of metal layers without damaging or degrading the operating characteristics of the semiconductor memory device.

[0051] Figure 5 is a representative cross-sectional view illustrating a semiconductor memory device according to an embodiment of the present disclosure. Figure 6 is an example Figure 5 A top view of an example of a memory structure. Figure 7 is an example Figure 5 A top view of an example of a logical structure. Figure 5 It is a diagram used to facilitate understanding of the present disclosure and does not represent a cross-sectional view taken along any particular direction.

[0052] Reference Figure 5 and Figure 6 , the semiconductor memory device 100 may include a cell region CR, a step region SR extending from the cell region CR in a first direction FD, and a peripheral region PR extending from the step region SR in the first direction FD. The cell region CR, the step region SR, and the peripheral region PR may be sequentially disposed in the first direction FD.

[0053] The memory structure C may include a source plate 12, and a plurality of electrode layers 20 and a plurality of interlayer dielectric layers 22 alternately stacked on the source plate 12. The electrode layer 20 may include a conductive material. For example, the electrode layer 20 may include at least one selected from a doped semiconductor (e.g., doped silicon), a metal (e.g., tungsten, copper, or aluminum), a conductive metal nitride (e.g., titanium nitride or tantalum nitride), and a transition metal (e.g., titanium or tantalum). The interlayer dielectric layer 22 may include silicon oxide. Each electrode layer 20 may include at least one source select line SSL, a plurality of word lines WL1 to WL6, and at least one drain select line DSL. As an example, the electrode layer 20 may constitute Figure 1 The row line RL.

[0054] The electrode layers 20 may extend from the cell region CR into the step region SR at different lengths, thereby forming a step structure in the step region SR. In the step region SR, each electrode layer 20 may have a pad region LP exposed by another electrode layer 20 thereon.

[0055] A plurality of common source lines CSL that divide the electrode layer 20 and the interlayer dielectric layer 22 into a plurality of blocks or / and a plurality of fingers may be defined. The common source line CSL may extend in the first direction FD and may be arranged along the second direction SD. The common source line CSL may be coupled to the source plate 12 by passing through the alternately stacked electrode layer 20 and the interlayer dielectric layer 22 in the third direction TD. A sidewall dielectric layer (not shown) may be defined on both sidewalls of each common source line CSL in the second direction SD to isolate the common source line CSL from the electrode layer 20. A slit SLT may be defined in the drain select line DSL. The slit SLT may extend in the first direction FD and may divide the drain select line DSL into units smaller than the blocks or / and the fingers.

[0056] A plurality of vertical channels CH may be defined in the cell region CR. The vertical channel CH may pass through the electrode layer 20 and the interlayer dielectric layer 22 in the third direction TD. The vertical channel CH may pass through all of the source selection line SSL, the plurality of word lines WL1 to WL6, and the drain selection line DSL. Although not numbered, each vertical channel CH may include a channel layer and a gate dielectric layer. The channel layer may include polycrystalline silicon or monocrystalline silicon, and may include P-type impurities such as boron (B) in some regions. The gate dielectric layer may have a shape of a stem tube or a cylindrical shell surrounding the outer wall of the channel layer. The gate dielectric layer may include a tunnel dielectric layer, a charge storage layer, and a blocking layer sequentially stacked from the outer wall of the channel layer inwardly. In some embodiments, the gate dielectric layer may have an ONO (oxide-nitride-oxide) stacked structure in which an oxide layer, a nitride layer, and an oxide layer are sequentially stacked. A source select transistor may be configured where the source select line SSL surrounds the vertical channel CH. Memory cells may be arranged where word lines WL1 to WL6 surround the vertical channel CH. Drain select transistors may be arranged where drain select lines DSL surround the vertical channel CH.

[0057] A dielectric layer 40 may be defined on the source plate 12 to cover the top and side surfaces of the alternately stacked electrode layers 20 and the interlayer dielectric layers 22, and to cover the side surfaces of the vertical channel CH. In the step region SR, a first opening OFC1 may be defined in the dielectric layer 40 and the alternately stacked electrode layers 20 and the interlayer dielectric layers 22. In the cell region CR, a second opening OFC2 may be defined in the dielectric layer 40 and the alternately stacked electrode layers 20 and the interlayer dielectric layers 22. The first opening OFC1 and the second opening OFC2 may pass through the dielectric layer 40 and the electrode layers 20 and the interlayer dielectric layers 22. In an embodiment, the first opening OFC1 may pass through the source select line SSL and the word lines WL1 and WL2. The second opening OFC2 may pass through all of the source select line SSL, the plurality of word lines WL1 to WL6, and the drain select line DSL. Although Figure 5 and Figure 6 The first opening OFC1 passing through the source selection line SSL and the word lines WL1 and WL2 is illustrated, and it should be noted that the first opening OFC1 may also pass through at least one of the source selection line SSL, the plurality of word lines WL1 to WL6, and the drain selection line DSL according to the extension of the word lines WL1 to WL6 in the step region SR. The first opening OFC1 and the second opening OFC2 may be filled with a dielectric layer 42.

[0058] A dielectric layer 44 may be defined on the dielectric layers 40 and 42 to cover the top surface of the vertical channel CH. In the cell region CR, a plurality of bit lines BL may be disposed on the dielectric layer 44. The bit lines BL may extend in the second direction SD and may be disposed or arranged in the first direction FD. Figure 6 Only one bit line BL is illustrated in FIG. 1 , but it should be understood that a plurality of bit lines BL are repeatedly provided or arranged in the first direction FD. The bit line BL may be coupled to the vertical channel CH through a bit line contact BLC.

[0059] A dielectric layer 46 may be defined on the dielectric layer 44 to cover the bit line BL. A source line SL may be disposed on the dielectric layer 46. The source line SL may be coupled to the common source line CSL through a contact (not shown). A dielectric layer 48 may be defined on the dielectric layer 46 to cover the source line SL.

[0060] In the step region SR, the first contacts C1 may be respectively disposed on the pad regions LP of the electrode layer 20. The first contacts C1 may be coupled to the pad regions LP of the electrode layer 20 in the step region SR and may protrude from the pad regions LP in the third direction TD.

[0061] A plurality of top wirings TM1 and TM2 may be disposed on the dielectric layers 44 and 46. One end of each of the top wirings TM1 and TM2 may be coupled to the first contact C1 in the step region SR. The other ends of some of the top wirings TM1 and TM2 may extend to the top of the first opening OFC1 in the step region SR, and the other ends of the other top wirings TM1 and TM2 may extend to the top of the second opening OFC2 in the cell region CR. The top wirings TM1 and TM2 may include a first top wiring TM1 extending to the top of the first opening OFC1 and a second top wiring TM2 extending to the top of the second opening OFC2. The first top wiring TM1 may be disposed in the step region SR or substantially in the step region SR. The second top wiring TM2 may be disposed in the step region SR and extend into the cell region CR.

[0062] The first contact C1 connected to the first top wiring TM1 may be disposed closer to the peripheral region PR than the first contact C1 connected to the second top wiring TM2. The first contact C1 connected to the second top wiring TM2 may be disposed closer to the cell region CR than the first contact C1 connected to the first top wiring TM1. The first top wiring TM1 may be disposed closer to the peripheral region PR than the second top wiring TM2. The region where the first top wiring TM1 is distributed and the region where the second top wiring TM2 is distributed may be dispersed along the first direction FD. Therefore, the first top wiring TM1 and the second top wiring TM2 may be prevented from being disposed at a high density in a specific region, and the bottleneck of the top wirings TM1 and TM2 can be prevented, suppressed or minimized.

[0063] The first top wiring TM1 may be disposed in the same layer as the bit line BL. In this case, the first top wiring TM1 may be formed in the same process step as the bit line BL, and may be made of the same material as the bit line BL.

[0064] The second top wiring TM2 may be disposed in a layer higher than the bit line BL in the third direction TD. For example, the second top wiring TM2 may be disposed in the same layer as the source line SL. In this case, the second top wiring TM2 may be formed in the same process step as the source line SL, and may be made of the same material as the source line SL. Although it is described above that the first top wiring TM1 and the second top wiring TM2 are disposed in different layers, it should be noted that the first top wiring TM1 and the second top wiring TM2 may be disposed in the same layer.

[0065] The vertical vias V1 and V2 respectively connected to the other ends of the first and second top wirings TM1 and TM2 opposite to one end may pass through the first and second openings OFC1 and OFC2 in the third direction TD. The vertical vias V1 and V2 may include a first vertical via V1 connected to the first top wiring TM1 and a second vertical via V2 connected to the second top wiring TM2.

[0066] Above the first opening OFC1, top ends of the first vertical vias V1 may be connected to the first top wirings TM1, respectively. Below the first opening OFC1, bottom ends of the first vertical vias V1 may be connected to the logic structure P. Above the second opening OFC2, top ends of the second vertical vias V2 may be connected to the second top wirings TM2, respectively. Below the second opening OFC2, bottom ends of the second vertical vias V2 may be connected to the logic structure P.

[0067] Reference Figure 5 and Figure 7 , the logic structure P may include a substrate 10 and a plurality of pass transistors PTR disposed on the substrate 10 . Figure 5 and Figure 7The pass transistor PTR disposed in the step region SR and at the edge of the cell region CR adjacent to the step region SR is illustrated. Although not shown here, in other embodiments, the pass transistor PTR may be disposed only in the cell region CR and not in the step region SR.

[0068] An active area ACT defined by an isolation layer 10A may be defined in the substrate 10. Each transfer transistor PTR may include a gate G and a source region S and a drain region D on opposite sides of the gate G in each active area ACT. A dielectric layer 50 may be defined on the substrate 10 to cover the transfer transistors PTR. A second contact C2 may be defined on the source region S of the transfer transistor PTR. The second contact C2 may be respectively connected to the source region S of the transfer transistor PTR through the dielectric layer 50.

[0069] The lower wirings UM1 and UM2 may be disposed on the dielectric layer 50. A dielectric layer 52 covering the lower wirings UM1 and UM2 may be defined on the dielectric layer 50. The source plate 12 may be disposed on the dielectric layer 52.

[0070] Refer again Figure 7 , one end of the lower wiring UM1 and UM2 may be respectively connected to the second contact C2. The other end of the lower wiring UM1 may extend to the bottom of the first opening OFC1, and the other end of the lower wiring UM2 may extend to the bottom of the second opening OFC2. The vertical vias V1 and V2 may be respectively connected to the other ends of the lower wirings UM1 and UM2. The lower wirings UM1 and UM2 may include a first lower wiring UM1 connected to the first vertical via V1 and a second lower wiring UM2 connected to the second vertical via V2.

[0071] The lower wirings UM1 and UM2 may be formed to have a property that does not exhibit process failures (e.g., hillocks) at the highest temperature (hereinafter referred to as "process critical temperature") in the process of forming the memory structure C. In other words, the lower wirings UM1 and UM2 may be formed of a material having a melting point higher than the process critical temperature and thus having heat resistance characteristics at the process critical temperature. For example, the material forming the lower wirings UM1 and UM2 may include tungsten (W). On the other hand, the conductive material used to form the top wirings TM1 and TM2 may include a material having a resistivity lower than that of the conductive material forming the lower wirings UM1 and UM2. For example, the material used to form the top wirings TM1 and TM2 may be a material having a low resistivity, such as copper or aluminum, although it may cause process failures at a temperature lower than the process critical temperature. Because the top wirings TM1 and TM2 are formed in a subsequent stage or step for manufacturing the memory structure C, a material having a low melting point and a low resistivity may be used as a conductive material for forming the top wirings TM1 and TM2. Due to the above-mentioned limitations in the manufacturing process, the resistivity of the lower wirings UM1 and UM2 may have a relatively larger value than the resistivity of the top wirings TM1 and TM2.

[0072] The transfer transistor PTR may include a first transfer transistor PTR1 coupled to the first lower wiring UM1 and a second transfer transistor PTR2 coupled to the second lower wiring UM2. The first transfer transistor PTR1 may be disposed closer to the peripheral region PR than the second transfer transistor PTR2 in the first direction. The first lower wiring UM1 may be disposed closer to the peripheral region PR than the second lower wiring UM2 in the first direction. An area where the first lower wiring UM1 is disposed and an area where the second lower wiring UM2 is disposed may be dispersed along the first direction FD. Therefore, the first lower wiring UM1 and the second lower wiring UM2 may be prevented from being disposed at a high density in a specific area, and a bottleneck of the lower wirings UM1 and UM2 may be prevented, suppressed, or minimized.

[0073] According to the present embodiment, since the bottleneck of the top wirings TM1 and TM2 and the bottleneck of the lower wirings UM1 and UM2 can be prevented, suppressed or minimized, the number of top wirings that can be provided in a single metal layer can be increased, and the number of lower wirings that can be provided in a single metal layer can be increased. Therefore, the number of metal layers required for providing the top wirings and the lower wirings can be reduced.

[0074] Figure 8 is a representative cross-sectional view illustrating a semiconductor memory device according to an embodiment of the present disclosure. Fig. 9 is an example Figure 8 A top view of an example of a memory structure. Fig.10 is an example Figure 8 A top view of an example of a logical structure. Figure 8It is a diagram for facilitating understanding of the present disclosure and does not represent a cross-sectional view cut in any particular direction.

[0075] Reference Figures 8 to 10 , the first openings OFC1 may be disposed in the step region SR, and the second and third openings OFC2 and OFC3 may be disposed in the cell region CR and spaced apart in the first direction FD. Figures 8 to 10 Two openings in the cell region CR are illustrated, but it should be noted that the number of openings provided in the cell region CR is not limited thereto. A plurality of openings may be defined in the cell region CR in the first direction FD.

[0076] The first openings OFC1 to the third openings OFC3 may pass through the dielectric layer 40 and the alternately stacked electrode layers 20 and the interlayer dielectric layer 22. The first openings OFC1 to the third openings OFC3 may be filled with the dielectric layer 42. The first opening OFC1 may pass through the source selection line SSL and the word lines WL1 and WL2. The second openings OFC2 and the third openings OFC3 may pass through all of the source selection line SSL, the plurality of word lines WL1 to WL6, and the drain selection line DSL. Although Figure 8 and Fig. 9 The first opening OFC1 passing through the source selection line SSL and the word lines WL1 and WL2 is illustrated, but it should be noted that the first opening OFC1 may also pass through at least one of the source selection line SSL, the plurality of word lines WL1 to WL6 and the drain selection line DSL according to the extension of the word lines WL1 to WL6 to the step region SR.

[0077] One ends of the top wirings TM1, TM2, and TM3 may be respectively coupled to the first contact C1 in the step region SR. The other ends of some of the top wirings TM1, TM2, and TM3 may extend to the top of the first opening OFC1 of the step region SR, the other ends of some of the top wirings TM1, TM2, and TM3 may extend to the top of the second opening OFC2 of the cell region CR, and the other ends of the other top wirings TM1, TM2, and TM3 may extend to the top of the third opening OFC3 of the cell region CR. The top wirings TM1, TM2, and TM3 may include a first top wiring TM1 extending to the top of the first opening OFC1, a second top wiring TM2 extending to the top of the second opening OFC2, and a third top wiring TM3 extending to the top of the third opening OFC3.

[0078] The first contact C1 coupled to the first top wiring TM1 may be closer to the peripheral region PR in the first direction than the first contact C1 coupled to the second top wiring TM2. The first contact C1 coupled to the second top wiring TM2 may be closer to the peripheral region PR in the first direction than the first contact C1 coupled to the third top wiring TM3.

[0079] The first top wiring TM1 may be disposed in the step region SR. One end of the second top wiring TM2 and the third top wiring TM3 may be disposed in the step region SR, and the other end may be disposed in the cell region CR. The first top wiring TM1 may be disposed closer to the peripheral region PR than the second top wiring TM2 in the first direction. The second top wiring TM2 may be disposed closer to the peripheral region PR than the third top wiring TM3 in the first direction. The region where the first top wiring TM1 is distributed, the region where the second top wiring TM2 is distributed, and the region where the third top wiring TM3 is distributed may be dispersed along the first direction FD. Therefore, the first top wiring TM1 to the third top wiring TM3 can be prevented from being disposed at a high density in a specific region, and the bottleneck of the top wirings TM1 to TM3 can be prevented, suppressed, or minimized.

[0080] The first top wiring TM1 may be provided in the same layer as the bit line BL. The second top wiring TM2 may be provided in a layer higher than the bit line BL in the third direction TD. For example, the second top wiring TM2 may be provided in the same layer as the source line SL. The third top wiring TM3 may be provided in a layer higher than the source line SL in the third direction. Although Figure 8 It is illustrated that the third top wiring TM3 is provided in a layer higher than the source line SL, but the third top wiring TM3 may be provided in the same layer as the source line SL.

[0081] Vertical vias V1, V2, and V3 respectively connected to the first top wiring TM1, the second top wiring TM2, and the third top wiring TM3 may be provided in the first opening OFC1, the second opening OFC2, and the third opening OFC3, respectively. The vertical vias V1, V2, and V3 may include a first vertical via V1 connected to the first top wiring TM1, a second vertical via V2 connected to the second top wiring TM2, and a third vertical via V3 connected to the third top wiring TM3.

[0082] Above the first opening OFC1, top ends of the first vertical vias V1 may be connected to the first top wirings TM1, respectively. Below the first opening OFC1, the bottom ends of the first vertical vias V1 may be connected to the logic structure P. Above the second opening OFC2, top ends of the second vertical vias V2 may be connected to the second top wirings TM2, respectively. Below the second opening OFC2, the bottom ends of the second vertical vias V2 may be connected to the logic structure P. Above the third opening OFC3, top ends of the third vertical vias V3 may be connected to the third top wirings TM3, respectively. Below the third opening OFC3, the bottom ends of the third vertical vias V3 may be connected to the logic structure P.

[0083] Reference Figure 8 and Fig.10 , the ends of the lower wirings UM1, UM2, and UM3 may be respectively coupled to the source regions S of the transfer transistors PTR1, PTR2, and PTR3 through the second contact C2. The end of the lower wiring UM1 may extend to the bottom of the first opening OFC1. The end of the lower wiring UM2 may extend to the bottom of the second opening OFC2, and the end of the lower wiring UM3 may extend to the bottom of the third opening OFC3. The first vertical via to the third vertical via V1, V2, and V3 may be respectively coupled to the other ends of the lower wirings UM1, UM2, and UM3. The lower wirings UM1, UM2, and UM3 may include a first lower wiring UM1 coupled to the first vertical via V1, a second lower wiring UM2 coupled to the second vertical via V2, and a third lower wiring UM3 coupled to the third vertical via V3.

[0084] The transfer transistors PTR1, PTR2, and PTR3 may include a first transfer transistor PTR1 coupled to the first lower wiring UM1, a second transfer transistor PTR2 coupled to the second lower wiring UM2, and a third transfer transistor PTR3 coupled to the third lower wiring UM3. The first transfer transistor PTR1 may be disposed closer to the peripheral region PR in the first direction than the second transfer transistor PTR2. The second transfer transistor PTR2 may be disposed closer to the peripheral region PR in the first direction than the third transfer transistor PTR3.

[0085] The first lower wiring UM1 may be disposed closer to the peripheral region PR than the second lower wiring UM2 in the first direction. The second lower wiring UM2 may be disposed closer to the peripheral region PR than the third lower wiring UM3 in the first direction. An area where the first lower wiring UM1 is disposed, an area where the second lower wiring UM2 is disposed, and an area where the third lower wiring UM3 is disposed may be dispersed along the first direction FD. Therefore, the first to third lower wirings UM1 to UM3 may be prevented from being disposed at a high density in a specific area, and a bottleneck of the lower wirings UM1 to UM3 can be prevented, suppressed, or minimized.

[0086] In order to connect the transfer transistor PTR3 farthest from the peripheral region PR to the electrode layer 20, a longer wiring must be used. If the length of the wiring increases, the load may increase. Therefore, since the operating voltage may drop significantly during the process of transmitting the operating voltage from the transfer transistor PTR3 to the electrode layer 20 through the wiring, an operating voltage with a low level may be applied to the electrode layer 20.

[0087] Therefore, if an operating voltage with a low level is applied to the electrode layer 20, the reliability of the semiconductor memory device may be degraded. For example, if a low programming voltage is applied to a word line in a programming operation, the degree of rise of the threshold voltage of the memory cell may be reduced, resulting in a slow cell whose cell distribution characteristic is degraded. In other words, a slow failure may be caused. Therefore, it is necessary to reduce the load of the wiring connecting the transfer transistor PTR3 from the peripheral region PR and the electrode layer 20.

[0088] As described above, since the resistivity of the conductive material forming the top wirings TM1, TM2 and TM3 is lower than the resistivity of the conductive material forming the lower wirings UM1, UM2 and UM3, in order to reduce the load of the wiring connecting the transfer transistor PTR3 and the corresponding electrode layer 20, the length of the lower wiring UM3 connecting the transfer transistor PTR3 and the corresponding electrode layer 20 should be shortened.

[0089] By distributing a plurality of openings OFC2 and OFC3 in the cell region CR along the first direction FD (which is also the arrangement direction of the transfer transistors PTR1 to PTR3), the distance between the transfer transistor PTR3 and the opening OFC3 can be shortened. Therefore, since the lower wiring UM3 for connecting the transfer transistor PTR3 and the electrode layer 20 can be configured to have a short length for connecting the opening OFC3 and the transfer transistor PTR3, the load of the wiring UM3 can be reduced, and the operating voltage drop caused by the load of the wiring UM3 can be suppressed, so that the reliability of the semiconductor memory device can be improved.

[0090] Fig.11 is a block diagram schematically illustrating an example of a memory system including a semiconductor memory device according to an embodiment of the present disclosure.

[0091] Reference Fig.11 , a memory system 600 according to an embodiment may include a nonvolatile memory device (NVM device) 610 and a memory controller 620 .

[0092] The nonvolatile memory device 610 may be composed of the above-mentioned semiconductor memory device and may be operated in the above-mentioned manner. The memory controller 620 may be configured to control the nonvolatile memory device 610. The combination of the nonvolatile memory device 610 and the memory controller 620 may be configured as a memory card or a solid state disk (SSD). The SRAM 621 is used as a working memory of the processing unit (CPU) 622. The host interface (host I / F) 623 includes a data exchange protocol of a host connected to the memory system 600.

[0093] The error correction code block (ECC) 624 detects and corrects errors included in data read from the nonvolatile memory device 610 .

[0094] The memory interface (memory I / F) 625 interfaces with the nonvolatile memory device 610 of the present embodiment. The processing unit 622 performs overall control operations for data exchange of the memory controller 620.

[0095] Although not shown in the drawings, it is obvious to those skilled in the art that the memory system 600 according to the embodiment may be additionally provided with a ROM storing code data for interfacing with a host. The nonvolatile memory device 610 may be provided as a multi-chip package consisting of a plurality of flash memory chips.

[0096] As described above, the memory system 600 according to the embodiment can be provided as a high-reliability storage medium with a low probability of error. Specifically, the non-volatile memory device of the present embodiment can be included in a memory system such as a solid-state disk (SSD) that is being actively studied recently. In this case, the memory controller 620 can be configured to communicate with an external (e.g., host) through one of various interface protocols such as USB (Universal Serial Bus) protocol, MMC (Multimedia Card) protocol, PCI-E (Peripheral Component Interconnect Express) protocol, SATA (Serial Advanced Technology Attachment) protocol, PATA (Parallel Advanced Technology Attachment) protocol, SCSI (Small Computer System Interface) protocol, ESDI (Enhanced Small Disk Interface) protocol, and IDE (Integrated Drive Electronics) protocol.

[0097] Fig.12 is a block diagram schematically illustrating a computing system including a semiconductor memory device according to an embodiment of the present disclosure.

[0098] Reference Fig.12, the computing system 700 according to the embodiment may include a memory system 710 electrically connected to a system bus 760, a microprocessor (CPU) 720, a RAM 730, a user interface 740, and a modem 750 such as a baseband chipset. In the case where the computing system 700 according to the embodiment is a mobile device, a battery (not shown) for providing an operating voltage of the computing system 700 may be additionally provided. Although not shown in the drawings, it is obvious to a person skilled in the art that the computing system 700 according to the embodiment may be additionally provided with an application chipset, a camera image processor (CIS), a mobile DRAM, etc. The memory system 710 may be configured, for example, as an SSD (solid state drive / disk) that uses a non-volatile memory to store data. Otherwise, the memory system 710 may be configured as a fusion flash memory (e.g., OneNAND flash memory).

[0099] Although the exemplary embodiments of the present disclosure have been described for exemplary purposes, it will be understood by those skilled in the art that various modifications, additions and substitutions may be made without departing from the scope and spirit of the present disclosure. Therefore, the embodiments disclosed above and in the accompanying drawings should be considered only in a descriptive sense and are not intended to limit the technical scope. The technical scope of the present disclosure is not limited by the embodiments and the accompanying drawings. The spirit and scope of the present disclosure may be interpreted in conjunction with the appended claims, and all equivalents falling within the scope of the appended claims are encompassed.

[0100] CROSS-REFERENCE TO RELATED APPLICATIONS

[0101] This application claims the priority of Korean Patent Application No. 10-2019-0167561 filed on December 16, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference.

Claims

1. A semiconductor memory device, comprising: a cell region, the cell region defining a plurality of vertical channels passing through a plurality of electrode layers and a plurality of interlayer dielectric layers alternately stacked on a source plate; a stepped region disposed adjacent to the cell region in a first direction parallel to a top surface of the source plate and defining a plurality of contacts coupled to the plurality of electrode layers extending at different lengths; a first opening, the first opening passing through the plurality of electrode layers and the plurality of interlayer dielectric layers in a vertical direction in the step region; a second opening, the second opening passing through the plurality of electrode layers and the plurality of interlayer dielectric layers in the vertical direction in the cell region; A plurality of lower wirings, the plurality of lower wirings being arranged below the source plate and connected to a peripheral circuit, the peripheral circuit being defined on a substrate below the source plate; a plurality of top wirings disposed above the plurality of electrode layers and the plurality of interlayer dielectric layers and coupled to the plurality of contacts; as well as a plurality of vertical vias, the plurality of vertical vias connecting the plurality of lower wirings and the plurality of top wirings, wherein the plurality of vertical through holes include a plurality of first vertical through holes passing through the first opening and a plurality of second vertical through holes passing through the second opening, Wherein, the plurality of top wirings include: a plurality of first top wirings coupled to the first vertical vias; and a plurality of second top wirings, the plurality of second top wirings being coupled to the second vertical vias, wherein the plurality of first top wirings are arranged in the step region, and One ends of the plurality of second top wirings are disposed in the step region, and opposite ends of the plurality of second top wirings are disposed in the cell region.

2. The semiconductor memory device according to claim 1, wherein The plurality of contacts coupled to the plurality of second top wirings are closer to the cell region than the plurality of contacts coupled to the plurality of first top wirings.

3. The semiconductor memory device according to claim 1, further comprising: a plurality of bit lines, the plurality of bit lines being disposed above the plurality of electrode layers in the cell region, The plurality of first top wirings and the plurality of bit lines are arranged in the same layer.

4. The semiconductor memory device according to claim 1, further comprising: a plurality of bit lines, the plurality of bit lines being disposed above the plurality of electrode layers in the cell region, The plurality of second top wirings are arranged in a layer higher than the plurality of bit lines.

5. The semiconductor memory device according to claim 4, further comprising: a plurality of source lines, the plurality of source lines being arranged in a layer higher than the plurality of bit lines in the cell region, The plurality of second top wirings and the plurality of source lines are arranged in the same layer.

6. The semiconductor memory device according to claim 1, in, The peripheral circuit includes a plurality of pass transistors, and The plurality of transfer transistors are arranged in the step region and the cell region.

7. The semiconductor memory device according to claim 6, in, The plurality of lower wirings include: a plurality of first lower wirings coupled to the plurality of first vertical vias; and a plurality of second lower wirings, the plurality of second lower wirings being coupled to the plurality of second vertical vias, Wherein, the semiconductor memory device further comprises: a peripheral region disposed adjacent to the step region in the first direction opposite to the unit region, and The plurality of transfer transistors coupled to the plurality of first lower wirings are closer to the peripheral region than the plurality of transfer transistors coupled to the plurality of second lower wirings.

8. The semiconductor memory device according to claim 1, wherein: The plurality of top wirings are formed of a material having a lower resistivity than that of the plurality of lower wirings.

9. The semiconductor memory device according to claim 1, in, In the cell region, the plurality of electrode layers include at least one source selection line, a plurality of word lines, and at least one drain selection line stacked sequentially, and The second opening passes through the source selection line, the plurality of word lines and the drain selection line of the cell region.

10. A semiconductor memory device, comprising: a cell region having a plurality of vertical channels passing through a plurality of electrode layers and a plurality of interlayer dielectric layers alternately stacked on a source plate; a stepped region adjacent to the cell region in a first direction parallel to a top surface of the source plate and having a plurality of contacts coupled to the plurality of electrode layers extending into the stepped region with different lengths; a first opening, the first opening passing through the plurality of electrode layers and the plurality of interlayer dielectric layers in a vertical direction in the step region; a second opening and a third opening, wherein the second opening and the third opening pass through the plurality of electrode layers and the plurality of interlayer dielectric layers in the vertical direction in the cell region and are arranged along the first direction; A plurality of lower wirings, the plurality of lower wirings being arranged below the source plate and connected to a peripheral circuit, the peripheral circuit being defined on a substrate below the source plate; a plurality of top wirings disposed above the plurality of electrode layers and the plurality of interlayer dielectric layers and coupled to the plurality of contacts; as well as a plurality of vertical vias, the plurality of vertical vias connecting the plurality of lower wirings and the plurality of top wirings, The plurality of vertical through holes include a plurality of first vertical through holes passing through the first opening, a plurality of second vertical through holes passing through the second opening, and a plurality of third vertical through holes passing through the third opening. Wherein, the plurality of top wirings include: a plurality of first top wirings coupled to the plurality of first vertical vias; a plurality of second top wirings coupled to the plurality of second vertical vias; and a plurality of third top wirings, the plurality of third top wirings being coupled to the plurality of third vertical vias, wherein the plurality of first top wirings are arranged in the step region, and One ends of the plurality of second top wirings and the plurality of third top wirings are disposed in the step region, and opposite ends of the plurality of second top wirings and the plurality of third top wirings are disposed in the cell region.

11. The semiconductor memory device according to claim 10, wherein: The multiple contacts connected to the multiple second top wirings are arranged closer to the cell region than the multiple contacts connected to the multiple first top wirings, and the multiple contacts connected to the multiple third top wirings are arranged closer to the cell region than the multiple contacts connected to the multiple second top wirings.

12. The semiconductor memory device according to claim 10, further comprising: a plurality of bit lines, the plurality of bit lines being disposed above the plurality of electrode layers in the cell region, The plurality of first top wirings and the plurality of bit lines are arranged in the same layer.

13. The semiconductor memory device according to claim 10, further comprising: a plurality of bit lines, the plurality of bit lines being disposed above the plurality of electrode layers in the cell region, The plurality of second top wirings and the plurality of third top wirings are arranged in a layer higher than the plurality of bit lines.

14. The semiconductor memory device according to claim 13, further comprising: a plurality of source lines, the plurality of source lines being arranged in a layer higher than the plurality of bit lines in the cell region, The plurality of second top wirings and the plurality of third top wirings are arranged in the same layer as the plurality of source lines.

15. The semiconductor memory device according to claim 10, in, The peripheral circuit includes a plurality of pass transistors, and The plurality of transfer transistors are arranged in the step region and the cell region.

16. The semiconductor memory device according to claim 15, further comprising: a peripheral region adjacent to the step region and disposed opposite to the unit region in the first direction, Wherein, the plurality of lower wirings include: a plurality of first lower wirings coupled to the plurality of first vertical vias; a plurality of second lower wirings coupled to the plurality of second vertical vias; and a plurality of third lower wirings coupled to the plurality of third vertical vias, and Among them, the multiple transfer transistors connected to the multiple first lower wirings are closer to the peripheral area than the transfer transistors connected to the multiple second lower wirings, and the transfer transistors connected to the multiple second lower wirings are closer to the peripheral area than the transfer transistors connected to the multiple third lower wirings.

17. The semiconductor memory device according to claim 10, wherein: The plurality of top wirings are formed of a material having a lower resistivity than that of the plurality of lower wirings.

18. A semiconductor memory device, the semiconductor memory device comprising: a plurality of pass transistors, the plurality of pass transistors being defined in a substrate, the substrate defining a cell region, a step region extending from the cell region in a first direction, and a peripheral region extending from the step region in the first direction; a plurality of electrode layers and a plurality of interlayer dielectric layers, the plurality of electrode layers and the plurality of interlayer dielectric layers being alternately stacked on the source plate above the plurality of transfer transistors; a vertical channel passing through the plurality of electrode layers and the plurality of interlayer dielectric layers in the cell region; a plurality of lower wirings, the plurality of lower wirings being disposed between the plurality of transfer transistors and the source plate and being coupled to the plurality of transfer transistors; a plurality of top wirings, the plurality of top wirings being disposed above the plurality of electrode layers and the plurality of interlayer dielectric layers, and the plurality of top wirings being coupled to the plurality of electrode layers in the step region through a plurality of contacts respectively coupled to the plurality of electrode layers; as well as a plurality of vertical vias, the plurality of vertical vias connecting the plurality of top wirings and the plurality of lower wirings, The plurality of vertical through holes include: a first vertical through hole passing through a first opening defined in the plurality of electrode layers and the plurality of interlayer dielectric layers in the stepped region, and a second vertical through hole passing through a second opening defined in the plurality of electrode layers and the plurality of interlayer dielectric layers in the cell region. Wherein, the plurality of top wirings include: a plurality of first top wirings coupled to the first vertical vias; and a plurality of second top wirings, the plurality of second top wirings being coupled to the second vertical vias, wherein the plurality of first top wirings are arranged in the step region, and One ends of the plurality of second top wirings are disposed in the step region, and opposite ends of the plurality of second top wirings are disposed in the cell region.

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