Interposer and semiconductor package with interposer

Abstract

An interposer and a semiconductor package having the same are provided. The interposer includes a base layer having a first surface and a second surface, a redistribution structure on the first surface, an interposer protection layer on the second surface, a pad wiring layer on the interposer protection layer, an interposer through electrode passing through the base layer and the interposer protection layer and electrically connecting the redistribution structure to the pad wiring layer, an interposer connection terminal attached to the pad wiring layer, and a wiring protection layer including a first portion covering a portion of the interposer protection layer adjacent to the pad wiring layer, a second portion covering a portion of a top surface of the pad wiring layer, and a third portion covering a side surface of the pad wiring layer. The third portion is disposed between the first portion and the second portion. The first portion to the third portion have different thicknesses from each other.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2019-0158456, filed December 2, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The inventive concept relates to an interposer (or "intermediate board" or "intermediate") and a semiconductor package having the same, and more particularly, to an interposer having a redistribution layer and a semiconductor package having the same. BACKGROUND

[0003] Due to the demand for compact and multi-functional high-performance electronic products, semiconductor packages are desired to be light and highly integrated and have high performance and speed. Accordingly, there is an increasing demand for semiconductor packages for systems having high memory bandwidth. Since the memory bandwidth is proportional to the data transfer rate and the number of data transfer lines, the memory bandwidth can be increased by increasing the memory operation rate or the number of data transfer lines. Accordingly, semiconductor packages using an interposer are being introduced to increase the number and density of connection bumps of connection pads (or referred to as "pads" or "solder pads") attached to semiconductor chips. SUMMARY

[0004] The inventive concept provides an interposer for increasing memory bandwidth and a semiconductor package having the same.

[0005] According to an exemplary embodiment of the inventive concept, an interposer includes a base layer having a first surface and a second surface opposite the first surface, a redistribution structure on the first surface of the base layer, an interposer protection layer on the second surface of the base layer, a pad wiring layer on the interposer protection layer, an interposer through electrode passing through the base layer and the interposer protection layer and electrically connecting the redistribution structure to the pad wiring layer, an interposer connection terminal attached to the pad wiring layer, and a wiring protection layer including a first portion covering a portion of the interposer protection layer adjacent to the pad wiring layer, a second portion covering a portion of a top surface of the pad wiring layer, and a third portion covering a side surface of the pad wiring layer. The third portion is disposed between the first portion and the second portion. The first portion, the second portion, and the third portion have different thicknesses from each other in a vertical direction with respect to the first surface.

[0006] According to an exemplary embodiment of the inventive concept, a semiconductor package includes: a interposer including a base layer having a first surface and a second surface opposite to the first surface, a redistribution structure on the first surface of the base layer, an interposer protection layer on the second surface of the base layer, a plurality of pad wiring layers on the interposer protection layer, a plurality of interposer through electrodes passing through the base layer and the interposer protection layer and electrically connecting the redistribution structure to the plurality of pad wiring layers, a plurality of interposer connection terminals attached to the plurality of pad wiring layers, and a plurality of wiring protection layers on the interposer protection layer, the plurality of interposer through electrodes are grouped into a plurality of interposer through electrode groups, each of the plurality of wiring protection layers includes a first portion, a second portion, a third portion, and a fourth portion, the first portion covers a corresponding portion of the interposer protection layer adjacent to a corresponding pad wiring layer, the second portion covers a portion of a top surface of the corresponding pad wiring layer, the third portion covers a side surface of the corresponding pad wiring layer, the fourth portion covers a lower portion of a corresponding interposer connection terminal, the third portion is disposed between the first portion and the second portion, and the second portion is disposed between the third portion and the fourth portion; first and second semiconductor chips horizontally separated from each other on the redistribution structure and electrically connected to a first one of the plurality of interposer through electrode groups and a second one of the plurality of interposer through electrode groups, respectively, through the redistribution structure; and a package base substrate on which the interposer is mounted and to which the plurality of interposer connection terminals are connected.

[0007] According to an exemplary embodiment of the inventive concept, an interposer includes: a base layer having a first surface and a second surface opposite to the first surface; an interposer through electrode passing through the base layer and including a protrusion vertically extending away from the second surface of the base layer; an interposer protection layer on the second surface of the base layer, the interposer protection layer having a top surface coplanar with a top surface of the protrusion and surrounding a side surface of the protrusion; a pad wiring layer on the interposer protection layer and connected to the protrusion, the interposer protection layer disposed between the base layer and the pad wiring layer; an interposer connection terminal attached to the pad wiring layer; and a wiring protection layer including a first portion, a second portion, and a third portion, the first portion covering a portion of the interposer protection layer adjacent to the pad wiring layer, the second portion covering a portion of a top surface of the pad wiring layer, and the third portion covering a side surface of the pad wiring layer. The third portion is disposed between the first portion and the second portion. The first portion, the second portion, and the third portion have different thicknesses from each other in a vertical direction with respect to the first surface. BRIEF DESCRIPTION OF DRAWINGS

[0008] Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] FIG. 1Ais a cross-sectional view of an interposer according to an embodiment, FIG. 1B is an enlarged cross-sectional view of an interposer connection terminal portion of the interposer according to the embodiment;

[0010] FIGS. 2A-2I is a cross-sectional view of a stage in a method of manufacturing an interposer according to an embodiment,

[0011] FIGS. 3A-3C is an enlarged cross-sectional view of an interposer connection terminal portion of the interposer according to the embodiment;

[0012] FIGS. 4A-4C is a plan view showing a shape of a buffer protection layer of an interposer according to an embodiment,

[0013] FIG. 5A is a cross-sectional view of a semiconductor package having an interposer according to an embodiment, FIG. 5B is a cross-sectional view of a first semiconductor chip included in a semiconductor package having an interposer according to an embodiment; and

[0014] FIG. 6A and FIG. 6B is a cross-sectional view of a stage in a method of manufacturing a semiconductor package having an interposer according to an embodiment. DETAILED DESCRIPTION

[0015] FIG. 1A is a cross-sectional view of an interposer according to an embodiment. FIG. 1B is an enlarged cross-sectional view of an interposer connection terminal portion of the interposer according to the embodiment. In detail, FIG. 1B is FIG. 1A is an enlarged cross-sectional view of a region IB in

[0016] Referring to FIG. 1A , the interposer 500 can include a bulk layer 510, a redistribution structure 570 on a first surface 512 of the bulk layer 510, and a plurality of pad wiring layers 524 on a second surface 514 of the bulk layer 510. Although the first surface 512 and the second surface 514 are at the bottom and the top of the bulk layer 510, respectively, in FIG. 1A , the first surface 512 and the second surface 514 can be referred to as a top surface and a bottom surface, respectively, in a semiconductor package 1 having the interposer 500. For example, FIG. 5A , the interposer 500 of FIG. 1A is flipped upside down in the semiconductor package 1 of FIG. 5A .

[0017] The base layer 510 can include a semiconductor material, glass, ceramic, or plastic. For example, the base layer 510 can include silicon. In some embodiments, the base layer 510 can be formed of a silicon semiconductor substrate. A plurality of interposer through electrodes 530 extending from the first surface 512 to the second surface 514 (e.g., through the entire base layer) can be disposed in the base layer 510. Each interposer through electrode 530 can include a conductive plug through the base layer 510 and a conductive barrier film surrounding the conductive plug. The conductive plug can have a column shape, and the conductive barrier film can have a cylindrical shape surrounding the sidewall of the conductive plug. A plurality of via dielectric layers can be between the base layer 510 and the interposer through electrodes 530 to surround the sidewall of the interposer through electrodes 530.

[0018] The redistribution structure 570 can include a redistribution dielectric layer 576 and a plurality of first redistribution pads 572 and a plurality of second redistribution pads 574 on opposite surfaces of the redistribution dielectric layer 576, respectively. The second redistribution pads 574 can be on the first surface 512 of the base layer 510 and electrically connected to the interposer through electrodes 530. In an exemplary embodiment, the second redistribution pads 574 can contact bottom surfaces of the interposer through electrodes 530, respectively. The term "contact" as used herein refers to direct connection (i.e., touching), unless otherwise indicated by context. The interposer through electrodes 530 can electrically connect the second redistribution pads 574 to the pad wiring layer 524. The various pads of the semiconductor chip described herein can be conductive terminals connected to internal wiring of the semiconductor chip and can transmit signals and / or supply voltages between the internal wiring and / or internal circuitry of the semiconductor chip and external sources. The redistribution structure 570 can also include various pads that function as conductive terminals connected to internal wiring of the redistribution structure 570 and can transmit signals and / or supply voltages between the internal wiring and internal circuitry of the semiconductor chip or between the internal wiring and external sources.

[0019] The redistribution structure 570 can also include a plurality of redistribution lines 577 and a plurality of redistribution vias 578 electrically connecting the first redistribution pads 572 to the second redistribution pads 574. Although in the exemplary embodiment of FIG. 5, the redistribution structure 570 includes a single redistribution dielectric layer 576, in other embodiments, the redistribution structure 570 can include a plurality of redistribution dielectric layers. FIG. 1AIn some embodiments, redistribution lines 577 can be arranged on at least one of the opposite surfaces of redistribution dielectric layer 576. In some embodiments, redistribution lines 577 can be connected to at least some of first redistribution pads 572 and can extend at the same vertical level as first redistribution pads 572. In some embodiments, redistribution lines 577 can be connected to at least some of second redistribution pads 574 and can extend at the same vertical level as second redistribution pads 574. Redistribution vias 578 can penetrate at least a portion of redistribution dielectric layer 576. Redistribution vias 578 can connect first redistribution pads 572 to second redistribution pads 574, connect first redistribution pads 572 to redistribution lines 577, connect second redistribution pads 574 to redistribution lines 577, or connect redistribution lines 577 to each other.

[0020] In some embodiments, first redistribution pads 572, second redistribution pads 574, redistribution lines 577, and redistribution vias 578 can include copper, nickel, stainless steel, or a copper alloy such as beryllium copper. In some embodiments, redistribution dielectric layer 576 can include at least one selected from oxides, nitrides, and photo imageable dielectrics (PID). In some embodiments, redistribution dielectric layer 576 can include silicon oxide, silicon nitride, epoxy, or polyimide.

[0021] Interposer protection layer 550, pad wiring layer 524, a plurality of interposer connection terminals 540, and a plurality of wiring protection layers 560 can be arranged on second surface 514 of base layer 510. Pad wiring layer 524 can be on interposer protection layer 550 and connected to interposer through electrodes 530 that penetrate interposer protection layer 550. Interposer connection terminals 540 can be on pad wiring layer 524. Wiring protection layers 560 can surround interposer connection terminals 540 and cover pad wiring layer 524.

[0022] The wiring protection layer 560 can cover a surface of the pad wiring layer 524 on the interposer protection layer 550 that is not covered by the interposer connection terminal 540. In some embodiments, each wiring protection layer 560 can completely cover a surface of a corresponding pad wiring layer 524 that is not covered by a corresponding interposer connection terminal 540. Each wiring protection layer 560 can have a terminal opening 560O that exposes a portion of a top surface of each of the pad wiring layers 524. Each interposer connection terminal 540 can be connected to a corresponding one of the pad wiring layers 524 through the terminal opening 560O. The terminal opening 560O can be filled by a lower portion of an under bump metal (UBM) layer 542. The terminal opening 560O can have a circular shape or an elliptical shape from a top view, but is not limited thereto. The wiring protection layer 560 can cover a portion of a surface of the interposer protection layer 550 that is adjacent to the pad wiring layer 524, but can not cover other portions of the surface of the interposer protection layer 550.

[0023] The interposer protection layer 550 can include an inorganic material, and the wiring protection layer 560 can include an organic material. For example, the interposer protection layer 550 can include silicon oxide, silicon nitride, or a stacked structure of silicon oxide and silicon nitride, and the wiring protection layer 560 can include a polymer material. In some embodiments, the wiring protection layer 560 can be formed of a PIDsuch as polyimide.

[0024] The pad wiring layer 524 can include copper, nickel, stainless steel, or a copper alloy such as beryllium copper. Each interposer connection terminal 540 can include a UBM layer 542 on one of the pad wiring layers 524 and an interposer conductive cap 544 on the UBM layer 542. In some embodiments, the interposer connection terminal 540 can include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin, gold (Au), or solder, but is not limited thereto. Each interposer connection terminal 540 can include a plurality of layers or a single layer.

[0025] Referring to FIG. 1BThe interposer through electrode 530 can protrude vertically outward from the second surface 514 of the base layer 510. For example, the interposer through electrode 530 can extend beyond the second surface 514 of the base layer 510 toward the interposer conductive cap 544. The interposer protective layer 550 can cover the second surface 514 of the base layer 510. The interposer protective layer 550 can surround the side surface of the protrusion of the interposer through electrode 530 that protrudes from the second surface 514 of the base layer 510. In some embodiments, the interposer protective layer 550 can cover the side surface of the portion of the interposer through electrode 530 that protrudes from the second surface 514 of the base layer 510. In some embodiments, the interposer protective layer 550 can completely cover the side surface of the protrusion of the interposer through electrode 530. In some embodiments, the interposer protective layer 550 can contact the side surface of the protrusion of the interposer through electrode 530. In some embodiments, the top surface of the interposer protective layer 550 can be coplanar with the top surface of the protrusion of the interposer through electrode 530 that protrudes from the second surface 514 of the base layer 510.

[0026] The pad wiring layer 524 can be disposed on portions of the top surface of the interposer protective layer 550 and the top surface of the interposer through electrode 530. The bottom surface of the pad wiring layer 524 can be in contact with the top surface of the interposer through electrode 530 and the portions of the top surface of the interposer protective layer 550 adjacent to the interposer through electrode 530. In some embodiments, the bottom surface of the pad wiring layer 524 can be substantially flat. The horizontal width and the horizontal area of the pad wiring layer 524 can be larger than the horizontal width and the horizontal area of the top surface of the interposer through electrode 530, respectively. In some embodiments, the pad wiring layer 524 and the interposer through electrode 530 can be concentric in a top view.

[0027] The wiring protection layer 560 may cover a portion of the top surface and side surfaces of the pad wiring layer 524. The wiring protection layer 560 may also cover a portion of the top surface of the interposer protection layer 550 adjacent to the pad wiring layer 524. In some embodiments, the wiring protection layer 560 may contact the side surface of the pad wiring layer 524, a portion of the top surface of the pad wiring layer 524, and a portion of the top surface of the interposer protection layer 550 adjacent to the pad wiring layer 524. A first thickness T1 of a portion of the wiring protection layer 560 covering a portion of the top surface of the interposer protection layer 550 away from the pad wiring layer 524 may be greater than a second thickness T2 of a portion of the wiring protection layer 560 covering a portion of the top surface of the pad wiring layer 524. For example, the wiring protection layer 560 may include a first portion having the first thickness T1 covering the top surface of the interposer protection layer 550 and a second portion having the second thickness T2 covering the top surface of the pad wiring layer 524. In some example embodiments, the wiring protection layer 560 may include a first portion having a first thickness T1 that contacts the top surface of the interposer protection layer 550 and a second portion having a second thickness T2 that contacts the top surface of the pad wiring layer 524. The pad wiring layer 524 may have a third thickness T3 that is smaller than the first thickness T1 and larger than the second thickness T2. The thickness of the portion of the wiring protection layer 560 that covers the top surface of the interposer protection layer 550 and is proximate to the pad wiring layer 524 may be the sum of the second thickness T2 and the third thickness T3. For example, the wiring protection layer 560 may further include a third portion between the first portion and the second portion. The third portion may cover the side surface of the pad wiring layer 524 with a thickness that is the sum of the second thickness T2 and the third thickness T3. In some embodiments, the third portion may contact the side surface of the pad wiring layer 524 with a thickness that is the sum of the second thickness T2 and the third thickness T3. The fourth thickness T4 of the interposer protection layer 550 may be smaller than the third thickness T3. In some embodiments, the first thickness T1 may be greater than 5 μm, the second thickness T2 may be greater than 3 μm and less than 5 μm, the third thickness T3 may be greater than the second thickness T2 and less than 5 μm, and the fourth thickness T4 may be equal to or less than 3 μm.

[0028] The wiring protection layer 560 may extend horizontally from the side surface of the pad wiring layer 524 to a first width D1. In some embodiments, the wiring protection layer 560 may cover a portion of the top surface of the interposer protection layer 550. The portion of the top surface of the interposer protection layer 550 is adjacent to the pad wiring layer 524 and has a first width D1. The first width D1 may be greater than the third thickness T3 and less than twice the third thickness T3. In some embodiments, the first width D1 may be greater than 5 μm and less than 10 μm. In some embodiments, the first width D1 may be greater than the first thickness T1.

[0029] The interposer protection layer 550 can extend between the wiring protection layer 560 and the base layer 510 and between the pad wiring layer 524 and the base layer 510, and can be in contact with side surfaces of the interposer through electrode 530. A bottom surface of the wiring protection layer 560 and a bottom surface of the pad wiring layer 524 (i.e., a surface of the wiring protection layer 560 facing the base layer 510 and a surface of the pad wiring layer 524 facing the base layer 510) can be coplanar with each other.

[0030] The interposer connection terminal 540 can be on the pad wiring layer 524. A horizontal width and a horizontal area of the interposer connection terminal 540 can be smaller than a horizontal width and a horizontal area of the pad wiring layer 524, respectively. The interposer connection terminal 540 can include a UBM layer 542 on the pad wiring layer 524 and an interposer conductive cap 544 on the UBM layer 542. In some embodiments, the UBM layer 542 can be in contact with the pad wiring layer 524. In some embodiments, the interposer conductive cap 544 can include Ag, tin (Sn), Au, or solder. In some embodiments, the interposer conductive cap 544 can include SnAg.

[0031] The UBM layer 542 can extend to protrude from a top surface of the wiring protection layer 560. The UBM layer 542 can cover a portion of the top surface of the wiring protection layer 560. In some embodiments, a horizontal width and a horizontal area of an upper portion of the UBM layer 542 can be larger than a horizontal width and a horizontal area of a lower portion of the UBM layer 542, respectively. The lower portion of the UBM layer 542 can fill the terminal opening 560O, and the upper portion of the UBM layer 542 can be in contact with the top surface of the wiring protection layer 560. The wiring protection layer 560 can cover side surfaces of the lower portion of the UBM layer 542, but not cover side surfaces of the upper portion of the UBM layer 542 and a top surface of the UBM layer 542. In some embodiments, the wiring protection layer 560 can surround the side surfaces of the lower portion of the UBM layer 542 having a relatively smaller horizontal width and a horizontal area, but not surround the side surfaces of the upper portion of the UBM layer 542 having a relatively larger horizontal width and a horizontal area.

[0032] Referring to FIG. 1A and FIG. 1B Because the interposer 500 includes the wiring protection layer 560 covering the pad wiring layer 524 and surrounding the interposer connection terminal 540, the wiring protection layer 560 can protect the pad wiring layer 524 and absorb stress that can be applied to the interposer connection terminal 540 during formation of the semiconductor package 1 having the interposer 500. FIG. 5A In addition, due to the wiring protection layer 560, an electrical short between adjacent interposer connection terminals 540 can be prevented. Thus, reliability of the semiconductor package 1 can be prevented from deteriorating.

[0033] Furthermore, on the second surface 514 of the base layer 510 of the interposer 500, the wiring protection layer 560 may cover the pad wiring layer 524 and only a portion of the interposer protection layer 550 adjacent to the pad wiring layer 524, but may not cover other portions of the interposer protection layer 550. Therefore, warping of the interposer 500 may be prevented or reduced, compared to when the wiring protection layer 560 including an organic material having a relatively large coefficient of thermal expansion (CTE) completely covers the interposer protection layer 550 on the second surface 514 of the base layer 510.

[0034] When using FIG. 6A The second adhesive layer 22 in FIG. 6A When the second supporting base 12 is attached to the second surface 514 of the base layer 510 of the interposer 500 and then the second supporting base 12 and the second adhesive layer 22 are removed to form a semiconductor package with the interposer 500, the contact area between the second adhesive layer 22 and the wiring protection layer 560 is minimized, thereby preventing part of the second adhesive layer 22 from remaining as residue on the second surface 514 of the base layer 510 of the interposer 500.

[0035] FIGS. 2A-2I is a cross-sectional view of a stage in a method of manufacturing an interposer according to an embodiment.

[0036] Reference FIG. 2A The interposer through-electrode 530 is formed to extend from the first surface 512 of the interposer substrate 510p toward the second surface 514p of the interposer substrate 510p. In some embodiments, the interposer substrate 510p may include a silicon semiconductor substrate.

[0037] The interposer through-electrode 530 may extend from the first surface 512 of the interposer substrate 510p toward the second surface 514p, such that the interposer through-electrode 530 does not completely pass from the first surface 512 of the interposer substrate 510p to the second surface 514p of the interposer through-electrode 530. For example, the interposer through-electrode 530 may be buried inside the interposer substrate 510p.

[0038] Reference FIG. 2B A redistribution structure 570 is formed on the first surface 512 of the interposer substrate 510p. The redistribution structure 570 includes a second redistribution pad 574 on the first surface 512 of the interposer substrate 510p, a redistribution dielectric layer 576 on the first surface 512 of the interposer substrate 510p and covering the second redistribution pad 574, and a first redistribution pad 572 on the redistribution dielectric layer 576. The second redistribution pad 574 may be connected to the interposer through-electrode 530.

[0039] The redistribution structure 570 can also include redistribution lines 577 and redistribution vias 578 electrically connecting the first redistribution pad 572 to the second redistribution pad 574. The redistribution lines 577 can be disposed on a top surface or a bottom surface of the redistribution dielectric layer 576 or inside the redistribution dielectric layer 576. Each redistribution via 578 can penetrate at least a portion of the redistribution dielectric layer 576.

[0040] Referring to FIG. 2C The resulting structure of FIG. 2B is inverted upside down, and the interposer base 510p is attached to the first support base 10 such that the first surface 512 of the interposer base 510p faces the first support base 10. The interposer base 510p can be attached to the first support base 10 with the first adhesive layer 20 between the interposer base 510p and the first support base 10. The first support base 10 can include a semiconductor base, a glass base, a ceramic base, or a plastic base.

[0041] Referring to FIG. 2C and FIG. 2D The interposer base 510p is partially removed to expose the interposer through electrodes 530, thereby forming a bulk layer 510. The bulk layer 510 can be formed by partially removing the interposer base 510p from the second surface 514p, thereby exposing the interposer through electrodes 530. The first surface 512 of the interposer base 510p can be the first surface 512 of the bulk layer 510, and a surface of the interposer base 510p that exposes the interposer through electrodes 530 and is opposite the first surface 512 of the bulk layer 510 can be the second surface 514 of the bulk layer 510.

[0042] The interposer through electrodes 530 can vertically protrude from the second surface 514 of the bulk layer 510. In some embodiments, the interposer through electrodes 530 can include a protrusion having a predetermined thickness. For example, the interposer base 510p can be partially removed by planarization such as chemical mechanical polishing, thereby exposing the interposer through electrodes 530. Thereafter, the interposer base 510p can be selectively removed such that the interposer through electrodes 530 vertically protrude from the bulk layer 510 to have a protrusion.

[0043] Referring to FIG. 2E, an interposer protection layer 550 is formed to cover the second surface 514 of the base layer 510 and expose the top surface of the interposer through-electrode 530. In some embodiments, the interposer protection layer 550 can be formed by forming a preliminary interposer protection layer covering the second surface 514 of the base layer 510 and the interposer through-electrode 530, and partially removing the preliminary interposer protection layer to expose the top surface of the interposer through-electrode 530. The top surface of the interposer protection layer 550 can be coplanar with the top surface of the interposer through-electrode 530 protruding from the second surface 514 of the base layer 510. In some embodiments, the top surface of the interposer protection layer 550 can be coplanar with the top surface of the protruding portion of the interposer through-electrode 530.

[0044] The interposer protective layer 550 may include an inorganic material. In some embodiments, the interposer protective layer 550 may include a stack of at least two different material layers. For example, the interposer protective layer 550 may include a silicon oxide layer on the second surface 514 of the base layer 510 and a silicon nitride layer on the silicon oxide layer. In some embodiments, the silicon oxide layer may be thinner than the silicon nitride layer. For example, the interposer protective layer 550 may have a thickness equal to or less than 3 μm.

[0045] Reference FIG. 2F , a pad wiring layer 524 is formed on the interposer through-electrode 530. The horizontal width and horizontal area of ​​each pad wiring layer 524 may be respectively larger than the horizontal width and horizontal area of ​​the top surface of the corresponding interposer through-electrode 530, so that each pad wiring layer 524 covers the top surface of the corresponding interposer through-electrode and a portion of the top surface of the interposer protection layer 550 adjacent to the corresponding interposer through-electrode 530.

[0046] Reference FIG. 2G , forming a preliminary wiring protection layer 560p to cover the pad wiring layer 524 and the interposer protection layer 550. For example, the preliminary wiring protection layer 560p can be formed by coating. In some embodiments, the preliminary wiring protection layer 560p can include a PID.

[0047] The preliminary wiring protection layer 560p may be formed to have a first thickness T1 (at a position of 0.05mm) on a portion of the interposer protection layer 550 away from the top surface of the pad wiring layer 524. FIG. 1B ) than the second thickness T2 of the portion thereof on the top surface of the pad wiring layer 524 (in FIG. 1B The preliminary wiring protection layer 560p may be formed such that a first thickness T1 of a portion thereof on the top surface of the interposer protection layer 550 away from the pad wiring layer 524 is greater than a third thickness T3 of the pad wiring layer 524 (in FIG. 1BThe second thickness T2 of the portion of the pad wiring layer 524 on which the via protection layer 550 is formed is smaller than the third thickness T3 of the pad wiring layer 524.

[0048] Referring to FIG. 2G and FIG. 2H The wiring protection layer 560 is formed by partially removing the preliminary wiring protection layer 560p, the wiring protection layer 560 exposing a portion of the top surface of the interposer protection layer 550 and a portion of the top surface of each of the pad wiring layers 524. The wiring protection layer 560 can be formed by partially removing the preliminary wiring protection layer 560p by performing exposure and development (i.e., a photolithography process) on the preliminary wiring protection layer 560p.

[0049] The wiring protection layer 560 can expose a portion of the top surface of the interposer protection layer 550 away from each of the pad wiring layers 524 by a width that is not less than the first width D1 (in FIG. 1B The wiring protection layer 560 can cover a portion of the top surface of each of the pad wiring layers 524 near an edge of the corresponding pad wiring layer 524, an entire side surface of the corresponding pad wiring layer 524, and a portion of the top surface of the interposer protection layer 550 away from the corresponding pad wiring layer 524 by the first width D1 (in FIG. 1B The wiring protection layer 560 can cover a portion of the top surface of each of the pad wiring layers 524 near an edge of the corresponding pad wiring layer 524, an entire side surface of the corresponding pad wiring layer 524, and a portion of the top surface of the interposer protection layer 550 away from the corresponding pad wiring layer 524 by the first width D1 (in

[0050] Referring to FIG. 2I The interposer connection terminals 540 each including the UBM layer 542 and the interposer conductive cap 544 are formed. The UBM layer 542 covers a portion (i.e., the central portion) of the top surface of the pad wiring layer 524 that is exposed and not covered by the wiring protection layer 560. The interposer conductive cap 544 covers the top surface of the UBM layer 542. In some embodiments, the UBM layer 542 can be formed by plating (e.g., an electroplating process or an electroless plating process).

[0051] Thereafter, the interposer 500 can be formed by removing the first adhesive layer 20 and the first support substrate 10 from the redistribution structure 570.

[0052] FIGS. 3A-3C is an enlarged sectional view of a portion of the interposer connection terminal portion of the interposer according to an embodiment. In detail, FIGS. 3A-3C is an enlarged sectional view of a portion corresponding to the region IB in FIG. 1A In FIG. 1A and 1B and FIGS. 3A-3C like reference numerals designate like elements, and redundant descriptions can be omitted.

[0053] Referring to FIG. 3A The interposer connection terminal 540a can be on the pad wiring layer 524. The horizontal width and the horizontal area of the interposer connection terminal 540a can be smaller than the horizontal width and the horizontal area of the pad wiring layer 524, respectively. The interposer connection terminal 540a can include a UBM layer 542a on the pad wiring layer 524, an interposer conductive pillar 546a on the UBM layer 542a, and an interposer conductive cap 544a on the interposer conductive pillar 546a.

[0054] The UBM layer 542a can extend to protrude from a top surface of the wiring protection layer 560. The UBM layer 542a can cover a portion of the top surface of the wiring protection layer 560. In some embodiments, the horizontal width and the horizontal area of the upper portion of the UBM layer 542a can be larger than the horizontal width and the horizontal area of the lower portion of the UBM layer 542a, respectively. In some embodiments, the UBM layer 542a can contact the pad wiring layer 524, the side surface of the wiring protection layer 560, and the top surface of the wiring protection layer 560.

[0055] The interposer conductive pillar 546a can be between the UBM layer 542a and the interposer conductive cap 544a. The interposer conductive pillar 546a can include copper, nickel, stainless steel, or a copper alloy such as beryllium copper. The horizontal width and the horizontal area of the interposer conductive pillar 546a can be substantially the same as the horizontal width and the horizontal area of the upper portion of the UBM layer 542a, respectively. As used herein, terms such as "same," "equal," "planar," or "coplanar" when referring to orientation, layout, position, shape, size, composition, amount, or other measurement do not necessarily mean a perfectly identical orientation, layout, position, shape, size, composition, amount, or other measurement, but are intended to include an almost identical orientation, layout, position, shape, size, composition, amount, or other measurement within acceptable variations that can occur, for example, due to manufacturing processes. The term "substantially" can be used herein to emphasize this meaning, unless the context or other statement indicates otherwise. For example, an item described as "substantially the same" can be perfectly identical, perfectly equal, or perfectly planar, or can be identical within acceptable variations that can occur, for example, due to manufacturing processes.

[0056] Referring to FIG. 3B The interposer connection terminal 540a can include a UBM layer 542a on the pad wiring layer 524, an interposer conductive pillar 546a on the UBM layer 542a, and an interposer conductive cap 544a on the interposer conductive pillar 546a.

[0057] The wire protection layer 560a can cover portions of the top surface of the pad wire layer 524 and the side surface of the pad wire layer 524. The wire protection layer 560a can also cover the side surface of the UBM layer 542a and the lower portions of the side surface of the interposer conductive pillar 546a. The top end (e.g., the top surface) of the wire protection layer 560a can be located at a lower vertical level than the top surface of the interposer conductive pillar 546a. In some embodiments, the top end of the wire protection layer 560a can be connected to the side surface of the interposer conductive pillar 546a. The wire protection layer 560a can also cover portions of the top surface of the interposer protection layer 550 that are near the pad wire layer 524. The wire protection layer 560a can horizontally extend a first width D1 from the side surface of the pad wire layer 524. In some embodiments, the wire protection layer 560a can contact portions of the top surface of the pad wire layer 524, the side surface of the pad wire layer 524, the side surface of the UBM layer 542a, and the lower portions of the side surface of the interposer conductive pillar 546a. The wire protection layer 560a can also contact portions of the top surface of the interposer protection layer 550 that are near the pad wire layer 524.

[0058] Referring to FIG. 3C , the interposer connection terminal 540a can include the UBM layer 542a on the pad wire layer 524, the interposer conductive pillar 546a on the UBM layer 542a, and the interposer conductive cap 544a on the interposer conductive pillar 546a.

[0059] The wire protection layer 560b can cover portions of the top surface of the pad wire layer 524 and the side surface of the pad wire layer 524. The wire protection layer 560b can cover the side surface of the UBM layer 542a and the side surface of the interposer conductive pillar 546a. The top end of the wire protection layer 560b can be substantially at the same vertical level as the top surface of the interposer conductive pillar 546a. The wire protection layer 560b can also cover portions of the top surface of the interposer protection layer 550 that are near the pad wire layer 524. The wire protection layer 560b can horizontally extend the first width D1 from the side surface of the pad wire layer 524.

[0060] FIGS. 4A-4C is a plan view illustrating a shape of a buffer protection layer of an interposer according to an embodiment. In FIG. 1A and 1B and FIGS. 4A-4C , like numerals refer to like elements throughout, and redundant descriptions can be omitted.

[0061] Referring to FIG. 4A , a plurality of pad wire layers 524 can be arranged on the interposer protection layer 550. Each pad wire layer 524 can have a quadrilateral shape, such as a rectangular shape and a square shape, as viewed from a top view. The pad wire layers 524 can be separated from each other. In some embodiments, the pad wire layers 524 can be arranged in a matrix of rows and columns.

[0062] Each of the plurality of wiring protection layers 560 can cover a portion of a top surface of a corresponding one of the pad wiring layers 524 and a portion of the top surface of the interposer protection layer 550 adjacent to the corresponding one of the pad wiring layers 524. Each of the wiring protection layers 560 can have a terminal opening 560O exposing the portion of the top surface of the corresponding one of the pad wiring layers 524. The terminal opening 560O can have a circular shape or an elliptical shape, but is not limited thereto, from a top view. The interposer connection terminal 540 FIG. 1A ) can be connected to the pad wiring layer 524 through the terminal opening 560O. The terminal opening 560O can be filled with FIG. 1B a lower portion of the UBM layer 542 in the interposer connection terminal 540, FIG. 3A a lower portion of the UBM layer 542a in the interposer connection terminal 540a, FIG. 3B the UBM layer 542a and a lower portion of the interposer conductive pillar 546a in the interposer connection terminal 540a, or FIG. 3C the UBM layer 542a and the interposer conductive pillar 546a in the interposer connection terminal 540a.

[0063] According to a top view, an area defined by an edge of each of the wiring protection layers 560 can be larger than an area of each of the pad wiring layers 524. The edge of each of the wiring protection layers 560 can have a quadrilateral shape, such as a rectangular shape and a square shape, from a top view. The wiring protection layers 560 can be separated from each other. In some embodiments, the wiring protection layers 560 can be arranged in a matrix of rows and columns.

[0064] Referring to FIG. 4B , a plurality of pad wiring layers 524a can be arranged on the interposer protection layer 550. The pad wiring layer 524a can include a plurality of pads 524aP and at least one connection line 524aL. A plurality of interposer connection terminals 540 (in FIG. 1B ) or 540a (in FIGS. 3A-3C ) can be on the pads 524aP. The connection line 524aL can extend from at least one of the pads 524aP to another pad adjacent to the at least one pad along a top surface of the interposer protection layer 550.

[0065] The pads 524aP can have a rectangular shape or a square shape, from a top view. Some of the pads 524aP can be separated from each other. Some of the pads 524aP can be connected to each other by the connection line 524aL. One connection line 524aL and two pads 524aP connected to each other by the connection line 524aL can be integrally formed.

[0066] Each of the plurality of wiring protection layers 560c can cover a portion of a top surface of one of the pad wiring layers 524a and a portion of the top surface of the interposer protection layer 550 adjacent to the one of the pad wiring layers 524a.

[0067] The wiring protection layers 560c can include a plurality of pad protection layers 560cP and at least one wire protection layer 560cL. Each pad protection layer 560cP can cover one of the pads 524aP and a portion of the top surface of the interposer protection layer 550 adjacent to the one of the pads 524aP. Each pad protection layer 560cP can have a terminal opening 560cO exposing a portion of a top surface of one of the pads 524aP. The wire protection layer 560cL can cover the connection wire 524aL and a portion of the top surface of the interposer protection layer 550 adjacent to the connection wire 524aL. The wiring protection layers 560c can partially expose the top surface of the pad wiring layers 524a and can fully cover the top surface of the connection wire 524aL.

[0068] In an example embodiment, some of the plurality of pad wiring layers 524a can include a pad wiring layer having a first pad, a second pad, and a connection wire 524aL. The first pad can have the interposer connection terminal 540 disposed thereon (see also FIG. 1B and FIGS. 3A-3B ). The second pad can have another interposer connection terminal disposed thereon and adjacent to the interposer connection terminal. The connection wire 524aL can extend from the first pad to the second pad along a top surface of the interposer protection layer 550. The wiring protection layer 560c can cover a top surface of the connection wire 524aL and a side surface of the connection wire 524aL. In an example embodiment, the wiring protection layer 560c can fully cover the top surface of the connection wire 524aL and the side surface of the connection wire 524aL.

[0069] Referring to FIG. 4C , a plurality of pad wiring layers 524b can be disposed on the interposer protection layer 550. The pad wiring layers 524b can include a plurality of pads 524bP, a plurality of through-electrode connections 524bC, and a plurality of connection wires 524bL connecting the pads 524bP to the through-electrode connections 524bC. A plurality of interposer connection terminals 540 (in FIG. 1B ) or 540a (in FIGS. 3A-3CThe pads 524bP can be on the dielectric layer 524bP. The pads 524bP can have a quadrilateral shape, such as a rectangular shape and a square shape, as viewed from the top. The through-electrode connectors 524bC can be disposed on the dielectric layer through-electrodes 530 to be electrically connected to the dielectric layer through-electrodes 530. The connection lines 524bL can extend from the pads 524bP to the through-electrode connectors 524bC along the top surface of the dielectric layer protection layer 550. One pad 524bP and one through-electrode connector 524bC can be connected to each other by one connection line 524bL. In some embodiments, the pads 524bP, the through-electrode connectors 524bC, and the connection lines 524bL can be integrally formed.

[0070] The plurality of wiring protection layers 560d can include a plurality of pad protection layers 560dP, a plurality of connector protection layers 560dC, and a plurality of line protection layers 560dL. Each pad protection layer 560dP can cover one of the pads 524bP and a portion of the top surface of the dielectric layer protection layer 550 adjacent to the one of the pads 524bP. Each pad protection layer 560dP can have a terminal opening 560dO exposing a portion of the top surface of one pad 524bP. Each connector protection layer 560dC can cover one of the through-electrode connectors 524bC and a portion of the top surface of the dielectric layer protection layer 550 adjacent to the one of the through-electrode connectors 524bC. Each line protection layer 560dL can cover one of the connection lines 524bL and a portion of the top surface of the dielectric layer protection layer 550 adjacent to the one of the connection lines 524bL. The wiring protection layers 560d can partially expose the top surface of the pad wiring layer 524b and can completely cover the top surface of the connection lines 524bL and the top surface of the through-electrode connectors 524bC.

[0071] In an exemplary embodiment, the plurality of pad wiring layers 524b can include a pad wiring layer having the pads 524bP, the through-electrode connectors 524bC, and the connection lines 524bL. The pads 524bP can have the dielectric layer connection terminals 540 disposed thereon, and the through-electrode connectors 524bC can have the dielectric layer through-electrodes 530 disposed thereunder (see also FIG. 1B and FIGS. 3A-3BThe connection line 524bL can extend along a top surface of the interposer passivation layer 550 and connect the pad 524bP to the through-electrode connection 524bC. The interposer connection terminal 540 can not vertically overlap the interposer through-electrode 530. The wiring passivation layer 560d can cover a top surface of the connection line 524bL and side surfaces of the connection line 524bL as well as a top surface of the through-electrode connection 524bC and side surfaces of the through-electrode connection 524bC. In an exemplary embodiment, the wiring passivation layer 560d can completely cover the top surface of the connection line 524bL and the side surfaces of the connection line 524bL as well as the top surface of the through-electrode connection 524bC and the side surfaces of the through-electrode connection 524bC.

[0072] FIG. 5A is a cross-sectional view of a semiconductor package 1 having an interposer 500 according to an embodiment. FIG. 5B is a cross-sectional view of a first semiconductor chip 1000 included in a semiconductor package 1 having an interposer 500 according to an embodiment.

[0073] Referring to FIG. 5A and FIG. 5B , the semiconductor package 1 can include a package substrate base 600 on which the interposer 500 is mounted and at least one first semiconductor chip 1000 and a second semiconductor chip 400 attached to the interposer 500. The first semiconductor chip 1000 and the second semiconductor chip 400 can be horizontally separated from each other on the redistribution structure 570 of the interposer 500. As used herein, a semiconductor package can include a package substrate (or referred to as a package substrate base), one or more semiconductor chips (or semiconductor dies) stacked on the package substrate, and an encapsulant formed on the package substrate and covering the semiconductor chips. The semiconductor package can also include a redistribution structure.

[0074] The first semiconductor chip 1000 can be electrically connected to the interposer 500 by a plurality of first connection terminals 140. The second semiconductor chip 400 can be electrically connected to the interposer 500 by a plurality of second connection terminals 440. The first semiconductor chip 1000 can include a plurality of first top connection pads 122. The second semiconductor chip 400 can include a plurality of second top connection pads 420. The interposer 500 can include a plurality of first redistribution pads 572. The first connection terminals 140 can be between the first top connection pads 122 and some of the first redistribution pads 572. The second connection terminals 440 can be between the second top connection pads 420 and others of the first redistribution pads 572.

[0075] Each first connection terminal 140 can include a first conductive pillar 142 on the first top connection pad 122 and a first conductive cap 144 on the first conductive pillar 142. Each second connection terminal 440 can include a second conductive pillar 442 on the second top connection pad 420 and a second conductive cap 444 on the second conductive pillar 442.

[0076] The first semiconductor chip 1000 includes the first sub-semiconductor chip 100 and the plurality of second sub-semiconductor chips 200. Although in FIG. 5B In the embodiment, the first semiconductor chip 1000 includes four second sub-semiconductor chips 200, but embodiments are not limited thereto. For example, the first semiconductor chip 1000 can include at least two second sub-semiconductor chips 200. In some embodiments, the number of the plurality of second sub-semiconductor chips 200 included in the first semiconductor chip 1000 can be a multiple of four. In some embodiments, the number of the plurality of second sub-semiconductor chips 200 can be any number greater than four. The second sub-semiconductor chips 200 can be sequentially stacked on the first sub-semiconductor chip 100 in a vertical direction. When the first sub-semiconductor chip 100 and the second sub-semiconductor chips 200 are sequentially stacked, the active side of each of the first sub-semiconductor chip 100 and the second sub-semiconductor chips 200 can face downward. In an exemplary embodiment, active components such as transistors and memories can be formed near the active side.

[0077] The first sub-semiconductor chip 100 can include a first semiconductor base 110 having first semiconductor devices 112 (e.g., transistors or memories) on an active side, a first top connection pad 122 and a first bottom connection pad 124 on the active side and a non-active side of the first semiconductor base 110, respectively, a first through electrode 130 passing through at least a portion of the first semiconductor base 110 and electrically connecting the first top connection pad 122 to the first bottom connection pad 124, and a first protective insulating layer 150 exposing at least a portion of the first top connection pad 122 and covering the active side of the first semiconductor base 110.

[0078] The first semiconductor base 110 can include, for example, a semiconductor material such as silicon (Si). Alternatively, the first semiconductor base 110 can include a semiconductor material, for example, germanium (Ge) or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). The first semiconductor base 110 can include conductive regions, for example, impurity-doped wells. The first semiconductor base 110 can have various isolation structures including a shallow trench isolation (STI) structure.

[0079] In the present specification, the top surface and the bottom surface of a semiconductor substrate (e.g., the first semiconductor substrate 110) refer to the active side and the non-active side of the semiconductor substrate, respectively. For example, even when the active side of the semiconductor substrate is located below the non-active side in a final product, in the present specification, the active side of the semiconductor substrate is referred to as the top surface, and the non-active side of the semiconductor substrate is referred to as the bottom surface. The term "top" can be used for an element (e.g., a transistor or a memory) located on the active side of the semiconductor substrate, and the term "bottom" can be used for an element located on the non-active side of the semiconductor substrate.

[0080] The first semiconductor device 112 including various kinds of individual devices can be formed on the active side of the first semiconductor substrate 110. The individual devices can include various microelectronic devices, for example, a metal oxide semiconductor field effect transistor (MOSFET) (such as a complementary metal oxide semiconductor (CMOS) transistor), a system large scale integrated circuit (LSI), an image sensor (such as a CMOS image sensor (CIS)), a micro electro mechanical system (MEMS), an active element, and a passive element. The individual devices can be electrically connected to the conductive region of the first semiconductor substrate 110. The first semiconductor device 112 can further include a conductive wiring or a plug electrically connecting the individual devices or at least two individual devices to the conductive region of the first semiconductor substrate 110. Each individual device can be electrically isolated from other individual devices by a dielectric film.

[0081] For example, the first sub-semiconductor chip 100 can include a dynamic random access memory (DRAM) chip, a static RAM (SRAM) chip, a flash memory chip, an electrically erasable programmable ROM (EEPROM) chip, a phase change RAM (PRAM) chip, a magnetic RAM (MRAM) chip, or a resistive RAM (RRAM) chip. For example, the first sub-semiconductor chip 100 can include a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, or an application processor (AP) chip.

[0082] In some embodiments, the first semiconductor chip 1000 can be a high bandwidth memory (HBM) DRAM including the first sub-semiconductor chip 100 as a master chip and the second sub-semiconductor chip 200 as a slave chip. In some embodiments, the first sub-semiconductor chip 100 can include a buffer chip including a serial-to-parallel conversion circuit and / or a parallel-to-serial conversion circuit. In some embodiments, the first sub-semiconductor chip 100 can include a buffer chip for controlling a slave chip in an HBM DRAM. When the first sub-semiconductor chip 100 includes a buffer chip for controlling an HBM DRAM semiconductor chip, the first sub-semiconductor chip 100 can be referred to as a master chip, and the second sub-semiconductor chip 200 can be referred to as a slave chip.

[0083] Although the first top connection pad 122 is buried in the first semiconductor base 110 in FIG. 5B Embodiments are not limited thereto. In some embodiments, the first top connection pad 122 can protrude from a top surface of the first semiconductor base 110.

[0084] In this specification, the first semiconductor base 110 can include a base substrate including a semiconductor material, various conductive material layers and insulating material layers formed on the base substrate to form the first semiconductor device 112, a wiring pattern electrically connected to the first semiconductor device 112, and a wiring via. In some embodiments, the first semiconductor base 110 refers to an object including a semiconductor material as a main component, rather than an object formed only of a semiconductor material.

[0085] Each of the second sub-semiconductor chips 200 includes a second semiconductor base 210 having a second semiconductor device 212 (e.g., a transistor or a memory) on an active side, an internal top connection pad 222 and an internal bottom connection pad 224 on the active side and a non-active side of the second semiconductor base 210, respectively, a second through electrode 230 passing through at least a portion of the second semiconductor base 210 and electrically connecting the internal top connection pad 222 to the internal bottom connection pad 224, and a second protective insulating layer 250 exposing at least a portion of the internal top connection pad 222 and covering the active side of the second semiconductor base 210. The second protective insulating layer 250 can include an inorganic material such as an oxide or a nitride. For example, the second protective insulating layer 250 can include at least one selected from silicon oxide and silicon nitride. In some embodiments, the second protective insulating layer 250 can include silicon nitride.

[0086] The second semiconductor base 210, the internal top connection pad 222, the internal bottom connection pad 224, and the second through electrode 230 are substantially the same as the first semiconductor base 110, the first top connection pad 122, the first bottom connection pad 124, and the first through electrode 130, respectively, and thus detailed descriptions thereof will be omitted.

[0087] For example, the second sub-semiconductor chip 200 can include a DRAM chip, an SRAM chip, a flash memory chip, an EEPROM chip, a PRAM chip, an MRAM chip, or an RRAM chip. In some embodiments, the second sub-semiconductor chip 200 can include an HBMDRAM semiconductor chip. The first sub-semiconductor chip 100 can be referred to as a master chip, and the second sub-semiconductor chip 200 can be referred to as a slave chip.

[0088] The internal connection terminal 240 can be attached to the internal bottom connection pad 224 of each of the second sub-semiconductor chips 200. The internal connection terminal 240 can be electrically connected to the first bottom connection pad 124 of the first sub-semiconductor chip 100 via the internal top connection pad 222 of the second sub-semiconductor chip 200, the internal bottom connection pad 224 of the second sub-semiconductor chip 200, and the second through electrode 230.

[0089] The internal connection terminal 240 can include an internal conductive pillar 242 on the internal top connection pad 222 and an internal conductive cap 244 on the internal conductive pillar 242.

[0090] The insulating adhesive layer 350 can be between two adjacent chips among the first sub-semiconductor chip 100 and the second sub-semiconductor chips 200. The insulating adhesive layer 350 can include a non-conductive film (NCF), a non-conductive paste (NCP), an insulating polymer, or an epoxy resin. The insulating adhesive layer 350 can surround the internal connection terminal 240 and can be filled between the first sub-semiconductor chip 100 and the second sub-semiconductor chip 200 adjacent thereto or between two adjacent second sub-semiconductor chips 200.

[0091] In some embodiments, among the second sub-semiconductor chips 200, the second sub-semiconductor chip 200 on the top farthest from the first sub-semiconductor chip 100 can not include the internal bottom connection pad 224 and the second through electrode 230. In some embodiments, among the second sub-semiconductor chips 200, the second sub-semiconductor chip 200 on the top farthest from the first sub-semiconductor chip 100 can be thicker than the other second sub-semiconductor chips 200. The present application is not limited thereto. In some embodiments, the second sub-semiconductor chips 200 can have the same thickness. In some embodiments, the second sub-semiconductor chips 200 can include the same kind of semiconductor chips.

[0092] The horizontal width and the horizontal area of the first sub-semiconductor chip 100 can be greater than the horizontal width and the horizontal area of each of the second sub-semiconductor chips 200, respectively. The first semiconductor chip can further include a molding layer 300 on the first sub-semiconductor chip 100 to surround the side surface of the second sub-semiconductor chips 200 and the side surface of the insulating adhesive layer 350. For example, the molding layer 300 can include an epoxy molding compound (EMC).

[0093] Referring to FIG. 5AThe second semiconductor chip 400 can include a third semiconductor base 410, a second top connection pad 420, a third protective insulating layer 450, and a second connection terminal 440. The second connection terminal 440 can include a second conductive pillar 442 on the second top connection pad 420 and a second conductive cap 444 on the second conductive pillar 442. The third semiconductor base 410, the second top connection pad 420, the third protective insulating layer 450, and the second connection terminal 440 can be substantially similar to the first semiconductor base 110, the first top connection pad 122, the first protective insulating layer 150, and the first connection terminal 140, respectively, or substantially similar to the second semiconductor base 120, the inner top connection pad 222, the second protective insulating layer 250, and the inner connection terminal 240, respectively, and thus, detailed descriptions thereof will be omitted.

[0094] For example, the second semiconductor chip 400 can include a CPU chip, a GPU chip, or an AP chip.

[0095] The interposer 500 can include a base layer 510, a redistribution structure 570 on a first surface 512 of the base layer 510, and a pad wiring layer 524 on a second surface 514 of the base layer 510. The redistribution structure 570 can include a redistribution dielectric layer 576 and a first redistribution pad 572 and a second redistribution pad 574 on opposite surfaces of the redistribution dielectric layer 576, respectively. Thus, the first redistribution pad 572 can be on a top surface of the interposer 500, and the pad wiring layer 524 can be on a bottom surface of the interposer 500. Because the interposer 500 has been described in detail with reference to FIGS. 1 to 4, redundant descriptions of the interposer 500 will be omitted. FIGS. 1A-4C Because the interposer 500 has been described in detail with reference to FIGS. 1 to 4, redundant descriptions of the interposer 500 will be omitted.

[0096] The first underfill layer 380 can be between the first semiconductor chip 1000 and the interposer 500. The second underfill layer 480 can be between the second semiconductor chip 400 and the interposer 500. The first underfill layer 380 can surround the first connection terminal 140, and the second underfill layer 480 can surround the second connection terminal 440.

[0097] The semiconductor package 1 can further include a package molding layer 800 on the interposer 500 to surround side surfaces of the first semiconductor chip 1000 and the second semiconductor chip 400. For example, the package molding layer 800 can include an EMC.

[0098] In some embodiments, the package molding layer 800 can cover the top surface of the interposer 500 and the side surfaces of each of the first semiconductor chip 1000 and the second semiconductor chip 400, without covering the top surfaces of each of the first semiconductor chip 1000 and the second semiconductor chip 400. In this case, the semiconductor package 1 can further include a heat dissipation unit 950 covering the top surfaces of the first semiconductor chip 1000 and the second semiconductor chip 400. The heat dissipation unit 950 can include a heat spreader or a heat sink. In some embodiments, the heat dissipation unit 950 can be on the top surface of the package substrate base 600 and surround the first semiconductor chip 1000, the second semiconductor chip 400, and the interposer 500.

[0099] The semiconductor package 1 can further include a thermal interface material (TIM) 900 between each of the first semiconductor chip 1000 and the second semiconductor chip 400 and the heat dissipation unit 950 to increase thermal coupling between each of the first semiconductor chip 1000 and the second semiconductor chip 400 and the heat dissipation unit 950. The TIM 900 can include a thermal paste or a thermal film (or a thermal tape).

[0100] The interposer connection terminals 540 can be attached to the pad wiring layers 524, respectively. The interposer connection terminals 540 can electrically connect the interposer 500 to the package substrate base 600. A board underfill layer 580 can be between the interposer 500 and the package substrate base 600. The board underfill layer 580 can surround the interposer connection terminals 540.

[0101] The package substrate base 600 can include a substrate board layer 610, a board top pad 622 on a top surface of the substrate board layer 610, and a board bottom pad 624 on a bottom surface of the substrate board layer 610. In some embodiments, the package substrate base 600 can include a printed circuit board (PCB). For example, the package substrate base 600 can include a multi-layer PCB. The substrate board layer 610 can include at least one material selected from phenol formaldehyde resin, epoxy resin, and polyimide.

[0102] A solder resist layer (not shown) can be formed on each of the top and bottom surfaces of the substrate board layer 610 and can expose the board top pad 622 and the board bottom pad 624. The interposer connection terminals 540 can be connected to the board top pad 622, and the package connection terminals 640 can be connected to the board bottom pad 624. The interposer connection terminals 540 can electrically connect the pad wiring layers 524 to the board top pad 622. The package connection terminals 640 connected to the board bottom pad 624 can connect the semiconductor package 1 to the outside.

[0103] In some embodiments, the heat dissipation unit 950 can also perform an electromagnetic wave shielding function, and can be connected to at least one ground plate top pad 622 among the plurality of plate top pads 622 of the package base substrate 600.

[0104] According to an embodiment, the wiring protection layer 560 of the interposer 500 covers the pad wiring layer 524 and surrounds the interposer connection terminals 540 in the semiconductor package 1, and thus the wiring protection layer 560 can protect the pad wiring layer 524 and absorb stress that can be applied to the interposer connection terminals 540 in the semiconductor package 1. In addition, the wiring protection layer 560 can prevent electrical shorting between adjacent interposer connection terminals 540. Thus, reliability degradation of the semiconductor package 1 can be prevented.

[0105] In addition, on the second surface 514 of the base layer 510 of the interposer 500, the wiring protection layer 560 can cover the pad wiring layer 524, and can cover only a portion of the interposer protection layer 550 adjacent to the pad wiring layer 524 without covering other portions of the interposer protection layer 550. Thus, compared to when the interposer protection layer 550 including the wiring protection layer 560 having a relatively large CTE is completely covered on the second surface 514 of the base layer 510, warping of the interposer 500 can be prevented or reduced.

[0106] FIG. 6A and FIG. 6B is a cross-sectional view of a stage in a method of manufacturing a semiconductor package having an interposer according to an embodiment.

[0107] Referring to FIG. 6A The interposer 500 is attached to the second support substrate 12 so that the plurality of interposer connection terminals 540 of the interposer 500 face the second support substrate 12. The interposer 500 can be attached to the second support substrate 12 using a second adhesive layer 22 between the interposer 500 and the second support substrate 12. The second support substrate 12 can include a semiconductor substrate, a glass substrate, a ceramic substrate, or a plastic substrate.

[0108] Thereafter, at least one first semiconductor chip 1000 and a second semiconductor chip 400 are mounted on the interposer 500. The first semiconductor chip 1000 can be connected to the interposer 500 through the first connection terminals 140 between the first top connection pads 122 and some of the first redistribution pads 572. The second semiconductor chip 400 can be connected to the interposer 500 through the second connection terminals 440 between the second top connection pads 420 and others of the first redistribution pads 572.

[0109] A first underfill layer 380 surrounding the first connection terminals 140 may be between the first semiconductor chip 1000 and the interposer 500 , and a second underfill layer 480 surrounding the second connection terminals 440 may be between the second semiconductor chip 400 and the interposer 500 .

[0110] Reference FIG. 6B , a package mold layer 800 may be formed on the interposer 500 to surround side surfaces of the first and second semiconductor chips 1000 and 400. For example, the package mold layer 800 may include EMC.

[0111] In some embodiments, the package mold layer 800 may be formed to cover the top surface of the interposer 500 and the side surfaces of each of the first and second semiconductor chips 1000 and 400, without covering the top surface of each of the first and second semiconductor chips 1000 and 400. The TIM 900 may be attached to the top surface of the first and second semiconductor chips 1000 and 400, and the top surface of the package mold layer 800.

[0112] Afterwards, if FIG. 5A As shown in FIG, the second adhesive layer 22 and the second supporting substrate 12 are removed from the interposer 500, and the interposer 500 having the first semiconductor chip 1000 and the second semiconductor chip 400 mounted thereon is mounted on the package base substrate 600. The interposer 500 can be connected to the package base substrate 600 via the interposer connection terminals 540 between the pad wiring layer 524 and the board top pad 622.

[0113] The semiconductor package 1 may be formed by attaching the heat dissipation unit 950 to the top surface of the package base substrate 600 such that the heat dissipation unit 950 surrounds the first semiconductor chip 1000 , the second semiconductor chip 400 , and the interposer 500 and contacts the TIM 900 .

[0114] On the second surface 514 of the base layer 510 of the interposer 500 in the semiconductor package 1, the wiring protection layer 560 may cover the pad wiring layer 524 and only a portion of the interposer protection layer 550 adjacent to the pad wiring layer 524, without covering other portions of the interposer protection layer 550. Therefore, when the second adhesive layer 22 and the second supporting substrate 12 are attached to the interposer 500 and then removed from the interposer 500, the contact area between the second adhesive layer 22 and the wiring protection layer 560 is minimized, thereby preventing a portion of the second adhesive layer 22 from remaining as residue on the second surface 514 of the base layer 510 of the interposer 500.

[0115] While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details can be made therein without departing from the spirit and scope of the claims.

Claims

1. An interposer, the interposer comprising: a base layer having a first surface and a second surface opposite the first surface; a redistribution structure on the first surface of the base layer; an interposer passivation layer on the second surface of the base layer; a pad wiring layer on the interposer passivation layer; an interposer through electrode passing through the base layer and the interposer passivation layer and electrically connecting the redistribution structure to the pad wiring layer; an interposer connection terminal attached to the pad wiring layer; and a wiring passivation layer including a first portion covering a portion of the interposer passivation layer adjacent to the pad wiring layer, a second portion covering a portion of a top surface of the pad wiring layer, and a third portion covering a side surface of the pad wiring layer, wherein the third portion is disposed between the first portion and the second portion, and wherein the first portion, the second portion, and the third portion have different thicknesses from each other in a vertical direction with respect to the first surface of the base layer, wherein the wiring passivation layer covers the pad wiring layer and only a portion of the interposer passivation layer adjacent to the pad wiring layer, and does not cover other portions of the interposer passivation layer.

2. The interposer of claim 1, the interposer through electrode includes a protrusion vertically extending beyond the second surface of the base layer toward the interposer connection terminal. wherein 3. The interposer of claim 2, the interposer passivation layer is disposed between the base layer and the pad wiring layer and around a side surface of the protrusion. wherein 4. The interposer of claim 2, a top surface of the interposer passivation layer is coplanar with a top surface of the protrusion. wherein 5. The interposer of claim 1, a first thickness of the first portion is greater than a second thickness of the second portion. wherein 6. The interposer of claim 5, a third thickness of the third portion is greater than the first thickness. wherein, 7. The interposer of claim 6, the wiring passivation layer horizontally extends from the side surface of the pad wiring layer and covers the portion of the interposer passivation layer from the side surface of the pad wiring layer in a horizontal direction with respect to the first surface of the base layer with a first width, and wherein the first width is greater than a thickness of the pad wiring layer and less than twice the thickness of the pad wiring layer.

8. The interposer of claim 1, the interposer connection terminal includes an under bump metal layer and an interposer conductive cap on the under bump metal layer, and wherein, wherein the under bump metal layer extends from a top surface of the pad wiring layer and protrudes above a top surface of the wiring passivation layer, and wherein the wiring passivation layer further includes a fourth portion at least partially covering a side surface of the under bump metal layer.

9. The interposer of claim 8, the interposer connection terminal further includes an interposer conductive pillar between the interposer conductive cap and the under bump metal layer, and wherein wherein a top surface of the wiring passivation layer is at a lower vertical level than a top surface of the interposer conductive pillar.

10. The interposer of claim 8, the interposer connection terminal further includes an interposer conductive pillar between the interposer conductive cap and the under bump metal layer, and wherein wherein the wiring passivation layer covers a side surface of the interposer conductive pillar.

11. The interposer of any one of claims 1 to 10, ​ wherein The pad wiring layer includes a first pad, a second pad, and a connection line, the interposer connection terminal is arranged on the first pad, another interposer connection terminal is arranged on the second pad, and the connection line extends from the first pad to the second pad along a top surface of the interposer protection layer, and wherein the wiring protection layer completely covers a top surface of the connection line and a side surface of the connection line.

12. The interposer of any one of claims 1 to 10, wherein The pad wiring layer includes a pad, a through-electrode connection, and a connection line, the interposer connection terminal is arranged on the pad, the interposer through-electrode is arranged on the through-electrode connection, and the connection line extends along a top surface of the interposer protection layer and connects the pad to the through-electrode connection, wherein the interposer connection terminal is not vertically stacked with the interposer through-electrode, and wherein the wiring protection layer completely covers a top surface of the connection line and a side surface of the connection line and a top surface of the through-electrode connection and a side surface of the through-electrode connection.

13. A semiconductor package, the semiconductor package comprising: an interposer including: a base layer having a first surface and a second surface opposite to the first surface; a redistribution structure on the first surface of the base layer; an interposer protection layer on the second surface of the base layer; a plurality of pad wiring layers on the interposer protection layer; a plurality of interposer through-electrodes through the base layer and the interposer protection layer and electrically connecting the redistribution structure to the plurality of pad wiring layers; a plurality of interposer connection terminals attached to the plurality of pad wiring layers; and a plurality of wiring protection layers on the interposer protection layer, wherein the plurality of interposer through-electrodes are grouped into a plurality of interposer through-electrode groups, wherein each of the plurality of wiring protection layers includes a first portion covering a respective portion of the interposer protection layer adjacent to a respective pad wiring layer, a second portion covering a portion of a top surface of the respective pad wiring layer, a third portion covering a side surface of the respective pad wiring layer, and a fourth portion covering a lower portion of the respective interposer connection terminal, wherein the third portion is disposed between the first portion and the second portion, and wherein the second portion is disposed between the third portion and the fourth portion; first and second semiconductor chips horizontally separated from each other on the redistribution structure and electrically connected to a first one of the plurality of interposer through-electrode groups and a second one of the plurality of interposer through-electrode groups, respectively, through the redistribution structure; and a package base substrate on which the interposer is mounted and to which the plurality of interposer connection terminals are connected, wherein the plurality of wiring protection layers cover the plurality of pad wiring layers and only portions of the interposer protection layer adjacent to the plurality of pad wiring layers, without covering other portions of the interposer protection layer.

14. The semiconductor package of claim 13, wherein the redistribution structure includes: a redistribution dielectric layer; a plurality of first redistribution pads on a surface of a redistribution dielectric layer, wherein the surface of the redistribution dielectric layer is spaced apart from the second surface of the base layer, and the plurality of first redistribution pads are grouped into a plurality of first redistribution pad groups; and a plurality of second redistribution pads on the first surface of the base layer, wherein the plurality of second redistribution pads are connected to the plurality of via electrodes and electrically connected to the plurality of first redistribution pads, wherein the first semiconductor chip is connected to a first group among the plurality of first redistribution pad groups through a plurality of first connection terminals, and wherein the second semiconductor chip is connected to a second group among the plurality of first redistribution pad groups through a plurality of second connection terminals.

15. The semiconductor package of claim 13, wherein, a via protection layer disposed between the base layer and each of the plurality of pad wiring layers, and around a side surface of a protrusion of each of the plurality of via electrodes, the protrusion extending vertically away from the second surface of the base layer, and wherein a top surface of the via protection layer is coplanar with a top surface of the protrusion.

16. The semiconductor package of claim 13, wherein a first thickness of the first portion is greater than a second thickness of the second portion, wherein a third thickness of the third portion is greater than the first thickness of the first portion, wherein the first thickness of the first portion is greater than a fourth thickness of each of the plurality of pad wiring layers, and wherein the first thickness, the second thickness, the third thickness, and the fourth thickness are measured in a vertical direction with respect to the first surface of the base layer.

17. The semiconductor package of claim 16, wherein each of the plurality of wiring protection layers extends horizontally from the side surface of the corresponding pad wiring layer, and covers the corresponding portion of the via protection layer adjacent to the corresponding pad wiring layer in a horizontal direction with respect to the first surface of the base layer from the side surface of the corresponding pad wiring layer by a first width, the first width being greater than the fourth thickness.

18. An interposer, the interposer comprising: a base layer having a first surface and a second surface opposite to the first surface; a via electrode passing through the base layer, and including a protrusion extending vertically away from the second surface of the base layer; a via protection layer on the second surface of the base layer, wherein the via protection layer has a top surface coplanar with a top surface of the protrusion and surrounds a side surface of the protrusion; a pad wiring layer on the via protection layer and connected to the protrusion, wherein the via protection layer is disposed between the base layer and the pad wiring layer; a via connection terminal attached to the pad wiring layer; and a wiring protection layer including a first portion, a second portion, and a third portion, the first portion covering a portion of the via protection layer adjacent to the pad wiring layer, the second portion covering a portion of a top surface of the pad wiring layer, and the third portion covering a side surface of the pad wiring layer, wherein the third portion is disposed between the first portion and the second portion, and wherein the first portion, the second portion, and the third portion have different thicknesses from each other in a vertical direction with respect to the first surface of the base layer, The wiring protection layer covers only a portion of the interposer protection layer adjacent to the pad wiring layer, but does not cover other portions of the interposer protection layer.

19. The interposer of claim 18, wherein, The wiring protection layer extends horizontally from the side surface of the pad wiring layer and covers the portion of the interposer protection layer with a first width from the side surface of the pad wiring layer, wherein the first thickness of the first portion is greater than the second thickness of the second portion, and wherein the third thickness of the third portion is greater than the first thickness of the first portion.

20. The interposer of claim 18, wherein, The wiring protection layer includes an organic material, and wherein the interposer protection layer includes an inorganic material.

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