Semiconductor memory device with contact plugs

Abstract

Disclosed is a semiconductor memory device having a contact plug, the semiconductor memory device including: a substrate having a memory cell region at which a plurality of active regions are defined; a word line having a stack structure of a lower word line layer and an upper word line layer, and extending over the plurality of active regions in a first horizontal direction, and a buried insulating layer is located on the word line; a bit line structure arranged on the plurality of active regions, extending in a second horizontal direction perpendicular to the first horizontal direction, and having a bit line; and a word line contact plug electrically connected to the lower word line layer by penetrating the buried insulating layer and the upper word line layer, and having a plug extension in an upper portion of the word line contact plug, the plug extension having a horizontal width greater than a horizontal width of a lower portion of the word line contact plug.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2019-0170203, filed on December 18, 2019, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The inventive concept relates to a semiconductor memory device, and more specifically, to a semiconductor memory device having a contact plug. Background Technology

[0003] With the rapid development of the electronics industry and user demands, electronic devices are becoming more compact and lighter. Therefore, semiconductor memory devices used in electronic devices typically require high integration, leading to a reduction in the design size of components for semiconductor memory devices. Consequently, ensuring the reliability of electrical connections between components in semiconductor memory devices becomes challenging. Summary of the Invention

[0004] The inventive concept provides a semiconductor memory device having contact plugs capable of providing reliable electrical connections.

[0005] According to one aspect of the inventive concept, a semiconductor memory device is provided. The semiconductor memory device includes: a substrate having a memory cell region and a peripheral circuit region, defining a plurality of active regions in the memory cell region and defining at least one logic active region in the peripheral circuit region; word lines having a stacked structure of a lower word line layer and an upper word line layer, extending across the plurality of active regions in a first horizontal direction, and a buried insulating layer located on the word lines; a bit line structure disposed on the plurality of active regions, extending in a second horizontal direction perpendicular to the first horizontal direction, and having bit lines; and a word line contact plug electrically connected to the word lines by penetrating the buried insulating layer, and having a plug extension in the upper portion of the word line contact plug having a horizontal width greater than the horizontal width of the lower portion of the word line contact plug.

[0006] A semiconductor memory device includes: a substrate having a memory cell region and a peripheral circuit region, defining a plurality of active regions in the memory cell region and defining at least one logic active region in the peripheral circuit region; a word line having a stacked structure of a lower word line layer and an upper word line layer, and extending across the plurality of active regions in a first horizontal direction, with a buried insulating layer located on the word line; a bit line structure disposed on the plurality of active regions, extending in a second horizontal direction perpendicular to the first horizontal direction, and having bit lines; and a word line contact plug electrically connected to the lower word line layer by penetrating the buried insulating layer and the upper word line layer, and having a plug extension in the upper portion of the word line contact plug having a horizontal width greater than the horizontal width of the lower portion of the word line contact plug, wherein the side surface of the word line contact plug between the top and bottom surfaces of the upper word line layer is completely surrounded by the upper word line layer.

[0007] A semiconductor memory device includes: a substrate having a memory cell region and a peripheral circuit region, defining a plurality of active regions in the memory cell region and defining at least one logic active region in the peripheral circuit region; a plurality of word lines filled with a plurality of word line trenches, each word line trench extending across the plurality of active regions in a first horizontal direction to be parallel to each other, and each of the plurality of word lines having a stacked structure of a lower word line layer and an upper word line layer, and a plurality of buried insulating layers located on the plurality of word lines; a plurality of bit line structures disposed on the plurality of active regions, each bit line structure extending in a second horizontal direction perpendicular to the first horizontal direction to be parallel to each other, and each bit line structure having a bit line and an insulating cover line covering the bit line; and a filling insulating layer. The space between the plurality of bit line structures is filled; a word line contact plug having a plug extension in its upper portion, the plug extension having a horizontal width greater than the horizontal width of the lower portion of the word line contact plug, the word line contact plug being connected to the lower word line layer by penetrating a filling insulating layer, a buried insulating layer and an upper word line layer, and having a side surface at a horizontal position between the top and bottom surfaces of the upper word line layer, the side surface being completely covered by the upper word line layer; a plurality of buried contacts filling the lower portion of the space between the plurality of bit line structures and connected to the plurality of active regions; and a plurality of bonding pads filling the upper portion of the space between the plurality of bit line structures, extending over the plurality of bit line structures, and comprising the same material as the material included in the word line contact plug. Attached Figure Description

[0008] Exemplary embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which the same reference numerals refer to the same elements throughout. In the drawings:

[0009] Figure 1 This is a schematic planar layout of the main components of a semiconductor memory device, based on an exemplary embodiment of the inventive concept.

[0010] Figures 2A to 2G , Figures 3A to 3G , Figures 4A to 4G , Figures 5A to 5G , Figures 6A to 6G , Figures 7A to 7G , Figures 8A to 8G as well as Figures 9A to 9G This is a cross-sectional view illustrating a stage in a method of manufacturing a semiconductor memory device according to an exemplary embodiment of the inventive concept;

[0011] Figures 10A to 10G This is a cross-sectional view showing a semiconductor memory device according to an exemplary embodiment of the inventive concept at a stage; and

[0012] Figure 11 It is a cross-sectional view used to compare the cross-sections of the contact plugs of a semiconductor memory device according to an example embodiment of the inventive concept. Detailed Implementation

[0013] Figure 1 This is a schematic planar layout of the main components of a semiconductor memory device, based on an example embodiment of the inventive concept.

[0014] Reference Figure 1 The semiconductor memory device 1 may include a memory cell region CR and a peripheral circuit region PR. The semiconductor memory device 1 may include a plurality of active regions ACT in the memory cell region CR and a plurality of logical active regions ACTP in the peripheral circuit region PR.

[0015] According to some embodiments, a plurality of active regions ACT in a memory cell region CR can be arranged to have a major axis in a diagonal direction in a first horizontal direction (X direction) and a second horizontal direction (Y direction).

[0016] Multiple word lines (WL) can each extend vertically in the X direction across multiple active regions (ACT) within a memory cell region (CR) and be parallel to each other. Multiple bit lines (BL) can each extend vertically above the multiple word lines (WL) in a second horizontal direction (Y direction) intersecting the first horizontal direction (X direction) and be parallel to each other. The multiple bit lines (BL) can be connected to the multiple active regions (ACT) via direct contacts (DC).

[0017] According to some embodiments, a plurality of buried contacts BC can be formed between two adjacent bit lines BL among a plurality of bit lines BL. According to some embodiments, the plurality of buried contacts BC can be arranged in a line in a first horizontal direction (X direction) and a second horizontal direction (Y direction).

[0018] Multiple landing pads (or "pads") LP can be formed on multiple buried contacts BC. The multiple landing pads LP can be arranged to at least partially overlap with the multiple buried contacts BC in the vertical direction (Z direction). In some embodiments, each of the multiple landing pads LP can extend over one of the two adjacent bit lines BL.

[0019] Multiple memory nodes (SNs) can be formed above multiple bonding pads (LPs). Multiple memory nodes (SNs) can be formed above multiple bit lines (BLs). Multiple memory nodes (SNs) can each be a corresponding lower electrode of multiple capacitors. Multiple memory nodes (SNs) can be connected to multiple active regions (ACTs) via multiple bonding pads (LPs) and multiple buried contacts (BCs).

[0020] Multiple gate line patterns (GLPs) can be arranged on multiple logic active regions (ACTPs) within a peripheral circuit region (PR). According to some embodiments, some of the multiple gate line patterns (GLPs) can each extend longitudinally in a first horizontal direction (X-direction) on the logic active region (ACTP) to be parallel to each other, and the remaining gate line patterns (GLPs) can each extend longitudinally in a second horizontal direction (Y-direction) on the logic active region (ACTP) to be parallel to each other. However, the embodiments are not limited to this. For example, each of the multiple gate line patterns (GLPs) can have various widths, or can have curves, or can extend in various horizontal directions with variable widths.

[0021] For ease of explanation, components other than the multiple logic active regions (ACTPs) and multiple gate line patterns (GLPs) are omitted from the peripheral circuit area (PR). Although in Figure 1 Multiple gate line patterns (GLPs) are arranged only on multiple logic active regions (ACTPs), but the embodiments are not limited to this. For example, at least some of the multiple gate line patterns (GLPs) may extend outside the logic active regions (ACTPs), that is, extend to... Figures 2E to 2G Above the logic device isolation layer 115.

[0022] Multiple gate line patterns (GLPs) may be formed at the same level as multiple bit lines (BLs). According to some embodiments, the multiple gate line patterns (GLPs) and the multiple bit lines (BLs) may comprise the same material or at least partially comprise the same material. For example, a whole or part of the process for forming the multiple gate line patterns (GLPs) may be the same as a whole or part of the process for forming the multiple bit lines (BLs).

[0023] Figures 2A to 2G , Figures 3A to 3G , Figures 4A to 4G , Figures 5A to 5G , Figures 6A to 6G , Figures 7A to 7G , Figures 8A to 8Gas well as Figures 9A to 9G This is a cross-sectional view illustrating a stage in a method of manufacturing a semiconductor memory device according to an exemplary embodiment of the inventive concept. Figures 10A to 10G This is a cross-sectional view showing a semiconductor memory device in a stage according to an example embodiment of the inventive concept. Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A and Figure 10A It is along Figure 1 A sectional view of the stage intercepted by line A-A' in the middle; Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B and Figure 10B It is along Figure 1 A sectional view of the stage intercepted by line B-B' in the middle; Figure 2C , Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Figure 9C and Figure 10C It is along Figure 1 A sectional view of the stage intercepted by line C-C' in the middle; Figure 2D , Figure 3D , Figure 4D , Figure 5D , Figure 6D , Figure 7D , Figure 8D , Figure 9D and Figure 10D It is along Figure 1 A sectional view of the stage intercepted by line D-D' in the middle; Figure 2E , Figure 3E , Figure 4E , Figure 5E , Figure 6E , Figure 7E , Figure 8E , Figure 9E and Figure 10E It is along Figure 1 A sectional view of the stage intercepted by line E-E' in the middle; Figure 2F , Figure 3F , Figure 4F , Figure 5F , Figure 6F , Figure 7F , Figure 8F , Figure 9F and Figure 10F It is along Figure 1 A sectional view of the stage intercepted by line F-F' in the middle; and Figure 2G , Figure 3G , Figure 4G , Figure 5G , Figure 6G , Figure 7G , Figure 8G , Figure 9G and Figure 10G It is along Figure 1 A sectional view of the stage cut by line G-G' in the middle.

[0024] Reference Figures 2A to 2G Device isolation trenches 116T and logic device isolation trenches 115T can be formed in the substrate 110, and device isolation layers 116 filling the device isolation trenches 116T and logic device isolation layers 115 filling the logic device isolation trenches 115T can be formed. The top surfaces of the substrate 110, device isolation layers 116 and logic device isolation layers 115 can be at the same vertical level.

[0025] For example, substrate 110 may include silicon (Si), such as crystalline Si, polycrystalline Si, or amorphous Si. Optionally, substrate 110 may include a semiconductor element, such as germanium (Ge) or at least one compound semiconductor selected from silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). Substrate 110 may have a silicon-on-insulator (SOI) structure. For example, substrate 110 may include a buried oxide (BOX) layer. Substrate 110 may include conductive regions, such as doped wells or doped structures.

[0026] Device isolation layer 116 and logic device isolation layer 115 may comprise a material including at least one selected from, for example, silicon oxide, silicon nitride, and silicon oxynitride layers. Device isolation layer 116 may be a single layer comprising one type of insulating layer, a double layer comprising two types of insulating layers, or a multilayer comprising at least three types of insulating layers. For example, device isolation layer 116 may be a double layer or multilayer comprising oxide and nitride layers. However, embodiments of the inventive concept are not limited to the above-described structure of device isolation layer 116. A plurality of active regions 118 may be located in the memory cell region CR (see [link to relevant documentation]) of substrate 110. Figure 1 The active region ACT is defined by device isolation layer 116, and multiple logic active regions 117 can be located in the peripheral circuit region PR of substrate 110 (see Figure 1 The logic active region (ACTP) is defined by logic device isolation layer 115.

[0027] In this specification, the portion of the substrate 110 with multiple active regions 118 and its adjacent portions are referred to as cell regions CR, and the portion of the substrate 110 with multiple logic active regions 117 and its adjacent portions are referred to as peripheral circuit regions PR.

[0028] According to some embodiments, device isolation layer 116 and logic device isolation layer 115 can be formed together, and both can be referred to as a device isolation structure. For example, device isolation layer 116 and logic device isolation layer 115 can be formed simultaneously from the same material in the same process. Device isolation layer 116 can be a portion of the device isolation structure defining a plurality of active regions 118, and logic device isolation layer 115 can be a portion of the device isolation structure defining a plurality of logic active regions 117. The portion of the device isolation structure located at the boundary between cell region CR and peripheral circuit region PR can be either device isolation layer 116 or logic device isolation layer 115. Device isolation layer 116 and logic device isolation layer 115 may not be clearly distinguishable from each other at the boundary between cell region CR and peripheral circuit region PR.

[0029] and Figure 1 Similar to the active region ACT in the diagram, each of the active regions 118 can have a relatively long island shape, with a short axis and a long axis, according to the plan view. (And...) Figure 1 Similar to the ACTP logical active region, each of the logical active regions 117 can have a rectangular shape according to the plan view. However, the embodiment is not limited to this, and each of the logical active regions 117 can have any planar shape of various other planar shapes.

[0030] Multiple word line trenches 120T may be formed in the substrate 110. The multiple word line trenches 120T may have a line shape that extends longitudinally parallel to each other in a first horizontal direction (X direction) and is arranged at equal intervals across the active region 118 in a second horizontal direction (Y direction). According to some embodiments, steps may be present on the bottom surface of the multiple word line trenches 120T. For example, the height of each of the multiple word line trenches 120T in the vertical direction (Z direction) may vary along the first horizontal direction (X direction). According to some embodiments, in order to form the multiple word line trenches 120T, each having steps at its bottom surface, the device isolation layer 116 and the substrate 110 may be etched separately by separate etching processes, thus having different etching depths. For example, the etching depth of the substrate 110 may be greater than the etching depth of the device isolation layer 116, such that the depth of each of the multiple word line trenches 120T may be at a higher vertical level above the substrate 110 and at a lower vertical level above the device isolation layer 116. According to some embodiments, in order to form a plurality of word line trenches 120T, each having a step at its bottom surface, the device isolation layer 116 and the substrate 110 can be etched simultaneously, but with different etching depths due to the difference between the respective etching rates of the device isolation layer 116 and the substrate 110.

[0031] After cleaning the resulting structure in which multiple word line trenches 120T are formed, multiple gate dielectric layers 122, multiple word lines 120, and multiple buried insulating layers 124 can be formed within the multiple word line trenches 120T in the order stated herein. The multiple word lines 120 can constitute... Figure 1 Multiple word lines 120. The multiple word lines 120 may have a line shape that extends longitudinally parallel to each other in a first horizontal direction (X direction) and is arranged at equal intervals across the active regions 118 in a second horizontal direction (Y direction). The top surface of the multiple word lines 120 may be at a lower level than the top surface of the substrate 110. The bottom surface of the multiple word lines 120 may have an irregular shape and may form transistors with saddle-fin structures, such as saddle-fin field-effect transistors (FinFETs), in the multiple active regions 118.

[0032] In this specification, the term "horizontal" / "vertical horizontal" refers to the height of the substrate 110 from the main surface or top surface in the vertical direction (Z direction). For example, "at the same level" or "at a certain level" means "at the same height from the main surface or top surface of the substrate 110 in the vertical direction (Z direction)" or "at a certain position relative to the main surface or top surface of the substrate 110 in the vertical direction (Z direction)," and "at a lower / higher level" means "at a lower / higher position relative to the main surface or top surface of the substrate 110 in the vertical direction (Z direction)."

[0033] Each of the multiple word lines 120 may be a stack comprising a lower word line layer 120a and an upper word line layer 120b. For example, the lower word line layer 120a may be formed of a metallic material, a conductive metal nitride, or a combination thereof. According to some embodiments, the lower word line layer 120a may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or a combination thereof. For example, the upper word line layer 120b may include doped polysilicon. The lower surface of the upper word line layer 120b may contact the upper surface of the lower word line layer 120a. According to some embodiments, the lower word line layer 120a may include a core layer and a barrier layer disposed between the core layer and the gate dielectric layer 122. For example, the core layer may include a metallic material or a conductive metal nitride, such as W, WN, TiSiN, or WSiN, and the barrier layer may include a metallic material or a conductive metal nitride, such as Ti, TiN, Ta, or TaN. As used here, when an element is referred to as "contacting" another element or "in contact" with another element, there is no intermediate element at the point of contact.

[0034] According to some embodiments, before or after the formation of the multiple word lines 120, impurity ions can be implanted into the active region 118 of the substrate 110 on both sides of each of the multiple word lines 120, thereby forming a source region and a drain region within the multiple active regions ACT.

[0035] Each of the plurality of gate dielectric layers 122 may be formed of at least one selected from silicon oxide, silicon nitride, silicon oxynitride, oxide / nitride / oxide (ONO), and a high-k dielectric film having a dielectric constant higher than that of silicon oxide. For example, each of the plurality of gate dielectric layers 122 may have a dielectric constant of about 10 to about 25. According to some embodiments, a plurality of gate dielectric layers 122 may be formed from at least one selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium oxynitride silicon (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium oxynitride silicon (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). For example, the plurality of gate dielectric layers 122 may be formed from HfO2, Al2O3, HfAlO3, Ta2O3, or TiO2.

[0036] The top surfaces of the plurality of buried insulating layers 124 may be substantially at the same level as the top surface of the substrate 110. Each of the plurality of buried insulating layers 124 may include at least one material layer selected from silicon oxide, silicon nitride, silicon oxynitride, and combinations thereof. The bottom surface of each of the plurality of buried insulating layers 124 may contact the top surface of the corresponding word line 120 of the plurality of word lines 120.

[0037] Reference Figures 3A to 3G An insulating layer pattern (including a first insulating layer pattern 112 and a second insulating layer pattern 114) is formed to cover a device isolation layer 116, multiple active regions 118, multiple buried insulating layers 124, a logic device isolation layer 115, and multiple logic active regions 117. For example, the insulating layer pattern (including the first insulating layer pattern 112 and the second insulating layer pattern 114) may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a metal dielectric layer, or a combination thereof. According to some embodiments, the insulating layer pattern (including the first insulating layer pattern 112 and the second insulating layer pattern 114) can be formed by stacking multiple insulating layers including the first insulating layer pattern 112 and the second insulating layer pattern 114. According to some embodiments, the first insulating layer pattern 112 may include a silicon oxide layer, and the second insulating layer pattern 114 may include a silicon nitride layer.

[0038] According to some embodiments, the first insulating layer pattern 112 may include a non-metallic dielectric layer, and the second insulating layer pattern 114 may include a metallic dielectric layer. For example, the first insulating layer pattern 112 may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof. For example, the second insulating layer pattern 114 may include at least one selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium oxynitride silicon (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium oxynitride silicon (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

[0039] Subsequently, a plurality of direct contact holes 134H are formed to penetrate the insulating layer patterns (including the first insulating layer pattern 112 and the second insulating layer pattern 114) and expose the source regions in the corresponding active regions 118. According to some embodiments, the direct contact holes 134H may extend inside the corresponding active regions 118 (i.e., source regions). For example, each direct contact hole 134H may extend to a level lower than the level of the top surface of the corresponding active region 118 and the device isolation layer 116.

[0040] Reference Figures 4A to 4G A direct contact conductive layer is formed on multiple active regions 118 and a device isolation layer 116 to fill the direct contact via 134H and cover an insulating layer pattern (including a first insulating layer pattern 112 and a second insulating layer pattern 114). The direct contact conductive layer may include, for example, Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or combinations thereof. According to some embodiments, the direct contact conductive layer may include an epitaxial silicon layer. According to some embodiments, the direct contact conductive layer may include doped polysilicon.

[0041] Subsequently, a metal conductive layer and an insulating capping layer for forming the bit line structure 140 are sequentially formed to cover the insulating layer pattern (including the first insulating layer pattern 112 and the second insulating layer pattern 114) and the direct contact conductive layer.

[0042] According to some embodiments, the metal conductive layer may have a stacked structure in which a first metal conductive layer and a second metal conductive layer are stacked. The metal conductive layer may have a conductive layer stacked structure including a two-layer structure, but this is only an example, and the embodiments are not limited thereto. For example, the metal conductive layer may include a single layer or a stacked structure including at least three layers.

[0043] The first metal conductive layer, the second metal conductive layer, and the insulating cap layer are etched to form multiple bit lines 147 and multiple insulating cap lines 148, each of the multiple bit lines 147 including a first metal conductive pattern 145 and a second metal conductive pattern 146 having a linear shape.

[0044] According to some embodiments, the first metal conductive pattern 145 may include TiN or Ti-Si-N (TSN), and the second metal conductive pattern 146 may include tungsten (W) or W and tungsten silicide (WSi). x According to some embodiments, the first metallic conductive pattern 145 can be used as a diffusion barrier. According to some embodiments, the plurality of insulating cover lines 148 may include a silicon nitride layer.

[0045] A bit line 147 and an insulating cover line 148 covering the bit line 147 can constitute a bit line structure 140. Multiple bit line structures 140, including multiple bit lines 147 and multiple insulating cover lines 148, can each extend longitudinally in a second horizontal direction (Y direction) parallel to the main surface of the substrate 110, so as to be parallel to each other. Multiple bit lines 147 can constitute... Figure 1Multiple bit lines BL. According to some embodiments, each of the multiple bit line structures 140 may further include a conductive semiconductor pattern 132 between an insulating layer pattern (including a first insulating layer pattern 112 and a second insulating layer pattern 114) and a first metal conductive pattern 145. The conductive semiconductor pattern 132 may include doped polysilicon. According to some embodiments, the conductive semiconductor pattern 132 may be omitted.

[0046] During the etching process that forms multiple bit lines 147, portions of the direct contact conductive layer that are not vertically stacked with the multiple bit lines 147 can also be etched, thereby forming multiple direct contact conductive patterns 134. In this case, the insulating layer patterns (including the first insulating layer pattern 112 and the second insulating layer pattern 114) can be used as an etching stop layer during the etching process that forms the multiple bit lines 147 and the multiple direct contact conductive patterns 134. The multiple direct contact conductive patterns 134 can constitute... Figure 1 Multiple direct contact DC components. Multiple bit lines 147 can be electrically connected to multiple active regions 118 via multiple direct contact conductive patterns 134.

[0047] According to some embodiments, the conductive semiconductor pattern 132 may also be formed during a process of removing a portion of the direct contact conductive layer to form the direct contact conductive pattern 134. For example, the conductive semiconductor pattern 132 may be a portion of the direct contact conductive layer that is vertically stacked with the bit line 147 but not vertically stacked with the direct contact hole 134H and located on an insulating layer pattern (including the first insulating layer pattern 112 and the second insulating layer pattern 114), and the direct contact conductive pattern 134 may be a portion of the direct contact conductive layer that is vertically stacked with the direct contact hole 134H and contacts the active region 118.

[0048] Insulating spacer structure 150 may cover two sidewalls of each of the plurality of bit line structures 140. Each of the plurality of insulating spacer structures 150 may include a first insulating spacer 152, a second insulating spacer 154, and a third insulating spacer 156. The second insulating spacer 154 may include a material having a lower dielectric constant than the first insulating spacer 152 and the third insulating spacer 156. According to some embodiments, the first insulating spacer 152 and the third insulating spacer 156 may include nitride layers, and the second insulating spacer 154 may include an oxide layer. According to some embodiments, the first insulating spacer 152 and the third insulating spacer 156 may include nitride layers, and the second insulating spacer 154 may include a material having etch selectivity relative to the first insulating spacer 152 and the third insulating spacer 156. For example, when the first insulating spacer 152 and the third insulating spacer 156 include nitride layers, the second insulating spacer 154 may include an oxide layer and may be removed during a subsequent process to become an air spacer.

[0049] Multiple buried contact holes 170Hs can be formed between each of the multiple bit lines 147. The internal space of each of the multiple buried contact holes 170Hs can be defined by an insulating spacer structure 150 that respectively covers the sidewalls of two adjacent bit lines 147 and an active region 118 between the two adjacent bit lines 147. In addition, the internal space of each of the multiple buried contact holes 170Hs can also be defined by the side surfaces of a first insulating layer pattern 112 and a second insulating layer pattern 114 of one of the two adjacent bit lines 147.

[0050] A plurality of buried contact holes 170Hs can be formed by using a plurality of insulating spacer structures 150 and a plurality of insulating cover lines 148 as an etching mask to partially remove insulating layer patterns (including first insulating layer pattern 112 and second insulating layer pattern 114) and active regions 118, wherein each of the plurality of insulating spacer structures 150 covers two sidewalls of each of the plurality of bit line structures 140. According to some embodiments, a plurality of buried contact holes 170Hs can be formed by first performing an anisotropic etching process that partially removes insulating layer patterns (including first insulating layer pattern 112 and second insulating layer pattern 114) and active regions 118 using insulating spacer structures 150 and a plurality of insulating cover lines 148 as an etching mask, and then performing an isotropic etching process that further partially removes active regions 118, such that the corresponding spacer spacer structure 150 of the buried contact hole 170H, defined by the active regions 118, can extend, wherein each of the insulating spacer structures 150 covers two sidewalls of each of the plurality of bit line structures 140.

[0051] Multiple gate line structures 140P can be formed on the logic active region 117. According to some embodiments, at least one dummy bit line structure 140D can be arranged between each bit line structure 140 and each gate line structure 140P.

[0052] Each of the plurality of gate line structures 140P may include a gate line 147P and an insulating cap line 148 covering the gate line 147P. The plurality of gate lines 147P included in the plurality of gate line structures 140P may be formed together with a plurality of bit lines 147. For example, the plurality of gate lines 147P may be a stack of a first metal conductive pattern 145 and a second metal conductive pattern 146. A gate insulating layer pattern 142 may be disposed between each gate line 147P and each logic active region 117. According to some embodiments, each of the plurality of gate line structures 140P may further include a conductive semiconductor pattern 132 between the gate insulating layer pattern 142 and the first metal conductive pattern 145. The plurality of gate lines 147P may constitute Figure 1 Multiple gate line patterns GLP.

[0053] The gate insulating spacer 150P may cover both sidewalls of each gate line structure 140P. The gate insulating spacer 150P may include, for example, a nitride layer. According to some embodiments, the gate insulating spacer 150P may include a single layer, but the embodiments are not limited thereto. The gate insulating spacer 150P may have a stacked structure comprising two or more layers.

[0054] Each dummy bit line structure 140D may extend longitudinally in a second horizontal direction (Y direction) parallel to the bit line structure 140. Each dummy bit line structure 140D may have a structure substantially similar to that of each bit line structure 140. Each dummy bit line structure 140D may include a dummy bit line 147D and an insulating cover line 148, wherein the dummy bit line 147D includes a first metallic conductive pattern 145 and a second metallic conductive pattern 146. The two sidewalls of the dummy bit line structure 140D may be covered by at least one of an insulating spacer structure 150 and a gate insulating spacer 150P.

[0055] According to some embodiments, the horizontal width of the dummy bit line 147D in the first horizontal direction (X direction) may be larger than the horizontal width of each of the bit lines 147 in the first horizontal direction (X direction). According to some other embodiments, the horizontal width of the dummy bit line 147D in the first horizontal direction (X direction) may be equal to the horizontal width of each of the bit lines 147 in the first horizontal direction (X direction). According to some embodiments, a plurality of dummy bit line structures 140D may be included, and the dummy bit lines 147D of some of the plurality of dummy bit line structures 140D may have a horizontal width in the first horizontal direction (X direction) that is larger than the horizontal width of each bit line 147, while the dummy bit lines 147D of other of the plurality of dummy bit line structures 140D may have a horizontal width in the first horizontal direction (X direction) that is equal to the horizontal width of each bit line 147.

[0056] Reference Figures 5A to 5G A plurality of buried contacts 170 and a plurality of insulating barriers 180 are formed in the space between a plurality of insulating spacer structures 150 that respectively cover the sidewalls of a plurality of bit line structures 140. The plurality of buried contacts 170 and the plurality of insulating barriers 180 may be alternately arranged in a second horizontal direction (Y direction) between every two adjacent insulating spacer structures 150, which respectively cover the sidewalls of the plurality of bit line structures 140. For example, the plurality of buried contacts 170 may comprise polysilicon. For example, the plurality of insulating barriers 180 may comprise a nitride layer.

[0057] According to some embodiments, a plurality of buried contacts 170 may be arranged in a line in each of a first horizontal direction (X direction) and a second horizontal direction (Y direction). Each of the plurality of buried contacts 170 may extend from the active region 118 in a vertical direction (Z direction) perpendicular to the substrate 110. The plurality of buried contacts 170 may constitute Figure 1 Multiple buried contact components BC.

[0058] Multiple buried contacts 170 can be arranged in a space defined by multiple insulating spacer structures 150 and multiple insulating fences 180, which respectively cover the sidewalls of multiple bit line structures 140. The multiple buried contacts 170 can fill the lower part of the space between the multiple insulating spacer structures 150, which respectively cover the sidewalls of multiple bit line structures 140.

[0059] The top surfaces of the multiple buried contacts 170 may be at a lower level than the top surfaces of the multiple insulating cover wires 148. The top surfaces of the multiple insulating fences 180 may be at the same level as the top surfaces of the multiple insulating cover wires 148 in the vertical direction (Z direction).

[0060] Multiple mating pad holes 190H may be defined by multiple insulating spacer structures 150 and multiple buried contacts 170. The multiple mating pad holes 190H may be vertically stacked with the multiple buried contacts 170. The multiple buried contacts 170 may be exposed at the bottom of the multiple mating pad holes 190H.

[0061] A fill insulating layer (including a first fill insulating layer 172 and a second fill insulating layer 174) can be formed around multiple gate line structures 140P on an insulating layer pattern (including a first insulating layer pattern 112 and a second insulating layer pattern 114). According to some embodiments, the fill insulating layers (including the first fill insulating layer 172 and the second fill insulating layer 174) can have a stacked structure in which the first fill insulating layer 172 and the second fill insulating layer 174 are stacked. According to some embodiments, the first fill insulating layer 172 may include an oxide, and the second fill insulating layer 174 may include a nitride. The top surface of the fill insulating layers (including the first fill insulating layer 172 and the second fill insulating layer 174) (i.e., the top surface of the second fill insulating layer 174) can be at the same level as the top surface of each gate line structure 140P.

[0062] While forming multiple buried contacts 170 and / or multiple insulating fences 180, the corresponding upper portions of the insulating cover line 148, including the bit line structure 140, the dummy bit line structure 140D, and the gate line structure 140P, the insulating spacer structure 150, and the gate insulating spacer 150P, can be partially removed, thereby reducing the level of the top surface of the bit line structure 140, the dummy bit line structure 140D, and the gate line structure 140P.

[0063] Reference Figures 6A to 6G Multiple contact holes CPHE, CPHF, and CPHG are formed that penetrate the filled insulating layer (including the first filled insulating layer 172 and the second filled insulating layer 174) and the insulating layer pattern (including the first insulating layer pattern 112 and the second insulating layer pattern 114). The multiple contact holes CPHE, CPHF, and CPHG may include a first contact hole CPHE, a second contact hole CPHF, and a third contact hole CPHG. The third contact hole CPHG may include a gate line contact hole CPHG1 and a bit line contact hole CPHG2. The first contact hole CPHE and the second contact hole CPHF may be referred to as a word line contact hole CPHE and a logic active region contact hole CPHF, respectively.

[0064] The word line contact hole CPHE can extend to the lower word line layer 120a by penetrating the filler insulating layer (including the first filler insulating layer 172 and the second filler insulating layer 174), the insulating layer pattern (including the first insulating layer pattern 112 and the second insulating layer pattern 114), the buried insulating layer 124, and the upper word line layer 120b. According to some embodiments, the word line contact hole CPHE can extend into the lower word line layer 120a.

[0065] The logic active region contact hole CPHF can extend into the logic active region 117 by penetrating the filling insulating layer (including the first filling insulating layer 172 and the second filling insulating layer 174) and the insulating layer pattern (including the first insulating layer pattern 112 and the second insulating layer pattern 114). According to some embodiments, the logic active region contact hole CPHF can extend into the logic active region 117.

[0066] According to some embodiments, the third contact hole CPHG (i.e., gate line contact hole CPHG1 and bit line contact hole CPHG2) can extend into the first metal conductive pattern 145 by penetrating the insulating cover line 148 and the second metal conductive pattern 146. According to some embodiments, the third contact hole CPHG (i.e., gate line contact hole CPHG1 and bit line contact hole CPHG2) can extend into the first metal conductive pattern 145. According to some other embodiments, the third contact hole CPHG (i.e., gate line contact hole CPHG1 and bit line contact hole CPHG2) can extend into the second metal conductive pattern 146 by penetrating the insulating cover line 148. According to some other embodiments, the third contact hole CPHG (i.e., gate line contact hole CPHG1 and bit line contact hole CPHG2) can extend into the second metal conductive pattern 146.

[0067] For example, the gate line contact hole CPHG1 can extend into the gate line 147P through the insulating cover wire 148, and the bit line contact hole CPHG2 can extend into the bit line 147 through the insulating cover wire 148. According to some embodiments, the gate line contact hole CPHG1 can extend into the gate line 147P through the insulating cover wire 148, and the bit line contact hole CPHG2 can extend into the bit line 147 through the insulating cover wire 148.

[0068] According to some embodiments, the first contact hole CPHE, the second contact hole CPHF, and the third contact hole CPHG can be formed simultaneously using the same etching process. According to some other embodiments, at least one of the first contact hole CPHE, the second contact hole CPHF, and the third contact hole CPHG can be formed sequentially using separate etching processes.

[0069] Reference Figures 7A to 7G An extended mask pattern MKE is formed having an extended opening MKEO that exposes portions of the fill insulating layers (including a first fill insulating layer 172 and a second fill insulating layer 174 adjacent to the first contact hole CPHE) and the first contact hole CPHE. The extended mask pattern MKE may cover the remaining portions of the fill insulating layers (including the first fill insulating layer 172 and the second fill insulating layer 174). The extended mask pattern MKE may fill the second contact hole CPHF and the third contact hole CPHG, and may cover the bit line structure 140, the dummy bit line structure 140D, the gate line structure 140P, the buried contact 170, and the insulating fence 180.

[0070] Subsequently, a hole extension HE can be formed in the upper part of the first contact hole CPHE by removing the portion of the fill insulating layer (including the first fill insulating layer 172 and the second fill insulating layer 174) exposed through the extended opening MKEO using an extended mask pattern MKE as an etching mask. After forming the hole extension HE, the extended mask pattern MKE can be removed. When forming the hole extension HE, the vertical level of the bottom surface of the first contact hole CPHE can be lowered. (Refer to...) Figures 8A to 8G After forming the hole extension HE and removing the extension mask pattern MKE, a bonding pad material layer 190P is formed to fill the plurality of bonding pad holes 190H and the plurality of contact holes CPHE, CPHF and CPHG and to cover the plurality of bit line structures 140, the plurality of gate line structures 140P and at least one dummy bit line structure 140D.

[0071] The hole extension HE can be formed by partially removing the filler insulating layers (including the first filler insulating layer 172 and the second filler insulating layer 174). Due to the hole extension HE, the upper horizontal width and horizontal profile of the first contact hole CPHE can be increased. For example, the upper horizontal width of the first contact hole CPHE adjacent to the second filler insulating layer 174 can be wider than the lower horizontal width of the first contact hole CPHE adjacent to the lower portion of the first filler insulating layer 172. The bottom surface of the hole extension HE can have a vertical level higher than the first vertical level LV1 of the top surface of the bit line 147 or gate line 147P (i.e., the top surface of the second metallic conductive pattern 146). For example, the vertical level of the bottom surface of the hole extension HE can be higher than the first vertical level LV1 of the top surface of the second metallic conductive pattern 146 and lower than the second vertical level LV2 of the top surface of the insulating cap line 148 or the top surface of the filler insulating layers (including the first filler insulating layer 172 and the second filler insulating layer 174) (i.e., the top surface of the second filler insulating layer 174). In some embodiments, the vertical level of the bottom surface of the hole extension HE may be lower than the vertical level of the top surface of the first filling insulating layer 172.

[0072] According to some embodiments, the bonding pad material layer 190P may include a conductive barrier layer and a conductive pad material layer disposed on the conductive barrier layer. For example, the conductive barrier layer may include a metal, a conductive metal nitride, or a combination thereof. According to some embodiments, the conductive barrier layer may have a Ti / TiN stacked structure. According to some embodiments, the conductive pad material layer may include tungsten (W).

[0073] According to some embodiments, a metal silicide layer may be formed on the plurality of buried contacts 170 prior to the formation of the bonding pad material layer 190P. The metal silicide layer may be disposed between the plurality of buried contacts 170 and the bonding pad material layer 190P. The metal silicide layer may include, but is not limited to, cobalt silicide (CoSi). x Nickel silicide (NiSi) x ) or manganese silicide (MnSi) x ).

[0074] Multiple hard mask patterns HMKC and HMKP are formed on the bonding pad material layer 190P. According to some embodiments, the multiple hard mask patterns HMKC and HMKP can be formed by extreme ultraviolet (EUV) lithography. The multiple hard mask patterns HMKC and HMKP may include unit hard mask patterns HMKC and logic hard mask patterns HMKP. The unit hard mask patterns HMKC are disposed on the multiple bonding pad holes 190H and the portions of the bonding pad material layer 190P surrounding the multiple bonding pad holes 190H. The logic hard mask patterns HMKP are disposed on the multiple contact holes CPHE, CPHF, and CPHG and the portions of the bonding pad material layer 190P surrounding the multiple contact holes CPHE, CPHF, and CPHG. In some embodiments, the unit hard mask patterns HMKC may at least partially overlap with the bonding pad holes 190H, and the logic hard mask patterns HMKP may be vertically overlapped with the contact holes CPHE, CPHF, and CPHG.

[0075] Reference Figures 9A to 9G By using the unit hard mask pattern HMKC as an etching mask to remove Figures 8A to 8G The portions of multiple bit line structures 140 surrounding multiple bonding pad holes 190H and the portions of bonding pad material layers 190P surrounding multiple bonding pad holes 190H are used to form multiple bonding pads 190 that at least partially fill the multiple bonding pad holes 190H and extend over the multiple bit line structures 140. The multiple bonding pads 190 may be separated from each other, and recesses 190R are located therebetween. (Refer to...) Figure 9C Alternatively, portions of each of the multiple insulating fences 180 can be removed by using the unit hard mask pattern HMKC as an etching mask.

[0076] Multiple bonding pads 190 may be arranged on multiple buried contacts 170 and may extend over multiple bit lines 140. According to some embodiments, the multiple bonding pads 190 may extend over multiple bit lines 147. The multiple bonding pads 190 may be arranged on the multiple buried contacts 170 for respective electrical connections to the multiple buried contacts 170. The multiple bonding pads 190 may be respectively connected to the active region 118 via the multiple buried contacts 170. The multiple bonding pads 190 may constitute... Figure 1 Multiple bonding pads LP.

[0077] Each buried contact 170 may be located between two adjacent bit line structures 140, and each mating pad 190 may extend from between the two adjacent bit line structures 140 having buried contact 170 therebetween to over one of the two adjacent bit line structures 140.

[0078] Multiple logic bit lines (BLPs) and multiple contact plugs (CPEs, CPFs, and CPGs) filling the multiple contact holes (CPHE, CPHF, and CPHG) are formed by removing portions of the bonding pad material layer 190P around the multiple contact holes (CPHE, CPHF, and CPHG) using a logic hard mask pattern (HMKP) as an etching mask. The multiple logic bit lines (BLPs) can be portions of the bonding pad material layer 190P on the multiple contact plugs (CPE, CPF, and CPG) that are at a level higher than the second vertical level (LV2).

[0079] Multiple contact plugs CPE, CPF, and CPG may include multiple first contact plugs CPE, multiple second contact plugs CPF, and multiple third contact plugs CPG. Multiple third contact plugs CPG may include multiple gate line contact plugs CPG1 and multiple bit line contact plugs CPG2. The first contact plugs CPE and second contact plugs CPF may be referred to as word line contact plugs CPE and logic active region contact plugs CPF, respectively.

[0080] The word line contact plug CPE can extend to the lower word line layer 120a by penetrating a portion of the top surface of each word line 120, including a filler insulation layer (including a first filler insulation layer 172 and a second filler insulation layer 174), an insulation layer pattern (including a first insulation layer pattern 112 and a second insulation layer pattern 114), a buried insulation layer 124, and an upper word line layer 120b.

[0081] Each word line contact plug CPE may have a plug extension PE. The plug extension PE may be a portion of the fill hole extension HE of the word line contact plug CPE. Due to the plug extension PE, the horizontal width and horizontal profile of the upper portion of the word line contact plug CPE may be increased. The bottom surface of the plug extension PE may have a vertical level higher than the first vertical level LV1 of the top surface of the second metallic conductive pattern 146. For example, the vertical level of the bottom surface of the plug extension PE may be higher than the first vertical level LV1 of the top surface of the second metallic conductive pattern 146 and lower than the second vertical level LV2 of the top surface of the insulating cover line 148. In some embodiments, the vertical level of the bottom surface of the plug extension PE may be lower than the vertical level of the top surface of the first fill insulating layer 172.

[0082] The side surface of the portion of the word line contact plug CPE adjacent to the top surface of the lower word line layer 120a can be surrounded by the upper word line layer 120b. For example, the side surface of the portion of the word line contact plug CPE at the level corresponding to the upper word line layer 120b (i.e., the level between the top and bottom surfaces of the upper word line layer 120b) can be completely covered by the upper word line layer 120b.

[0083] The logic active region contact plug CPF can extend into the logic active region 117 by penetrating the fill insulation layer (including the first fill insulation layer 172 and the second fill insulation layer 174) and the insulation layer pattern (including the first insulation layer pattern 112 and the second insulation layer pattern 114).

[0084] According to some embodiments, the third contact plug CPG (i.e., gate line contact plug CPG1 and bit line contact plug CPG2) can extend to the first metal conductive pattern 145 by penetrating the insulating cover line 148 and the second metal conductive pattern 146. According to some other embodiments, the third contact plug CPG (i.e., gate line contact plug CPG1 and bit line contact plug CPG2) can extend to the second metal conductive pattern 146 by penetrating the insulating cover line 148. For example, gate line contact plug CPG1 can extend to gate line 147P by penetrating the insulating cover line 148, and bit line contact plug CPG2 can extend to bit line 147 by penetrating the insulating cover line 148.

[0085] Multiple bonding pads 190, multiple logic bit lines BLP, first contact plug CPE, second contact plug CPF, and third contact plug CPG can be formed simultaneously using the same etching process, which uses both the unit hard mask pattern HMKC and the logic hard mask pattern HMKP as etching masks.

[0086] Reference Figures 10A to 10D A semiconductor memory device 1 comprising multiple capacitor structures 200 can be formed by sequentially forming multiple lower electrodes 210, a capacitor dielectric layer 220, and an upper electrode 230 on multiple bonding pads 190. The multiple lower electrodes 210 can be electrically connected to the multiple bonding pads 190, respectively. The capacitor dielectric layer 220 can conformally cover the multiple lower electrodes 210. The upper electrode 230 can cover the capacitor dielectric layer 220. The upper electrode 230 can face the multiple lower electrodes 210, and the capacitor dielectric layer 220 is located between the upper electrode 230 and the multiple lower electrodes 210. The capacitor dielectric layer 220 and the upper electrode 230 can be integrally formed to cover the multiple lower electrodes 210 in a certain region (e.g., a memory cell region CR). The multiple lower electrodes 210 can constitute... Figure 1 The image shows multiple storage node SNs.

[0087] Each of the plurality of lower electrodes 210 may have, but is not limited to, a solid cylindrical shape with a circular horizontal cross-section. According to some embodiments, each of the plurality of lower electrodes 210 may have a cylindrical shape with a closed bottom. According to some embodiments, when viewed from above, the plurality of lower electrodes 210 may be arranged in a zigzag pattern in a first horizontal direction (X direction) or a second horizontal direction (Y direction). According to some other embodiments, the plurality of lower electrodes 210 may be arranged in a matrix pattern in lines in the first horizontal direction (X direction) and the second horizontal direction (Y direction). The plurality of lower electrodes 210 may include, for example, doped silicon, a metal such as tungsten or copper, or a conductive metal compound such as titanium nitride. Although not specifically shown, the semiconductor memory device 1 may also include at least one support pattern contacting the sidewalls of the plurality of lower electrodes 210.

[0088] The capacitor dielectric layer 220 may include, for example, TaO, TaAlO, TaON, AlO, AlSiO, HfO, HfSiO, ZrO, ZrSiO, TiO, TiAlO, BST ((Ba,Sr)TiO), STO (SrTiO), BTO (BaTiO), PZT (Pb(Zr,Ti)O), (Pb,La)(Zr,Ti)O, Ba(Zr,Ti)O, Sr(Zr,Ti)O, or combinations thereof.

[0089] The upper electrode 230 may include, for example, doped silicon, Ru, RuO, Pt, PtO, Ir, IrO, SRO (SrRuO), BSRO ((Ba,Sr)RuO), CRO (CaRuO), BaRuO, La (Sr,Co)O, Ti, TiN, W, WN, Ta, TaN, TiAlN, TiSiN, TaAlN, TaSiN, or combinations thereof.

[0090] Before forming the plurality of capacitor structures 200, an insulating structure 195 filling the recess 190R can be formed. According to some embodiments, each of the insulating structures 195 may include an interlayer insulating layer and an etch stop layer. For example, the interlayer insulating layer may include an oxide layer, and the etch stop layer may include a nitride layer. Although in Figure 10A and Figure 10C The top surface of the insulating structure 195 is at the same level as the bottom surfaces of the plurality of lower electrodes 210, but the embodiments are not limited thereto. For example, the top surface of the insulating structure 195 may be at a higher level than the bottom surfaces of the plurality of lower electrodes 210, and the plurality of lower electrodes 210 may each extend toward the substrate 110 within the insulating structure 195.

[0091] The space between multiple logic bit lines (BLPs) can be filled with a cover insulating layer 250, which is flush with multiple capacitor structures 200. The cover insulating layer 250 may include, for example, an oxide layer or an ultra-low K (ULK) layer. The oxide layer may be selected from borosilicate glass (BPSG), phosphosilicate glass (PSG), borosilicate glass (BSG), undoped silicate glass (USG), tetraethyl orthosilicate (TEOS), and high-density plasma (HDP) layers. For example, the ULK layer may be selected from, for example, SiOC and SiCOH layers, both having an ultra-low dielectric constant K of about 2.2 to about 2.4.

[0092] Semiconductor memory device 1 includes: a substrate 110 having a plurality of active regions 118 and a plurality of logic active regions 117; a plurality of gate dielectric layers 122, a plurality of word lines 120, and a plurality of buried insulating layers 124 sequentially formed within a plurality of word line trenches 120T spanning the plurality of active regions 118 across the substrate 110; an insulating layer pattern (including a first insulating layer pattern 112 and a second insulating layer pattern 114) covering a device isolation layer 116, the plurality of active regions 118, and the plurality of buried insulating layers 124; a plurality of bit line structures 140 located on the insulating layer pattern (including the first insulating layer pattern 112 and the second insulating layer pattern 114); and a plurality of insulating spacer structures 150 respectively covering two corresponding sidewalls of the plurality of bit line structures 140. Multiple gate line structures 140P are located on multiple logic active regions 117; multiple gate insulating spacers 150P respectively cover two corresponding sidewalls of the multiple gate line structures 140P; multiple buried contacts 170 fill the lower portion of the space defined by multiple insulating fences 180 and multiple insulating spacer structures 150, and are connected to the multiple active regions 118; multiple bonding pads 190 fill the upper portion of the space defined by multiple insulating fences 180 and multiple insulating spacer structures 150, and each extends to the upper portion of each bit line structure 140; and multiple capacitor structures 200 include multiple lower electrodes 210, capacitor dielectric layers 220 and upper electrodes 230, and the multiple capacitor structures 200 are connected to the multiple bonding pads 190.

[0093] Multiple insulating barriers 180 may be arranged separately from each other in a second horizontal direction (Y direction) between every two adjacent insulating spacer structures 150, each of the multiple insulating spacer structures 150 covering the sidewalls of the multiple bit line structures 140. Each of the multiple insulating barriers 180 may extend from between the multiple buried contacts 170 to between the multiple mating pads 190.

[0094] The semiconductor memory device 1 may further include word line contact plugs CPE, logic active region contact plugs CPF, gate line contact plugs CPG1, and bit line contact plugs CPG2. The word line contact plugs CPE, logic active region contact plugs CPF, gate line contact plugs CPG1, and bit line contact plugs CPG2 may be formed of the same material.

[0095] Figures 10A to 10G A word line contact plug (CPE), a gate line contact plug (CPG1), a bit line contact plug (CPG2), and three logic active region contact plugs (CPF) are shown. However, the embodiments are not limited to this. For example, the semiconductor memory device 1 may include a plurality of word line contact plugs (CPE), a plurality of gate line contact plugs (CPG1), a plurality of bit line contact plugs (CPG2), and a plurality of logic active region contact plugs (CPF) to correspond to a plurality of word lines 120, a plurality of gate lines 147P, a plurality of bit lines 147, and a plurality of logic active regions 117.

[0096] Each word line contact plug (CPE) can extend to the lower word line layer 120a by penetrating the fill insulation layer (including the first fill insulation layer 172 and the second fill insulation layer 174), the insulation layer pattern (including the first insulation layer pattern 112 and the second insulation layer pattern 114), the buried insulation layer 124, and the upper word line layer 120b. Each logic active area contact plug (CPF) can be connected to the logic active area 117 by penetrating the fill insulation layer (including the first fill insulation layer 172 and the second fill insulation layer 174) and the insulation layer pattern (including the first insulation layer pattern 112 and the second insulation layer pattern 114).

[0097] Each gate line contact plug CPG1 can be connected to the gate line 147P via a through-insulation cover wire 148, and each bit line contact plug CPG2 can extend to the bit line 147 via the through-insulation cover wire 148. According to some embodiments, each gate line contact plug CPG1 and each bit line contact plug CPG2 can be connected to a first metal conductive pattern 145 via the through-insulation cover wire 148 and a second metal conductive pattern 146. According to some other embodiments, each gate line contact plug CPG1 and each bit line contact plug CPG2 can be connected to the second metal conductive pattern 146 via the through-insulation cover wire 148.

[0098] Multiple logic bit lines (BLPs) can be arranged on the insulating cover line 148 and the fill insulating layers (including the first fill insulating layer 172 and the second fill insulating layer 174). Each of the word line contact plugs (CPEs), logic active region contact plugs (CPFs), gate line contact plugs (CPG1s), and bit line contact plugs (CPG2s) can be connected to at least one of the multiple logic bit lines (BLPs). According to some embodiments, the word line contact plugs (CPEs), logic active region contact plugs (CPFs), gate line contact plugs (CPG1s), and bit line contact plugs (CPG2s) can comprise the same material as those included in the multiple logic bit lines (BLPs) and can be integrally formed with the multiple logic bit lines (BLPs). According to some embodiments, the word line contact plugs (CPEs), logic active region contact plugs (CPFs), gate line contact plugs (CPG1s), and bit line contact plugs (CPG2s) can comprise the same material as those included in the multiple bonding pads 190.

[0099] Because the word line contact plug CPE of the example embodiment of the semiconductor memory device 1 according to the inventive concept includes a plug extension PE as its upper part, and the plug extension PE has a larger horizontal width and a larger horizontal area compared with its lower part, the electrical connection between the word line contact plug CPE and the logic bit line BLP can provide improved reliability. While forming the hole extension HE to form the plug extension PE, the bottom surface of the word line contact hole CPHE can be lowered, thus preventing the problem of the word line 120 not being exposed at the bottom of the word line contact hole CPHE.

[0100] Furthermore, because the word line contact hole CPHE extends to the lower word line layer 120a, the word line contact plug CPE can contact both the upper word line layer 120b and the lower word line layer 120a, and therefore can be electrically connected to both the upper word line layer 120b and the lower word line layer 120a. Thus, the reliability of the electrical connection between the word line contact plug CPE and the word line 120a can be improved.

[0101] Figure 11 It is a cross-sectional view used to compare the cross-sections of the contact plugs of a semiconductor memory device according to an embodiment of the inventive concept.

[0102] Reference Figure 11 and Figures 10A to 10G The semiconductor memory device 1 may include a first contact plug CPE, a second contact plug CPF, and a third contact plug CPG. The first contact plug CPE and the second contact plug CPF may be referred to as the word line contact plug CPE and the logic active region contact plug CPF, respectively. The third contact plug CPG may include a gate line contact plug CPG1 and a bit line contact plug CPG2. The gate line contact plug CPG1 and the bit line contact plug CPG2 are substantially identical in shape to each other, except that they are connected to the gate line 147P and the bit line 147, respectively. Figure 11A cross-section of bit line contact plug CPG2 is shown to describe the third contact plug CPG, while gate line contact plug CPG1, which is not described, is not shown.

[0103] The word line contact plug (CPE) can extend from the logic bit line (BLP) to the lower word line layer (120a) by penetrating a portion of the top surface of each word line 120, including a filler insulating layer (including a first filler insulating layer 172 and a second filler insulating layer 174), an insulating layer pattern (including a first insulating layer pattern 112 and a second insulating layer pattern 114), a buried insulating layer 124, and an upper word line layer 120b.

[0104] The word line contact plug CPE may have a plug extension PE. Due to the plug extension PE, the horizontal width and horizontal profile of the upper part of the word line contact plug CPE can be increased. The bottom surface of the plug extension PE may have a vertical level higher than the first vertical level LV1 of the top surface of the second metallic conductive pattern 146. For example, the vertical level of the bottom surface of the plug extension PE may be higher than the first vertical level LV1 of the top surface of the second metallic conductive pattern 146, and lower than the second vertical level LV2 of the top surface of the insulating cover wire 148.

[0105] The side surface of the portion of the word line contact plug CPE adjacent to the top surface of the lower word line layer 120a can be completely surrounded by the upper word line layer 120b. For example, the side surface of the portion of the word line contact plug CPE at a level corresponding to that of the upper word line layer 120b (i.e., the level between the top and bottom surfaces of the upper word line layer 120b) can be completely covered by the upper word line layer 120b. For example, the upper word line layer 120b can contact the side surface of the portion of the word line contact plug CPE adjacent to the top surface of the lower word line layer 120a and extend around the word line contact plug CPE.

[0106] The logic active region contact plug CPF can extend from the logic bit line BLP to the logic active region 117 by penetrating the fill insulation layer (including the first fill insulation layer 172 and the second fill insulation layer 174) and the insulation layer pattern (including the first insulation layer pattern 112 and the second insulation layer pattern 114).

[0107] The third contact plug CPG (i.e., gate line contact plug CPG1) can extend to the gate line 147P through the insulating cover line 148, and the bit line contact plug CPG2 can extend to the bit line 147 through the insulating cover line 148. According to some embodiments, the third contact plug CPG (i.e., gate line contact plug CPG1 and bit line contact plug CPG2) can extend from the logic bit line BLP to the first metal conductive pattern 145 through the insulating cover line 148 and the second metal conductive pattern 146. According to some other embodiments, the third contact plug CPG (i.e., gate line contact plug CPG1 and bit line contact plug CPG2) can extend from the logic bit line BLP to the second metal conductive pattern 146 through the insulating cover line 148.

[0108] The ratio of the horizontal width WEH of the word line contact plug CPE at the second vertical level LV2 to the horizontal width WEL of the word line contact plug CPE at the first vertical level LV1, WEH / WEL, can be greater than each of the ratios of the horizontal width WFH of the logic active region contact plug CPF at the second vertical level LV2 to the horizontal width WFL of the logic active region contact plug CPF at the first vertical level LV1, WFH / WFL, and the ratio of the horizontal width WGH of the third contact plug CPG (i.e., gate line contact plug CPG1 and bit line contact plug CPG2) at the second vertical level LV2 to the horizontal width WGL of the third contact plug CPG (i.e., gate line contact plug CPG1 and bit line contact plug CPG2) at the first vertical level LV1.

[0109] According to some embodiments, the extension length of the word line contact plug CPE from the logic bit line BLP to the substrate 110 can be greater than the extension length of the logic active region contact plug CPF from the logic bit line BLP to the substrate 110, and the extension length of the logic active region contact plug CPF can be greater than the extension length of the third contact plug CPG (i.e., the gate line contact plug CPG1 and the bit line contact plug CPG2). For example, the word line contact plug CPE can extend to a vertical level lower than the vertical level of the logic active region contact plug CPF, and the logic active region contact plug CPF can extend to a vertical level lower than the vertical levels of the gate line contact plug CPG1 and the bit line contact plug CPG2.

[0110] According to some embodiments, the horizontal width WFL of the logic active region contact plug CPF at the first vertical level LV1 can be greater than the horizontal width WEL of the word line contact plug CPE at the first vertical level LV1, and the horizontal width WEL of the word line contact plug CPE at the first vertical level LV1 can be greater than the horizontal width WGL of the third contact plug CPG (i.e., the gate line contact plug CPG1 and the bit line contact plug CPG2) at the first vertical level LV1. However, the embodiments are not limited to this.

[0111] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the claims.

Claims

1. A semiconductor memory device, the semiconductor memory device comprising: The substrate has a memory cell area and a peripheral circuit area, with multiple active areas defined in the memory cell area and at least one logical active area defined in the peripheral circuit area. The word line has a stacked structure of a lower word line layer and an upper word line layer, and extends across the plurality of active regions in a first horizontal direction, wherein a buried insulating layer is located on the word line; Multiple bit line structures are arranged on the multiple active regions, each bit line structure extending in a second horizontal direction perpendicular to the first horizontal direction and having a bit line; Fill the space between the plurality of bit line structures with an insulating layer; and The word line contact plug is electrically connected to the lower word line layer by penetrating the filler insulation layer, the buried insulation layer and the upper word line layer, and has a plug extension in the upper part of the word line contact plug, the plug extension having a horizontal width greater than the horizontal width of the lower part of the word line contact plug.

2. The semiconductor memory device according to claim 1, wherein, The word line contact plug penetrates the buried insulation layer and the upper word line layer, and extends to the lower word line layer.

3. The semiconductor memory device according to claim 2, wherein, The side surface of the portion of the word line contact plug adjacent to the top surface of the lower word line layer is surrounded by the upper word line layer.

4. The semiconductor memory device according to claim 1, in, The bit line structure also has an insulating cover wire that covers the bit line, and the bit line has a stacked structure of a first metallic conductive pattern and a second metallic conductive pattern. The bit line structure also includes a bit line contact plug, which is electrically connected to the bit line by penetrating the insulating cover wire.

5. The semiconductor memory device according to claim 4, further comprising: A gate line structure, disposed on the at least one logic active region, and comprising a gate line with a stacked structure having a first metal conductive pattern and a second metal conductive pattern, wherein an insulating cap line covers the gate line; and The gate line contact plug is electrically connected to the gate line by penetrating the insulating cover wire.

6. The semiconductor memory device according to claim 5, wherein, The insulating layer also fills the space between the bit line structure and the gate line structure. The word line contact plug extends into the word line by penetrating both the filling insulation layer and the buried insulation layer.

7. The semiconductor memory device of claim 6, further comprising: The logic active area contact plug is electrically connected to the at least one logic active area by penetrating the filling insulation layer.

8. The semiconductor memory device of claim 7, further comprising: Multiple logic bit lines are arranged on the filler insulation layer and the insulation cover line. Each of the word line contact plug, logic active region contact plug, bit line contact plug, and gate line contact plug is connected to at least one of the plurality of logic bit lines.

9. The semiconductor memory device according to claim 8, wherein, Each of the word line contact plug, logic active region contact plug, bit line contact plug, and gate line contact plug is integrally formed with at least one of the plurality of logic bit lines.

10. The semiconductor memory device according to claim 7, wherein, The vertical level of the bottom surface of the plug extension is higher than the first vertical level of the top surface of the position line and lower than the second vertical level of the top surface of the insulating cover line.

11. The semiconductor memory device of claim 10, wherein, The ratio of the horizontal width of the word line contact plug at the second vertical level to the horizontal width of the word line contact plug at the first vertical level is greater than the ratio of the horizontal width of each of the logic active area contact plug and the bit line contact plug at the second vertical level to the horizontal width of each of the logic active area contact plug and the bit line contact plug at the first vertical level.

12. A semiconductor memory device, the semiconductor memory device comprising: The substrate has a memory cell area and a peripheral circuit area, with multiple active areas defined in the memory cell area and at least one logical active area defined in the peripheral circuit area. The word line has a stacked structure of a lower word line layer and an upper word line layer, and extends across the plurality of active regions in a first horizontal direction, wherein a buried insulating layer is located on the word line; Multiple bit line structures are arranged on the multiple active regions, each bit line structure extending in a second horizontal direction perpendicular to the first horizontal direction and having a bit line; Fill the space between the plurality of bit line structures with an insulating layer; and The word line contact plug is electrically connected to the lower word line layer by penetrating the filler insulation layer, the buried insulation layer, and the upper word line layer, and has a plug extension in the upper part of the word line contact plug, the plug extension having a horizontal width greater than the horizontal width of the lower part of the word line contact plug. Among them, the side surface of the word line contact plug between the top and bottom surfaces of the upper word line layer is completely surrounded by the upper word line layer.

13. The semiconductor memory device of claim 12, further comprising: A gate line structure is disposed on the at least one logic active region and has a gate line; as well as Bit line contact plugs and gate line contact plugs are electrically connected to the bit line and gate line, respectively. The bit line structure and gate line structure also include insulating cap wires that cover the bit lines and gate lines respectively, and The bit line contact plug and the gate line contact plug are electrically connected to the bit line and the gate line respectively by penetrating the insulating cover wire.

14. The semiconductor memory device according to claim 13, in, The insulating layer also fills the space between the bit line structure and the gate line structure. The word line contact plug extends into the lower word line layer by penetrating the filling insulation layer, the buried insulation layer, and the upper word line layer. The semiconductor memory device further includes a logic active region contact plug, which is electrically connected to the at least one logic active region by penetrating the filling insulating layer.

15. The semiconductor memory device according to claim 14, wherein, The ratio of the horizontal width of the word line contact plug at the second vertical level on the top surface of the insulating cover wire to the horizontal width of the word line contact plug at the first vertical level on the top surface of the bit line is greater than the ratio of the horizontal width of each of the logic active area contact plug and the bit line contact plug at the second vertical level to the horizontal width of each of the logic active area contact plug and the bit line contact plug at the first vertical level.

16. The semiconductor memory device of claim 12, further comprising: Multiple buried contacts are connected to the multiple active areas; as well as Multiple bonding pads are arranged on the multiple buried contacts and extend above the multiple bit line structures. The letter contact plug and the plurality of engagement pads are made of the same material.

17. A semiconductor memory device, the semiconductor memory device comprising: The substrate has a memory cell area and a peripheral circuit area, with multiple active areas defined in the memory cell area and at least one logical active area defined in the peripheral circuit area. Multiple word lines fill multiple word line grooves, each word line groove extending across the multiple active regions in a first horizontal direction to be parallel to each other, each of the multiple word lines having a stacked structure of a lower word line layer and an upper word line layer, wherein multiple buried insulating layers are located on the multiple word lines; Multiple bit line structures are arranged on the multiple active regions, each bit line structure extends in a second horizontal direction perpendicular to a first horizontal direction to be parallel to each other, and each bit line structure has a bit line and an insulating cover line covering the bit line. An insulating layer is filled to fill the space between the plurality of bit line structures; The word line contact plug has a plug extension in the upper part of the word line contact plug, the plug extension having a horizontal width greater than the horizontal width of the lower part of the word line contact plug, the word line contact plug being connected to the lower word line layer by penetrating the filler insulation layer, the buried insulation layer and the upper word line layer, and having a side surface at a horizontal position between the top surface and the bottom surface of the upper word line layer, the side surface being completely covered by the upper word line layer. Multiple buried contacts fill the lower portion of the space between the multiple bit line structures and are connected to the multiple active regions; and Multiple bonding pads fill the upper portion of the space between the multiple bit line structures, extend over the multiple bit line structures, and comprise the same material as the material included in the word line contact plugs.

18. The semiconductor memory device of claim 17, further comprising: A gate line structure is disposed on the at least one logic active region and includes a gate line and an insulating cover line covering the gate line, wherein the gate line comprises the same material as the material included in the bit line. as well as The gate line contact plug is electrically connected to the gate line by penetrating the insulating cover wire.

19. The semiconductor memory device of claim 18, further comprising: The position line contact plug is electrically connected to the position line by penetrating the insulating cover wire; as well as The logic active area contact plug is electrically connected to the at least one logic active area by penetrating the filling insulating layer. The word line contact plug, logic active area contact plug, bit line contact plug, and gate line contact plug are made of the same material.

20. The semiconductor memory device of claim 17, wherein, The upper word line layer includes doped polysilicon, and the lower word line layer includes a metal material, a conductive metal nitride, or a combination of a metal material and a conductive metal nitride.

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