Image sensing device, optical structure and forming method thereof

Abstract

An image sensor, an optical structure and a method for forming the same, wherein a photosensitive element can be formed on the front side of a semiconductor substrate. An optical refractive layer having a first refractive index can be formed on the back side of the semiconductor substrate. A grid structure including an opening is formed on the optical refractive layer. A shielding material layer is formed on the grid structure and the optical refractive layer. The shielding material layer is anisotropically etched using an anisotropic etching process, and the material of the optical refractive layer is also etched to form a non-planar distal surface portion in a physically exposed area of ​​the optical refractive layer, wherein these non-planar distal surface portions include random protrusions. An optically transparent layer can be formed on the non-planar distal surface portion of the optical refractive layer, and the optically transparent layer has a second refractive index different from the first refractive index. The refractive interface refracts incident light to a random direction and improves the quantum efficiency of the photosensitive element.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, and more particularly to a back-illuminated complementary metal-oxide-semiconductor (CMOS) image sensor and a method for forming the same. Background Art

[0002] Semiconductor image sensors are used to sense electromagnetic radiation (e.g., visible light, infrared radiation, and / or ultraviolet light). CMOS image sensors (CIS) and charged-coupled device (CCD) sensors are used in a variety of applications, such as digital cameras or embedded cameras in mobile devices. These devices utilize pixel arrays (which may include light-emitting diodes and transistors) to detect radiation using photogeneration of electron-hole pairs. Backside illuminated (BSI) image sensors are image sensors configured to detect light impinging on the back side of a semiconductor substrate. CMOS circuitry for detecting and processing the photogenerated signals may be formed on the front side of the semiconductor substrate. Summary of the invention

[0003] The present disclosure provides an optical structure, which may include a plurality of photosensitive elements, an optical refractive layer, a grid structure and an optically transparent layer, wherein the plurality of photosensitive elements are located on the front side of a semiconductor substrate. The optical refractive layer is located on the back side of the semiconductor substrate, wherein the optical refractive layer has a first refractive index, and the optical refractive layer may include a plurality of planar distal surface portions and a plurality of non-planar distal surface portions, and these non-planar distal surface portions may include a plurality of random protrusions. The grid structure is located on these planar distal surface portions and may include a plurality of openings, wherein these openings are located on these non-planar distal surface portions. The optically transparent layer extends vertically and passes through these openings in the grid structure and contacts these non-planar distal surface portions, wherein the optically transparent layer may have a second refractive index different from the first refractive index. By using these non-planar distal surface portions to provide a refractive interface, incident light can be refracted in a plurality of random directions.

[0004] According to another aspect of the present disclosure, an image sensor is provided, which may include a pixel array, an optical refractive layer, a grid structure, and an optically transparent layer. The pixel array is located on a semiconductor substrate, wherein each pixel of the pixel array may include at least one pixel, each of the at least one pixel may include a corresponding photosensitive element and a corresponding sensing circuit, and the photosensitive element and the sensing circuit are located on the front surface of the semiconductor substrate. The optical refractive layer is located on the back side of the semiconductor substrate, wherein the optical refractive layer has a first refractive index, the optical refractive layer may include a plurality of planar distal surface portions and a plurality of non-planar distal surface portions, and these non-planar distal surface portions may include a plurality of random protrusions. In a top view, each of these non-planar distal surface portions overlaps with the corresponding photosensitive elements in area. The grid structure is located on these planar distal surface portions, wherein the grid structure may include a plurality of openings, and these openings are located above these non-planar distal surface portions. The optically transparent layer extends vertically and passes through these openings in the grid structure, wherein the optically transparent layer has a second refractive index different from the first refractive index.

[0005] According to another aspect of the present disclosure, a method for forming an optical structure is proposed. First, a plurality of photosensitive elements are formed on the front side of a semiconductor substrate. Then, an optical refractive layer having a first refractive index is formed on the back side of the semiconductor substrate. Then, a grid structure is formed on the distal surface of the optical refractive layer, wherein the grid structure may include a plurality of openings, and these openings are located above a corresponding one of these photosensitive elements. Next, a shielding material layer is formed on the grid structure and the optical refractive layer. Then, an anisotropic etching process is used to anisotropically etch the shielding material layer, and the material of the optical refractive layer is etched simultaneously to form a plurality of non-planar distal surface portions on a plurality of physically exposed areas of the optical refractive layer, wherein the plurality of non-planar distal surface portions may include a plurality of random protrusions. Then, an optically transparent layer is formed on these non-planar distal surface portions of the optical refractive layer, wherein the optically transparent layer has a second refractive index, and the second refractive index is different from the first refractive index. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure is best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, as is standard practice in the industry, many features are only for illustration and are not drawn to scale. In fact, for clarity of discussion, the dimensions of many features may be scaled arbitrarily.

[0007] Figure 1A is a top view showing a first structure of a pixel array for an image sensor according to an embodiment of the present disclosure;

[0008] Figure 1B is a top view showing a second structure of a pixel array for an image sensor according to an embodiment of the present disclosure;

[0009] Figure 2A is a top view of a front sensing element in a sub-pixel region in an exemplary structure according to an embodiment of the present disclosure;

[0010] Figure 2B It is along Figure 2A A vertical cross-sectional view of an exemplary structure taken along a vertical plane BB';

[0011] Figure 3 is a vertical cross-sectional view of an exemplary structure after forming a metal interconnect structure in an interconnect level dielectric layer and connecting to a supporting substrate according to an embodiment of the present disclosure;

[0012] Figure 4 is a vertical cross-sectional view showing an exemplary structure after thinning of a semiconductor substrate according to an embodiment of the present disclosure;

[0013] Figure 5 is a vertical cross-sectional view of an exemplary structure after deep trench formation on the back side of a semiconductor substrate according to one embodiment of the present disclosure;

[0014] Figure 6 is a vertical cross-sectional view of an exemplary structure after the hard mask layer and the liner dielectric layer are removed according to one embodiment of the present disclosure;

[0015] Figure 7 is a vertical cross-sectional view of an exemplary structure after the formation of a dielectric metal oxide liner and a dielectric insulation layer according to an embodiment of the present disclosure;

[0016] Figure 8 is a vertical cross-sectional view showing an exemplary structure after a deep trench isolation structure is formed according to an embodiment of the present disclosure;

[0017] Fig. 9 is a vertical cross-sectional view showing an exemplary structure after the anti-reflection coating, the optical refractive layer, the dielectric grid material layer, the metal reflective material layer and the patterned photoresist layer are formed according to an embodiment of the present disclosure;

[0018] Fig. 10A is a vertical cross-sectional view of an exemplary structure after the composite grid structure according to one embodiment of the present disclosure is formed;

[0019] Fig. 10B yes Fig. 10A The hinged vertical plane A-A' corresponds to Fig. 10A The plane of the vertical section;

[0020] Fig.11A is a vertical cross-sectional view showing an exemplary structure after a shielding material layer and a patterned photoresist layer are formed according to an embodiment of the present disclosure;

[0021] Fig. 11B yes Fig.11A The hinged vertical plane A-A' corresponds to Fig.11A The plane of the vertical section;

[0022] Fig. 11C It is along Fig. 11B A vertical cross-sectional view of an exemplary structure taken along a vertical plane CC';

[0023] Fig. 12A is a vertical top view of an exemplary structure after a non-planar distal surface portion is formed on an optical refractive layer according to an embodiment of the present disclosure, wherein the non-planar distal surface portion is formed by anisotropically etching the masking material layer and also etching the top of the optical refractive layer;

[0024] Fig. 12B yes Fig. 12A The hinged vertical plane A-A' corresponds to Fig. 12A The plane of the vertical section;

[0025] Fig. 12C It is along Fig. 12B A vertical cross-sectional view of an exemplary structure taken along a vertical plane CC';

[0026] Fig.12D is a scanning electron microscope image showing a top surface of an optical refractive layer of a test sample according to an embodiment of the present disclosure;

[0027] Fig.13A is a vertical cross-sectional view of an exemplary structure after the photoresist layer is removed according to an embodiment of the present disclosure;

[0028] Fig. 13B yes Fig.13A The hinged vertical plane A-A' corresponds to Fig.13A A plane of vertical section perspective;

[0029] Fig. 13C It is along Fig. 13B A vertical cross-sectional view of an exemplary structure taken along a vertical plane CC';

[0030] Fig.14 is a vertical cross-sectional view showing an exemplary structure of an optically transparent layer, a color filter and a lens after being formed according to an embodiment of the present disclosure;

[0031] Fig.15A is a vertical cross-sectional view of an exemplary structure after the carrier substrate is removed according to an embodiment of the present disclosure;

[0032] Fig. 15B yes Fig.15Aanother vertical cross-sectional view of an exemplary structure;

[0033] Fig.16 FIG. 4 is a flow chart illustrating an exemplary process sequence for forming an image sensor according to an embodiment of the present disclosure.

[0034]

Explanation of symbols

[0035] 500,510:Semiconductor substrate

[0036] 600: front side sensing element

[0037] 601: substrate semiconductor layer

[0038] 602: second conductive type syringe photodiode layer

[0039] 603: first conductive type syringe photodiode layer

[0040] 605: transfer gate

[0041] 607: first conductivity type well

[0042] 608: floating diffusion area

[0043] 609: front surface

[0044] 612: Active area

[0045] 614: Gate dielectric

[0046] 615: Gate electrode

[0047] 620: Shallow Trench Isolation Structure

[0048] 630: Transfer transistor

[0049] 640: Reset transistor

[0050] 650: Source follower transistor

[0051] 660: Select transistor

[0052] 670:Internal connection level dielectric layer

[0053] 680:Metal Interconnect Structure

[0054] 682:Metal Interlayer Structure

[0055] 684: Metal wire structure

[0056] 689: Buffer layer

[0057] 690: Carrying substrate

[0058] 709: back surface

[0059] 711: liner dielectric layer

[0060] 712: Hard mask layer

[0061] 719: Deep Groove

[0062] 720: Deep trench isolation structure

[0063] 721,721L: Dielectric Metal Oxide Liner

[0064] 722,722L: Dielectric insulation layer

[0065] 732: Anti-reflective coating

[0066] 734: Optical refractive layer

[0067] 734N: Non-planar distal surface portion

[0068] 734R: Random protrusions

[0069] 740: Grid structure

[0070] 742: Dielectric grid structure

[0071] 742L: Dielectric grid material layer

[0072] 744:Metal Grid Structure

[0073] 744L: Metal reflective material layer

[0074] 747: Photoresist layer

[0075] 750, 750L: shielding material layer

[0076] 757: Photoresist layer

[0077] 770: Optically transparent layer

[0078] 780: Color filter

[0079] 781: Type I Color Filter

[0080] 782: Type II Color Filter

[0081] 783: Type III Color Filter

[0082] 790: Optical lens

[0083] 800: sub-pixel

[0084] 801: First pixel

[0085] 801D,802D,803D: Detection area

[0086] 801S, 802S, 803S: Sensing circuit area

[0087] 802: Second pixel

[0088] 803: The third pixel

[0089] 900: Pixels

[0090] 1000: Array

[0091] 1610,1620,1630,1640,1650,1660: Steps DETAILED DESCRIPTION

[0092] The following disclosure provides various embodiments or illustrations to implement different features of the present disclosure. The specific examples of components and configurations described below are used to simplify the present disclosure. As can be imagined, these descriptions are only illustrative and are not intended to limit the present disclosure. For example, in the description below, forming a first feature on or above a second feature may include certain embodiments in which the first and second features are directly in contact with each other; it may also include certain embodiments in which other features are formed between the first and second features, so that the first and second features may not be in direct contact. In addition, the present disclosure may reuse component symbols and / or labels in multiple embodiments. This repetition is based on the purpose of simplicity and clarity, and does not itself represent the relationship between the different embodiments and / or configurations discussed.

[0093] Furthermore, spatially corresponding terms, such as "under," "below," "below," "above," and the like, may be used herein to facilitate descriptions of the relationship between an element or feature depicted in a figure and one or more elements or features. These spatially corresponding terms are intended to encompass a variety of different orientations of the device during use or operation in addition to the orientation depicted in the figure. The device may be placed in other orientations (e.g., rotated 90 degrees or in other orientations), and the spatially corresponding descriptions used in the present disclosure may be interpreted accordingly.

[0094] Generally speaking, the structure and method disclosed herein can be used to improve the quantum efficiency of an image sensor, wherein the quantum efficiency is the proportion of photons that produce electron-hole pairs among all photons that impact the photoreactive material portion. The optical refractive layer of the photon has a random surface roughness, which can randomly refract the photons that impact the photosensitive element, thereby improving the quantum efficiency of the photosensitive element.

[0095] Increasing the probability of photon absorption in a photosensitive element can have a beneficial effect on the refractive structure in the photon light path of the image sensor. For example, the article "Broadband optical absorption by tunable Mie resonances in silicon nanocone arrays" published by Wang Ziyi's team in Scientific Reports Volume 5, Article No. 7810 in 2015 describes how refractive column arrays can increase the absorption coefficient of photons of various wavelengths in the optical range. However, manufacturing such a periodic column array can be an expensive process because it requires deep ultraviolet (DUV) etching to etch and pattern the periodic structure. Multiple embodiments of the present disclosure use an anisotropic etching process to manufacture a random reflective surface including multiple random protrusions to form a random refractive surface with lateral dimensions on the order of 100 nm. In the underlying optically transparent layer material, an etch chemistry is used to amplify process non-uniformities, wherein the process non-uniformities cause local variations in the thickness of the etching in the mask material layer, and the etch chemistry etches the optically transparent material at a greater rate than the material of the mask material layer. The random refractive surface is provided in the optical path of the impinging photons of the image sensor to increase the quantum efficiency of the image sensor.

[0096] according to Figure 1A and Figure 1B , which are top views of a first configuration of an array 1000 of pixels 900 and a second configuration of an array 1000 of pixels 900 for an image sensor. The image sensor may be a backside illuminated (BSI) image sensor. However, it should be noted that embodiments of the present disclosure may be used for frontside illuminated (FSI) image sensors.

[0097] Each pixel 900 represents a minimum unit area for generating an image by an image sensor. The pixel array area refers to an area of ​​the array 1000 that includes a plurality of pixels 900. The pixels 900 in the pixel array area may be arranged in rows and columns. For example, the pixel array area may include M rows and N columns, where M and N are in the range of 1 to 2. 16 Integer, for example, from 2 8 to 2 14 The rows of pixels 900 are numbered with consecutive integers ranging from 1 to M, and the columns of pixels 900 are numbered with consecutive integers ranging from 1 to N. Pixel Pij represents the pixel 900 at the i-th row and j-th column.

[0098] Each pixel 900 includes at least one photosensitive element, wherein at least one photosensitive element is configured to detect radiation in a given wavelength range. Each pixel 900 may include multiple photosensitive elements, wherein the multiple photosensitive elements are configured to detect radiation in corresponding wavelength ranges, and the corresponding wavelength ranges of the multiple photosensitive elements may be different. In one embodiment, each pixel 900 may include multiple sub-pixels, and each sub-pixel respectively includes a combination of a photosensitive element and an electronic circuit, wherein the combination of the photosensitive element and the electronic circuit is configured to detect radiation impinging on the photosensitive element. For example, the pixel 900 may include a sub-pixel configured to detect radiation in a red wavelength range (such as a range substantially from 635nm to 700nm), a sub-pixel configured to detect radiation in a green wavelength range (such as a range substantially from 520nm to 560nm), and a sub-pixel configured to detect radiation in a blue wavelength range (such as a range substantially from 450nm to 490nm). Such sub-pixels are respectively referred to as red sub-pixels, green sub-pixels, and blue sub-pixels.

[0099] Generally speaking, the pixel 900 generates information based on the impact radiation of the unit detection area. When the impact radiation in a specific wavelength range is detected in the unit detection area, the sub-pixel generates information based on the intensity of the impact radiation. The monochrome pixel 900 may include only one sub-pixel. The pixel 900 configured to detect the spectral distribution of the impact radiation includes a plurality of sub-pixels, wherein the plurality of sub-pixels have at least two different detection wavelength ranges. The light sensing element of the pixel array area may include a plurality of photodiodes, complementary metal oxide semiconductor (CMOS) image sensors, charge coupled device (CCD) sensors, active sensors, passive sensors, other applicable sensors or combinations thereof.

[0100] See also Figure 2A and Figure 2B , which illustrates a front side sensing element 600 in a sub-pixel region of an image sensor. The semiconductor substrate 500 includes a substrate semiconductor layer 601. The front side sensing element 600 includes all elements of an image sensor that can be formed on the front side surface 609 of the semiconductor substrate 500 or formed in the substrate semiconductor layer 601. Each sub-pixel includes a photosensitive element and a sensing circuit for the photosensitive element. A collection of sub-pixels can be used as a pixel, and the pixel array 1000 can be as follows Figure 1A or Figure 1B The arrays may be arranged as shown, or in any suitable array configuration to form an image sensor.

[0101] Each sub-pixel may be formed in or on a substrate semiconductor layer 601, wherein the substrate semiconductor layer 601 has a front surface 609 and a back surface. The substrate semiconductor layer 601 may include materials such as silicon, germanium, silicon-germanium alloys, compound semiconductor materials, or any semiconductor material having a band gap, wherein the energy of the band gap does not exceed the energy of the photons to be detected. The material in the substrate semiconductor layer 601 may be selected based on the energy range of the photons to be detected by the sub-pixels. In one embodiment, the substrate semiconductor layer 601 may include a single silicon crystal. Commercially available silicon crystal semiconductor substrates may be used for the semiconductor substrate 500. The semiconductor substrate 500 of this process step has a sufficient thickness to withstand multiple standard complementary metal-oxide-semiconductor (CMOS) process steps. For example, the thickness of the semiconductor substrate 500 may range substantially from 200 microns to 1 mm, although lesser or greater thicknesses may also be used.

[0102] The top of the substrate semiconductor layer 601 may be appropriately doped to form a first conductivity type, wherein the first conductivity type may be p-type or n-type. For example, an epitaxial semiconductor deposition process may be performed to form a single crystal epitaxial semiconductor material layer on the upper portion of the substrate semiconductor layer, wherein the atomic concentration of the first conductivity type dopant is substantially in the range of 1.0×10 13 / cm 3 to 1.0×10 16 / cm 3 , although lesser or greater atomic concentrations may be used. The thickness of the single crystal epitaxial semiconductor material layer is substantially in the range of 1 micron to 10 microns.

[0103] Ion implantation is performed around the region where the shallow trench isolation structure 620 may be subsequently formed to form a first conductivity type well 607. In the first conductivity type well 607, the atomic concentration of the first conductivity type dopant may be substantially in the range of 1.0×10 15 / cm 3 to 1.0×10 18 / cm 3 , although lesser or greater atomic concentrations may be used. Shallow trench isolation structures 620 may be formed to provide electrical isolation between different elements of the sub-pixel.

[0104] The layer stack includes a gate dielectric layer and a gate electrode layer, and by depositing and patterning the layer stack, a gate structure (including gate dielectric 614, transfer gate 605, gate electrode 615) can be formed on the front side surface 609 of the semiconductor substrate 500. Each patterned portion of the layer stack constitutes a gate structure (including gate dielectric 614, transfer gate 605, gate electrode 615), wherein the gate structure (including gate dielectric 614, transfer gate 605, gate electrode 615) includes a transfer gate structure (including gate dielectric 614, transfer gate 605) and a control gate structure (including gate dielectric 614, gate electrode 615). The transfer gate structure (including gate dielectric 614, transfer gate 605) is the gate structure of the transfer transistor 630, and the transfer gate structure (including gate dielectric 614, transfer gate 605) includes a stack of gate dielectric 614 and transfer gate 605. Each control gate structure (including gate dielectric 614, gate electrode 615) includes a corresponding layer stack of gate dielectric 614 and gate electrode 615 of other transistors in the sensing circuit, wherein the sensing circuit may include reset transistor 640, source follower transistor 650, select transistor 660 and other suitable transistors. The transistors are used to amplify the signal generated by the light sensing element of the sub-pixel.

[0105] The second conductivity type dopant can be embedded through the front side surface 609 of the semiconductor substrate 500 by at least one ion implantation process. The second conductivity type is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, the second conductivity type is n-type, and vice versa. Different doped regions doped with the second conductivity type can be formed by at least one ion implantation process. The second conductivity type syringe photodiode layer 602 can be formed under the front side surface 609 of the semiconductor substrate 500, so that in a top view, the periphery of the second conductivity type syringe photodiode layer 602 is located above the edge of the transfer gate 605. Different active regions (including: floating diffusion region 608, active region 612) with second conductivity type doping can be formed, wherein the different active regions include a floating diffusion region 608 as a drain region of the transfer transistor 630. During sensing (e.g., when the sub-pixel actively detects photon impact on the sub-pixel in order to obtain a frame or take a picture), the second conductive type syringe photodiode layer 602 accumulates charges (assuming that the second conductive type is n-type, the charges may be, for example, electrons), and the second conductive type syringe photodiode layer 602 serves as the source region of the transfer transistor 630. The active region 612 includes the source and drain regions of multiple transistors in the sensing circuit (including the reset transistor 640, the source follower transistor 650, and the select transistor 660).

[0106] By ion implantation of the first conductive type dopant, the first conductive type syringe photodiode layer 603 can be directly formed on top of the second conductive type syringe photodiode layer 602. The first conductive type syringe photodiode layer 603 can suppress interface depletion between the second conductive type syringe photodiode layer 602 and the first conductive type syringe photodiode layer 603, and electrically stabilize the second conductive type syringe photodiode layer 602.

[0107] An interconnect level dielectric layer 670 may be formed on the front side surface 609 of the semiconductor substrate 500, and a metal interconnect structure 680 (including a metal line structure 684 and a metal via structure 682) connecting nodes of different transistors (including a transfer transistor 630, a reset transistor 640, a source follower transistor 650, and a select transistor 660) may be formed in each sub-pixel. The interconnect level dielectric layer 670 may include a corresponding dielectric material, such as undoped silica glass, doped silica glass, organic silica glass, porous dielectric material, or a combination thereof. A dielectric liner including different dielectric materials (such as silicon nitride, silicon oxynitride, silicon oxide carbide, and / or dielectric metal oxide) may be selectively applied in the interconnect level dielectric layer 670. A plurality of metal interconnect structures 680 may include different metal via structures 682 and a plurality of metal line structures 684. For example, the floating diffusion region 608 may be connected to the gate electrode 615 of the source follower transistor 650 through a subset of the metal interconnect structures 680. The light sensing element may include a transfer transistor 630, and the light sensing element may be connected to a sensing circuit including other transistors (including a reset transistor 640, a source follower transistor 650, and a select transistor 660).

[0108] according to Figure 3 , additional interconnect-level dielectric layers 670 and additional metal interconnect structures 680 may be formed on the front side of the semiconductor substrate 500. The front side of the semiconductor substrate 500 components, the interconnect-level dielectric layers 670 and the structures formed therein may be bonded to a carrier substrate 690. The carrier substrate 690 may be temporarily attached to the components of the semiconductor substrate 500 and the interconnect-level dielectric layers 670 to ensure subsequent thinning of the semiconductor substrate 500 and subsequent processing of the thinned semiconductor substrate 500 components and the interconnect-level dielectric layers 670. The carrier substrate 690 may include a semiconductor material, an insulating material, or a metal material, and the thickness of the carrier substrate 690 may range substantially from 300 microns to 1 millimeter, although lesser or greater thicknesses may also be used.

[0109] Any suitable bonding method may be used to bond the carrier substrate 690 to the front side of the interconnect-level dielectric layer 670. Exemplary bonding methods for bonding the carrier substrate 690 to the interconnect-level dielectric layer 670 include, but are not limited to, oxide-to-oxide bonding, oxide-to-semiconductor bonding, fusion bonding, hybrid bonding, anodic bonding, direct bonding, other suitable bonding processes, and / or combinations thereof. Other suitable bonding techniques may be used within the contemplated scope of the present disclosure. A bonding buffer layer 689 may be optionally used to bond the interconnect-level dielectric layer 670 to the carrier substrate 690, wherein the bonding buffer layer 689 comprises an intermediate bonding material (e.g., silicon oxide, silicon nitride, or a semiconductor material).

[0110] according to Figure 4 The back side of the semiconductor substrate may be thinned by, for example, grinding, polishing, an isotropic etching process and / or an anisotropic etching process. During the thinning process, the carrier substrate 690 may mechanically support the semiconductor substrate 500. In one embodiment, the semiconductor substrate 500 may be thinned so that the thickness of the semiconductor substrate 500 substantially ranges from 1 micron to 12 millimeters, such as 1.5 microns to 8 microns. The thinned semiconductor substrate 510 or semiconductor substrate 500 refers to the semiconductor substrate 500 that has been thinned by the thinning process. The deep trench is subsequently formed on the thinned semiconductor substrate 510, and the thickness of the thinned semiconductor substrate 510 may be determined by the maximum depth of the deep trench. In one embodiment, the deep trench is subsequently formed on the back side of the semiconductor substrate 510, and the thickness of the thinned semiconductor substrate 510 may be a thickness that allows the deep trench to extend to the near side surface of the shallow trench isolation structure 620. The backside surface 709 of the thinned semiconductor substrate 510 may be polished to form a planar horizontal surface parallel to the frontside surface 609 of the thinned semiconductor substrate 510. The exemplary structure may then be flipped upside down for further processing.

[0111] according to Figure 5 , an optional pad dielectric layer 711 and a hard mask layer 712 may be formed on the backside surface 709 of the semiconductor substrate 510. If there is an optional pad dielectric layer 711, the optional pad dielectric layer 711 includes a silicon oxide layer, and the thickness of the optional pad dielectric layer 711 ranges substantially from 5nm to 50nm. The hard mask layer 712 includes an etching mask material, wherein the etching mask material of the corresponding pad dielectric layer 711 and / or the semiconductor substrate 510 can be selectively removed later. For example, the hard mask layer 712 may include silicon nitride, borosilicate glass, or a metal material. The thickness of the hard mask layer 712 may range substantially from 50nm to 800nm, although lesser or greater thicknesses may also be used.

[0112] A photoresist layer (not shown) may be disposed on the hard mask layer 712, and the photoresist layer may be etched and patterned to form openings, which may generally replicate the pattern of the shallow trench isolation structures 620 located below. A first etching process may be performed to transfer the pattern in the photoresist layer to the hard mask layer 712 and the optional liner dielectric layer 711. A second anisotropic etching process may be performed to etch the unmasked portion of the semiconductor substrate 510, wherein the second anisotropic etching process penetrates the semiconductor substrate 510 to transfer the pattern of the openings in the photoresist layer and the hard mask layer 712 to the corresponding top surfaces of the plurality of shallow trench isolation structures 620. The depth of the deep trench 719 may range substantially from 1 micron to 10 microns, such as from 1.5 microns to 8 microns. During the second anisotropic etching process, the photoresist layer may be completely consumed. The deep trench 719 may be formed and penetrate the semiconductor substrate 510.

[0113] The deep trenches 719 may define the area of ​​the sub-pixels 800. Each sub-pixel 800 may be located in a sub-pixel area, wherein the sub-pixel area is located in a pixel area, in other words, each sub-pixel 800 is located in a pixel area. For example, the pixel area may include a first sub-pixel 801 area, a second sub-pixel 802 area, and a third sub-pixel 803 area. In an illustrative example, the first sub-pixel 801 may be formed in an area including a photosensitive element for detecting green light, the second sub-pixel 802 may be formed in an area including a photosensitive element for detecting red light, and the third sub-pixel 803 may be formed in an area including a photosensitive element for detecting blue light. Each sub-pixel 800 may include a volume accommodating a patterned columnar portion of a semiconductor substrate 510, wherein adjacently connected deep trenches 719 laterally surround the semiconductor substrate 510. The pixel area of ​​a pixel includes all sub-pixel areas for a set of sub-pixels 800, and the sub-pixels 800 are included in the pixel.

[0114] according to Figure 6 , the hard mask layer 712 of the corresponding semiconductor substrate 510, the liner dielectric layer 711 and the shallow trench isolation structure 620 can be selectively removed. In an illustrative example, if the hard mask layer 712 includes silicon nitride, the hard mask layer 712 can be removed by a wet etching process using hot phosphoric acid. Subsequently, the liner dielectric layer 711 of the corresponding semiconductor substrate 510 can be selectively removed.

[0115] according to Figure 7, the dielectric metal oxide liner 721L may be conformally disposed on the physically exposed surface of the semiconductor substrate 510. When the shallow trench isolation structure 620 is physically exposed to the deep trench 719, the dielectric metal oxide liner 721L may be formed on the sidewalls of the deep trench 719, on the backside surface 709 of the semiconductor substrate 510, and on the shallow trench isolation structure 620. The dielectric metal oxide material contained in the dielectric metal oxide liner 721L has a dielectric constant substantially greater than 7.9 (i.e., a "high-k" dielectric material). Other suitable high-k materials may also be used. For example, the dielectric constant of the high-k dielectric material may substantially range from 7.9 to 100. Exemplary dielectric metal oxide materials that may be used for the dielectric metal oxide liner 721L include hafnium oxide, aluminum oxide, zirconium oxide, magnesium oxide, calcium oxide, yttrium oxide, tantalum oxide, strontium oxide, titanium oxide, lanthanum oxide, barium oxide, or combinations thereof. The contemplated scope of the present disclosure includes other suitable materials. The dielectric metal oxide liner 721L may be deposited using a chemical vapor deposition process or atomic layer deposition (ALD). The thickness of the dielectric metal oxide liner 721L may range substantially from 2 nm to 6 nm, although lesser or greater thicknesses may also be used.

[0116] The dielectric metal oxide liner 721L may be formed to provide negative charge traps. For example, the dielectric metal oxide liner 721L may be deposited using a non-stoichiometric oxygen-rich composition, or the dielectric metal oxide liner 721L may be surface treated, such as using a plasma, to form a non-stoichiometric oxygen-rich surface compression. In this example, the dielectric metal oxide liner 721L may include an oxygen-rich dielectric metal oxide material, thereby accumulating negative charges in the dielectric metal oxide liner 721L, wherein the oxygen-rich dielectric metal oxide material has negatively charged interstitial oxygen atoms and / or suspended or broken metal oxide bonds. In one illustrative example, the surface density of accumulated negative charges in the dielectric metal oxide liner 721L may range substantially from 5.0×10 9 to 1.0×10 14 electrons, such as 1.0×10 per square centimeter. 10 to 2.0×10 13 Electrons. The dielectric metal oxide material used for the dielectric metal oxide liner 721L can accumulate more negative charges than other dielectric materials (e.g., silicon nitride or silicon oxide). The negative charge of the dielectric metal oxide liner 721L increases hole accumulation in the interface portion of the first conductivity type well 607 and the base semiconductor layer 601 of the semiconductor substrate 510. A depletion region can be formed in a portion of the first conductivity type well 607 and the base semiconductor layer 601 of the semiconductor substrate 510 near the dielectric metal oxide liner 721L. The depletion region reduces dark current and / or white pixels of the image sensor.

[0117] The dielectric insulating layer 722L may be formed by conformally depositing a dielectric material in the remaining volume of the deep trench 719. The dielectric insulating layer 722L includes a dielectric material such as undoped silica glass, doped silica glass (e.g., borosilicate glass), or a combination thereof. The deep trench 719 may be filled (with or without seams and / or encapsulation cavities) using a combination of a dielectric metal oxide liner 721L and a dielectric insulating layer 722L.

[0118] according to Figure 8 , through the planarization process, the horizontal portion of the dielectric insulating layer 722L and the dielectric metal oxide liner 721L can be removed from the backside surface 709 of the semiconductor substrate 510. The dielectric insulating layer 722L and the horizontal portion of the dielectric metal oxide liner 721L can be removed by using a recess etching and / or chemical mechanical planarization process. In one embodiment, the dielectric metal oxide liner 721 can be used as an etch stop layer in the recess etching process for removing the horizontal portion of the dielectric insulating layer 722, and the dielectric metal oxide liner 721 can be used as a stop layer in the chemical mechanical planarization process for removing the horizontal portion of the dielectric insulating layer 722. The unidirectional etching process (e.g., wet etching process) etches the material of the dielectric metal oxide liner 721 and selectively etches to the semiconductor material of the semiconductor substrate 510. By performing this unidirectional etching process, the horizontal portion of the dielectric metal oxide liner 721 located on the backside surface 709 of the semiconductor substrate 510 can be removed successively. The deep trench isolation structure 720 refers to the dielectric metal oxide liner 721 and the remaining vertical extension of the dielectric insulation layer 722 used to fill the deep trench 719 .

[0119] Subsequently, according to Fig. 9 On the back surface 709 of the semiconductor substrate 510, an optional antireflective coating (ARC) layer 732, an optical refractive layer 734, a dielectric grid material layer 742L and a metal reflective material layer 744L may be deposited.

[0120] The optional anti-reflective coating layer 732 may include an anti-reflective coating material, wherein the anti-reflective coating material reduces reflection between the semiconductor material of the semiconductor substrate 510 and the material layer (i.e., the optical refractive layer 734) located above the semiconductor substrate 510. If there is an optional anti-reflective coating layer 732, the refractive index of the anti-reflective coating layer 732 may be between the refractive index of the semiconductor material of the semiconductor substrate 510 and the refractive index of the optical refractive layer 734. The optional anti-reflective coating layer 732 may include a single material layer and a multi-layer stack, wherein the multi-layer stack has a gradually changing refractive index. The optional anti-reflective coating layer 732 includes an optically transparent material, and the optional anti-reflective coating layer 732 may selectively include a semiconductor material, an insulating material, a conductive material, and / or a polymer material. The thickness of the anti-reflective coating layer 732 may substantially range from 50 nm to 300 nm, although smaller or larger thicknesses may also be used.

[0121] The optical refractive layer 734 may include a semiconductor material (e.g., silicon, germanium, silicon-germanium alloy, or III-V compound semiconductor) or a dielectric material (e.g., silicon oxide, silicon oxynitride, silicon nitride) or a dielectric metal oxide (e.g., aluminum oxide). The optical refractive layer 734 may include a material that is conducive to forming a groove in a subsequent anisotropic etching process, wherein the groove has a high aspect ratio. The optical refractive layer 734 may form an unpatterned (blank) material layer, wherein the unpatterned (blank) material layer has two horizontal plane surfaces, and the two horizontal plane surfaces are parallel to the back surface 709 of the semiconductor substrate 510. The distal surface of the optical refractive layer 734 may be the one of the two horizontal plane surfaces of the optical refractive layer 734 that is farther from the semiconductor substrate 510, in other words, the upper surface of the optical refractive layer 734.

[0122] The dielectric grid material layer 742L may include a dielectric material such as silicon oxide, a porous dielectric material, polyimide, or other dielectric material. The thickness of the dielectric grid material layer ranges substantially from 50 nm to 500 nm, although lesser or greater thicknesses may also be used. The metal reflective material layer 744L may include a metal material having a high reflectivity. For example, the metal reflective material layer 744L may include silver, aluminum, copper, gold, or other metal material with a high reflectivity. The thickness of the metal reflective material layer 744L ranges substantially from 50 nm to 500 nm, although lesser or greater thicknesses may also be used.

[0123] A photoresist layer 747 may be coated on the metal reflective material layer 744L, and the patterned photoresist layer 747 may be etched to form an opening in the region of the second conductive type syringe photodiode layer 602 (i.e., in the region of the photosensitive element, where the photosensitive element includes a corresponding PN junction between the second conductive type syringe photodiode layer 602 and the first conductive type well 607). The photoresist layer 747 may or may not cover the region of the transistors of the sensing circuit (e.g., the reset transistor 640, the source follower transistor 650, and the select transistor 660).

[0124] according to Fig. 10A and Fig. 10B , the portions of the dielectric grid material layer 742L and the metal reflective material layer 744L that are not covered by the patterned portion of the photoresist layer 747 are etched to form openings, wherein the openings penetrate the dielectric grid material layer 742L and the metal reflective material layer 744L. The remaining portion of the dielectric grid material layer 742L forms the dielectric grid structure 742, and the remaining portion of the metal reflective material layer 744L forms the metal grid structure 744. The composite grid structure refers to a grid structure 740 formed by stacking the dielectric grid structure 742 and the metal grid structure 744.

[0125] The grid structure 740 may be located on the periphery of the second conductive type syringe photodiode layer 602, and the grid structure 740 defines the light collection area of ​​each photosensitive element, wherein the photosensitive element is located in a corresponding sub-pixel 800. The pixel 900 may include a set of sub-pixels, wherein the sub-pixels are configured to sense different wavelengths. Each pixel 900 may be located in a corresponding pixel area, wherein the pixel area includes a set of sub-pixels 800. For example, the pixel 900 may include at least one instance of a first sub-pixel 801, at least one instance of a second sub-pixel 802, and at least one instance of a third sub-pixel 803. In an illustrative example, the pixel may include a first sub-pixel 801 located in the first sub-pixel area (such as a green sub-pixel), two second sub-pixels 802 located in the second sub-pixel area (such as two red sub-pixels), and a third sub-pixel 803 located in the third sub-pixel area (such as a blue sub-pixel). In general, the pixel 900 may include a combination of at least two sub-pixels 800, wherein at least two sub-pixels 800 are configured to detect light in different wavelength bands. Alternatively, the image sensor may be a monochrome image sensor including a single type of sub-pixel 800. In this case, each pixel 900 may include only one type of sub-pixel 800.

[0126] In general, the grid structure 740 includes at least one metal grid structure 744, and the metal grid structure 744 has a reflective sidewall. The grid structure 740 may include a composite grid structure, wherein the composite grid structure has a vertically stacked metal grid structure 744, and the metal grid structure 744 has a reflective sidewall and a dielectric grid structure 742. The grid structure 740 may be formed on the distal surface of the optical refractive layer 734. The grid structure 740 includes an opening, wherein the opening is located above the corresponding photosensitive element (including: transfer transistor 630). The planar distal surface portion of the distal surface of the optical refractive layer 734 is connected to the bottom surface of the grid structure, and the planar distal surface portion of the distal surface of the optical refractive layer 734 is the planar distal surface portion of the optical refractive layer 734. During the anisotropic etching process of patterning the grid structure, the portion of the distal surface of the optical refractive layer 734 that is not in contact with the grid structure 740 may be laterally and vertically recessed relative to a horizontal plane, wherein the horizontal plane includes the bottom surface of the grid structure.

[0127] The grid structure 740 can divide each sub-pixel 800 into a detection region and a sensing circuit region. For example, the first sub-pixel 801 can include a first detection region 801D and a first sensing region 801S, wherein the first detection region 801D is located on the second conductive type syringe photodiode layer 602 of the first sub-pixel 801, and the first sensing region 801S is located on the sensing circuit (including the transfer transistor 630, the reset transistor 640, the source follower transistor 650, and the selection transistor 660) of the first sub-pixel 801. The second sub-pixel 802 can include a second detection region 802D and a second sensing circuit region 802S, wherein the second detection region 802D is located on the second conductive type syringe photodiode layer 602 of the second sub-pixel 802, and the second sensing circuit region 802S is located on the sensing circuit (including the transfer transistor 630, the reset transistor 640, the source follower transistor 650, and the selection transistor 660) of the second sub-pixel 802. The third sub-pixel 803 may include a third detection region 803D and a third sensing circuit region 803S, wherein the third detection region 803D is located on the second conductive type syringe photodiode layer 602 of the third sub-pixel 803, and the third sensing circuit region 803S is located on the sensing circuit (including the transfer transistor 630, the reset transistor 640, the source follower transistor 650, and the selection transistor 660) of the third sub-pixel 803. In general, the set of all sub-pixels 800 in the pixel 900 may be arranged in any pattern, wherein the above pattern facilitates the periodic repetition of the pixels 900 in the array 1000 of pixels 900.

[0128] according to FIG. 11A to FIG. 11C, the shielding material layer 750L may be disposed on the grid structure 740 and the optical refractive layer 734. In a subsequent anisotropic etching process, the material included in the shielding material layer 750L may be etched by local etching rate variation. For example, in a deposition process (such as physical vapor deposition of materials with different particle sizes), the material is deposited with significant thickness variation, and the shielding material layer 750L may include this material. In addition, in other ways, the shielding material layer 750L may include a material that improves the grain boundary etching rate. In addition, in other ways, the mask material may include a material that exhibits pitting properties in a subsequent anisotropic etching process. In addition, in other ways, in a subsequent anisotropic etching process, the etching rate of the material included in the mask material may significantly depend on the local plasma conditions. Generally speaking, the shielding material layer 750L includes a material that has an unstable etching rate in a subsequent etching process, so that the thickness has significant local variations in the subsequent anisotropic etching process.

[0129] The shielding material layer 750L may include a metal material, a semiconductor material, or a dielectric material. If a metal material is used for the shielding material layer 750L, the shielding material layer 750L may include a conductive metal liner material (e.g., TiN, TaN, or WN), or a metal material (e.g., Ti, Ta, or W), or a stack of at least two metal materials. Other suitable materials are also within the scope of the present disclosure. In an illustrative example, the shielding material layer 750L may include a stack of a titanium nitride layer and a titanium layer. The thickness of the horizontal portion of the shielding material layer 750L may range substantially from 20 nm to 100 nm, although lesser or greater thicknesses may be employed.

[0130] A photoresist layer 757 may be coated on the shielding material layer 750L, and the patterned photoresist layer 757 may be etched to form openings in the mask regions of the detection regions (801D, 802D, 803D) and the sensing circuit regions (801S, 802S, 803S). In a subsequent anisotropic etching process, the patterned portion of the photoresist layer 757 is located on and protects the bottom portion of the shielding material layer 750L. In one embodiment, the patterned edge of the photoresist layer 757 may be located on the region of the grid structure 740.

[0131] according to FIG. 12A to FIG. 12C, the shielding material layer 750L may be anisotropically etched by performing an anisotropic etching process (e.g., a reactive ion etching process). A chemical reaction that causes a random variation in the etching rate of the shielding material layer 750L during the anisotropic etching process may be selected as the chemical reaction. The reasons for the random variation in etching rate may include, but are not limited to, the crystal structure of the shielding material layer 750L, local variations in material composition, high sensitivity of etching rate to local plasma conditions, pitting tendency during etching, sensitivity of plasma to local charge accumulation, or a combination thereof. Due to the variation in etching rate of the shielding material layer 750L, different regions of the optical refractive layer 734 may be physically exposed at different times during the anisotropic etching process.

[0132] The chemical reaction of the anisotropic etching process can be selected to co-etch the material of the optical refractive layer 734 to form a non-planar distal surface portion 734N on the physically exposed portion of the optical refractive layer 734, wherein the non-planar distal surface portion 734N includes the random protrusions 734R. Generally, at the end step of the anisotropic etching process, the non-planar distal surface portion 734N can be formed on the optical refractive layer 734 by anisotropically etching the masking material layer 750L and co-etching the top of the optical refractive layer 734.

[0133] Fig. 12A The partial enlarged view (inset) of FIG. 1 is a vertical cross-sectional profile of a random protrusion 734R in the non-planar distal surface portion 734N of the optical refractive layer 734, however, in various embodiments, the random protrusion 734R may have different vertical cross-sectional profiles. In general, the vertical cross-sectional profile of the random protrusion 734R may be varied by selecting the material and chemical reaction for etching the masking material layer 750L, wherein the chemical reaction is used to etch the masking material layer 750L and the optical refractive layer 734.

[0134] In one embodiment, by etching the physically exposed portion of the optical refractive layer 734 at a higher etching rate than the material of the masking material layer 750L, grooves having different depths can be formed in the optical refractive layer 734. In other words, the etching rate before the end of the anisotropic etching process is greater than the etching rate of the material of the masking material layer 750L during the anisotropic etching process, so as to physically expose multiple material portions of the optical refractive layer 734.

[0135] In one embodiment, the average lateral dimension of random protrusions 734R ranges from substantially 110 nm to 200 nm. The average lateral dimension refers to the diameter of an equivalent circle having the same area as random protrusions 734R. In one embodiment, the average vertical dimension of the random protrusions ranges from substantially 10 nm to 100 nm. The average vertical dimension refers to the height of a cylinder having the same horizontal cross-sectional shape as random protrusions 734R and the same volume as random protrusions 734R.

[0136] In general, the optical refractive layer 734 may be located on the back side of the semiconductor substrate 510. The optical refractive layer 734 has a first refractive index, and the optical refractive layer 734 includes a planar distal surface portion and a non-planar distal surface portion 734N, and the non-planar distal surface portion 734N includes a random protrusion 734R. The planar distal surface portion contacts a surface portion of the bottom surface of the grid structure 740, and the area of ​​the planar distal surface portion is the same as the area of ​​the bottom surface of the grid structure 740. In one embodiment, in a top view (i.e., along a direction perpendicular to the back side surface 709 of the semiconductor substrate 510), each non-planar distal surface portion 734N and the corresponding photosensitive element (including: transfer transistor 630) may overlap in area.

[0137] After the anisotropic etching process, the non-etched area of ​​the mask material layer 750L may form an array of mask structures 750. In one embodiment, the array of mask structures 750 may be located in the outer area of ​​the non-planar distal surface portion 734N of the optical refractive layer 734. The array of mask structures 750 may have sidewalls, wherein the sidewalls are located above and in contact with the top surface of the corresponding portion of the grid structure 740. In one embodiment, from a top view, each mask structure 750 in the array of mask structures 750 may be located on the corresponding sensing circuit (including the transfer transistor 630, the reset transistor 640, the source follower transistor 650, and the selection transistor 660), or may overlap with the corresponding sensing circuit (including the transfer transistor 630, the reset transistor 640, the source follower transistor 650, and the selection transistor 660). In one embodiment, the edge of the mask structure 750 may be located on the upper surface of the grid structure 740. In one embodiment, the mask structure 750 does not contact or is not located on the first sidewall of the grid structure 740, but contacts the second sidewall of the grid structure 740, wherein the first sidewall faces the corresponding opening in the grid structure 740, and the second sidewall faces away from one of the closest ends of the opening in the grid structure 740. Each region surrounded by each adjacent set of second sidewalls of the grid structure 740 may be located in a region in a corresponding sensing circuit region (801S, 802S, 803S).

[0138] Fig.12DA scanning electron micrograph (SEM) of the top surface of the optical refractive layer 734 of the test sample after forming the random protrusions 734R is shown. In the optical refractive layer 734, the random protrusions 734R may have random shapes and random size distributions and / or adjacent pairs of random protrusions 734R may have random spacings.

[0139] FIG. 13A to FIG. 13C An exemplary structure is shown after removal of the patterned photoresist layer 757. Removal of the pattern of the photoresist layer 757 may be effected, for example, by ashing.

[0140] according to Fig.14 , an optically transparent layer 770 having a planar upper surface may be formed on the grid structure 740. The optically transparent layer 770 may be formed by depositing a self-planarizing dielectric material such as flowable oxide (FOX). In other embodiments, the optically transparent layer 770 may be formed by depositing and planarizing a transparent dielectric material, such as by chemical mechanical planarization.

[0141] In the grid structure 740, the optically transparent layer 770 extends vertically to penetrate the opening, and the optically transparent layer 770 has a second refractive index different from the first refractive index. The optically transparent layer 770 can be formed on the non-planar distal surface portion 734N of the optical refractive layer 734. Therefore, photons impacting the photosensitive element (including the transfer transistor 630) below can be randomly refracted at the non-planar interface, wherein the non-planar interface is located between the optically transparent layer 770 and the non-planar distal surface portion 734N of the optical refractive layer 734, and the non-planar interface can increase the quantum efficiency of the photosensitive element (including the transfer transistor 630) in the image sensor.

[0142] Different color filter materials may be coated on the optically transparent layer 770, wherein the different color filter materials may be patterned to form different color filters 780. The color filter 780 may include a first type color filter 781 formed in the area of ​​the first pixel 801, a second type color filter 782 formed in the area of ​​the second pixel 802, and a third type color filter 783 formed in the area of ​​the third pixel 803. A combination of different color filter materials may be selected to allow light in a target wavelength range to pass through the color filter materials, and to allow light outside the target wavelength range to be absorbed by the color filter materials.

[0143] The optical lens 790 may be formed on the color filter 780 by coating an optically transparent material on the color filter 780 and by patterning the optically transparent material into a material portion having a convex surface centered about a corresponding opening below the grid structure 740 .

[0144] See also Fig.15A and Fig. 15B If there is a carrier substrate 690 and a bonding buffer layer 689, the carrier substrate 690 and the bonding buffer layer 689 can be separated from the interconnect level dielectric layer 670. Before or after the carrier substrate 690 is separated from the semiconductor substrate 510, the semiconductor substrate 510 and the device structure thereon can be singulated into a separate image sensor.

[0145] Generally speaking, the pixel array 1000 may be formed on a semiconductor substrate 510. Each pixel in the pixel array 1000 includes at least one sub-pixel, and each sub-pixel includes a corresponding light-sensing element (including: transfer transistor 630) and a corresponding sensing circuit (including: reset transistor 640, source follower transistor 650, select transistor 660), wherein the light-sensing element (including: transfer transistor 630) and the sensing circuit (including: reset transistor 640, source follower transistor 650, select transistor 660) are located on the front surface 609 of the semiconductor substrate 510. An optically transparent layer 770 may be located on the mask structure 750 array.

[0146] like Fig.16 As shown, a general method for forming an image sensor according to an embodiment of the present disclosure is provided. As shown in step 1610, a photosensitive element (including: transfer transistor 630) can be formed on the front side of the semiconductor substrate 500. As shown in step 1620, an optical refractive layer 734 can be formed on the back side of the semiconductor substrate 510, wherein the optical refractive layer 734 has a first refractive index, and the optical refractive layer 734 can be thinned after the photosensitive element (including: transfer transistor 630) is formed and before the optical refractive layer 734 is formed. As shown in step 1630, a grid structure 740 can be formed on the distal surface of the optical refractive layer 734, wherein the optical refractive layer 734 can be a flat horizontal surface (i.e., a top surface) away from the semiconductor substrate 510. The grid structure 740 includes an opening, wherein the opening is located above the corresponding photosensitive element (including: transfer transistor 630). As shown in step 1640, a shielding material layer 750L can be formed on the grid structure 740 and the optical refractive layer 734. As shown in step 1650, an anisotropic etching process may be used to anisotropically etch the masking material layer 750L and the material of the optical refractive layer 734, thereby forming a non-planar distal surface portion 734N including a random protrusion 734R on the physically exposed portion of the optical refractive layer 734. As shown in step 1660, an optically transparent layer 770 having a second refractive index different from the first refractive index may be formed on the non-planar distal surface portion 734N of the optical refractive layer 734.

[0147] As shown in all figures and according to various embodiments of the present disclosure, optical structures and methods of forming optical structures are provided, wherein the above methods manage the optical refractive layer of the image sensor to extend the optical path of the photons that hit the image sensor. The extension of the optical path can increase light absorption, thereby improving the quantum efficiency of the image sensor.

[0148] According to an embodiment of the present disclosure, an optical structure is provided, wherein the optical structure includes a front-side sensing element 600, an optical refractive layer 734, a grid structure 740, and an optically transparent layer 770. The front-side sensing element 600 may include a transfer transistor 630, and the front-side sensing element 600 may be connected to a sensing circuit, wherein the sensing circuit includes other transistors (including: a reset transistor 640, a source follower transistor 650, and a selection transistor 660), and the other transistors (including: the reset transistor 640, the source follower transistor 650, and the selection transistor 660) are located on the semiconductor front side. The optical refractive layer 734 is located on the back side of the semiconductor substrate 510, wherein the optical refractive layer 734 has a first refractive index, and the optical refractive layer 734 includes a planar distal surface portion and a non-planar distal surface portion 734N, and the non-planar distal surface portion 734N includes a random protrusion 734R. The grid structure 740 is located on the planar distal surface portion, and the grid structure 740 includes an opening, wherein the opening is located on the non-planar distal surface portion 734N. The optically transparent layer 770 extends vertically through the opening in the grid structure, wherein the optically transparent layer 770 contacts the non-planar distal surface portion 734N, and the optically transparent layer 770 has a second refractive index different from the first refractive index, thereby providing a refractive interface with the non-planar distal surface portion 734N, wherein the non-planar distal surface portion 734N refracts incident light into random directions.

[0149] According to another embodiment of the present disclosure, an image sensor is provided, wherein the image sensor comprises a pixel 900 array 1000, an optical refractive layer 734, a grid structure 740, and an optical transparent layer 770. The pixel 900 array 1000 is located on a semiconductor substrate 510, wherein each pixel 900 in the pixel 900 array 1000 comprises at least one sub-pixel 800, and each sub-pixel 800 comprises a corresponding front-side sensing element 600, wherein the front-side sensing element 600 may comprise a transfer transistor 630, and the front-side sensing element 600 may be connected to a sensing circuit, wherein the sensing circuit comprises other transistors (including: a reset transistor 640, a source follower transistor 650, and a selection transistor 660), and the other transistors (including: a reset transistor 640, a source follower transistor 650, and a selection transistor 660) are located on the semiconductor front side. The optical refractive layer 734 is located on the back side of the semiconductor substrate 510, wherein the optical refractive layer 734 has a first refractive index, and includes a planar distal surface portion and a non-planar distal surface portion 734N, wherein the non-planar distal surface portion 734N includes a random protrusion 734R. In a top view, each non-planar distal surface portion 734N overlaps with a corresponding photosensitive element in an area. The grid structure 740 is located on the planar distal surface portion, and the grid structure 740 includes an opening, wherein the opening is located above the non-planar distal surface portion 734N. The optically transparent layer 770 extends vertically and passes through the opening in the grid structure 740, and the optically transparent layer 770 has a second refractive index different from the first refractive index.

[0150] According to another embodiment of the present disclosure, a method for forming an optical structure includes a step of forming an optical structure on the front side of a semiconductor substrate 510. The method may optionally include a step of forming an optical refractive layer 734 having a first refractive index on the back side of the semiconductor substrate. The method may optionally include a step of forming a grid structure 740 on the distal surface of the optical refractive layer 734, wherein the grid structure 740 includes openings, and the openings are located above corresponding light sensing elements. The method may optionally include a step of forming a masking material layer on the grid structure 740 and the optical refractive layer 734. The method may optionally include a step of anisotropically etching the masking material layer 750 on the physically exposed portion of the optical refractive layer 734 using an anisotropic etching process, and a step of forming an optically transparent layer 770 on the non-planar distal surface portion of the optical refractive layer 734, wherein the anisotropic etching process also etches the material of the optical refractive layer 734 to form a non-planar distal surface portion, and the non-planar distal surface portion includes random protrusions, and the optically transparent layer 770 has a second refractive index different from the first refractive index.

[0151] In one embodiment, the average lateral dimension of the random protrusions may range substantially from 10 nm to 200 nm, for example.

[0152] In one embodiment, the average vertical dimension of the random protrusions may substantially range from 10 nm to 100 nm, for example.

[0153] In one embodiment, the optical refractive layer may include a semiconductor material or a dielectric material.

[0154] In one embodiment, the grid structure may include at least one metal grid structure, and the at least one metal grid structure has a plurality of reflective sidewalls.

[0155] In one embodiment, the optical structure may selectively include a mask structure array, wherein the mask structure array is located outside multiple regions of these non-planar distal surface portions of the optical refractive layer, the mask structure array has multiple side walls, and these side walls contact and are located on portions of the upper surface of the corresponding grid structure, wherein the optically transparent layer is located on the mask structure array.

[0156] In one embodiment, the image sensing element may selectively include a mask structure array, wherein the mask structure array is located outside multiple areas of these non-planar distal surface portions of the optical refractive layer, the mask structure array has multiple side walls, and these side walls contact and are located above and contact portions of the upper surfaces of these grid structures, wherein the optically transparent layer is located above the mask structure array.

[0157] In one embodiment, each mask structure in the mask structure array is located on a corresponding one of the sensing circuits, and in a top view, each mask structure overlaps with a corresponding one of the sensing circuits in area.

[0158] In one embodiment, the mask structure array does not contact or is not located on multiple first side walls in the grid structure, and the mask structure array contacts multiple second side walls in the grid structure, wherein these first side walls face corresponding these openings in the grid structure and these second side walls are away from one of the nearest ends of these openings in the grid structure.

[0159] In one embodiment, the average lateral size of the random protrusions may substantially range from 10 nm to 200 nm, for example.

[0160] In one embodiment, the optical refractive layer may include a semiconductor material or a dielectric material.

[0161] In one embodiment, wherein the grid structure has a composite grid structure, the composite grid structure may include a vertical stack, and the vertical stack may include a metal grid structure and a dielectric grid structure, wherein the metal grid structure has a plurality of sidewalls.

[0162] In one embodiment, the image sensor may selectively include a color filter element array and a lens array, wherein the color filter element array is located on the optically transparent layer, and the lens array is located on the color filter element array.

[0163] In one embodiment, the etching rate of the anisotropic etching process to etch through the mask material layer has multiple random variations to physically expose multiple different regions of the optical refractive layer at different time points. The etching rate before the end of the anisotropic etching process is greater than the etching rate of the material of the mask material layer during the anisotropic etching process to physically expose multiple material portions of the optical refractive layer.

[0164] In one embodiment, the method for forming an optical structure may selectively include coating and patterning a photoresist layer on a shielding material layer, wherein a plurality of patterned portions of the photoresist layer are located above and protect a plurality of portions of the shielding material layer, and after an anisotropic etching process, a plurality of unetched portions of the shielding material layer constitute a mask structure array.

[0165] In one embodiment, the average lateral dimension of the random protrusions may substantially range from 10 nm to 200 nm, and the average vertical dimension of the random protrusions may substantially range from 10 nm to 100 nm, for example.

[0166] In one embodiment, the optical refractive layer may include a semiconductor material or a dielectric material, and the grid structure may include at least one metal grid structure, and the at least one metal grid structure has a plurality of reflective sidewalls.

[0167] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. An optical structure, characterized in that: Include: A plurality of photosensitive elements are located on a front side of a semiconductor substrate; an optical refractive layer disposed on a back side of the semiconductor substrate, wherein the optical refractive layer has a first refractive index, the optical refractive layer comprises a plurality of planar distal surface portions and a plurality of non-planar distal surface portions, and the plurality of non-planar distal surface portions comprises a plurality of random protrusions; a grid structure disposed on the plurality of planar distal surface portions and comprising a plurality of openings, wherein the plurality of openings are disposed on the plurality of non-planar distal surface portions; an optically transparent layer extending vertically through the plurality of openings in the grid structure and contacting the plurality of non-planar distal surface portions, wherein the optically transparent layer has a second refractive index different from the first refractive index and provides a refractive interface using the plurality of non-planar distal surface portions to refract incident light in a plurality of random directions; as well as A mask structure array is located outside multiple areas of the multiple non-planar distal surface portions of the optical refractive layer, the mask structure array has multiple side walls, and the multiple side walls contact and are located on a portion of an upper surface of the corresponding grid structure, wherein the optically transparent layer is located on the mask structure array.

2. The optical structure according to claim 1, characterized in that: An average lateral dimension of the plurality of random protrusions is substantially in a range of 10 nm to 200 nm.

3. The optical structure according to claim 1, characterized in that: An average vertical dimension of the plurality of random protrusions is substantially in a range of 10 nm to 100 nm.

4. The optical structure according to claim 1, characterized in that: The optical refractive layer includes a semiconductor material or a dielectric material.

5. The optical structure according to claim 1, characterized in that: The grid structure includes at least one metal grid structure, and the at least one metal grid structure has a plurality of reflective side walls.

6. The optical structure according to claim 1, characterized in that: The plurality of planar distal surface portions contact a bottom surface of the grid structure.

7. An image sensor, characterized in that: Include: A pixel array is located on a semiconductor substrate, wherein each pixel of the pixel array includes at least one sub-pixel, each of the at least one sub-pixel includes a corresponding photosensitive element and a corresponding sensing circuit, and the photosensitive element and the sensing circuit are located on a front surface of the semiconductor substrate; an optical refractive layer disposed on a back side of the semiconductor substrate, wherein the optical refractive layer has a first refractive index, the optical refractive layer comprises a plurality of planar distal surface portions and a plurality of non-planar distal surface portions, and the plurality of non-planar distal surface portions comprise a plurality of random protrusions, wherein in a top view, each of the plurality of non-planar distal surface portions overlaps with the corresponding photosensitive element in an area; a grid structure disposed on the plurality of planar distal surface portions, wherein the grid structure comprises a plurality of openings, and the plurality of openings are disposed on the plurality of non-planar distal surface portions; as well as An optically transparent layer vertically extends through the plurality of openings in the grid structure, wherein the optically transparent layer has a second refractive index different from the first refractive index.

8. The image sensor according to claim 7, characterized in that: It also includes a mask structure array, wherein the mask structure array is located outside multiple areas of the multiple non-planar distal surface portions of the optical refractive layer, the mask structure array has multiple side walls, and the multiple side walls contact and are located on and contact a portion of an upper surface of the grid structure, wherein the optically transparent layer is located on the mask structure array.

9. The image sensor according to claim 8, characterized in that: Each mask structure in the mask structure array is located on a corresponding one of the plurality of sensing circuits, and from the top view, each of the plurality of mask structures overlaps with a corresponding one of the plurality of sensing circuits in an area.

10. The image sensor according to claim 8, wherein: The mask structure array does not contact or is not located on multiple first side walls in the grid structure, and the mask structure array contacts multiple second side walls in the grid structure, wherein the multiple first side walls face the corresponding multiple openings in the grid structure, and the multiple second side walls face away from one of the closest ends of the multiple openings in the grid structure.

11. The image sensor according to claim 7, wherein: An average lateral dimension of the plurality of random protrusions is substantially in a range of 10 nm to 200 nm.

12. The image sensor according to claim 7, wherein: An average vertical dimension of the plurality of random protrusions is substantially in a range of 10 nm to 100 nm.

13. The image sensor according to claim 7, wherein: The optical refractive layer includes a semiconductor material or a dielectric material.

14. The image sensor according to claim 7, wherein: The grid structure has a composite grid structure, the composite grid structure includes a vertical stack, the vertical stack includes a metal grid structure and a dielectric grid structure, and the metal grid structure has a plurality of sidewalls.

15. The image sensor according to claim 7, wherein: Also includes: A color filter element array is located on the optically transparent layer; and A lens array is located on the color filter element array.

16. A method for forming an optical structure, characterized in that: Include: Forming a plurality of photosensitive elements on a front side of a semiconductor substrate; Forming an optical refractive layer having a first refractive index on a back side of the semiconductor substrate; forming a grid structure on a distal surface of the optical refractive layer, wherein the grid structure comprises a plurality of openings, the plurality of openings being located above corresponding ones of the plurality of light sensing elements; forming a shielding material layer on the grid structure and the optical refractive layer; Anisotropically etching the masking material layer and etching a material of the optical refractive layer using an anisotropic etching process to form a plurality of non-planar distal surface portions on a plurality of physically exposed areas of the optical refractive layer, wherein the plurality of non-planar distal surface portions include a plurality of random protrusions; as well as An optically transparent layer is formed on the plurality of non-planar distal surface portions of the optically refractive layer, wherein the optically transparent layer has a second refractive index different from the first refractive index.

17. The method for forming an optical structure according to claim 16, characterized in that: in: The anisotropic etching process etches through the masking material layer at an etching rate having a plurality of random variations to physically expose a plurality of different regions of the optical refractive layer at different time points; as well as An etching rate before the anisotropic etching process is finished is greater than an etching rate of a material of the shielding material layer during the anisotropic etching process, so as to physically expose a plurality of material portions of the optical refractive layer.

18. The method for forming an optical structure according to claim 16, characterized in that: It also includes coating and patterning a photoresist layer on the shielding material layer, wherein multiple patterned portions of the photoresist layer are located on multiple portions of the shielding material layer and protect the multiple portions, and after the anisotropic etching process, multiple unetched portions of the shielding material layer form a mask structure array.

19. The method for forming an optical structure according to claim 16, characterized in that: in: An average lateral dimension of the plurality of random protrusions is substantially in the range of 10 nm to 200 nm; and An average vertical dimension of the random protrusions is substantially in the range of 10 nm to 100 nm.

20. The method for forming an optical structure according to claim 16, characterized in that: in: The optical refractive layer comprises a semiconductor material or a dielectric material; and The grid structure includes at least one metal grid structure, and the at least one metal grid structure has a plurality of reflective side walls.

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