Display panel and display device including the same

Abstract

A display panel and a display device including the display panel are provided. The display panel includes: a substrate including a first region, a second region and a third region, the first region including a transmission region, the second region and the third region being adjacent to the first region; a first pixel group and a second pixel group, both of which are arranged in the first region, the transmission region being arranged between the first pixel group and the second pixel group; a plurality of first connection lines extending in a first direction and electrically connected to a plurality of first pixels of the first pixel group; a plurality of second connection lines extending in the first direction and electrically connected to a plurality of second pixels of the second pixel group; and a plurality of third connection lines extending in a second direction and arranged in the third region, the plurality of third connection lines being electrically connected to the plurality of first connection lines and the plurality of second connection lines.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0170208 filed on December 18, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] One or more embodiments relate to a display device, and to a display panel including an expanded display area so that one image or a plurality of images can be displayed even in a region where components can be arranged or disposed, and a display device including the display panel. Background Art

[0004] The uses and applications of display devices have recently been diversified. In addition, as display devices become thinner and lighter, their scope of use has gradually expanded.

[0005] As display devices are used in various ways, they have been designed to have various shapes. In addition, functions that can be combined or associated with display devices are increasing.

[0006] It will be understood that this background in the technical section is intended, in part, to provide a useful background for understanding the technology. However, this background in the technical section may also include ideas, concepts or understandings that are not part of what was known or understood by a person skilled in the relevant art prior to the corresponding effective filing date of the subject matter disclosed herein. Summary of the invention

[0007] As a way to increase the functionality that can be combined or associated with a display device, an embodiment may provide a display device including a first area within the display area where components such as sensors or cameras can be arranged or set. However, it should be understood that the embodiments described herein should be considered only in a descriptive sense and not for limiting the present disclosure.

[0008] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure.

[0009] According to one or more embodiments, the display panel may include: a substrate including a first region, a second region and a third region, the first region including a transmission region, the second region and the third region being adjacent to the first region; a first pixel group and a second pixel group, both being arranged in the first region, the transmission region being arranged between the first pixel group and the second pixel group; a plurality of first connection lines extending in a first direction and electrically connected to a plurality of first pixels of the first pixel group; a plurality of second connection lines extending in the first direction and electrically connected to a plurality of second pixels of the second pixel group; and a plurality of third connection lines extending in the second direction and being arranged in the third region, the plurality of third connection lines being electrically connected to the plurality of first connection lines and the plurality of second connection lines, wherein the second direction intersects with the first direction.

[0010] The display panel may further include a plurality of wirings extending in the second direction in the second region, wherein the plurality of wirings may be electrically connected to the first pixel group and disconnected between the first pixel group and the second pixel group.

[0011] The plurality of wirings may include a data line supplying a data signal.

[0012] The plurality of wirings and the plurality of third connection lines may be provided on the same layer.

[0013] The plurality of first connection lines and the plurality of second connection lines may be disposed on the same layer.

[0014] The display panel may further include a plurality of auxiliary wirings extending in the second direction and electrically connected to the plurality of second pixels.

[0015] The plurality of second connection lines may be electrically connected to the plurality of auxiliary wirings.

[0016] The display panel may further include a first metal layer disposed in the first region, wherein the first metal layer may overlap the first pixel group and the plurality of first connection lines.

[0017] The display panel may further include a second metal layer disposed in the first region, the second metal layer being spaced apart from the first metal layer, wherein the second metal layer may overlap the second pixel group and the plurality of second connection lines.

[0018] The first metal layer and the second metal layer may receive a constant voltage from the conductive line.

[0019] Each of the plurality of first pixels and the plurality of second pixels may include a pixel circuit, the pixel circuit includes a thin film transistor, the thin film transistor may include a semiconductor layer and a gate electrode overlapping at least a portion of the semiconductor layer, and the first metal layer and the second metal layer may be arranged between the substrate and the semiconductor layer.

[0020] The third area may include a non-display area surrounding the second area.

[0021] The third region may surround at least a portion of the first region, and may be disposed between the first region and the second region.

[0022] The display panel may also include: a first conductive layer, arranged above the substrate; and a second conductive layer, arranged above the first conductive layer, wherein an insulating layer may be arranged between the first conductive layer and the second conductive layer, a plurality of third connecting lines may include the same material as the first conductive layer, and a plurality of first connecting lines and a plurality of second connecting lines may include the same material as the second conductive layer.

[0023] Each of the plurality of first pixels and the plurality of second pixels may include: a display element; and a pixel circuit including a thin film transistor. The thin film transistor may include: a semiconductor layer; a gate electrode overlapping at least a portion of the semiconductor layer; and an electrode layer electrically connected to the semiconductor layer. The plurality of third connection lines and the electrode layer may include the same material.

[0024] Each of the plurality of first pixels and the plurality of second pixels may include a contact metal layer, which is disposed between the display element and the thin film transistor and electrically connects the display element to the thin film transistor, and the plurality of first connection lines and the plurality of second connection lines may include the same material as the contact metal layer.

[0025] The first region may be at least partially surrounded by the second region.

[0026] The resolution of the first region may be lower than the resolution of the second region.

[0027] According to one or more embodiments, a display device may include: a display panel including a substrate, the substrate may include a first area, a second area and a third area, the first area including a transmission area, the second area and the third area being adjacent to the first area; and a component arranged in the first area of ​​the display panel, wherein the display panel may include: a first pixel group and a second pixel group, both arranged in the first area, the transmission area being arranged between the first pixel group and the second pixel group; a plurality of first connection lines extending in a first direction and electrically connected to a plurality of first pixels of the first pixel group; a plurality of second connection lines extending in the first direction and electrically connected to a plurality of second pixels of the second pixel group; and a plurality of third connection lines extending in a second direction and arranged in the third area, the plurality of third connection lines being electrically connected to the plurality of first connection lines and the plurality of second connection lines, wherein the second direction intersects with the first direction.

[0028] The assembly may include an imaging element.

[0029] These and / or other aspects will become apparent and more readily appreciated from the following description of the embodiments, the drawings and the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects, features and advantages of the embodiments will become more apparent from the following description made in conjunction with the accompanying drawings, in which:

[0031] Figure 1 is a perspective view of a display device according to an embodiment;

[0032] Figure 2 is a schematic cross-sectional view of a display device according to an embodiment;

[0033] Figure 3 is a plan view of a display panel according to an embodiment;

[0034] Figure 4A and Figure 4B is an equivalent circuit diagram of a main pixel and / or an auxiliary pixel that may be included in a display panel according to an embodiment;

[0035] Figure 5 is a view of an arrangement of a pixel circuit of a pixel of a display panel according to an embodiment;

[0036] Figure 6 is a schematic cross-sectional view of a pixel circuit of a pixel according to an embodiment;

[0037] Figure 7 is a plan view of a portion or region of a display device according to an embodiment;

[0038] Figure 8 yes Figure 7 an enlarged plan view of a portion or area of ​​a

[0039] Fig.9A and Fig. 9B is along Figure 8 A schematic cross-sectional view taken along line BB';

[0040] Figures 10 to 13 is a plan view of a portion or region of a display device according to an embodiment; and

[0041] FIG. 14A to FIG. 14D is a view showing a pixel arrangement of a display device according to an embodiment. DETAILED DESCRIPTION

[0042] Reference will now be made in detail to embodiments, examples of which are shown in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, embodiments are described below only by reference to the drawings to explain aspects of the description.

[0043] For describing the embodiments of the present disclosure, some parts that are not related to the description may not be provided, and like reference numerals refer to like elements throughout the specification.

[0044] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0045] The terms "and" and "or" may be used in a conjunctive or disjunctive sense and may be understood to be equivalent to "and / or". In the specification and claims, for the purpose of its meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of..." For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0046] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are given to the same or corresponding elements, and their repeated description will be omitted.

[0047] It will be understood that, although the terms "first", "second", etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another component. For example, without departing from the teachings of the present disclosure, the first element or component discussed below can be referred to as the second element or component. Similarly, the second element or component can also be referred to as the first element or component.

[0048] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0049] It will be further understood that when the terms “comprise,” “comprising,” “include,” and / or “including,” “have,” and / or “having” are used in this specification, they or it may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0050] When a layer, film, zone, substrate or region or element is referred to as being "on" another layer, film, zone, substrate or region or element, the layer, film, zone, substrate or region or element may be directly on another layer, film, zone, substrate or region or element, or there may be an intermediate layer, film, zone, substrate or region or element therebetween. Conversely, when a layer, film, zone, substrate or region or element is referred to as being "directly on" another layer, film, zone, substrate or region or element, there may be no intermediate layer, film, zone, substrate or region or element therebetween. In addition, when a layer, film, zone, substrate or region or element is referred to as being "below" another layer, film, zone, substrate or region or element, the layer, film, zone, substrate or region or element may be directly below another layer, film, zone, substrate or region or element, or there may be an intermediate layer, film, zone, substrate or region or element therebetween. In contrast, when a layer, film, region, substrate or area, or element is referred to as being "directly below" another layer, film, region, substrate or area, or element, there may be no intervening layers, films, regions, substrates or areas, or elements. In addition, "above" or "on" may include positioning above or below an object, and does not necessarily imply a direction based on gravity.

[0051] For ease of description, spatially relative terms such as "below", "under", "lower", "above", "upper", etc. may be used herein to describe the relationship between one element or component and another element or component as shown in the figure. It will be understood that the spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figure. For example, in the case where the device shown in the figure is turned over, a device positioned "below" or "below" another device can be placed "above" the other device. Therefore, the illustrative term "below" can include both lower and upper positions. The device may also be oriented in other directions, and therefore the spatially relative terms may be interpreted differently depending on the orientation.

[0052] In the drawings, the size and thickness of the elements may be exaggerated for better understanding, clarity and convenience of their description. However, the present disclosure is not limited to the sizes and thicknesses shown. In the drawings, the thickness of layers, films, panels, regions and other elements may be exaggerated for clarity. In the drawings, the thickness of some layers and regions may be exaggerated for better understanding and convenience of description.

[0053] In addition, the term "overlap" or "overlapping" means that the first object can be above or below the second object or the side of the second object, and vice versa. In addition, the term "overlap" can include stacking, stacking, facing or facing, extending on, covering or partially covering, or any other suitable term that a person of ordinary skill in the art will appreciate and understand. The terms "facing" and "facing" mean that the first element can be directly or indirectly opposite to the second element. In the case where the third element is between the first element and the second element, although still facing each other, the first element and the second element can be understood to be indirectly opposite to each other. When an element is described as "not overlapping" or "will not overlap" with another element, this can include these elements being spaced apart from each other, offset from each other or separated from each other or any other suitable term that a person of ordinary skill in the art will appreciate and understand.

[0054] When the embodiment can be implemented differently, a specific processing order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of the described order.

[0055] Furthermore, in the specification, the phrase “in a plan view” means when an object portion is viewed from above, and the phrase “in a schematic cross-sectional view” means when a schematic cross section taken by vertically cutting the object portion is viewed from the side.

[0056] It will be understood that when a layer, region, or component is referred to as being “connected” or “coupled” to another layer, region, or component, the layer, region, or component may be “directly connected” or “directly coupled” to the other layer, region, or component, or may be “indirectly connected” or “indirectly coupled” to the other layer, region, or component with other layers, regions, or components interposed therebetween. For example, it will be understood that when a layer, region, or component is referred to as being “electrically connected” or “electrically coupled” to another layer, region, or component, the layer, region, or component may be “directly electrically connected” or “directly electrically coupled” to the other layer, region, or component, or may be “indirectly electrically connected” or “indirectly electrically coupled” to the other layer, region, or component with other layers, regions, or components interposed therebetween.

[0057] Also, when an element is referred to as being “in contact with” or “in contact with” or the like, it may be “electrically in contact with” or “physically in contact with” the other element, or it may be “indirectly in contact with” or “directly in contact with” the other element.

[0058] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0059] In the following examples, the x-axis, y-axis, and z-axis are not limited to the three axes of the rectangular coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis may be perpendicular to each other, or may represent different directions that may not be perpendicular to each other.

[0060] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the embodiments belong. In addition, it will be further understood that, unless explicitly defined as such herein, terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly rigid sense.

[0061] Figure 1 is a perspective view of a display device 1 according to the embodiment.

[0062] Reference Figure 1 , the display device 1 may include a first area CA, a second area DA (hereinafter referred to as a display area), and a third area PA, the display area DA displays one image or multiple images, and the third area PA does not display one image or multiple images. The display device 1 may display a main image by using light emitted from a main pixel Pm arranged or provided in the display area DA.

[0063] The first area CA may be at least partially surrounded by the display area DA. Figure 2 As described, the first area CA may be a component area in which components such as sensors and / or cameras that use infrared rays, visible light, or sound may be arranged or set. The first area CA may include a transmission area TA, through which light and / or sound that may be output from the component to the outside or advance toward the component from the outside may pass. In an embodiment, when infrared rays pass through the first area CA, the transmittance may be about 10% or more, for example, about 20% or more, about 25% or more, about 50% or more, about 85% or more, or about 90% or more.

[0064] In an embodiment, the auxiliary pixel Pa may be arranged or set in the first area CA. The display device 1 may display a predetermined image by using light emitted from the auxiliary pixel Pa. The image displayed in the first area CA may be an auxiliary image. The resolution of the auxiliary image may be lower than the resolution of the image displayed in the display area DA. Since the first area CA may include a transmissive area TA through which light and / or sound may pass, the number of auxiliary pixels Pa that may be arranged or set per unit area in the first area CA may be lower than the number of main pixels Pm that may be arranged or set per unit area in the display area DA.

[0065] The first area CA may be at least partially surrounded by the display area DA. Figure 1 As shown in FIG. 1 , the first area CA may be completely surrounded by the display area DA.

[0066] The third area PA may externally surround the display area DA or be adjacent to the display area DA, and may be a non-display area in which pixels may not be arranged or disposed. Figure 7 ) may be arranged or disposed in the third area PA to bypass the transmission area TA, and the third connection line CL3 may transmit the data signal to the auxiliary pixel Pa arranged or disposed in the first area CA. Since the third connection line CL3 may be arranged or disposed in the third area PA, the transmittance of the first area CA may be improved. Figure 7 This is described in detail.

[0067] In an embodiment, the middle area MA may be arranged or disposed between the first area CA and the display area DA. The third connection line CL3 may be arranged or disposed in the middle area MA instead of the third area PA. In an embodiment, the third connection line CL3 may be arranged or disposed in the third area PA and the middle area MA. In the case where the third connection line CL3 may be arranged or disposed in the middle area MA, the middle area MA may be a non-display area where pixels may not be arranged or disposed. In an embodiment, the middle area MA may be omitted.

[0068] Hereinafter, although the display device 1 according to the embodiment is described as an organic light-emitting display device as an example, the display device 1 according to the embodiment is not limited thereto. In an embodiment, the display device 1 according to the embodiment may include various types of display devices, such as an inorganic light-emitting display and a quantum dot light-emitting display. For example, the emission layer of the display element arranged or provided to the display device 1 may include an organic material, may include an inorganic material, may include quantum dots, may include an organic material and quantum dots, or may include an inorganic material and quantum dots.

[0069] although Figure 1, it is shown that the first area CA can be arranged or set on one side (upper central area) of the display area DA, but the embodiment is not limited thereto. The shape of the display area DA can be circular, elliptical, or polygonal such as a triangle or a pentagon. Within the spirit and scope of the present disclosure, the position of the first area CA and the number of the first areas CA can be variously changed.

[0070] Figure 2 is the edge of the display device 1 according to the embodiment Figure 1 A schematic cross-sectional view taken along line AA'.

[0071] Reference Figure 2 , the display device 1 may include a display panel 10 and an assembly 20 , the display panel 10 includes a display element, and the assembly 20 corresponds to the first area CA.

[0072] The display panel 10 may include a substrate 100, a display element layer 200, and a thin film encapsulation layer 300 as a sealing member, the display element layer 200 may be arranged or disposed on the substrate 100, and the thin film encapsulation layer 300 seals the display element layer 200. As an example, the display panel 10 may include a bottom protective film 175 arranged or disposed under or below the substrate 100.

[0073] The substrate 100 may include glass or a polymer resin. The polymer resin may include, for example, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, and cellulose acetate propionate. The substrate 100 including the polymer resin may be flexible, rollable, and / or bendable. The substrate 100 may have a multilayer structure including a layer including a polymer resin and an inorganic layer (not shown).

[0074] The display element layer 200 may include a circuit layer, an organic light emitting diode OLED as a display element, and insulating layers IL and IL′ disposed therebetween, and the circuit layer may include a thin film transistor TFT.

[0075] The main pixel Pm may be arranged or disposed in the display area DA, and the main pixel Pm may include a thin film transistor TFT and an organic light emitting diode OLED electrically connected to the thin film transistor TFT.

[0076] The first auxiliary pixel Pa1 and the second auxiliary pixel Pa2 may be arranged or disposed in the first area CA, and each of the first auxiliary pixel Pa1 and the second auxiliary pixel Pa2 may include a thin film transistor TFT and an organic light emitting diode OLED electrically connected to the thin film transistor TFT. The first auxiliary pixel Pa1 and the second auxiliary pixel Pa2 may form a group in the first area CA and be defined as a first pixel group Pg1 and a second pixel group Pg2. Figure 2, the first pixel group Pg1 and the second pixel group Pg2 are shown to include one first auxiliary pixel Pa1 and one second auxiliary pixel Pa2, respectively, but the first pixel group Pg1 and the second pixel group Pg2 may include a plurality of first auxiliary pixels Pa1 and a plurality of second auxiliary pixels Pa2, respectively. The first connection line CL1 and the second connection line CL2 may be arranged or disposed at one side of the first pixel group Pg1 and the second pixel group Pg2, respectively, and the first connection line CL1 and the second connection line CL2 are electrically connected to the first auxiliary pixel Pa1 and the second auxiliary pixel Pa2, respectively.

[0077] The transmission area TA may be arranged or disposed between the first pixel group Pg1 and the second pixel group Pg2 in the first area CA. The display element may not be arranged or disposed in the transmission area TA. The transmission area TA may be a region through which light / signals that may be emitted from or incident to the component 20 may pass.

[0078] The component 20 may be located or arranged in the first area CA. The component 20 may include an electronic component using light or sound. For example, the component 20 may be a sensor such as an infrared sensor that can emit and / or receive light, a sensor that can output and sense light or sound to measure distance or recognize fingerprints, a small lamp that can output light, a speaker that can output sound, and a camera including an imaging device. The electronic component using light may use light of various wavelength bands including visible light, infrared light, and ultraviolet light. The component 20 arranged or arranged in the first area CA may be provided in plurality.

[0079] The first metal layer BML1 and the second metal layer BML2 may be arranged or disposed in the first area CA. In an embodiment, the first metal layer BML1 may be arranged or disposed to correspond to the first pixel group Pg1 and the first connection line CL1, and the second metal layer BML2 may be arranged or disposed to correspond to the second pixel group Pg2 and the second connection line CL2. The first metal layer BML1 and the second metal layer BML2 may prevent external light (e.g., light emitted from the component 20) from reaching the first pixel group Pg1 and the second pixel group Pg2. Since the first metal layer BML1 and the second metal layer BML2 may prevent reflection or diffraction of light that may occur when external light passes between the first connection line CL1 and between the second connection line CL2, image distortion (e.g., glare, haze, or other distortion) in the first area CA may be prevented.

[0080] In an embodiment, a constant voltage or signal may be applied to the first metal layer BML1 and the second metal layer BML2, and thus damage of the pixel circuit due to electrostatic discharge may be prevented. In an embodiment, the first metal layer BML1 and the second metal layer BML2 may receive different voltages.

[0081] The third area PA may surround the display area DA or be adjacent to the display area DA. The third connection lines CL3 may be arranged or disposed in the third area PA. The plurality of third connection lines CL3 may be electrically connected to the plurality of first connection lines CL1 and the plurality of second connection lines CL2, respectively, so that the plurality of first connection lines CL1 may be electrically connected to the plurality of second connection lines CL2.

[0082] The thin film encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Figure 2 A first inorganic encapsulating layer 310 and a second inorganic encapsulating layer 330 are shown with an organic encapsulating layer 320 disposed therebetween.

[0083] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include at least one inorganic insulating material among aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride and / or silicon oxynitride. The organic encapsulation layer 320 may include a polymer material. The polymer material may include acrylic resin, epoxy resin, polyimide and polyethylene.

[0084] The bottom protective film 175 may be attached or adhered to the back of the substrate 100 to support and protect the substrate 100. The bottom protective film 175 may include an opening 175OP corresponding to the first area CA. The bottom protective film 175 may improve the light transmittance of the first area CA by including the opening 175OP. For example, the bottom protective film 175 may include polyethylene terephthalate (PET) or polyimide (PI).

[0085] The area of ​​the first region CA may be larger than the area in which the component 20 may be arranged or disposed. Therefore, the area of ​​the opening 175OP of the bottom protective film 175 may not be consistent with the area of ​​the first region CA. For example, the area of ​​the opening 175OP may be smaller than or different from the area of ​​the first region CA.

[0086] Although not shown, elements such as an input sensing member that senses a touch input, an anti-reflection member including a polarizer and a retarder, or including a color filter and a black matrix, and a transparent window may be arranged or disposed on the display panel 10 .

[0087] Although the thin film encapsulation layer 300 may be used as an encapsulation member for sealing the display element layer 200 in the embodiment, the embodiment is not limited thereto. For example, as a member for sealing the display element layer 200, a sealing substrate may be used, which is attached or adhered to the substrate 100 through a sealant or glass frit.

[0088] Figure 3 is a plan view of the display panel 10 according to the embodiment.

[0089] Reference Figure 3, the display panel 10 may include a display area DA, and may include primary pixels Pm arranged or disposed in the display area DA. Each of the primary pixels Pm may include a display element such as an organic light emitting diode. Each primary pixel Pm may emit, for example, red light, green light, blue light, or white light through an organic light emitting diode. In the specification, the primary pixel Pm may be a pixel that emits red light, green light, blue light, or white light as described above. By referring to Figure 2 The described encapsulation member covers or overlaps and can protect the display area DA from external air or moisture.

[0090] The first area CA may be arranged or disposed inside the display area DA. The first auxiliary pixel Pa1 and the second auxiliary pixel Pa2 may be arranged or disposed in the first area CA. Each of the first auxiliary pixel Pa1 and the second auxiliary pixel Pa2 may include a display element such as an organic light emitting diode. Each of the first auxiliary pixel Pa1 and the second auxiliary pixel Pa2 may emit red light, green light, blue light, or white light through an organic light emitting diode. In the specification, each of the first auxiliary pixel Pa1 and the second auxiliary pixel Pa2 may be a sub-pixel emitting red light, green light, blue light, or white light as described above. Although not shown, each of the first auxiliary pixel Pa1 and the second auxiliary pixel Pa2 may be provided in plurality to constitute a first pixel group Pg1 and a second pixel group Pg2.

[0091] The transmission area TA may be arranged or disposed between the first auxiliary pixel Pa1 and the second auxiliary pixel Pa2 in the first area CA.

[0092] Since the first area CA may include the transmissive area TA, the resolution of the first area CA may be smaller than the resolution of the display area DA. For example, the resolution of the first area CA may be about 1 / 2 of the resolution of the display area DA. In an embodiment, the resolution of the display area DA may be about 400 ppi or higher, and the resolution of the first area CA may be about 200 ppi or higher, about 100 ppi, or about 50 ppi.

[0093] In an embodiment, one primary pixel Pm and one auxiliary pixel Pa may include the same pixel circuit. However, the embodiment is not limited thereto. The pixel circuit of the primary pixel Pm may be different from the pixel circuit of the auxiliary pixel Pa. Hereinafter, assuming that the primary pixel Pm and the auxiliary pixel Pa include the same pixel circuit, the circuit arrangement of the display panel 10 is described with the primary pixel Pm as the center.

[0094] Each of the pixels (e.g., the main pixel Pm, the first auxiliary pixel Pa1, and the second auxiliary pixel Pa2) may be electrically connected to an external circuit arranged or disposed in the third area PA. The first scan driving circuit 110, the second scan driving circuit 120, the emission control driving circuit 130, the terminal 140, the first power line 160, and the second power line 170 may be arranged or disposed in the third area PA.

[0095] The first scan driving circuit 110 may provide a scan signal to a pixel, for example, a main pixel Pm, a first auxiliary pixel Pa1, and a second auxiliary pixel Pa2, through a scan line SL. The first scan driving circuit 110 may provide an emission control signal to a pixel, for example, a main pixel Pm, a first auxiliary pixel Pa1, and a second auxiliary pixel Pa2, through an emission control line EL. The second scan driving circuit 120 may be arranged or disposed in parallel with the first scan driving circuit 110 with the display area DA disposed therebetween. Some or a predetermined number of pixels of the pixels (for example, the main pixel Pm, the first auxiliary pixel Pa1, and the second auxiliary pixel Pa2) arranged or disposed in the display area DA may be electrically connected to the first scan driving circuit 110, and the remaining or remaining pixels of the pixels (for example, the main pixel Pm, the first auxiliary pixel Pa1, and the second auxiliary pixel Pa2) may be electrically connected to the second scan driving circuit 120. In an embodiment, the second scan driving circuit 120 may be omitted. The pixels may be collectively referred to as the main pixel Pm, the first auxiliary pixel Pa1, and the second auxiliary pixel Pa2.

[0096] The terminal 140 may be arranged or disposed on one side of the substrate 100. The terminal 140 may be exposed by not being covered or overlapped by the insulating layer and electrically connected to the printed circuit board PCB. The terminal PCB-P of the printed circuit board PCB may be electrically connected to the terminal 140 of the display panel 10. The printed circuit board PCB may transmit a signal or power of a controller (not shown) to the display panel 10. The control signal generated by the controller may be transmitted to the first scan driving circuit 110 and the second scan driving circuit 120 respectively through the printed circuit board PCB. The controller may transmit the first power supply voltage ELVDD and the second power supply voltage ELVSS (see the following description) respectively through the first connection line 161 and the second connection line 171. Figure 4A and Figure 4B ) is supplied to the first power line 160 and the second power line 170. The first power supply voltage ELVDD may be supplied to pixels, for example, the primary pixel Pm, the first auxiliary pixel Pa1, and the second auxiliary pixel Pa2, through the driving voltage line PL electrically connected to the first power line 160, and the second power supply voltage ELVSS may be supplied to opposite electrodes of the pixels (for example, the primary pixel Pm, the first auxiliary pixel Pa1, and the second auxiliary pixel Pa2) electrically connected to the second power line 170.

[0097] The data driving circuit 150 may be electrically connected to the data line DL. The data signal of the data driving circuit 150 may be provided to pixels, for example, the primary pixel Pm, the first auxiliary pixel Pa1, and the second auxiliary pixel Pa2, through the connection line 151 and the data line DL, the connection line 151 may be electrically connected to the terminal 140, and the data line DL may be electrically connected to the connection line 151. Figure 3 1 and 2 show that the data driving circuit 150 can be arranged or disposed on the printed circuit board PCB, but in an embodiment, the data driving circuit 150 can be arranged or disposed on the substrate 100. For example, the data driving circuit 150 can be arranged or disposed between the terminal 140 and the first power line 160.

[0098] The first power line 160 may include a first sub-line 162 and a second sub-line 163 which may be parallel to each other and extend in the x direction with the display area DA disposed therebetween. The second power line 170 may have a substantially annular shape with an open side and may partially surround the display area DA.

[0099] Figure 4A and Figure 4B is an equivalent circuit diagram of a main pixel Pm and / or an auxiliary pixel Pa that may be included in the display panel 10 according to an embodiment.

[0100] Reference Figure 4A , pixels, for example, the main pixel Pm, the first auxiliary pixel Pa1, and the second auxiliary pixel Pa2, may include a pixel circuit PC and an organic light emitting diode OLED electrically connected to the pixel circuit PC, and the pixel circuit PC may be electrically connected to the scan line SL and the data line DL.

[0101] The pixel circuit PC may include a driving thin film transistor T1, a switching thin film transistor T2, and a storage capacitor Cst. The switching thin film transistor T2 may be electrically connected to the scan line SL and the data line DL, and may transmit a data signal Dm input through the data line DL to the driving thin film transistor T1 in response to a scan signal Sn input through the scan line SL.

[0102] The storage capacitor Cst may be electrically connected to the switching thin film transistor T2 and the driving voltage line PL, and may store a voltage corresponding to a difference between a voltage transferred from the switching thin film transistor T2 and a first power source voltage ELVDD (or driving voltage) supplied to the driving voltage line PL.

[0103] The driving thin film transistor T1 may be electrically connected to the driving voltage line PL and the storage capacitor Cst, and may control a driving current flowing from the driving voltage line PL through the organic light emitting diode OLED in response to a voltage stored in the storage capacitor Cst. The organic light emitting diode OLED may emit light with a predetermined brightness by using the driving current.

[0104] although Figure 4A FIG. 4 shows that the pixel circuit PC may include two thin film transistors and one storage capacitor, but the embodiment is not limited thereto. Figure 4B As shown in , the pixel circuit PC may include seven thin film transistors and one storage capacitor.

[0105] Reference Figure 4B , pixels, for example, the primary pixel Pm, the first auxiliary pixel Pa1, and the second auxiliary pixel Pa2, may include a pixel circuit PC and an organic light emitting diode OLED electrically connected to the pixel circuit PC. The pixel circuit PC may include a thin film transistor and a storage capacitor. The thin film transistor and the storage capacitor may be electrically connected to the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the driving voltage line PL.

[0106] although Figure 4B Pixels, for example, a main pixel Pm, a first auxiliary pixel Pa1, and a second auxiliary pixel Pa2 are shown, which may be electrically connected to signal lines SL, SL-1, EL, and DL, an initialization voltage line VL, and a driving voltage line PL, but the embodiment is not limited thereto. In an embodiment, at least one of the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the driving voltage line PL may be shared by a plurality of pixels that may be adjacent to each other.

[0107] The thin film transistor may include a driving thin film transistor T1 , a switching thin film transistor T2 , a compensation thin film transistor T3 , a first initialization thin film transistor T4 , an operation control thin film transistor T5 , an emission control thin film transistor T6 , and a second initialization thin film transistor T7 .

[0108] The signal line may include a scan line SL, a previous scan line SL-1, an emission control line EL, and a data line DL, the scan line SL may transmit a scan signal Sn, the previous scan line SL-1 may transmit the previous scan signal Sn-1 to the first initialization thin film transistor T4 and the second initialization thin film transistor T7, the emission control line EL may transmit an emission control signal En to the operation control thin film transistor T5 and the emission control thin film transistor T6, and the data line DL intersecting the scan line SL may transmit a data signal Dm. The driving voltage line PL may transmit a driving voltage ELVDD to the driving thin film transistor T1, and the initialization voltage line VL may transmit an initialization voltage Vint for initializing the driving thin film transistor T1 and the pixel electrode of the organic light emitting diode OLED.

[0109] The driving gate electrode G1 of the driving thin film transistor T1 can be electrically connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the driving source electrode S1 of the driving thin film transistor T1 can be electrically connected to the driving voltage line PL through the operation control thin film transistor T5, and the driving drain electrode D1 of the driving thin film transistor T1 can be electrically connected to the pixel electrode of the organic light emitting diode OLED through the emission control thin film transistor T6. The driving thin film transistor T1 can receive the data signal Dm according to the switching operation of the switching thin film transistor T2, and can drive the driving current I OLED Supplied to the organic light emitting diode OLED.

[0110] The switching gate electrode G2 of the switching thin film transistor T2 may be electrically connected to the scan line SL, the switching source electrode S2 of the switching thin film transistor T2 may be electrically connected to the data line DL, and the switching drain electrode D2 of the switching thin film transistor T2 may be electrically connected to the driving source electrode S1 of the driving thin film transistor T1, and may be electrically connected to the driving voltage line PL by operating the control thin film transistor T5 at the same time. The switching thin film transistor T2 may be turned on in response to the scan signal Sn transmitted through the scan line SL, and may perform a switching operation of transmitting the data signal Dm transmitted through the data line DL to the driving source electrode S1 of the driving thin film transistor T1.

[0111] The compensation gate electrode G3 of the compensation thin film transistor T3 may be electrically connected to the scan line SL, the compensation source electrode S3 of the compensation thin film transistor T3 may be electrically connected to the driving drain electrode D1 of the driving thin film transistor T1 and may be electrically connected to the pixel electrode of the organic light emitting diode OLED through the emission control thin film transistor T6 at the same time, and the compensation drain electrode D3 of the compensation thin film transistor T3 may be electrically connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization thin film transistor T4, and the driving gate electrode G1 of the driving thin film transistor T1. The compensation thin film transistor T3 may be turned on in response to the scan signal Sn transmitted through the scan line SL, and may make the driving thin film transistor T1 diode-connected by electrically connecting the driving gate electrode G1 to the driving drain electrode D1 of the driving thin film transistor T1.

[0112] The first initialization gate electrode G4 of the first initialization thin film transistor T4 may be electrically connected to the previous scan line SL-1, the first initialization source electrode S4 of the first initialization thin film transistor T4 may be electrically connected to the second initialization drain electrode D7 of the second initialization thin film transistor T7 and the initialization voltage line VL, and the first initialization drain electrode D4 of the first initialization thin film transistor T4 may be electrically connected to the first storage capacitor plate Cst1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation thin film transistor T3, and the driving gate electrode G1 of the driving thin film transistor T1. The first initialization thin film transistor T4 may be turned on in response to the previous scan signal Sn-1 transmitted through the previous scan line SL-1, and may perform an initialization operation of initializing the voltage of the driving gate electrode G1 of the driving thin film transistor T1 by transmitting the initialization voltage Vint to the driving gate electrode G1 of the driving thin film transistor T1.

[0113] The operation control gate electrode G5 of the operation control thin film transistor T5 can be electrically connected to the emission control line EL, the operation control source electrode S5 of the operation control thin film transistor T5 can be electrically connected to the driving voltage line PL, and the operation control drain electrode D5 of the operation control thin film transistor T5 can be electrically connected to the driving source electrode S1 of the driving thin film transistor T1 and the switching drain electrode D2 of the switching thin film transistor T2.

[0114] The emission control gate electrode G6 of the emission control thin film transistor T6 can be electrically connected to the emission control line EL, the emission control source electrode S6 of the emission control thin film transistor T6 can be electrically connected to the driving drain electrode D1 of the driving thin film transistor T1 and the compensation source electrode S3 of the compensation thin film transistor T3, and the emission control drain electrode D6 of the emission control thin film transistor T6 can be electrically connected to the second initialization source electrode S7 of the second initialization thin film transistor T7 and the pixel electrode of the organic light emitting diode OLED.

[0115] The operation control thin film transistor T5 and the emission control thin film transistor T6 may be simultaneously turned on in response to the emission control signal En transmitted through the emission control line EL to allow the driving voltage ELVDD to be transmitted to the organic light emitting diode OLED and thus allow the driving current I OLED Flow through the organic light emitting diode OLED.

[0116] The second initialization gate electrode G7 of the second initialization thin film transistor T7 may be electrically connected to the previous scan line SL-1, the second initialization source electrode S7 of the second initialization thin film transistor T7 may be electrically connected to the emission control drain electrode D6 of the emission control thin film transistor T6 and the pixel electrode of the organic light emitting diode OLED, and the second initialization drain electrode D7 of the second initialization thin film transistor T7 may be electrically connected to the first initialization source electrode S4 of the first initialization thin film transistor T4 and the initialization voltage line VL. The second initialization thin film transistor T7 may be turned on in response to the previous scan signal Sn-1 transmitted through the previous scan line SL-1, and may initialize the pixel electrode of the organic light emitting diode OLED.

[0117] although Figure 4B The case where the first initialization thin film transistor T4 and the second initialization thin film transistor T7 may be electrically connected to the previous scan line SL-1 is shown, but the embodiment is not limited thereto. In an embodiment, the first initialization thin film transistor T4 may be electrically connected to the previous scan line SL-1 and driven in response to the previous scan signal Sn-1, and the second initialization thin film transistor T7 may be electrically connected to a separate signal line (e.g., the next scan line) and driven in response to a signal transmitted through the separate signal line.

[0118] The second storage capacitor plate Cst2 of the storage capacitor Cst may be electrically connected to the driving voltage line PL, and the opposite electrode of the organic light emitting diode OLED may be electrically connected to the common voltage ELVSS. Therefore, the organic light emitting diode OLED may receive the driving current I from the driving thin film transistor T1. OLED And can emit light to display images.

[0119] although Figure 4B 2 shows that the compensation thin film transistor T3 and the first initialization thin film transistor T4 both have double gate electrodes, but the compensation thin film transistor T3 and the first initialization thin film transistor T4 may each have one gate electrode.

[0120] In an embodiment, the main pixel Pm, the first auxiliary pixel Pa1, and the second auxiliary pixel Pa2 may include the same pixel circuit PC. However, the embodiment is not limited thereto. The main pixel Pm, the first auxiliary pixel Pa1, and the second auxiliary pixel Pa2 may include pixel circuits PC with different structures, respectively. For example, the main pixel Pm may adopt Figure 4B The pixel circuit PC shown in FIG. 1 and the first auxiliary pixel Pa1 and the second auxiliary pixel Pa2 may adopt Figure 4A The pixel circuit PC shown in FIG. Various modifications can be made within the spirit and scope of the present disclosure.

[0121] Figure 5 1 is a view of an arrangement of a pixel circuit PC of a pixel of the display panel 10 according to the embodiment.

[0122] Reference Figure 5 , the driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7 may be arranged or disposed along the semiconductor layer 1130. The semiconductor layer 1130 may be arranged or disposed over a substrate on which a buffer layer may be formed or disposed, and the buffer layer may include an inorganic insulating material.

[0123] Some regions of the semiconductor layer 1130 may correspond to the semiconductor layers of the driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7. In other words, the semiconductor layers of the driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initialization thin film transistor T7 may be electrically connected to each other and may be bent into various shapes.

[0124] The semiconductor layer 1130 may include a channel region, a source region, and a drain region, and the source region and the drain region are arranged on opposite sides of the channel region. The source region and the drain region may be a source electrode and a drain electrode of a related or predetermined thin film transistor. Hereinafter, for the convenience of description, the source region and the drain region may be referred to as a source electrode and a drain electrode, respectively.

[0125] The driving thin film transistor T1 may include a driving gate electrode G1, a driving source electrode S1, and a driving drain electrode D1, the driving gate electrode G1 may overlap with the driving channel region, and the driving source electrode S1 and the driving drain electrode D1 may be on opposite sides of the driving channel region. The driving channel region may form a long channel length in a narrow space by having a substantially curved shape such as an Ω shape or an arch shape. In the case where the length of the driving channel region is long, the driving range of the gate voltage may be widened, and thus the grayscale of the light emitted from the organic light emitting diode OLED may be more finely controlled, and the display quality may be improved.

[0126] The switching thin film transistor T2 may include a switching gate electrode G2, a switching source electrode S2, and a switching drain electrode D2, the switching gate electrode G2 may overlap the switching channel region, and the switching source electrode S2 and the switching drain electrode D2 may be disposed on opposite sides of the switching channel region. The switching drain electrode D2 may be electrically connected to the driving source electrode S1.

[0127] The compensation thin film transistor T3 may be a dual thin film transistor and may include a compensation gate electrode G3, a compensation source electrode S3, and a compensation drain electrode D3, the compensation gate electrode G3 may overlap two compensation channel regions, and the compensation source electrode S3 and the compensation drain electrode D3 may be disposed on opposite sides of the compensation channel region. The compensation thin film transistor T3 may be electrically connected to the driving gate electrode G1 of the driving thin film transistor T1 through a node connection line 1174 described below.

[0128] The first initialization thin film transistor T4 may be a dual thin film transistor and may include a first initialization gate electrode G4, a first initialization source electrode S4, and a first initialization drain electrode D4, the first initialization gate electrode G4 may overlap with two first initialization channel regions, and the first initialization source electrode S4 and the first initialization drain electrode D4 may be disposed on opposite sides of the first initialization channel region.

[0129] The operation control thin film transistor T5 may include an operation control gate electrode G5, an operation control source electrode S5, and an operation control drain electrode D5, the operation control gate electrode G5 may overlap the operation control channel region, and the operation control source electrode S5 and the operation control drain electrode D5 may be disposed on opposite sides of the operation control channel region. The operation control drain electrode D5 may be electrically connected to the driving source electrode S1.

[0130] The emission control thin film transistor T6 may include an emission control gate electrode G6, an emission control source electrode S6, and an emission control drain electrode D6, the emission control gate electrode G6 may overlap the emission control channel region, and the emission control source electrode S6 and the emission control drain electrode D6 may be disposed on opposite sides of the emission control channel region. The emission control source electrode S6 may be electrically connected to the drive drain electrode D1.

[0131] The second initialization thin film transistor T7 may include a second initialization gate electrode G7 , a second initialization source electrode S7 , and a second initialization drain electrode D7 , the second initialization gate electrode G7 may overlap the second initialization channel region, and the second initialization source electrode S7 and the second initialization drain electrode D7 may be disposed on opposite sides of the second initialization channel region.

[0132] The thin film transistor may be electrically connected to the signal lines SL, SL-1, EL, and DL, the initialization voltage line VL, and the driving voltage line PL.

[0133] The scan line SL, the previous scan line SL- 1 , the emission control line EL, and the driving gate electrode G1 may be arranged or disposed over the semiconductor layer 1130 with an insulating layer(s) disposed therebetween.

[0134] The scan line SL may extend in the first direction. A plurality of regions or portions of the scan line SL may correspond to the switch gate electrode G2 and the compensation gate electrode G3, respectively. For example, regions of the scan line SL that may overlap with the channel region of the switch thin film transistor T2 and the channel region of the compensation thin film transistor T3, respectively, may be the switch gate electrode G2 and the compensation gate electrode G3, respectively.

[0135] The previous scan line SL-1 may extend in the first direction, and some regions or portions of the previous scan line SL-1 may correspond to the first initialization gate electrode G4 and the second initialization gate electrode G7, respectively. For example, regions of the previous scan line SL-1 that may overlap with the channel regions of the first initialization thin film transistor T4 and the second initialization thin film transistor T7, respectively, may be the first initialization gate electrode G4 and the second initialization gate electrode G7, respectively.

[0136] The emission control line EL may extend in the first direction. A plurality of regions of the emission control line EL may correspond to the operation control gate electrode G5 and the emission control gate electrode G6, respectively. For example, regions of the emission control line EL that may overlap with the channel region of the operation control thin film transistor T5 and the channel region of the emission control thin film transistor T6, respectively, may be the operation control gate electrode G5 and the emission control gate electrode G6, respectively.

[0137] The driving gate electrode G1 may be a floating electrode, and may be electrically connected to the compensation thin film transistor T3 through the node connection line 1174 described above.

[0138] The electrode voltage line HL may be arranged or disposed over the scan line SL, the previous scan line SL-1, the emission control line EL, and the driving gate electrode G1 with the insulating layer(s) disposed therebetween.

[0139] The electrode voltage line HL may extend in the first direction to intersect the data line DL and the driving voltage line PL. A portion of the electrode voltage line HL may cover or overlap at least a portion of the driving gate electrode G1, and may cooperate with the driving gate electrode G1 to form a storage capacitor Cst. For example, the driving gate electrode G1 may serve as a first storage capacitor plate CE1 (also referred to as a bottom electrode) of the storage capacitor Cst, and a portion of the electrode voltage line HL may serve as a second storage capacitor plate CE2 (also referred to as a top electrode) of the storage capacitor Cst.

[0140] The second storage capacitor plate CE2 of the storage capacitor Cst may be electrically connected to the driving voltage line PL. In this regard, the electrode voltage line HL may be electrically connected to the driving voltage line PL through the contact hole CNT, and the driving voltage line PL is arranged or disposed above the electrode voltage line HL. Therefore, the electrode voltage line HL may have the same voltage level (constant voltage) as the voltage level of the driving voltage line PL. For example, the electrode voltage line HL may have a constant voltage of about +5V. The electrode voltage line HL may be a lateral driving voltage line.

[0141] Since the driving voltage line PL may extend in the second direction and the electrode voltage line HL electrically connected to the driving voltage line PL may extend in the first direction intersecting the second direction, the driving voltage line PL and the electrode voltage line HL may form a mesh structure in the display area DA.

[0142] The data line DL, the driving voltage line PL, the initialization connection line 1173, and the node connection line 1174 may be arranged or disposed over the electrode voltage line HL with an insulating layer(s) disposed therebetween.

[0143] The data line DL may extend in the second direction and may be electrically connected to the switching source electrode S2 of the switching thin film transistor T2 through the contact hole 1154. A portion or region of the data line DL may be the switching source electrode S2.

[0144] As described above, the driving voltage line PL may extend in the second direction and may be electrically connected to the electrode voltage line HL through the contact hole CNT. The driving voltage line PL may be electrically connected to the operation control thin film transistor T5 through the contact hole 1155. The driving voltage line PL may be electrically connected to the operation control source electrode S5 through the contact hole 1155.

[0145] One end of the initialization connection line 1173 may be electrically connected to the first and second initialization thin film transistors T4 and T7 through the contact hole 1152 , and the other end of the initialization connection line 1173 may be electrically connected to an initialization voltage line VL described below through the contact hole 1151 .

[0146] One end of the node connection line 1174 may be electrically connected to the compensation drain electrode D3 through the contact hole 1156 , and the other end of the node connection line 1174 may be electrically connected to the driving gate electrode G1 through the contact hole 1157 .

[0147] The initialization voltage line VL may be arranged or disposed over the data line DL, the driving voltage line PL, the initialization link line 1173, and the node connection line 1174 with an insulating layer(s) disposed therebetween.

[0148] The initialization voltage line VL may extend in the first direction. The initialization voltage line VL may be electrically connected to the first initialization thin film transistor T4 and the second initialization thin film transistor T7 through the initialization connection line 1173. The initialization voltage line VL may have a constant voltage (eg, a constant voltage of about -2V).

[0149] The initialization voltage line VL may be arranged or disposed at the same layer as the pixel electrode 210 of the organic light emitting diode OLED, and may include a material that is the same as or similar to that of the pixel electrode 210. The pixel electrode 210 may be electrically connected to the emission control thin film transistor T6. The pixel electrode 210 may be electrically connected to the connection metal 1175 through the contact hole 1163, and the connection metal 1175 may be electrically connected to the emission control drain electrode D6 through the contact hole 1153.

[0150] although Figure 5 2 shows that the initialization voltage line VL may be arranged or provided at the same layer as the pixel electrode 210 , but in an embodiment, the initialization voltage line VL may be arranged or provided at the same layer as the electrode voltage line HL.

[0151] Figure 6 is a schematic cross-sectional view of a pixel circuit PC of a pixel according to the embodiment.

[0152] Reference Figure 6 , the auxiliary pixel Pa (hereinafter referred to as a pixel) and the transmission area TA may be arranged or disposed in the first area CA. The stacked structure of the pixel Pa may be described centering on the schematic cross-sectional structure of the first area CA.

[0153] The pixel Pa may include a thin film transistor TFT, a storage capacitor Cst, and an organic light emitting diode OLED. In order to ensure transmittance, the transmission area TA may include a transmission hole TAH in which some insulating layers may be removed.

[0154] The metal layer BML may be arranged or disposed under the thin film transistor TFT of the pixel Pa, and the metal layer BML may overlap with the thin film transistor TFT. Figure 6 Unlike the case of FIG. 1 , the metal layer BML that may overlap with the thin film transistor TFT may be omitted.

[0155] The substrate 100 may include a polymer resin. The substrate 100 may include at least one base layer and at least one inorganic layer, at least one base layer including an organic material. Although not shown, in an embodiment, the substrate 100 may include a first base layer, a first inorganic layer, a second base layer, and a second inorganic layer that may be sequentially stacked. The first base layer and the second base layer may each include a polymer resin. The first inorganic layer and the second inorganic layer may each be a barrier layer, and may include a single layer or multiple layers, the single layer or multiple layers including a silicon nitride (SiN x) and / or silicon oxide (SiO x ) of inorganic materials.

[0156] The buffer layer 111 may be arranged or disposed on the substrate 100, and may reduce or prevent foreign matter, moisture, or external air from penetrating from under the substrate 100, and provide a flat surface on the substrate 100. The buffer layer 111 may include an inorganic material such as an oxide or a nitride, an organic material, or an organic / inorganic composite material, and may include a single layer or multiple layers including an inorganic material and an organic material.

[0157] The metal layer BML may be arranged or disposed between the substrate 100 and the buffer layer 111. In an embodiment, the metal layer BML may be arranged or disposed between the second base layer and the second inorganic layer. In an embodiment, the metal layer BML may be provided in plurality in the first area CA, and some of the metal layers BML may be arranged or disposed on different layers.

[0158] The metal layer BML may be arranged or disposed under the pixel Pa to prevent the thin film transistor TFT arranged or disposed in the pixel Pa from being damaged or to prevent the characteristics of the thin film transistor TFT from being degraded.

[0159] The metal layer BML may be electrically connected to the wire GCL arranged or disposed on a different layer through a contact hole. The metal layer BML may receive a constant voltage or signal from the wire GCL. For example, the metal layer BML may receive a driving voltage ELVDD or a scan signal. Since the metal layer BML may receive a driving voltage ELVDD or a signal, the possibility of electrostatic discharge may be significantly reduced. In an embodiment, all metal layers BML may not receive an electrical signal. In the case where a plurality of metal layers BML are provided, at least one of the metal layers BML may be electrically floated, and the remaining metal layers BML may receive an electrical signal. Various modifications may be made within the spirit and scope of the present disclosure.

[0160] The metal layer BML may include at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). The metal layer BML may include a single layer or a multilayer including the above materials.

[0161] The thin film transistor TFT may be arranged or disposed on the buffer layer 111. The thin film transistor TFT may include a semiconductor layer A, a gate electrode GE, a source electrode SE, and a drain electrode DE, and the source electrode SE and the drain electrode DE may be electrode layers. The thin film transistor TFT may be electrically connected to the organic light emitting diode OLED to drive the organic light emitting diode OLED.

[0162] The semiconductor layer A may be arranged or disposed on the buffer layer 111, and may include polycrystalline silicon. In an embodiment, the semiconductor layer A may include amorphous silicon. In an embodiment, the semiconductor layer A may include an oxide of at least one of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The semiconductor layer A may include a channel region, a source region, and a drain region, and the source region and the drain region may be doped with impurities.

[0163] The semiconductor layer A may overlap the metal layer BML with the buffer layer 111 disposed therebetween. In an embodiment, the width of the semiconductor layer A may be smaller than the width of the metal layer BML. Therefore, when projected in a direction perpendicular to the substrate 100, the semiconductor layer A may completely overlap the metal layer BML. In an embodiment, the metal layer BML may be arranged or disposed to correspond to a pixel group Pg formed by pixels Pa. In this case, the semiconductor layer A may overlap the metal layer BML.

[0164] The first gate insulating layer 112 may cover or overlap the semiconductor layer A. The first gate insulating layer 112 may include an inorganic insulating material such as silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) and zinc oxide (ZnO). The first gate insulating layer 112 may include a single layer or a multilayer including an inorganic insulating material.

[0165] The gate electrode GE may be arranged or disposed over the first gate insulating layer 112 to overlap the semiconductor layer A. The gate electrode GE may include a single layer or multiple layers including molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti). For example, the gate electrode GE may be a single layer including molybdenum (Mo).

[0166] The second gate insulating layer 113 may cover or overlap the gate electrode GE. The second gate insulating layer 113 may include an inorganic insulating material such as silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2) and zinc oxide (ZnO). The second gate insulating layer 113 may include a single layer or a multilayer including an inorganic insulating material.

[0167] The top electrode CE2 of the storage capacitor Cst may be arranged or disposed on the second gate insulating layer 113. In the pixel circuit PC according to the embodiment, the top electrode CE2 may overlap the gate electrode GE thereunder. The gate electrode GE and the top electrode CE2 overlapping each other with the second gate insulating layer 113 disposed therebetween may constitute the storage capacitor Cst. The gate electrode GE may serve as the bottom electrode CE1 of the storage capacitor Cst.

[0168] The top electrode CE2 may include at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W) and copper (Cu), and include a single layer or multiple layers containing the above materials.

[0169] The interlayer insulating layer 115 may cover or overlap the top electrode CE2. The interlayer insulating layer 115 may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ) or zinc oxide (ZnO).

[0170] When the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 115 are collectively referred to as the inorganic insulating layer IL, the inorganic insulating layer IL may include a first hole H1 corresponding to the transmission area TA. The first hole H1 may expose the top surface of the buffer layer 111 or the substrate 100. The first hole H1 may include respective openings of the first gate insulating layer 112, the second gate insulating layer 113, and the interlayer insulating layer 115, which may overlap with each other and correspond to the transmission area TA. The respective openings may be formed separately by separate processes or simultaneously by the same process. In the case where the openings are formed by separate processes, a step difference may be formed on the inner surface of the first hole H1.

[0171] In embodiments, the inorganic insulating layer IL may include a groove exposing the buffer layer 111 instead of the first hole H1 .

[0172] In the embodiment, the inorganic insulating layer IL may not include the first hole H1 corresponding to the transmission area TA. Since the inorganic insulating layer IL may generally include an inorganic insulating material having excellent light transmittance, even if the inorganic insulating layer IL does not include the hole corresponding to the transmission area TA, the component 20 (see Figure 2 )The transmittance of the emitted / received light.

[0173] The source electrode SE and the drain electrode DE, which may be understood as an electrode layer, may be arranged or disposed on the interlayer insulating layer 115. The source electrode SE and the drain electrode DE may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and the source electrode SE and the drain electrode DE may include a single layer or multiple layers including the above materials. For example, the source electrode SE and the drain electrode DE may include a multilayer structure of Ti / Al / Ti.

[0174] The first planarization layer 117 may cover or overlap the source electrode SE and the drain electrode DE. The first planarization layer 117 may have a flat top surface so that the pixel electrode 221 disposed or provided thereon may be flatly formed.

[0175] The second planarization layer 118 may be arranged or disposed on the first planarization layer 117. The contact metal layer CM may be arranged or disposed between the first planarization layer 117 and the second planarization layer 118. The contact metal layer CM may electrically connect the drain electrode DE to the pixel electrode 221 through contact holes formed in the first planarization layer 117 and the second planarization layer 118, respectively.

[0176] The first planarization layer 117 and the second planarization layer 118 may include a single layer or multiple layers including an organic material or an inorganic material. The first planarization layer 117 and the second planarization layer 118 may include a general polymer (such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA) or polystyrene (PS)), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, and a mixture thereof. The first planarization layer 117 and the second planarization layer 118 may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2) or zinc oxide (ZnO). After forming the first planarization layer 117 and the second planarization layer 118, chemical mechanical polishing may be performed to provide a flat top surface. However, the present disclosure is not limited thereto, and other processes may be used to provide a flat top surface within the spirit and scope of the present disclosure.

[0177] The first and second planarization layers 117 and 118 may include a second hole H2 corresponding to the transmission area TA. The second hole H2 may overlap the first hole H1. Figure 6 It is shown that the second hole H2 may be larger than the first hole H1, but the first and second planarization layers 117 and 118 may be arranged or set to cover or overlap the edge of the first hole H1 of the inorganic insulating layer IL, and thus the width of the second hole H2 may be smaller than the width of the first hole H1.

[0178] The pixel electrode 221 on the second planarization layer 118 may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO) and aluminum zinc oxide (AZO). In an embodiment, the pixel electrode 221 may include a reflective layer, and the reflective layer includes silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound thereof. In an embodiment, the pixel electrode 221 may include ITO, IZO, ZnO or In on / below / below the reflective layer. 2 O 3 In an embodiment, the pixel electrode 221 may include a stack structure of ITO / Ag / ITO.

[0179] The pixel defining layer 119 may cover or overlap the edge of the pixel electrode 221. The pixel defining layer 119 may include an opening OP that overlaps each pixel electrode 221 and defines the emission area of ​​the pixel. The opening OP may be defined as the emission area of ​​the pixel Pa. The pixel defining layer 119 may prevent arcing, for example, from occurring at the edge of the pixel electrode 221 by increasing the distance between the edge of the pixel electrode 221 and the opposing electrode 223 disposed above the pixel electrode 221. The pixel defining layer 119 may include an organic insulating material including polyimide, polyamide, acrylic resin, benzocyclobutene, HMDSO, and phenolic resin, and the pixel defining layer 119 may be formed by spin coating or other processes within the spirit and scope of the present disclosure.

[0180] The pixel defining layer 119 may include a third hole H3 located or disposed in the transmission area TA. The third hole H3 may overlap the first hole H1 and the second hole H2. When the first hole H1, the second hole H2, and the third hole H3 are formed, the transmittance of the transmission area TA may be improved. The opposing electrode 223 described below may be arranged or disposed on the inner sidewalls of the first hole H1, the second hole H2, and the third hole H3. The pixel defining layer 119 may include Figure 6 The fourth hole H4 is shown in FIG. 1 , however, the present disclosure is not limited thereto. The pixel defining layer 119 may include any number of holes so that the light transmittance of the transmission area TA may be improved.

[0181] The first functional layer 222a may cover the pixel defining layer 119 or overlap it. The first functional layer 222a may include a single layer or multiple layers. Although not shown, the first functional layer 222a may include a hole transport layer (HTL) that may have a single layer structure. Alternatively, although not shown, the first functional layer 222a may include a hole injection layer (HIL) and the HTL. The first functional layer 222a may include a body to commonly correspond to the pixels Pa and Pm included in the first area CA and the display area DA.

[0182] The emission layer 222b may be arranged or disposed on the first functional layer 222a, corresponding to each of the pixel electrodes 221. The emission layer 222b may include a polymer material or a low molecular weight material, and may emit red light, green light, blue light, or white light.

[0183] The second functional layer 222c may be formed or disposed on the emission layer 222b. The second functional layer 222c may include a single layer or multiple layers. Although not shown, the second functional layer 222c may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The second functional layer 222c may include a body to commonly correspond to the pixels Pa and Pm included in the first area CA and the display area DA. In an embodiment, the first functional layer 222a and / or the second functional layer 222c may be omitted.

[0184] The relative electrode 223 may be arranged or disposed on the second functional layer 222c. The relative electrode 223 may include a conductive material having a low work function. For example, the relative electrode 223 may include a (semi) transparent layer, the (semi) transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or an alloy thereof. Alternatively, the relative electrode 223 may include a (semi) transparent layer including ITO, IZO, ZnO or In on / below / below the (semi) transparent layer including the above materials. 2 O 3The opposing electrode 223 may be provided as one body in the first area CA and the display area DA.

[0185] The pixel electrode 221 , the opposite electrode 223 , and layers arranged or disposed therebetween in the display area DA may constitute an organic light emitting diode OLED.

[0186] The capping layer 250 may be formed or disposed on the opposite electrode 223. The capping layer 250 may include, for example, lithium fluoride (LiF). Alternatively, the capping layer 250 may include an inorganic insulating material such as silicon nitride and / or include an organic insulating material. In an embodiment, the capping layer 250 may be omitted.

[0187] The first functional layer 222a, the second functional layer 222c, the opposing electrode 223, and the cover layer 250 may include a transmissive hole TAH corresponding to the transmissive area TA. For example, the first functional layer 222a, the second functional layer 222c, the opposing electrode 223, and the cover layer 250 may include openings corresponding to the transmissive area TA, respectively. In an embodiment, the widths of the plurality of openings that may form the transmissive hole TAH may be substantially the same. For example, the width of the opening of the opposing electrode 223 may be substantially the same as the width of the transmissive hole TAH.

[0188] When the transmission hole TAH corresponds to the transmission area TA, the transmission hole TAH may overlap the transmission area TA. In this case, the area of ​​the transmission hole TAH may be smaller than the area of ​​the first hole H1 formed in the inorganic insulating layer IL. For this reason, Figure 6 2 shows that the width Wt of the transmissive hole TAH is smaller than the width W1 of the first hole H1. Here, the area of ​​the transmissive hole TAH and the area of ​​the first hole H1 may be defined as the area of ​​the opening having the smallest area.

[0189] In the case where the transmission hole TAH is provided, a portion of the relative electrode 223 may be removed from the transmission area TA, and thus, the transmittance of the transmission area TA may be significantly improved. The relative electrode 223 located or provided in the first area CA may be formed by removing a portion of the relative electrode 223 that may correspond to the transmission area TA by laser lift-off, or may be formed by fine metal mask (FMM) mask patterning. Hereinafter, in the embodiment, it is assumed that the relative electrode 223 is formed in the first area CA by FMM mask patterning for description. However, the present disclosure is not limited thereto.

[0190] The organic light emitting diode OLED may be sealed by a thin film encapsulation layer 300. The thin film encapsulation layer 300 may be disposed or provided on the cover layer 250. The thin film encapsulation layer 300 may prevent external moisture or foreign substances from penetrating into the organic light emitting diode OLED.

[0191] The thin film encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Figure 6 3 shows that the thin film encapsulation layer 300 has a structure in which a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330 are stacked. In embodiments, the number of organic encapsulation layers, the number of inorganic encapsulation layers, and a stacking order may be modified.

[0192] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may include at least one inorganic insulating material such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride and silicon oxynitride, and may be formed by using chemical vapor deposition (CVD). However, the present disclosure is not limited thereto. The organic encapsulation layer 320 may include a polymer material. The polymer material may include a silicon resin, an acrylic resin, an epoxy resin, a polyimide and a polyethylene.

[0193] Each of the first inorganic encapsulation layer 310, the organic encapsulation layer 320, and the second inorganic encapsulation layer 330 may include a body to cover or overlap the display area DA and the first area CA. Accordingly, the first inorganic encapsulation layer 310, the organic encapsulation layer 320, and the second inorganic encapsulation layer 330 may be arranged or disposed inside the transmission hole TAH.

[0194] In an embodiment, the organic encapsulation layer 320 may include a body to cover or overlap the display area DA and the first area CA, and may not be arranged or disposed in the transmission area TA. In other words, the organic encapsulation layer 320 may include an opening corresponding to the transmission area TA. In this case, the first inorganic encapsulation layer 310 may contact the second inorganic encapsulation layer 330 inside the transmission hole TAH.

[0195] Figure 7 is a plan view of a portion or region of a display device 1 according to an embodiment, Figure 8 yes Figure 7 an enlarged plan view of a portion or area of Fig.9A and Fig. 9B is along Figure 8 A schematic cross-sectional view of the display device 1 taken along line BB′.

[0196] Reference Figure 7 , the first pixel group Pg1 and the second pixel group Pg2 may be arranged or disposed in the first area CA with the transmission area TA disposed therebetween. Figure 7 A first pixel group Pg1 and a second pixel group Pg2 are shown, but Fig.10As shown in FIG, the first pixel group Pg1 and the second pixel group Pg2 may be provided in plural. The first pixel group Pg1 and the second pixel group Pg2 may be spaced apart from each other in the second direction with the transmission area TA provided therebetween.

[0197] Each of the first pixel group Pg1 and the second pixel group Pg2 may include pixels. The first pixel group Pg1 may include a first pixel Pa1, and the second pixel group Pg2 may include a second pixel Pa2. Figure 7 In the embodiment, the plurality of first pixels Pa1 and the plurality of second pixels Pa2 may be arranged or disposed along the first direction, but in the embodiment, the plurality of first pixels Pa1 and the plurality of second pixels Pa2 may be arranged or disposed along the first direction and the second direction to form a matrix.

[0198] As mentioned above Figure 2 As described, the data line DL (e.g., a plurality of first lines) may extend in the second direction in the display area DA. In an embodiment, the data line DL may be electrically connected to the first pixel group Pg1. In this case, the first pixel group Pg1 may be closest to the display area DA. The data line DL may extend from a pixel located or disposed in the display area DA, and may be electrically connected to the first pixel Pa1 of the first pixel group Pg1. However, the present disclosure is not limited thereto.

[0199] The data line DL may be electrically connected to the first pixel group Pg1 and may not be electrically connected to the second pixel group Pg2. When the data line DL is not electrically connected to the second pixel group Pg2, the data line DL may be disconnected in the transmission area TA between the first pixel group Pg1 and the second pixel group Pg2.

[0200] In a comparative example, in the case where the data line extends from the first pixel group to the second pixel group, the data line may be arranged or set to cross the transmission area between the first pixel group and the second pixel group. Since the data line is arranged or set to cross the transmission area, the transmittance of the transmission area may be reduced. In this case, when light passes between the data lines crossing the transmission area, diffraction and reflection of light occur. In the case where a component such as a camera may be set, the light passing between the data lines crossing the transmission area causes distortion of the captured image, such as light diffusion or blurring.

[0201] Therefore, the display device 1 according to the embodiment provides a structure in which the data line DL may be disconnected between the first pixel group Pg1 and the second pixel group Pg2, so that the data line DL may not cross the transmission area TA, and the data signal may be received by bypassing the connection line (e.g., the third connection line CL3) of the first area CA. Thus, since the data line DL may not cross the transmission area TA, the transmittance of the transmission area TA may be increased, and the distortion of the image caused by the diffraction and reflection of light may be prevented from occurring.

[0202] In the first pixel group Pg1, the plurality of first pixels Pa1 may be electrically connected to the plurality of first connection lines CL1 extending in the first direction, respectively. In this case, for example, when the first pixels Pa1 may be electrically connected to the first connection lines CL1, the first connection lines CL1 may be electrically connected to Figure 5 Since the first pixel Pa1 receives the data signal through the first connection line CL1, each of the first connection lines CL1 may be electrically connected to the switching thin film transistor T2 of the pixel circuit PC. In this case, each of the first connection lines CL1 may be directly electrically connected to the switching thin film transistor T2, or may be electrically connected to the data line DL to transmit the data signal to the switching thin film transistor T2.

[0203] Similarly, in the second pixel group Pg2, the plurality of second pixels Pa2 may be electrically connected to the plurality of second connection lines CL2 extending in the first direction, respectively. Similarly, for example, since the second pixels Pa2 may receive data signals through the second connection lines CL2, each of the second connection lines CL2 may be electrically connected to Figure 5 The switching thin film transistor T2 of the pixel circuit PC.

[0204] Unlike the first pixel Pa1, the second pixel Pa2 may be disconnected from the data line DL and not electrically connected to the data line DL. Figure 7 As shown in , each of the second pixels Pa2 may include an auxiliary data line DL'. The pixel circuit PC, for example, the switching thin film transistor T2, may be electrically connected to the second connection line CL2 through the auxiliary data line DL'. Each of the second connection lines CL2 may be directly electrically connected to the switching thin film transistor T2 without passing through the auxiliary data line DL'.

[0205] The third connection lines CL3 may extend in the second direction and may be arranged or disposed in the third area PA. Each of the third connection lines CL3 may be electrically connected to the first connection lines CL1 and the second connection lines CL2, each of which extends in the first direction. In an embodiment, the first connection lines CL1 and the second connection lines CL2 may extend to the third area PA across the first area CA. The plurality of first connection lines CL1 may be electrically connected to the plurality of third connection lines CL3, respectively, through the plurality of first contact holes CNT1a, and the plurality of second connection lines CL2 may be electrically connected to the third connection lines CL3, respectively, through the plurality of second contact holes CNT2a.

[0206] In an embodiment, the first pixel Pa1 and the second pixel Pa2 arranged or disposed on the same column may be electrically connected to the same third connection line CL3. For example, a data signal transmitted to the first pixel Pa1 through the data line DL may be transmitted to the third connection line CL3 through the first connection line CL1, and transmitted to the second pixel Pa2 located on the same column through the second connection line CL2 electrically connected to the third connection line CL3. Thus, even if the data line DL may be disconnected in the transmission area TA, the first pixel Pa1 and the second pixel Pa2 on the same column may receive the same data signal.

[0207] like Figure 7 As shown in the figure, the lines VL, SL-1, SL and EL extending in the first direction may be arranged or set in the first area CA. The lines VL, SL-1, SL and EL may be arranged or set not only in the first area CA, but also in the third area PA and the second area (or display area) DA. The lines VL, SL-1, SL and EL may be initialization voltage lines VL, previous scan lines SL-1, scan lines SL and emission control lines EL, respectively, and may supply initialization voltages, previous scan signals, scan signals and emission control signals to pixels, respectively. Similar to other connecting lines in the embodiment, the lines VL, SL-1, SL and EL may overlap with the metal layer BML and may not overlap with the transmission area TA. The metal layer BML may be arranged or set below the lines VL, SL-1, SL and EL, and may prevent diffraction and reflection of light caused by the lines VL, SL-1, SL and EL.

[0208] Refer to the enlarged Figure 7 A portion or region of the first pixel group Pg1 Figure 8 , one end and the other end of the first connection line CL1 may be electrically connected to the data line DL and the third connection line CL3 through the contact holes CNT1a and CNT1b, respectively.

[0209] Reference Fig.9A and Fig. 9B , the data line DL and the third connection line CL3 may be arranged or disposed on the same layer and may include the same or similar materials. The first connection line CL1 may be arranged or disposed on a different layer from the data line DL and the third connection line CL3 and may include different materials. In this case, when an element is referred to as being arranged or disposed on the same layer or referred to as including the same or similar materials, the element may be formed by using the same mask process during the manufacturing process. One end and the other end of the first connection line CL1 may be electrically connected to the third connection line CL3 and the data line DL through contact holes CNT1a and CNT1b, respectively.

[0210] In an embodiment, Fig.9AAs shown in , the first insulating layer IL1 may be arranged or disposed on the substrate 100, the data line DL and the third connection line CL3 may be arranged or disposed on the first insulating layer IL1, the second insulating layer IL2 may be arranged or disposed on the data line DL and the third connection line CL3, and the first connection line CL1 may be arranged or disposed on the second insulating layer IL2. The first connection line CL1 may be electrically connected to the third connection line CL3 and the data line DL through the contact holes CNT1a and CNT1b passing through the second insulating layer IL2.

[0211] Refer to Figure 6 In an embodiment, the data line DL and the third connection line CL3 may include a material that is the same as or similar to that of the source electrode SE and the drain electrode DE of the thin film transistor TFT. The first connection line CL1 may include a material that is the same as or similar to that of the contact metal layer CM. In this case, the first insulating layer IL1 may include a buffer layer 111, a first gate insulating layer 112, a second gate insulating layer 113, and an interlayer insulating layer 115. The second insulating layer IL2 may include a first planarizing layer 117 and a second planarizing layer 118. Some of the above layers may be removed, or other layers may be added.

[0212] In an embodiment, Fig. 9B As shown in FIG. 1 , the first insulating layer IL1 may be arranged or disposed on the substrate 100, the first connection line CL1 may be arranged or disposed on the first insulating layer IL1, the second insulating layer IL2 may be arranged or disposed on the first connection line CL1, and the data line DL and the third connection line CL3 may be arranged or disposed on the second insulating layer IL2. The first connection line CL1 may be electrically connected to the third connection line CL3 and the data line DL through the contact holes CNT1a and CNT1b passing through the second insulating layer IL2.

[0213] Refer to Figure 6 In an embodiment, the data line DL and the third connection line CL3 may include a material that is the same as or similar to that of the source electrode SE and the drain electrode DE of the thin film transistor TFT. The first connection line CL1 may include a material that is the same as or similar to that of the top electrode CE2 or the gate electrode GE of the storage capacitor Cst.

[0214] For example, in the case where the first connection line CL1 includes a material that is the same as or similar to that of the top electrode CE2 of the storage capacitor Cst, the first insulating layer IL1 may include a buffer layer 111, a first gate insulating layer 112, and a second gate insulating layer 113. The second insulating layer IL2 may include an interlayer insulating layer 115, a first planarizing layer 117, and a second planarizing layer 118. For example, in the case where the first connection line CL1 includes a material that is the same as or similar to that of the gate electrode GE, the first insulating layer IL1 may include a buffer layer 111 and a first gate insulating layer 112. The second insulating layer IL2 may include a second gate insulating layer 113, an interlayer insulating layer 115, a first planarizing layer 117, and a second planarizing layer 118.

[0215] although Fig.9A and Fig. 9B The first connection line CL1 is described as an example, but the second connection line CL2 may have the same structure as the first connection line CL1. The first and second connection lines CL1 and CL2 may be arranged or disposed on the same layer and may include the same or similar material.

[0216] Figures 10 to 13 is a plan view of a portion or region of the display device 1 according to the embodiment. Figures 10 to 13 Shows Figure 7 deformation.

[0217] In addition to the first pixel group Pg1 and the second pixel group Pg2 being provided in plural, Fig.10 The embodiment shown in Figure 7 The embodiments shown in are substantially the same. In the following, the differences are mainly described and the Figure 7 , Figure 8 , Fig.9A and Fig. 9B Duplicate description in .

[0218] Reference Fig.10 , the first pixel group Pg1 and the second pixel group Pg2 may be provided in plurality. The first pixel groups Pg1-1 and Pg1-2 may be spaced apart from each other at a predetermined interval d in the first direction, and the second pixel groups Pg2-1 and Pg2-2 may be spaced apart from each other at a predetermined interval d in the first direction. The transmission area TA may be arranged or disposed between the first pixel groups Pg1-1 and Pg1-2 and the second pixel groups Pg2-1 and Pg2-2. The first pixel groups Pg1-1 and Pg1-2 and the second pixel groups Pg2-1 and Pg2-2 may be spaced apart from each other in the second direction with the transmission area TA disposed therebetween. In an embodiment, the area of ​​the transmission area TA may be adjusted by adjusting the predetermined interval d between the first pixel groups Pg1-1 and Pg1-2 and between the second pixel groups Pg2-1 and Pg2-2.

[0219] Each of the first pixel groups Pg1-1 and Pg1-2 and the second pixel groups Pg2-1 and Pg2-2 may include pixels. Each of the first pixel groups Pg1-1 and Pg1-2 may include a first pixel Pa1, and each of the second pixel groups Pg2-1 and Pg2-2 may include a second pixel Pa2.

[0220] The plurality of first pixel groups Pg1 may be electrically connected to the plurality of first connection lines CL1 extending in the first direction, respectively. In an embodiment, the (1-1)th pixel group Pg1-1 may be electrically connected to the (1-1)th connection line CL1-1, and the (1-2)th pixel group Pg1-2 may be electrically connected to the (1-2)th connection line CL1-2. In this case, some or a predetermined number of the (1-2)th connection lines CL1-2 may cross the (1-1)th pixel group Pg1-1, and may overlap with the (1-1)th pixel group Pg1-1.

[0221] Similarly, each of the second pixel groups Pg2 may be electrically connected to the second connection lines CL2 extending in the first direction, respectively. In an embodiment, the (2-1)th pixel group Pg2-1 may be electrically connected to the (2-1)th connection line CL2-1, and the (2-2)th pixel group Pg2-2 may be electrically connected to the (2-2)th connection line CL2-2. In this case, some or a predetermined number of the (2-2)th connection lines CL2-2 may cross the (2-1)th pixel group Pg2-1, and may overlap with the (2-1)th pixel group Pg2-1.

[0222] The third connection lines CL3-1 and CL3-2 extending in the second direction may be arranged or disposed outside the first area CA, for example, arranged or disposed in the third area PA. The (1-1)th connection line CL1-1 and the (2-1)th connection line CL2-1 may be electrically connected to the (3-1)th connection line, respectively. The (1-2)th connection line CL1-2 and the (2-2)th connection line CL2-2 may be electrically connected to the (3-2)th connection line CL3-2, respectively.

[0223] Reference Fig.11 , Fig.11 An embodiment may be similar to Fig.10 of the embodiments, and with Fig.10 The embodiment may be different in that the third connection lines CL3-1 and CL3-2 may be arranged or disposed on opposite sides (eg, left and right sides) of the first area CA.

[0224] The (3-1)th connection line CL3-1 extending in the second direction may be located or disposed in the third area PA on one side of the first area CA, and the (3-2)th connection line CL3-2 extending in the second direction may be located or disposed in the third area PA on the other side of the first area CA. The (3-1)th connection line CL3-1 and the (3-2)th connection line CL3-2 may provide data signals to pixel groups arranged or disposed on the same column.

[0225] In an embodiment, the (1-1)th pixel group Pg1-1 may be electrically connected to the (1-1)th connection line CL1-1, and the (2-1)th pixel group Pg2-1 may be electrically connected to the (2-1)th connection line CL2-1. The (1-1)th connection line CL1-1 and the (2-1)th connection line CL2-1 may be electrically connected to the (3-1)th connection line CL3-1, respectively.

[0226] Similarly, the (1-2)th pixel group Pg1-2 may be electrically connected to the (1-2)th connection line CL1-2, and the (2-2)th pixel group Pg2-2 may be electrically connected to the (2-2)th connection line CL2-2. The (1-2)th connection line CL1-2 and the (2-2)th connection line CL2-2 may be electrically connected to the (3-2)th connection line CL3-2, respectively.

[0227] In this case, with Fig.10 Differently, the (1-2)th connection line CL1-2 may not overlap with the (1-1)th pixel group Pg1-1. The first connection lines CL1-1 and CL1-2 electrically connected to the first pixel groups Pg1-1 and Pg1-2 may be electrically connected to adjacent third connection lines CL3-1 and CL3-2 among the third connection lines CL3-1 and CL3-2, respectively. Therefore, the (1-2)th connection line CL1-2 may not overlap with the (1-1)th pixel group Pg1-1, and the (1-1)th connection line CL1-1 may not overlap with the (1-2)th pixel group Pg1-2. This may be equally applicable to the second pixel group Pg2.

[0228] although Figure 7 The embodiment describes a structure in which the data line DL extending in the second direction may be disconnected in the transmission area TA, but the embodiment may be applicable to the lines VL, SL-1, SL, and EL extending in the first direction.

[0229] Reference Fig.12First, the first pixel groups Pg1-1 and Pg1-2 may be spaced apart from each other at a predetermined interval d in the second direction, and the second pixel groups Pg2-1 and Pg2-2 may be spaced apart from each other at a predetermined interval d in the second direction. The transmission area TA may be located or disposed between the first pixel groups Pg1-1 and Pg1-2 and the second pixel groups Pg2-1 and Pg2-2, and the first pixel groups Pg1-1 and Pg1-2 and the second pixel groups Pg2-1 and Pg2-2 may be spaced apart from each other in the first direction with the transmission area TA disposed therebetween. In an embodiment, the area of ​​the transmission area TA may be adjusted by adjusting the predetermined interval d between the first pixel groups Pg1-1 and Pg1-2 and between the second pixel groups Pg2-1 and Pg2-2.

[0230] The plurality of first pixel groups Pg1 may be electrically connected to the plurality of first connection lines CL1 extending in the second direction, respectively. In an embodiment, the (1-1)th pixel group Pg1-1 may be electrically connected to the (1-1)th connection line CL1-1, and the (1-2)th pixel group Pg1-2 may be electrically connected to the (1-2)th connection line CL1-2. In this case, some or a predetermined number of the (1-1)th connection lines CL1-1 may cross the (1-2)th pixel group Pg1-2, and may overlap with the (1-2)th pixel group Pg1-2.

[0231] Similarly, the plurality of second pixel groups Pg2 may be electrically connected to the plurality of second connection lines CL2 extending in the second direction, respectively. In an embodiment, the (2-1)th pixel group Pg2-1 may be electrically connected to the (2-1)th connection line CL2-1, and the (2-2)th pixel group Pg2-2 may be electrically connected to the (2-2)th connection line CL2-2. In this case, some or a predetermined number of the (2-1)th connection lines CL2-1 may cross the (2-2)th pixel group Pg2-2, and may overlap with the (2-2)th pixel group Pg2-2.

[0232] The third connection lines CL3-1 and CL3-2 extending in the first direction may be arranged or disposed outside the first area CA, for example, arranged or disposed in the third area PA. The (1-1)th connection line CL1-1 and the (2-1)th connection line CL2-1 may be electrically connected to the (3-1)th connection line CL3-1, respectively. The (1-2)th connection line CL1-2 and the (2-2)th connection line CL2-2 may be electrically connected to the (3-2)th connection line CL3-2, respectively.

[0233] The embodiment shows that each of the third connection lines CL3 - 1 and CL3 - 2 may include four lines, and the four lines may transmit the initialization voltage, the previous scan signal, the scan signal, and the emission control signal to each pixel, respectively.

[0234] Auxiliary lines VL', SL-1', SL' and EL' extending in the first direction may be arranged or disposed in the second pixel group Pg2. The auxiliary lines VL', SL-1', SL' and EL' may transmit an initialization voltage, a previous scan signal, a scan signal and an emission control signal to the second pixel Pa2 on the same row, respectively.

[0235] Fig.13 An embodiment may be similar to Fig.12 However, Fig.13 Examples and Fig.12 The embodiment may be different in that the third connection lines CL3-1 and CL3-2 may be arranged or disposed on opposite sides (eg, top and bottom sides) of the first area CA.

[0236] A plurality of (3-1)th connection lines CL3-1 extending in the first direction may be located or disposed in the third area PA on one side (bottom side) of the first area CA, and a plurality of (3-2)th connection lines CL3-2 extending in the first direction may be located or disposed in the third area PA on the other side (top side) of the first area CA. The (3-1)th connection line CL3-1 and the (3-2)th connection line CL3-2 may each transmit an initialization voltage, a previous scan signal, a scan signal, and an emission control signal to a pixel group on the same row.

[0237] FIG. 14A to FIG. 14D is a view showing a pixel arrangement of a display device 1 according to the embodiment. FIG. 14A to FIG. 14D The pixel arrangement of the first area CA is shown.

[0238] Reference Fig.14A The transmission area TA may be arranged or disposed between the pixel groups Pg. The pixel groups Pg and the transmission area TA may be arranged or disposed alternately. Fig.14A In the case of a pixel arrangement of FIG. 4 , the resolution of the first area CA may be approximately 1 / 2 of the resolution of the display area DA.

[0239] Similarly, refer to Fig. 14B The transmission area TA may be arranged or disposed between the pixel groups Pg, and the transmission area TA may have a structure in which the transmission areas TA may be connected to each other as one body. Fig. 14B In the case of a pixel arrangement of FIG. 4 , the resolution of the first area CA may be approximately 1 / 4 of the resolution of the display area DA.

[0240] Reference Fig. 14C , the resolution of the first area CA may be about 3 / 8 of the resolution of the display area DA. Fig.14D , the resolution of the first area CA may be about 1 / 16 of the resolution of the display area DA.

[0241] The first area CA may have FIG. 14A to FIG. 14D In an embodiment, the first area CA may have a locally different pixel arrangement structure. For example, the first area CA may adopt a structure in which a pixel arrangement with a relatively high resolution is applied to a portion of the first area CA that may be adjacent to the display area DA, and the area of ​​the transmission area TA may increase toward the central portion thereof. In an embodiment, the display device 1 may have a pixel arrangement structure in which a plurality of first areas CA may be provided and the plurality of first areas CA may respectively have different pixel arrangement structures.

[0242] So far, the display device 1 has been mainly described, however, the embodiment is not limited thereto. For example, a method of manufacturing a display device also falls within the scope of the present disclosure.

[0243] According to the embodiment, a display panel including an expanded display area so that an image can be displayed even in a region where components can be arranged or set and a display device including the display panel can be realized. However, the scope of the present disclosure is not limited by this effect.

[0244] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the drawings, it will be understood by those of ordinary skill in the art that various changes in form and detail may be made in the embodiments without departing from the spirit and scope as defined in the claims below.

Claims

1. A display panel, comprising: A substrate, comprising a first region, a second region and a third region, wherein the first region comprises a transmission region, and the second region and the third region are adjacent to the first region; A first pixel group and a second pixel group are both arranged in the first area, and the transmission area is arranged between the first pixel group and the second pixel group; a plurality of first connection lines extending in a first direction and electrically connected to a plurality of first pixels of the first pixel group; a plurality of second connection lines extending in the first direction and electrically connected to a plurality of second pixels of the second pixel group; as well as a plurality of third connection lines extending in the second direction and arranged in the third region, the plurality of third connection lines being electrically connected to the plurality of first connection lines and the plurality of second connection lines, The second direction intersects with the first direction.

2. The display panel according to claim 1, further comprising a plurality of wirings extending in the second direction in the second region, in, The plurality of wirings are electrically connected to the first pixel group and disconnected between the first pixel group and the second pixel group.

3. The display panel according to claim 2, wherein: The plurality of wirings include a data line supplying a data signal.

4. The display panel according to claim 3, wherein: The plurality of wirings and the plurality of third connection lines are disposed on the same layer.

5. The display panel according to claim 1, wherein: The plurality of first connection lines and the plurality of second connection lines are disposed on the same layer. 6 . The display panel according to claim 1 , further comprising a plurality of auxiliary wirings extending in the second direction and electrically connected to the plurality of second pixels.

7. The display panel according to claim 6, wherein: The plurality of second connection lines are electrically connected to the plurality of auxiliary wirings.

8. The display panel according to claim 1, further comprising a first metal layer, wherein the first metal layer is disposed in the first region. in, The first metal layer overlaps the first pixel group and the plurality of first connection lines.

9. The display panel according to claim 8, further comprising a second metal layer disposed in the first region, the second metal layer being spaced apart from the first metal layer, in, The second metal layer overlaps the second pixel group and the plurality of second connection lines.

10. The display panel according to claim 9, wherein: The first metal layer and the second metal layer receive a constant voltage from a conductive line.

11. The display panel according to claim 9, wherein: Each of the plurality of first pixels and the plurality of second pixels comprises a pixel circuit, wherein the pixel circuit comprises a thin film transistor, The thin film transistor includes a semiconductor layer and a gate electrode overlapping at least a portion of the semiconductor layer, and The first metal layer and the second metal layer are disposed between the substrate and the semiconductor layer.

12. The display panel according to claim 1, wherein: The third area includes a non-display area surrounding the second area.

13. The display panel according to claim 1, wherein: The third region surrounds at least a portion of the first region and is disposed between the first region and the second region.

14. The display panel according to claim 1, further comprising: A first conductive layer, disposed above the substrate; as well as A second conductive layer is disposed above the first conductive layer, wherein: An insulating layer is provided between the first conductive layer and the second conductive layer, The plurality of third connection lines and the first conductive layer include the same material, and The plurality of first connection lines and the plurality of second connection lines include the same material as the second conductive layer.

15. The display panel according to claim 1, wherein: Each pixel of the plurality of first pixels and the plurality of second pixels comprises: display components, and A pixel circuit including a thin film transistor, The thin film transistor comprises: Semiconductor layer; a gate electrode overlapping at least a portion of the semiconductor layer, and an electrode layer electrically connected to the semiconductor layer, and The plurality of third connection lines and the electrode layer include the same material.

16. The display panel according to claim 15, wherein: Each of the plurality of first pixels and the plurality of second pixels includes a contact metal layer disposed between the display element and the thin film transistor and electrically connecting the display element to the thin film transistor, and The plurality of first connection lines and the plurality of second connection lines include the same material as the contact metal layer.

17. The display panel according to claim 1, wherein: The first region is at least partially surrounded by the second region.

18. The display panel according to claim 1, wherein: The resolution of the first region is lower than the resolution of the second region.

19. A display device comprising: A display panel, comprising a substrate, the substrate comprising a first area, a second area and a third area, the first area comprising a transmissive area, and the second area and the third area are disposed adjacent to the first area; as well as A component is disposed in the first area of ​​the display panel, Wherein, the display panel comprises: A first pixel group and a second pixel group are both arranged in the first area, and the transmission area is between the first pixel group and the second pixel group; a plurality of first connection lines extending in a first direction and electrically connected to a plurality of first pixels of the first pixel group; a plurality of second connection lines extending in the first direction and electrically connected to a plurality of second pixels of the second pixel group; and A plurality of third connection lines extending in a second direction intersecting the first direction and disposed in the third region, the plurality of third connection lines being electrically connected to the plurality of first connection lines and the plurality of second connection lines.

20. The display device according to claim 19, wherein: The assembly includes an imaging element.

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