Unregulated Power Converter with Current Sharing Control

Abstract

The present application relates to an unregulated power converter with current sharing control. According to one aspect, the present invention discloses an unregulated power converter, which includes a plurality of switching energy storage converter (STC) modules, which are configured to be connected in parallel and connected to a load. The plurality of STC modules include a first STC module, which is configured to generate a first output current; and a second STC module, which is configured to generate a second output current. The first STC module includes an output current (OC) measurement circuit, which is configured to measure the value of the first output current; and a dead time (DT) adjuster, which is configured to compare the value of the first output current with the value of the minimum output current provided by the plurality of STC modules. The DT adjuster is configured to adjust the dead time in response to the value of the first output current being greater than the value of the minimum output current.

Description

Technical Field

[0001] This specification relates to an unregulated power converter with current sharing control. Background Art

[0002] In response to two or more switching energy storage converter (STC) modules being connected in parallel to a load, the output current from one of the STC modules may begin to diverge from the output current from another STC module. For example, due to differences in STC resonant output impedances, differences in energy storage resonant frequencies, different temperature distributions, and / or the effects of parasitic elements, one or more of the STC modules may consume a disproportionate or excessive portion of the load. The uneven distribution of output current between the connected STC modules may adversely affect the efficiency of the converter, as well as increase the risk of damage to the converter (e.g., damage that may occur when one or more STC modules provide a higher output current than other STC modules). Summary of the invention

[0003] According to one aspect, an unregulated power converter includes a plurality of switching energy storage converter (STC) modules configured to be connected in parallel and connected to a load. The plurality of STC modules include a first STC module configured to generate a first output current; and a second STC module configured to generate a second output current. The first STC module includes an output current (OC) measurement circuit configured to measure the value of the first output current; and a dead time (DT) adjuster configured to compare the value of the first output current with the value of the minimum output current provided by the plurality of STC modules. The DT adjuster is configured to adjust the dead time in response to the value of the first output current being greater than the value of the minimum output current.

[0004] According to some aspects, the non-regulated power converter includes one or more of the following features (or any combination thereof). The DT regulator is configured to determine a current sharing (CS) dead time based on a difference between a minimum output current and a first output current, wherein the DT regulator is configured to increase the dead time by a CS dead time. The first STC module includes an STC circuit, the STC circuit including one or more resonant capacitors, one or more resonant inductors, and a plurality of switches. The STC module includes a control logic component, the control logic component being configured to generate one or more control signals to control a plurality of switches so that an updated dead time is inserted at the end of an STC phase or at the end of an STC cycle. The updated dead time is a time period during which a plurality of switches are deactivated. The non-regulated power converter includes a current sharing (CS) interface connected to a plurality of STC modules, wherein the CS interface is configured to provide a value of a minimum output current using a plurality of STC modules. The CS interface may include a dedicated analog pin, wherein a voltage on the dedicated analog pin indicates a value of a minimum output current. The CS interface may include one or more digital communication lines connected between a plurality of STC modules. The DT regulator is configured to obtain a value of a minimum output current via a CS interface. The first STC module includes a current sharing (CS) circuit connected to the CS interface, wherein the CS circuit is configured to obtain a value of the minimum output current from the CS interface, and in response to a value of the first output current being less than a value of the minimum output current, update the value of the minimum output current to the value of the first output current.

[0005] According to one aspect, an unregulated power converter includes a plurality of switching energy storage converter (STC) modules, which are configured to be connected in parallel and connected to a load. The plurality of STC modules include a first STC module, which is configured to generate a first output current; and a second STC module, which is configured to generate a second output current. The unregulated power converter includes a current sharing (CS) interface connected to the plurality of STC modules, wherein the CS interface is configured to provide a minimum output current value using the plurality of STC modules, and the minimum output current value is the minimum value of the first output current and the second output current. The first STC module is configured to increase the dead time in response to the value of the first output current being greater than the value of the minimum output current.

[0006] According to some aspects, the unregulated power converter includes one or more features (or any combination thereof) of the above / following features. The first STC module includes an STC circuit, which includes one or more resonant capacitors, one or more resonant inductors and multiple switches. The first STC module may include an output current (OC) measurement circuit, which is configured to measure the value of the first output current, wherein the OC measurement circuit is coupled to the output node of the STC circuit. The first STC module may include a dead time (DT) adjuster, which is configured to compare the value of the first output current with the value of the minimum output current from the CS interface, wherein the DT adjuster is configured to increase the dead time in response to the value of the first output current being greater than the value of the minimum output current. The first STC module includes a control logic component, which is configured to generate control signals for multiple switches so that an adjusted dead time is added at the end of an STC phase or an STC cycle, wherein the adjusted dead time is a time period during which multiple switches are deactivated. The first STC module includes a current sharing (CS) circuit connected to a CS interface, wherein the CS circuit is configured to obtain a value of a minimum output current from the CS interface, and in response to the value of the first output current being less than the value of the minimum output current, the value of the minimum output current is updated to the value of the first output current. The first STC module is configured to convert an input voltage to a first output voltage during a plurality of STC cycles, wherein the plurality of STC cycles include a first STC cycle, followed by a second STC cycle, and the first STC module is configured to increase the dead time between the first STC cycle and the second STC cycle. The first STC module is configured to convert an input voltage to a first output voltage during a plurality of STC cycles, wherein a single STC cycle includes a plurality of STC phases, wherein each STC phase is configured to generate a different resonant frequency. The first STC module is configured to increase the dead time between STC phases adjacent in time within a single STC cycle. The first STC module is configured to determine a current sharing (CS) dead time based on the difference between the minimum output current and the first output current, wherein the adjusted dead time includes a default dead time plus a CS dead time. The CS interface includes one or more digital serial communication lines connected to the plurality of STC modules. The CS interface includes a dedicated analog pin, wherein a voltage on the dedicated analog pin indicates a value of a minimum output current.

[0007] According to one aspect, a method for controlling an unregulated power converter includes measuring, by a first switching energy storage converter (STC) module connected in parallel with a second STC module, a value of a first output current generated by a first STC module; obtaining, by the first STC module, a value of a minimum output current via a current sharing (CS) interface; comparing, by the first STC module, the value of the first output current with the value of the minimum output current; determining, by the first STC module, a current sharing (CS) dead time in response to the value of the first output current being greater than the value of the minimum output current; and increasing, by the first STC module, a dead time associated with an STC cycle of the first STC module by a CS dead time determined by the dead time.

[0008] According to some aspects, the method may include one or more of the above / following features. Dead time is inserted at the end of the STC cycle or at the end of the STC phase. The method may include comparing, by the second STC module, a second output current generated by the second STC module with a minimum output current from the CS interface, and updating, by the second STC module, the minimum output current on the CS interface to correspond to the second output current in response to the second output current being less than the minimum output current. The determined CS dead time may be proportional to the difference between the first output current and the minimum output current.

[0009] The details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A An unregulated power converter having a plurality of switching tank converter (STC) modules according to one aspect is shown.

[0011] Figure 1B An example of a first STC module according to an aspect is shown.

[0012] Figure 2 An example of an STC circuit of an STC module according to an aspect is shown.

[0013] Figure 3A A digital implementation of a current sharing (CS) interface for an unregulated power converter according to one aspect is shown.

[0014] Figure 3B An example of a current sharing (CS) circuit of an STC module according to an aspect is shown.

[0015] Figure 4 A simulated implementation of a CS interface according to an aspect is shown.

[0016] Figure 5 A flow chart depicting exemplary operation of an STC module according to an aspect is shown.

[0017] Figure 6 Control signals of a control logic component of an STC module are shown without enabling a current sharing mechanism according to one aspect.

[0018] Fig. 7A Control signals of a control logic component of an STC module are shown with a current sharing mechanism enabled according to one aspect.

[0019] Figure 7B Shown is a graph depicting current waveforms of two STC modules according to one aspect.

[0020] Fig. 8A Control signals of the control logic component of the STC module are shown with the current sharing mechanism enabled according to another aspect.

[0021] Figure 8B Shown is a graph depicting current waveforms of two STC modules according to another aspect.

[0022] Fig. 9 A simulated implementation of a dead time (DT) adjuster of an STC module according to one aspect is shown.

[0023] Fig.10 A digital implementation of a DT regulator of an STC module according to one aspect is shown.

[0024] Fig.11 Shown is a graph depicting output current from two STC modules according to an aspect.

[0025] FIG. 12A to FIG. 12C Various signals of an unregulated converter without a current sharing mechanism enabled are shown according to an aspect.

[0026] FIG. 13A to FIG. 13C Various signals of an unregulated converter with a current sharing mechanism enabled according to an aspect are shown. DETAILED DESCRIPTION

[0027] The following description provides an unregulated power converter having a plurality of STC modules configured to be connected in parallel to a load, wherein each STC module is configured to deliver substantially the same output current over time, regardless of differences in STC resonant output impedance, differences in energy storage resonant frequency, different temperature distributions, and / or the effects of parasitic elements (e.g., resistance, inductance, or capacitance). Thus, the overall efficiency of the unregulated power converter can be improved, and the risk of STC module damage can be reduced or eliminated.

[0028] The non-regulated power converter includes a current sharing (CS) interface connected to a plurality of STC modules. In some examples, each STC module is configured to communicate with the CS interface to obtain the value of the minimum output current provided by the STC module. If the first STC module generates a first output current, the second STC module generates a second output current, and the third STC module generates a third output current, the value of the minimum output current is the minimum of the first output current, the second output current, and the third output current. In some examples, the CS interface includes an analog implementation, wherein the CS interface is a dedicated analog pin connected to the STC module, and the analog voltage on the dedicated pin indicates the value of the minimum output current. In some examples, the CS interface includes a digital implementation, wherein the CS interface is one or more digital (serial or parallel) communication lines between the STC modules, wherein the value of the minimum output current is digitally exchanged between the STC modules.

[0029] Each STC module may include an STC circuit (e.g., including one or more resonant energy storage devices), an output current (OC) measurement circuit, a current sharing (CS) circuit, a dead time (DT) adjuster, and a control logic component. The STC circuit may include one or more resonant capacitors, one or more resonant inductors, one or more filter capacitors, and multiple switches (e.g., transistors). The switch may be controlled by a control signal generated by the control logic component. In addition, the activation / deactivation of the switch may control the STC phase of the STC cycle of the corresponding STC module, wherein each STC phase generates a different resonant frequency in the resonant energy storage device. In some examples, a specific STC cycle includes four STC phases, such as a first STC phase, a second STC phase, a third STC phase, and a fourth STC phase. In some examples, during a single STC cycle, the first STC phase and the third STC phase are activated simultaneously, followed by the simultaneous activation of the second STC phase and the fourth STC phase.

[0030] Each STC module can provide (and / or update) the value of the minimum output current on the CS interface. For example, the CS circuit of the corresponding STC module can compare the value of its output current with the value of the minimum output current on the CS interface, and if its output current is less than the minimum output current, the CS circuit can use the value of the output current to update the value of the minimum output current. In some examples, the CS circuit includes one or more analog components. In some examples, the CS circuit includes one or more digital components.

[0031] Each STC module can obtain the value of the minimum output current from the CS interface, and compare the value of the minimum output current with its corresponding output current. For example, the OC measurement circuit of the corresponding STC module can measure its average output current. If the value of its corresponding output current is greater than the value of the minimum output current from the CS interface, the STC module can adjust the dead time during the STC cycle. The dead time can be the time period when the switch of the STC circuit is deactivated. The DT regulator of the corresponding STC module can receive the output current from the OC measurement circuit and the minimum output current from the CS interface, and adjust the dead time so that the dead time increases at the end of the STC phase and / or the end of the STC cycle (for example, after the deactivation of the first STC phase / third STC phase, and / or after the deactivation of the second STC phase / fourth STC phase). The control logic component can receive the updated dead time, and then generate appropriate control signals for the switches of the STC circuit so that the updated dead time is achieved at the end of the STC phase and / or the STC cycle. An increase in dead time may result in a decrease in the output current provided by the stronger STC module, causing the output currents provided by the STC modules to converge toward each other.

[0032] Figure 1A An unregulated power converter 100 having a plurality of switching tank converter (STC) modules 102 is shown according to one aspect. Figure 1B An example of a first STC module 102-1 according to one aspect is shown. The unregulated power converter 100 can control the output current provided by the STC modules 102 so that each STC module 102 is configured to deliver substantially the same current to the load 104 (e.g., I OUT1 , I- OUT2 and I OUT3 For example, for an STC module 102 that provides more output current than other STC modules 102, a current sharing (CS) dead time 117 may be added to the dead time 116 at the end of an STC cycle and / or at the end of an STC phase, wherein the addition of the CS dead time 117 may result in a reduction in the output current provided by the stronger STC module 102, such that the output currents provided by the STC modules 102 converge toward each other.

[0033] The unregulated power converter 100 may receive an input voltage (V- IN ) and generates an output voltage (V OUT The unregulated power converter 100 may also be referred to as an STC converter. The STC converter may not include a voltage feedback loop. The unregulated power converter 100 may scale down the input voltage (V IN), where N is an integer and may depend on the circuit topology of the unregulated power converter 100 (e.g., the output voltage (V- OUT ) is V IN For example, if the value of N is four, the output voltage (V OUT ) is V IN / 4. However, the value of N may include any integer.

[0034] like Figure 1A As shown, the STC modules 102 are connected in parallel with respect to each other. For example, each STC module in the STC modules 102 receives an input voltage (V IN ), and the output of the STC module 102 is coupled to the load 104. Each STC module 102 can be considered as a IN ) is converted into different power levels of corresponding output voltages. The STC module 102 may include a first STC module 102-1, a second STC module 102-2, and a third STC module 102-3. Figure 1A Three STC modules 102 are shown, but the unregulated power converter 100 may include any number of STC modules 102 , such as two STC modules 102 or more than three STC modules 102 connected in parallel.

[0035] The first STC module 102-1 can receive an input voltage (V IN ) and using the first output current (I OUT1 ) will input voltage (V IN ) is converted to the first output voltage (V OUT1 The second STC module 102-2 can receive an input voltage (V IN ) and utilize the second output current (I- OUT2 ) will input voltage (V IN ) is converted into a second output voltage (V OUT2 The third STC module 102-3 can receive an input voltage (V IN ) and the input voltage (V IN ) is converted to a third output voltage (V OUT3 As discussed further below, the unregulated power converter 100 may implement an output current control mechanism that causes the output current (eg, I OUT1 ,I OUT2 ,I OUT3 ) can be substantially equal to each other. In some examples, the output current control mechanism responds to the current sharing (CS) enable signal (EN CS ) and is activated.

[0036] Details of the first STC module 102-1 relative to Figure 1B However, it should be noted that the second STC module 102-2 and the third STC module 102-3 (or any other STC module 102) may be the same as the first STC module 102-1 and may include any of the details discussed herein. Each STC module 102 may receive a minimum output current (I OUT_MIN ) value. The minimum output current (I OUT_MIN ) may indicate a value of a minimum output current provided by the STC module 102 (eg, I OUT1 ,I OUT2 ,I OUT3 Each STC module 102 can set the minimum output current (I OUT_MIN ) is compared with its corresponding output current. For example, the first STC module 102-1 compares the minimum output current (I OUT_MIN ) value and the first output current (I OUT1 ) is compared with the value of the second STC module 102-2. OUT_MIN ) value and the second output current (I OUT2 ) is compared with the value of the third STC module 102-3. OUT_MIN ) value and the third output current (I OUT3 ) values ​​to be compared.

[0037] For a specific STC module, if the output current is greater than the minimum output current (I OUT_MIN ), the STC module 102 may adjust the dead time 116 so that the current provided by the STC module 102 is more evenly balanced. In some examples, the dead time 116 is the default dead time 115, but when the value of the output current is greater than the minimum output current (I OUT_MIN ), the dead time 116 is updated to include the CS dead time 117 plus the default dead time 115.

[0038] When STC modules 102 are connected in parallel to increase current capacity, one or more STC modules 102 may provide a higher current than provided by other STC modules 102 due to differences in STC resonant output impedance, energy storage resonant frequency, and / or due to parasitic elements in the unregulated power converter 100. However, according to the embodiments discussed herein, if a particular STC module 102 is generating a current greater than the minimum output current (I OUT_MIN), then in order to reduce the output current amount of the stronger STC module 102, the STC module 102 may increase the dead time 116 (e.g., add the CS dead time 117 to the default dead time 115). In some examples, the STC module 102 may increase the dead time 116 at the end of the STC cycle (e.g., between STC cycles) and / or at the end of each STC phase, which may cause the output current to move toward the minimum output current (I OUT_MIN ) reduces and / or increases the minimum output current (IOUT_MIN) so that all STC modules 102 provide substantially the same current.

[0039] For example, the first STC module 102-1 may receive a minimum output current (I OUT_MIN ) value. In some examples, the minimum output current (I OUT_MIN ) is analog data (e.g., in an analog format). In some examples, the minimum output current (I OUT_MIN ) is digital data (e.g., in digital format). The minimum output current (I OUT_MIN ) indicates the value of the minimum output current provided by the STC module 102 (eg, the first output current (I OUT1 ), the second output current (I OUT2 ) and the third output current (I OUT3 )). In other words, the minimum output current (I OUT_MIN ) may be the value of the minimum output current supplied by the weakest STC module 102 to the load 104. For example, if the first output current (I- OUT1 ) is 25A, the second output current (I OUT2 ) is 24A, and the third output current (I OUT3 ) is 23A, then the minimum output current (I OUT_MIN ) is 23A (for example, where the third STC module 102-3 is considered to be the weakest STC module 102).

[0040] The CS interface 118 may be one or more components (eg, analog and / or digital) configured to share a minimum output current (I OUT_MIN In some examples, the CS interface 118 includes one or more analog components configured to provide the minimum output current (I OUT_MINIn some examples, the CS interface 118 includes a dedicated pin (e.g., an external pin or a pin external to the STC module 102), where each STC module 102 is connected to the dedicated pin. The voltage level (e.g., analog voltage level) on the dedicated pin may indicate the minimum output current (I OUT_MIN In some examples, the first STC module 102-1 can obtain the minimum output current (I OUT_MIN ).

[0041] In some examples, the CS interface 118 includes one or more digital components configured to provide the minimum output current (I OUT_MIN In some examples, the CS interface 118 includes sharing a minimum output current (I ) between the STC modules 102. OUT_MIN ). In some examples, the digital communication line defines a digital serial interface. In some examples, the digital communication line defines a parallel interface. The first STC module 102-1, the second STC module 102-2, and the third STC module 102-3 can be connected to each other via a digital communication line.

[0042] In more detail, the first STC module 102-1 may receive the minimum output current (I OUT_MIN ), and if the first output current (I OUT1 ) is less than the minimum output current (I OUT_MIN ), the first STC module 102-1 can use the first output current (I OUT1 ) value to update the minimum output current (I OUT_MIN Then, the second STC module 102-2 may receive the minimum output current (I OUT_MIN ), and if the second output current (I OUT2 ) is less than the minimum output current (I OUT_MIN ), the second STC module 102-2 can use the second output current (I OUT2 ) value to update the minimum output current (I OUT_MIN Then, the third STC module 102-3 may receive the minimum output current (I OUT_MIN ), and if the third output current (I OUT3 ) is less than the minimum output current (I OUT_MIN ), the third STC module 102-3 uses the third output current (I OUT3 ) value to update the minimum output current (I OUT_MIN), and the process continues like this.

[0043] like Figure 1B As shown, the first STC module 102-1 includes an STC circuit 106, which receives an input voltage (V IN ) and with a first output current (I OUT1 ) generates the first output voltage (V OUT1 ). The STC circuit 106 may include one or more resonant energy storage devices that absorb power at one or more frequencies (e.g., resonant frequencies). The STC circuit 106 may include one or more resonant capacitors 103, one or more resonant inductors 105, and a switch 107. The STC circuit 106 may define any number of resonant branches. The switch 107 may be activated (e.g., turned on) or deactivated (e.g., not turned on) based on a control signal 121 that controls the STC phase of the STC cycle.

[0044] The first STC module 102-1 includes an output current (OC) measurement circuit 108, a current comparator 110, a current sharing (CS) circuit 112, a dead time (DT) adjuster 114, and a control logic component 120. The OC measurement circuit 108 is coupled to the STC circuit 106. In some examples, the OC measurement circuit 108 is coupled to the output node of the STC circuit 106. The OC measurement circuit 108 can measure (or detect) the first output current (I OUT1 ) is an average value of the first output current (I OUT1 ) level (or average value). In some examples, the OC measurement circuit 108 includes a resistor (e.g., a shunt resistor). In some examples, the OC measurement circuit 108 includes a current sensing circuit. For example, the OC measurement circuit 108 can read the drain-to-source voltage of a switching transistor connected to the output voltage or ground and generate a signal proportional to the STC output current.

[0045] The CS circuit 112 can be coupled to the OC measurement circuit 108. The CS circuit 112 can communicate with the CS interface 118 to obtain the minimum output current (I OUT_MIN ) value. In some examples, CS circuit 112 can obtain a minimum output current (I OUT_MIN ) value. In some examples, CS circuit 112 may determine the first output current (I OUT1 ) is the minimum output current provided by the STC module 102, and if so, a first output current (I OUT1 ) as the minimum output current (I OUT_MIN). In some examples, CS circuit 112 includes one or more analog components, such as a comparator and one or more transistors. In some examples, CS circuit 112 includes one or more digital components, such as one or more digital processors and one or more memory devices, the one or more memory devices including executable instructions that, when executed by the digital processor, are configured to evaluate the first output current (I OUT1 ) is greater than the minimum output current (I OUT_MIN ), and based on the result, provides or updates the minimum output current (I OUT_MIN ).

[0046] The DT regulator 114 may receive a minimum output current (I OUT_MIN ) and receives a first output current (I OUT1 ). The DT regulator 114 can adjust the first output current (I OUT1 ) value and the minimum output current (I OUT_MIN ) is compared. If the result of the comparison indicates that the first output current (I OUT1 ) is greater than the minimum output current (I OUT_MIN ), the DT adjuster 114 may adjust the dead time 116 to be achieved at the end of the next STC phase or the end of the next STC cycle. OUT1 ) is equal to or less than the minimum output current (I OUT_MIN ), the DT adjuster 114 may not adjust the dead time 116.

[0047] In some examples, if the first output current (I OUT1 ) is greater than the minimum output current (I OUT_MIN ), the DT regulator 114 may determine (or calculate) the CS dead time 117. The DT regulator 114 may determine (or calculate) the CS dead time 117 based on the first output current (I OUT1 ) value and the minimum output current (I OUT_MIN ) to calculate the CS dead time 117. In some examples, the DT adjuster 114 may calculate the CS dead time 117 based on the following equation: CS DT = K*(I OUT1 -I OUT_MIN ), where parameter K is a scaling parameter. Therefore, the value of the CS dead time 117 can be related to the first output current (I OUT1 ) and the minimum output current (I OUT_MIN ) (e.g., the greater the difference, the greater the CS dead time 117). The CS dead time 117 may be an additional period of time added to the default dead time 115. For example, if the first output current (IOUT1 ) is equal to or less than the minimum output current (I OUT_MIN ), the dead time 116 only includes the default dead time 115 (eg, not adjusted). However, if the first output current (I OUT1 ) is greater than the minimum output current (I OUT_MIN ), the dead time 116 includes the default dead time 115 plus the calculated CS dead time 117.

[0048] In some examples, the DT adjuster 114 includes an analog circuit having one or more analog components, such as an operational transconductance amplifier (OTA) that sinks current from a (dead time) delay ramp. In some examples, the DT adjuster 114 includes a comparator, a transistor, a capacitor, a delay, and / or other analog components. In some examples, the DT adjuster 114 includes a digital circuit having one or more digital components, such as a register, an analog-to-digital converter (ADC), a serial-to-parallel (S / P) converter, a parallel-to-serial (P / S) converter, and / or one or more digital processors. In some examples, the DT adjuster 114 includes a combination of one or more analog components and one or more digital components.

[0049] The control logic component 120 may generate a control signal 121 to enable or disable the STC phase of the STC cycle of the first STC module 102-1. In some examples, the control logic component 120 (and / or the DT adjuster 114) receives a CS enable signal (EN CS ), the CS enable signal activates the current sharing control mechanism discussed in this article. For example, if the CS enable signal (EN CS ) is in a first state (eg, a low state), the current sharing control mechanism is deactivated, and the dead time 116 includes a fixed value of the default dead time 115. However, if the CS enable signal (EN CS ) is in a second state (e.g., a high state), the current sharing control mechanism is activated, and the dead time 116 may be adjusted to additionally include the CS dead time 117. In some examples, the control signal 121 may activate / deactivate the switch 107 of the STC circuit 106 to control the activation / deactivation of the STC phase. The control logic component 120 may be connected to the DT adjuster 114. In addition, in some examples, it should be noted that some functions of the DT adjuster 114 may be included in the control logic component 120 (and vice versa). The control logic component 120 receives the dead time 116 from the DT adjuster 114 and is configured to generate a control signal 121 to control the switch 107 so that the updated dead time 116 is inserted between STC cycles or between STC phases of the STC cycle.

[0050] Figure 2An example of an STC circuit 206 according to an aspect is shown. The STC circuit 206 may be Figure 1B 106 and may include any of the details discussed herein. The STC circuit 206 is not a voltage regulator (e.g., an unregulated power converter) and therefore does not include a voltage feedback loop. The STC circuit 206 may convert an input voltage (V IN ), where N is an integer depending on the circuit topology. In some examples, N is four (e.g., V OUT =V IN / 4). However, N can be any integer.

[0051] like Figure 2 As shown, the STC circuit 206 includes a resonant capacitor 244 (C1), a resonant inductor 246 (L1), a filter capacitor 248 (C2), a resonant capacitor 250 (C3), and a resonant inductor 252 (L2). In addition, the STC circuit 206 includes a switch 224 (Q1), a switch 226 (Q2), a switch 228 (Q3), a switch 230 (Q4), a switch 232 (Q5), a switch 234 (Q6), a switch 236 (Q7), a switch 238 (Q8), a switch 240 (Q9), and a switch 242 (Q10). Each of the switches can be a transistor (e.g., a field effect transistor (FET), a metal oxide semiconductor FET (MOSFET), a bipolar junction transistor (BJT), or other types of transistors). In some examples, the gate of the switch is configured to receive a control signal (e.g., Figure 1B The STC circuit 206 may operate in a plurality of STC phases, such as a first STC phase, a second STC phase, a third STC phase, and a fourth STC phase, which may be controlled by Figure 2 Switch control in.

[0052] In the first STC phase, switch 224 (Q1) and switch 232 (Q5) are activated. In the second STC phase, switch 226 (Q2), switch 234 (Q6) and switch 236 (Q7) are activated. In the third STC phase, switch 228 (Q3), switch 238 (Q8) and switch 240 (Q9) are activated. In the fourth STC phase, switch 230 (Q4) and switch 242 (Q10) are activated. In some examples, the first STC phase and the third STC phase are activated simultaneously. In some examples, the second STC phase and the fourth STC phase are activated simultaneously.

[0053] The resonant frequencies of the STC circuit 206 may be frequency (phase 1) = 1 / (2*pi*sqrt(C1*L1)), frequency (phase 2) = 1 / (2*pi*sqrt((C1*C2 / (C1+C2))*L1)), frequency (phase 3) = 1 / (2*pi*sqrt((C3*C2 / (C3+C2))*L2)), and frequency (phase 4) = 1 / (2*pi*sqrt(C3*L2)). Figure 2 In the example of FIG. 1 , the STC circuit 206 has a ratio value (N) of 4, where the input voltage (V IN ) divided by 4 (for example, the first output voltage (V OUT1 ) is the input voltage (V IN However, the techniques discussed herein may be applied to STC circuits 206 having any ratio value N.

[0054] The STC cycle includes activating a first STC phase and a third STC phase (simultaneously) during a first time period, and then activating a second STC phase and a fourth STC phase (simultaneously) during a second time period. Figure 1B A dead time 116) exists between the first time period and the second time period (eg, a dead time between STC phases within a single STC cycle).

[0055] During the dead time, all switches in the STC circuit 206 are deactivated. In some examples, during the dead time, one or more of the switches in the STC circuit 206 are deactivated (but one or more switches remain activated). For example, the dead time can be inserted to avoid cross conduction and allow the current to properly discharge to 0A (to achieve zero current switching and / or zero voltage switching, thereby providing high efficiency). Additionally, in some examples, there is a dead time (e.g., a dead time between consecutive STC cycles) before activating a subsequent STC cycle (e.g., a dead time between consecutive STC cycles). Figure 1B As discussed further below, see Figure 1B , in response to the first output voltage (V OUT1 ) is greater than the minimum output current (I OUT_MIN ), the first STC module 102-1 may increase the dead time 116 between STC phases and / or increase the dead time 116 at the end of an STC cycle (and before a subsequent STC cycle).

[0056] Figure 3A A digital implementation of a current sharing (CS) interface 318 between the first STC module 302-1, the second STC module 302-2, and the third STC module 302-3 is shown. Figure 3BFIG. 4 shows an example of a current sharing (CS) circuit 312 of a first STC module 302-1 according to an aspect. The CS interface 318 may be Figure 1A 1 and 2. The first STC module 302-1, the second STC module 302-2 and the third STC module 302-3 may be respectively Figure 1A The first STC module 102-1, the second STC module 102-2 and the third STC module 102-3 may include any of the details discussed herein.

[0057] The CS interface 318 may be a digital serial interface that enables the first STC module 302-1, the second STC module 302-2, and the third STC module 302-3 to communicate in order to share the minimum output current (I OUT_MIN ). The CS interface 318 includes one or more digital communication lines 319 connected between the first STC module 302-1, the second STC module 302-2, and the third STC module 302-3. In some examples, the digital communication lines 319 define a digital serial interface configured to serially transmit digital data between the STC modules.

[0058] Relative to Figure 3B , the CS circuit 312 includes a memory device 323 and one or more digital processors 325 configured to perform operations of the CS circuit 312. For example, in operation 301, the CS circuit 312 may determine a first output current (I OUT1 ) is greater than the minimum output current (I OUT_MIN If yes, then in operation 303, the CS circuit 312 can set the minimum output current (I OUT_MIN ) is stored in the memory device 323, and in operation 305, the CS circuit 312 may transmit the minimum output current (I OUT_MIN ) is transmitted to the second STC module 302-2. If not, then in operation 307, the CS circuit 312 may use the first output current (I OUT1 ) updates the minimum output current (I OUT_MIN ) value, and in operation 309, the CS circuit 312 can set the minimum output current (I OUT_MIN ) is stored in the memory device 323. Then, in operation 311, the CS circuit 312 may transmit the minimum output current (I OUT_MIN ) is transmitted to the second STC module 302-2.

[0059] The second STC module 302-2 may include a CS circuit 312 and may perform the same operation as Figure 3AAs shown, the second STC module 302-2 can transmit the minimum output current (I OUT_MIN ) is transmitted to the third STC module 302-3. The third STC module 302-3 may include a CS circuit 312 and may perform the same operation as Figure 3A As shown, the third STC module 302-3 can transmit the minimum output current (I OUT_MIN ) is transmitted to the first STC module 302-1.

[0060] Figure 4 FIG. 4 shows a simulated implementation of a CS interface 418 according to an aspect. Figure 4 As shown, the CS interface 418 may include a dedicated analog pin 419 connected to a voltage source 461 (VCC) via a resistor 460. The analog voltage on the dedicated analog pin 419 may indicate the minimum output current (I OUT_MIN ) value.

[0061] Each STC module (e.g. Figure 1A Each STC module 102 is connected to the dedicated analog pin 419. Each STC module is configured to determine whether the value of its corresponding output current is less than the current minimum output current (I OUT_MIN ) and, if so, provides its output current as the minimum output current (I OUT_MIN ) value. For example, the first STC module (eg, Figure 1A The first STC module 102-1 includes a first CS circuit 412-1, and the second STC module (eg, Figure 1A The second STC module 102-2) includes a second CS circuit 412-2, and the third STC module (eg, Figure 1A The third STC module 102-3) includes a third CS circuit 412-3.

[0062] Each of the first CS circuit 412-1, the second CS circuit 412-2, and the third CS circuit 412-3 is connected to a dedicated analog pin 419. The first CS circuit 412-1, the second CS circuit 412-2, or the third CS circuit 412-3 may update the minimum output current (I OUT_MIN ) value, such as the voltage on the dedicated analog pin 419. For example, if the first output current (I OUT1 ) is less than the voltage on the dedicated analog pin 419, the first CS circuit 412-1 may update the voltage on the dedicated analog pin 419 to correspond to (eg, be the same as) the first output current (I OUT1 ) voltage. If the second output current (I OUT2) is less than the voltage on the dedicated analog pin 419, the second CS circuit 412-2 may update the voltage on the dedicated analog pin 419 to correspond to (eg, be the same as) the second output current (I OUT2 ) voltage. If the third output current (I OUT3 ) is less than the voltage on the dedicated analog pin 419, the third CS circuit 412-3 may update the voltage on the dedicated analog pin 419 to correspond to (eg, be the same as) the third output current (I OUT3 ) voltage.

[0063] The first CS circuit 412-1 includes an operational transconductance amplifier (OTA) 456-1 and a transistor 458-1. The OTA 456-1 receives the voltage on the dedicated analog pin 419 and compares it with the first output current (I OUT1 ) is compared. The output of OTA456-1 is connected to the gate of transistor 458-1. In some examples, transistor 458-1 is a P-channel transistor. The source of transistor 458-1 is connected to dedicated analog pin 419. The drain of transistor 458-1 can be connected to ground. If the first output current (I OUT1 ) is less than the voltage on the dedicated analog pin 419, the OTA 456-1 can activate the transistor 458-1 so that the first output current (I OUT1 ) is the voltage on dedicated analog pin 419.

[0064] The second CS circuit 412-2 includes an OTA 456-2 and a transistor 458-2. The OTA 456-2 receives the voltage on the dedicated analog pin 419 and compares it with the second output current (I OUT2 ) is compared. The output of OTA 456-2 is connected to the gate of transistor 458-2. In some examples, transistor 458-2 is a P-channel transistor. The source of transistor 458-2 is connected to dedicated analog pin 419. The drain of transistor 458-2 can be connected to ground. If the second output current (I OUT2 ) is less than the voltage on the dedicated analog pin 419, the OTA 456-2 can activate the transistor 458-2 so that the second output current (I OUT2 ) is the voltage on dedicated analog pin 419.

[0065] The third CS circuit 412-3 includes an OTA 456-3 and a transistor 458-3. The OTA 456-3 receives the voltage on the dedicated analog pin 419 and compares it with the third output current (I OUT3) is compared. The output of OTA 456-3 is connected to the gate of transistor 458-3. In some examples, transistor 458-3 is a P-channel transistor. The source of transistor 458-3 is connected to dedicated analog pin 419. The drain of transistor 458-3 can be connected to ground. If the third output current (I OUT3 ) is less than the voltage on the dedicated analog pin 419, the OTA 456-3 can activate the transistor 458-3 so that the third output current (I OUT3 ) is the voltage on dedicated analog pin 419.

[0066] Figure 5 A flowchart 500 depicting exemplary operation of an STC module is shown according to one aspect. Figure 1A and Figure 1B The first SCT module 102-1 explains Figure 5 , but the operation can be applied to any of the STC modules discussed in this article.

[0067] In operation 502, the first STC module 102-1 may measure an average output current (I OUT1 In operation 504, the first STC module 102-1 may obtain the minimum output current (I OUT_MIN ) value. In operation 506, the first STC module 102-1 may determine the CS enable signal (EN CS ) is received. If not, then in operation 510, the dead time 116 is the default dead time 115. If yes, then in operation 508, the first STC module 102-1 determines the first output current (I OUT1 ) is greater than the minimum output current (I OUT_MIN ), and the operation returns to operation 508 to (eg, periodically or continuously) redetermine the first output current (I OUT1 ) is greater than the minimum output current (I OUT_MIN If yes, then in operation 512, the first STC module 102-1 calculates the CS dead time 117. In some examples, the first STC module 102-1 calculates the CS dead time 117 based on the first output current (I OUT1 ) value and the minimum output current (I OUT_MIN ) to calculate the CS dead time 117, multiplying the difference by a parameter K (e.g., K*(I OUT1 -I OUT_MIN )). In operation 514 , the first STC module 102 - 1 adjusts the dead time 116 by adding the CS dead time 117 to the default dead time 115 .

[0068] Figure 6 FIG. 6 shows a control signal 621 of the control logic component 620 without enabling the current sharing mechanism according to an aspect. For example, the control signal 621 may depict a control signal 621 in response to the CS control signal (EN CS ) is disabled and the STC phase is enabled. The control logic component 620 may be Figure 1B In some examples, with respect to a particular STC module, the first STC phase and the third STC phase may be activated simultaneously, and the second STC phase and the fourth STC phase may be activated simultaneously. The control signal 621 is provided to the STC circuit (e.g., Figure 1B STC circuit 106) to control the switch (e.g., Figure 1B The switch 107) can realize various STC phases of the STC module. Figure 2 In the STC circuit 206, the control signal 621 may include a signal for controlling the transistors (Q1 to Q10) to implement the first STC phase to the fourth STC phase.

[0069] An STC cycle may include activation of a first STC phase and a third STC phase, followed by activation of a second STC phase and a fourth STC phase, followed by another STC cycle. Figure 6 As shown, a default dead time 615-1 (e.g., Figure 1B In addition, in some examples, a default dead time 615-2 (e.g., a default dead time 615-2) may be provided at the end of a particular STC cycle but before activation of a subsequent STC cycle, such as after activation of the second STC phase and the fourth STC phase, but before activation of the first STC phase and the third STC phase in the next STC phase. Figure 1B The default dead time is 115).

[0070] Fig. 7A FIG. 7 shows a control signal 721 of the control logic component 720 when the current sharing mechanism is enabled according to an aspect. The control logic component 720 may be Figure 1A According to one aspect, the control signal 721 may depict an example of a control logic component 120 in response to a CS control signal (EN CS ) is enabled and the STC phase is enabled.

[0071] With respect to a particular STC module, the first STC phase and the third STC phase may be activated simultaneously, and the second STC phase and the fourth STC phase may be activated simultaneously. The control signal 721 is provided to the STC circuit (e.g., Figure 1B STC circuit 106) to control the switch (e.g., Figure 1B The switch 107) can realize various STC phases of the STC module. Figure 2 For the STC circuit 206, the control signal 721 may include a signal for controlling the transistors (Q1 to Q10) to implement the first STC phase to the fourth STC phase.

[0072] An STC cycle may include activation of a first STC phase and a third STC phase, followed by activation of a second STC phase and a fourth STC phase, followed by another STC cycle. Fig. 7A As shown, at the end of the STC cycle, the current sharing (CS) dead time 717 (for example, Figure 1B The CS dead time 117) is added to the default dead time 715 (e.g., Figure 1B For example, after disabling (or deactivating) the second STC cycle and the fourth STC cycle, the updated dead time includes the CS dead time 717 plus the default dead time 715.

[0073] Figure 7B A graph 700 depicting current waveforms of two STC modules within their resonant energy storages is shown according to one aspect. For example, Figure 7B The current waveform involves the addition of CS dead time at the end of the STC cycle, as Fig. 7A The graph 700 includes a first STC module (eg, Figure 1A and Figure 1B The first current waveform 701 generated by the first STC module 102-1 and the second STC module (eg, Figure 1A The second current waveform 703 generated by the second STC module 102-2. Figure 7B In the example of , the first STC module has added CS dead time at the end of the STC cycle. In addition, despite the addition of CS dead time, the first STC module can still enable zero current switching (ZCS) as indicated by points 705, 707, 709 and 711, thereby improving the efficiency of the power converter.

[0074] Fig. 8A FIG. 8 shows a control signal 821 of the control logic component 820 when the current sharing mechanism is enabled according to an aspect. The control logic component 820 may be Figure 1A According to one aspect, the control signal 821 may depict an example of a control logic component 120 in response to a CS control signal (EN CS ) is enabled and the STC phase is enabled, where the CS dead time is added after each STC phase (e.g., as Fig. 7AThe opposite is added only at the end of the STC cycle as shown).

[0075] With respect to a particular STC module, the first STC phase and the third STC phase may be activated simultaneously, and the second STC phase and the fourth STC phase may be activated simultaneously. The control signal 821 is provided to the STC circuit (e.g., Figure 1B STC circuit 106) to control the switch (e.g., Figure 1B The switch 107) can realize various STC phases of the STC module. Figure 2 For the STC circuit 206, the control signal 821 may include a signal for controlling the transistors (Q1 to Q10) to implement the first STC phase to the fourth STC phase.

[0076] An STC cycle may include activation of a first STC phase and a third STC phase, followed by activation of a second STC phase and a fourth STC phase, followed by another STC cycle. Fig. 8A As shown, at the end of each STC phase, the CS dead time is added to the default dead time 815. In some examples, the control logic component 820 can divide (e.g., split) the calculated CS dead time into CS dead time 817-1 and CS dead time 817-2. Fig. 8A As shown, the CS dead time 817-1 may be added to the default dead time 815 after deactivation of the first STC phase and the third STC phase, and the CS dead time 817-2 may be added to the default dead time 815 after deactivation of the second STC phase and the fourth STC phase.

[0077] Figure 8B A graph 800 depicting current waveforms of two STC modules within their resonant energy storages is shown according to one aspect. For example, Figure 8B The current waveform involves the addition of the CS dead time at the end of each STC phase, as Fig. 8A Graph 800 includes a first STC module (eg, Figure 1A and Figure 1B The first current waveform 801 generated by the first STC module 102-1 and the second STC module (eg, Figure 1A The second current waveform 803 generated by the second STC module 102-2. Figure 8B In the example of , the first STC module has added CS dead time at the end of each STC cycle. In addition, despite the addition of CS dead time, the first STC module can still enable zero current switching (ZCS) as indicated by points 805, 807 and 809, thereby improving the efficiency of the power converter.

[0078] Fig. 91 shows an example of a simulated implementation of a DT adjuster 914 according to an aspect. The DT adjuster 914 may be Figure 1B In general, the DT regulator 914 can adjust the first output current (I OUT1 ) value and the minimum output current (I OUT_MIN ) value, and if the first output current (I OUT1 ) is greater than the minimum output current (I OUT_MIN ), the DT adjuster 914 is based on the next STC cycle (EN PHASE_X+1 ) within the first output current (I OUT1 ) and the minimum output current (I OUT_MIN ) to adjust the dead time (DT). In some examples, the DT adjuster 914 is configured to increase the dead time at the end of each STC phase. In some examples, the DT adjuster 914 is a circuit that can use an OTA to adjust the dead time, and the OTA sinks current from the dead time delay ramp.

[0079] DT regulator 914 includes OTA 976, transistor 974, current source 966, voltage source 962, transistor 972, capacitor 970, and Schmitt trigger 968. OTA 976 compares the minimum output current (I OUT_MIN ) voltage (called V(I OUT_MIN )) and the first output current (I OUT1 ) voltage (called V(I OUT_MIN )). The output of OTA 976 is coupled to the gate of transistor 974. The drain of transistor 974 is connected to current source 966, and the source of transistor 974 may be coupled to ground 964. In some examples, transistor 974 is an N-channel transistor. Current source 966 is connected to voltage source 962 and is configured to provide a bias current (I BIAS ). If V(I OUT_MIN ) is greater than V(I OUT_MIN ), then OTA 976 activates transistor 974. The gate of transistor 972 receives the phase enable signal (EN PHASE_X ), the source of transistor 972 is coupled to ground 964, and the drain of transistor 972 is connected to current source 966. Capacitor 970 is connected to the input of Schmitt trigger 968 and ground 964. The input of Schmitt trigger 968 is connected to current source 966 and capacitor 970. The output of Schmitt trigger 968 is the next phase enable signal (EN PHASE_X+1 ), which delays the CS dead time.

[0080] The output of Schmitt trigger 968 may be responsive to the voltage on capacitor 970 reaching a certain Schmitt trigger threshold V THThe voltage on capacitor 970 reaches the Schmitt trigger threshold V TH The time from DT to C can be DT = C * V TH / I CHARGE and I CHARGE =(I BIAS -I CURRENT_SHARING ). Current I CURRENT_SHARING is the current absorbed by transistor 974, when V(I OUT1 ) is higher than V(I OUT_MIN ), the current is K*(V(I OUT1 )-V(I OUT_MIN )). Therefore, DT CS (Current sensing dead time) = C*V TH / (I BIAS -K*(V(I OUT1 )-V(I OUT_MIN )). The DT value can be responsive to V(I OUT1 ) is different from V(I OUT_MIN ) increases. In addition, in response to V(I OUT1 ) is less than V(I OUT_MIN ), DT may not be changed. In this case, DT is the default value, which is DT DEFAULT =C*V TH / (I BIAS ). This timing can be responsive to the signal EN PHASE_X The DT regulator 914 may generate an enable signal (EN) for the next STC phase. PHASE_X+1 ).

[0081] Fig.10 An example of a digital implementation of the DT adjuster 1014 is shown. The DT adjuster 1014 may be Figure 1B 1014 is an example of a DT adjuster 1014 and may include any of the details discussed herein. In some examples, the DT adjuster 1014 is a digital finite state machine.

[0082] The DT adjuster 1014 includes a parallel-to-serial (P / S) converter 1082, a serial-to-parallel (S / P) converter 1084, a first register 1088, an analog-to-digital converter (ADC) 1086, a second register 1090, a digital processor 1092, and a phase generator 1094. The S / P converter 1084 may be connected to the CS interface (e.g., Figure 3A The digital communication line 319) receives the minimum output current (I OUT_MIN) value. In some examples, the S / P converter 1084 is connected to a digital communication line that includes a signal indicating the minimum output current (I OUT_MIN ) of the value of the serial digital (eg, N bits) data. The S / P converter 1084 converts the minimum output current (I OUT_MIN ) is converted from a serial format to a parallel format. The first register 1088 stores the minimum output current (I OUT_MIN )’s digital value.

[0083] ADC 1086 may receive a first output current (I OUT1 For example, ADC 1086 may be connected to an OC measurement circuit (eg, Figure 1B ADC 1086 converts the first output current (I OUT1 ) is converted into a digital value. The second register 1090 is connected to the output of the ADC 1086, and the ADC 1086 stores the first output current (I OUT1 )

[0084] The digital processor 1092 reads the minimum output current (I OUT_MIN ) and reads the first output current (I OUT1 ), and in operation 901, from the minimum output current (I OUT_MIN ) minus the first output current (I OUT1 ) to obtain a result (e.g., an error value). In operation 1093, the digital processor 1092 determines whether the result (e.g., the error value) is above a threshold value (e.g., zero). If so, in operation 1095, the digital processor 1092 sets the minimum output current (I OUT_MIN ) is updated to the first output current (I OUT1 ), the first output current is provided to the P / S converter 1082 to change the information into a serial format to be placed on the CS interface (e.g., a digital communication line). In addition, if yes, then in operation 1097, the digital processor 1092 calculates the dead time. For example, the digital processor 1092 calculates the dead time (DT) as the default dead time plus the CS dead time. The CS dead time is I OUT1 and I OUT_MIN The difference is multiplied by the parameter K. The calculated dead time is provided to the phase generator 1094. If not, the digital processor 1092 determines the dead time as a default dead time, which is provided to the phase generator 1094.

[0085] In some examples, phase generator 1094 is included as part of DT adjuster 1014. In some examples, phase generator 1094 is included as a control logic component (e.g., Figure 1B The phase generator 1094 may include one or more phase counters 1096 and one or more dead time (DT) phase counters 1098. The phase counter 1096 may include an n-bit counter driven by an internal clock to count phase delays. The DT phase counter 1098 may include an n-bit counter driven by an internal clock to count dead time delays. If the internal clock operates at 200Mhz to drive the control logic component, the counter (e.g., the phase counter 1096 or the DT phase counter 1098) may count delays in ticks of 5ns. For a first phase P1 having a duration of 1us, the phase generator 1094 may set the end of the counter to be equal to 1000ns / 5ns=200 decimal. After counting the phase P1, the phase generator 1094 resets the counter and updates the end of the counter register with a new digital value associated with the duration of the delay DT. For example, if DT is set equal to 100ns, the phase generator 1094 sets the end of the counter equal to 100n / 5ns=20. If current sharing is effective and DT is determined to be increasing, the phase generator 1094 updates the end of the counter from the default value of 20 to the new value. If the new DT is 150ns, the phase generator 1094 changes the end of the counter from 20 to 30 (150ns / 5ns). After setting DT, the end of the counter is set to obtain a second phase P2, and DT is set again, and so on.

[0086] Fig.11 A graph 1100 depicting a first output current 1101 (e.g., from a first STC module) and a second output current 1103 (e.g., from a second STC module) relative to time is shown according to an aspect. For example, the second STC module can be considered a weaker module (e.g., providing less output current) while the first STC module can be considered a stronger module (e.g., providing more output current). At the beginning until line 1105, the first STC module and the second STC module operate independently. Line 1105 indicates a point in time when the first STC module and the second STC module are connected in parallel (but the current sharing mechanism is not enabled). Line 1107 shows a point in time when the current sharing mechanism is activated. As shown in FIG. Fig.11As shown, after the first STC module and the second STC module are connected in parallel (e.g., after line 1105), the first output current 1101 and the second output current 1103 begin to diverge, thereby providing unequal currents. However, when the current sharing mechanism is activated (at line 1105), the first output current 1101 and the second output current 1103 begin to converge toward each other, which ultimately results in the first output current 1101 and the second output current 1103 having substantially the same value.

[0087] FIG. 12A to FIG. 12C 1 shows various signals of an unregulated converter without a current sharing mechanism enabled according to one aspect. For example, Fig. 12A A first average output current 1201 (eg, generated by a first STC module) and a second average output current 1203 (eg, generated by a second STC module connected in parallel with the first STC module) are depicted over time. Fig. 12B A first output current waveform 1205 (eg, generated by a first STC module) and a second output current waveform 1207 (eg, generated by a second STC module) are shown. Fig. 12C 1209 is shown as a control signal for enabling the STC phase of the STC module. Fig. 12A As shown, the first average output current 1201 does not match (eg, is substantially unequal to) the second average output current 1203, which may adversely affect the performance of the power converter having the STC module. Fig. 12C As shown, the default dead time provided between phases is relatively small.

[0088] FIG. 13A to FIG. 13C The effect of the STC converter with the current sharing mechanism enabled according to one aspect is shown. For example, Fig.13A A first average output current 1301 (eg, generated by a first STC module) and a second average output current 1303 (eg, generated by a second STC module connected in parallel with the first STC module) are depicted over time. Fig. 13B A first output current waveform 1305 (eg, generated by a first STC module) and a second output current waveform 1307 (eg, generated by a second STC module) are shown. Fig. 13C The control signal 1309 for enabling the STC phase of the STC module is shown. Fig.13A As shown, the first average output current 1301 matches (eg, is substantially equal to) the second average output current 1303, which can improve the performance of the power converter having the STC module. Fig. 13C As shown, CS dead time 1316 is added at the end of the STC cycle.

[0089] According to one aspect, an unregulated power converter includes a plurality of switching energy storage converter (STC) modules, the plurality of STC modules being configured to be connected in parallel and connected to a load, the plurality of STC modules including a first STC module configured to generate a first output current, and a second STC module configured to generate a second output current, the first STC module including an output current (OC) measurement circuit configured to measure a value of the first output current, and a dead time (DT) adjuster configured to compare the value of the first output current with a value of a minimum output current provided by the plurality of STC modules, the DT adjuster being configured to adjust the dead time in response to the value of the first output current being greater than the value of the minimum output current.

[0090] According to some aspects, the DT regulator is configured to determine a current sharing (CS) dead time based on a difference between a minimum output current and a first output current, and the DT regulator is configured to increase the dead time by the CS dead time. The first STC module includes an STC circuit, the STC circuit including one or more resonant capacitors, one or more resonant inductors, and a plurality of switches; a control logic component, the control logic component is configured to generate one or more control signals to control the plurality of switches so that an updated dead time is inserted at the end of an STC phase or at the end of an STC cycle, the updated dead time being a time period during which the plurality of switches are deactivated; and / or a current sharing (CS) interface connected to a plurality of STC modules, the CS interface being configured to provide a value of a minimum output current using a plurality of STC modules, and the DT regulator being configured to obtain the value of the minimum output current via the CS interface. The CS interface is configured to obtain the value of the minimum output current from the CS interface, and in response to the value of the first output current being less than the value of the minimum output current, the value of the minimum output current is updated to the value of the first output current. The CS interface includes a dedicated analog pin, wherein the voltage on the dedicated analog pin indicates the value of the minimum output current. The CS interface includes one or more digital communication lines connected between multiple STC modules.

[0091] According to one aspect, an unregulated power converter includes a plurality of switching energy storage converter (STC) modules, the plurality of STC modules are configured to be connected in parallel and connected to a load, the plurality of STC modules include a first STC module configured to generate a first output current, and a second STC module configured to generate a second output current, and a current sharing (CS) interface connected to the plurality of STC modules, the CS interface being configured to provide a minimum output current value using the plurality of STC modules, the minimum output current value being the minimum of the first output current and the second output current. The first STC module is configured to increase a dead time in response to the value of the first output current being greater than the value of the minimum output current.

[0092] According to some aspects, the first STC module includes an STC circuit, which includes one or more resonant capacitors, one or more resonant inductors and multiple switches; an output current (OC) measurement circuit, which is configured to measure the value of the first output current, and the OC measurement circuit is coupled to the output node of the STC circuit; a dead time (DT) adjuster, which is configured to compare the value of the first output current with the value of the minimum output current from the CS interface, and the DT adjuster is configured to increase the dead time in response to the value of the first output current being greater than the value of the minimum output current; a control logic component, which is configured to generate control signals for multiple switches so that an adjusted dead time is added at the end of an STC phase or an STC cycle, and the adjusted dead time is a time period during which the multiple switches are deactivated; and / or a current sharing (CS) circuit connected to the CS interface, the CS circuit is configured to obtain the value of the minimum output current from the CS interface, and in response to the value of the first output current being less than the value of the minimum output current, update the value of the minimum output current to the value of the first output current. The first STC module is configured to convert an input voltage to a first output voltage during a plurality of STC cycles, the plurality of STC cycles comprising a first STC cycle followed by a second STC cycle, the first STC module being configured to increase a dead time between the first STC cycle and the second STC cycle. The first STC module is configured to convert an input voltage to a first output voltage during a plurality of STC cycles, wherein a single STC cycle comprises a plurality of STC phases, wherein each STC phase is configured to generate a different resonant frequency, the first STC module being configured to increase a dead time between temporally adjacent STC phases within a single STC cycle.

[0093] According to one aspect, a method for controlling an unregulated power converter includes measuring, by a first switching energy storage converter (STC) module connected in parallel with a second STC module, a value of a first output current generated by a first STC module; obtaining, by the first STC module, a value of a minimum output current via a current sharing (CS) interface; comparing, by the first STC module, the value of the first output current with the value of the minimum output current; determining, by the first STC module, a current sharing (CS) dead time in response to the value of the first output current being greater than the value of the minimum output current; and increasing, by the first STC module, a dead time associated with an STC cycle of the first STC module by a CS dead time determined by the dead time.

[0094] According to some aspects, a dead time is inserted at the end of an STC cycle or at the end of an STC phase, and the method may include comparing, by a second STC module, a second output current generated by the second STC module with a minimum output current from a CS interface, and updating, by the second STC module, the minimum output current on the CS interface to correspond to the second output current in response to the second output current being less than the minimum output current, wherein the determined CS dead time is proportional to a difference between the first output current and the minimum output current.

[0095] Although certain features of the described embodiments have been described as described herein, those skilled in the art will now appreciate that many modifications, alternatives, variations, and equivalents are contemplated. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations that fall within the scope of the embodiments. It should be understood that these modifications and variations are presented only by way of example and not limitation, and that various changes in form and detail may be made. In addition to mutually exclusive combinations, any portion of the apparatus and / or method described herein may be combined in any combination. The embodiments described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

Claims

1. A power converter, comprising: A plurality of switch storage converter STC modules, the plurality of STC modules are configured to be connected in parallel and connected to a load, the plurality of STC modules do not include a voltage feedback loop, the plurality of STC modules include a first STC module configured to generate a first output current, and a second STC module configured to generate a second output current, the first STC module includes: an output current OC measurement circuit, wherein the OC measurement circuit is configured to measure a value of the first output current; a dead time DT adjuster configured to compare the value of the first output current with a value of a minimum output current provided by the plurality of STC modules, the DT adjuster configured to adjust a dead time in response to the value of the first output current being greater than the value of the minimum output current; and A current sharing CS circuit is configured to update the value of the minimum output current to the value of the first output current in response to the value of the first output current being smaller than the value of the minimum output current.

2. The power converter according to claim 1, wherein the DT regulator is configured to determine a current sharing CS dead time based on a difference between the minimum output current and the first output current, and the DT regulator is configured to increase the dead time by the CS dead time.

3. The power converter according to claim 1, wherein the first STC module comprises: an STC circuit, the STC circuit comprising one or more resonant capacitors, one or more resonant inductors, and a plurality of switches; and A control logic component is configured to generate one or more control signals to control the plurality of switches so that an updated dead time is inserted at the end of an STC phase or at the end of an STC cycle, the updated dead time being a time period during which the plurality of switches are deactivated.

4. The power converter according to claim 1, further comprising: A current-sharing CS interface is connected to the plurality of STC modules, and the CS interface is configured to provide the value of the minimum output current using the plurality of STC modules. 5 . The power converter of claim 4 , wherein the CS interface comprises a dedicated analog pin, wherein a voltage on the dedicated analog pin indicates the value of the minimum output current. 6 . The power converter of claim 4 , wherein the CS interface comprises one or more digital communication lines connected between the plurality of STC modules. 7 . The power converter of claim 4 , wherein the DT regulator is configured to obtain the value of the minimum output current via the CS interface.

8. The power converter of claim 4, wherein the CS circuit is connected to the CS interface.

9. A power converter, comprising: A plurality of switch storage converter STC modules, the plurality of STC modules are configured to be connected in parallel and connected to a load, the plurality of STC modules do not include a voltage feedback loop, the plurality of STC modules include a first STC module configured to generate a first output current, and a second STC module configured to generate a second output current; and a current-sharing CS interface, the CS interface being connected to the plurality of STC modules, the CS interface being configured to provide a value of a minimum output current using the plurality of STC modules, the value of the minimum output current being a minimum value of the first output current and the second output current, wherein the first STC module is configured to increase the dead time in response to the value of the first output current being greater than the value of the minimum output current, and The first STC module includes a current sharing CS circuit, and the CS circuit is configured to update the value of the minimum output current to the value of the first output current in response to the value of the first output current being less than the value of the minimum output current.

10. The power converter according to claim 9, wherein the first STC module further comprises: an STC circuit, the STC circuit comprising one or more resonant capacitors, one or more resonant inductors, and a plurality of switches; an output current OC measurement circuit, the OC measurement circuit being configured to measure the value of the first output current, the OC measurement circuit being coupled to an output node of the STC circuit; a dead time DT regulator configured to compare the value of the first output current with the value of the minimum output current from the CS interface, the DT regulator configured to increase the dead time in response to the value of the first output current being greater than the value of the minimum output current; and A control logic component is configured to generate control signals for the plurality of switches so that a dead time is added at the end of an STC phase or an STC cycle, the dead time being a time period during which the plurality of switches are deactivated. 11 . The power converter of claim 9 , wherein the CS circuit is connected to the CS interface, the CS circuit being configured to obtain the value of the minimum output current from the CS interface.

12. The power converter of claim 9, wherein the first STC module is configured to convert an input voltage to a first output voltage during a plurality of STC cycles, the plurality of STC cycles comprising a first STC cycle followed by a second STC cycle, the first STC module being configured to increase the dead time between the first STC cycle and the second STC cycle.

13. The power converter of claim 9, wherein the first STC module is configured to convert an input voltage to a first output voltage during a plurality of STC cycles, wherein a single STC cycle comprises a plurality of STC phases, wherein each STC phase is configured to generate a different resonant frequency, and wherein the first STC module is configured to increase the dead time between temporally adjacent STC phases within the single STC cycle.

14. The power converter of claim 9, wherein the first STC module is configured to determine a current sharing CS dead time based on a difference between the minimum output current and the first output current, wherein the dead time comprises a default dead time plus the CS dead time.

15. The power converter of claim 9, wherein the CS interface comprises one or more digital communication lines connected to the plurality of STC modules.

16. The power converter of claim 9, wherein the CS interface comprises a dedicated analog pin, wherein a voltage on the dedicated analog pin indicates the value of the minimum output current.

17. A method for controlling an unregulated power converter, the method comprising: Measuring, by a first STC module connected in parallel with a second switching energy storage converter STC module, a value of a first output current generated by the first STC module, wherein the first STC module or the second STC module does not include a voltage feedback loop; The first STC module obtains a value of a minimum output current via a current sharing CS interface; comparing, by the first STC module, the value of the first output current with the value of the minimum output current; determining, by the first STC module, a current sharing CS dead time in response to the value of the first output current being greater than the value of the minimum output current; a CS dead time determined by the first STC module increasing a dead time associated with an STC cycle of the first STC module; as well as The value of the minimum output current is updated to the value of the first output current by the first STC module in response to the value of the first output current being less than the value of the minimum output current.

18. The method of claim 17, wherein the dead time is inserted at the end of an STC cycle or at the end of an STC phase.

19. The method of claim 17, further comprising: comparing, by the second STC module, a second output current generated by the second STC module with the minimum output current from the CS interface, and The minimum output current on the CS interface is updated by the second STC module to correspond to the second output current in response to the second output current being less than the minimum output current.

20. The method of claim 17, wherein the determined CS dead time is proportional to a difference between the first output current and the minimum output current.

21. A power converter, comprising: A plurality of switch energy storage converter STC modules, wherein the plurality of STC modules are configured to be connected in parallel and connected to a load, wherein the plurality of STC modules do not include a voltage feedback loop, and wherein the plurality of STC modules include a first STC module and a second STC module, wherein the first STC module includes: an output current OC measurement circuit configured to measure a value of a first output current generated by the first STC module; a digital interface configured to receive a value of a minimum output current provided by the plurality of STC modules; a dead time DT adjuster configured to compare the value of the first output current with the value of the minimum output current provided by the plurality of STC modules, the DT adjuster configured to adjust a dead time in response to the value of the first output current being greater than the value of the minimum output current; and A current sharing CS circuit is configured to update the value of the minimum output current to the value of the first output current in response to the value of the first output current being smaller than the value of the minimum output current.

22. The power converter of claim 21, wherein the DT regulator is configured to determine a current sharing CS dead time based on a difference between the minimum output current and the first output current, and the DT regulator is configured to increase the dead time by the CS dead time.

23. The power converter of claim 21 , wherein the first STC module comprises: An STC circuit includes one or more resonant capacitors, one or more resonant inductors, and a plurality of switches.

24. The power converter of claim 23, wherein the first STC module comprises: A control logic component is configured to generate one or more control signals to control the plurality of switches so that an updated dead time is inserted at the end of an STC phase or at the end of an STC cycle, the updated dead time being a time period during which the plurality of switches are deactivated.

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