Array substrate and manufacturing and control method thereof, and display device

Abstract

The present application provides an array substrate, a manufacturing and control method thereof, and a display device. The array substrate includes: a first sub-pixel, a second sub-pixel, and a virtual sub-pixel located in a display area. In the target direction, the attenuation degree of the first sub-pixel is greater than the brightness attenuation degree of the second sub-pixel, and the light-emitting layer of the virtual sub-pixel is used to emit light of the same color as that of the first sub-pixel. Since the virtual sub-pixel also includes a connecting electrode electrically connecting the pixel circuit and its light-emitting layer, the brightness attenuation of the first sub-pixel can be effectively compensated by driving the virtual sub-pixel to emit light, thereby improving the problem of poor display effect of the display device. The display device made of the array substrate has a good display effect.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a manufacturing and control method thereof, and a display device. Background Art

[0002] With the development of display technology, the display screens of display devices are no longer satisfied with the original full-screen design, and a series of special-shaped (notch) screens with notches have emerged. Summary of the Invention

[0003] The present disclosure provides an array substrate, a manufacturing and control method thereof, and a display device. The technical solutions are as follows:

[0004] In one aspect, an array substrate is provided, comprising: a base substrate, and a first sub-pixel, a second sub-pixel, and a dummy sub-pixel located within a display area of ​​the base substrate, wherein the display area has a notch, and in a target direction along a center of the display area approaching the notch, a brightness attenuation degree of the first sub-pixel is greater than a brightness attenuation degree of the second sub-pixel;

[0005] Each sub-pixel includes: a pixel circuit, a connecting electrode, a light-emitting layer and an electrode layer. The light-emitting layer is electrically connected to the pixel circuit through the connecting electrode, and the light-emitting layer is also electrically connected to the electrode layer. The pixel circuit is used to drive the light-emitting layer to emit light through the connecting electrode, and the light-emitting layer in the virtual sub-pixel and the light-emitting layer in the first sub-pixel are used to emit light of the same color.

[0006] Optionally, the connection electrode of the virtual sub-pixel and the connection electrode of the first sub-pixel are located in the same layer.

[0007] Optionally, in the virtual sub-pixel, an area of ​​an orthographic projection of the connecting electrode on the base substrate is smaller than or equal to an area of ​​an orthographic projection of the light-emitting layer on the base substrate.

[0008] Optionally, in the virtual sub-pixel, a ratio of an area of ​​an orthographic projection of the connecting electrode on the base substrate to an area of ​​an orthographic projection of the light-emitting layer on the base substrate is in a range of 7% to 15%.

[0009] Optionally, the array substrate further comprises: an auxiliary electrode, and the auxiliary electrode and the connecting electrode in the virtual sub-pixel are arranged in sequence in a direction away from the base substrate;

[0010] The pixel circuit of the dummy sub-pixel, the auxiliary electrode, the connection electrode of the dummy sub-pixel, and the light-emitting layer of the dummy sub-pixel are electrically connected in sequence.

[0011] Optionally, the auxiliary electrode and the source and drain in the pixel circuit of the virtual sub-pixel are located in the same layer.

[0012] Optionally, the array substrate further includes: a data line, a power signal line, a first shift register GOA unit and a first shift register EOA unit;

[0013] The data line, the power signal line, the first GOA unit and the first EOA unit are all electrically connected to the pixel circuit of the virtual sub-pixel;

[0014] The data line is used to provide a data signal to the pixel circuit of the virtual sub-pixel, the power signal line is used to provide a power signal to the pixel circuit of the virtual sub-pixel, the first GOA unit is used to provide a gate drive signal to the pixel circuit of the virtual sub-pixel, and the first EOA unit is used to provide a light-emitting control signal to the pixel circuit of the virtual sub-pixel.

[0015] Optionally, the array substrate further includes: a virtual GOA unit and a virtual EOA unit, and the virtual GOA unit and the virtual EOA unit are both electrically connected to the pixel circuit of the first sub-pixel, and the first sub-pixel and the virtual sub-pixel are sequentially arranged and adjacent along the target direction;

[0016] The first EOA unit, the first GOA unit and the first sub-pixel are arranged in sequence along the gate line scanning direction, the virtual GOA unit and the first GOA unit are arranged in sequence along the target direction, and the virtual EOA unit and the first EOA unit are arranged in sequence along the target direction;

[0017] Alternatively, the virtual EOA unit, the virtual GOA unit and the first sub-pixel are arranged in sequence along the gate line scanning direction, the virtual GOA unit and the first GOA unit are arranged in sequence in the opposite direction of the target direction, and the virtual EOA unit and the first EOA unit are arranged in sequence in the opposite direction of the target direction.

[0018] Optionally, the array substrate further includes: at least one switch circuit corresponding one-to-one to at least one signal line in the signal line set;

[0019] Each of the signal lines includes two conductive segments, and the two conductive segments are electrically connected through a switch circuit corresponding to the signal line, and the signal line set includes: the data line, the power signal line, a signal line electrically connected between the first GOA unit and the pixel circuit of the virtual sub-pixel, and a signal line electrically connected between the first EOA unit and the pixel circuit of the virtual sub-pixel;

[0020] The switch circuit is also electrically connected to the control signal terminal. The switch circuit is used to control the on / off state of the two conductive segments electrically connected thereto in response to a control signal provided by the control signal terminal.

[0021] Optionally, the at least one switching circuit includes: a switching circuit corresponding to the data line, and a switching circuit corresponding to the power signal line.

[0022] Optionally, the array substrate further includes: a third sub-pixel located in the display area;

[0023] The colors of light emitted by the first sub-pixel, the second sub-pixel and the third sub-pixel are different, and in the gate line scanning direction, two sub-pixels for emitting light of a target color are arranged side by side between the second sub-pixel and the third sub-pixel, and the target color is the same as the color of the light emitted by the first sub-pixel.

[0024] In another aspect, a method for manufacturing an array substrate is provided, the method comprising:

[0025] Sequentially forming a pixel circuit structure, a driving electrode structure, a light-emitting layer structure, and an electrode layer structure in the display area of ​​the base substrate to obtain a first sub-pixel, a second sub-pixel, and a dummy sub-pixel;

[0026] The pixel circuit structure includes: a pixel circuit for each sub-pixel, the driving electrode structure includes a connecting electrode for each sub-pixel, the light-emitting layer structure includes a light-emitting layer for each sub-pixel, and the electrode layer structure includes an electrode layer for each sub-pixel. In each sub-pixel, the light-emitting layer is electrically connected to the pixel circuit via the connecting electrode, and the light-emitting layer is also electrically connected to the electrode layer. The pixel circuit is configured to drive the light-emitting layer to emit light via the connecting electrode.

[0027] The display area has a notch. In a target direction close to the notch along the center of the display area, the brightness attenuation of the first sub-pixel is greater than the brightness attenuation of the second sub-pixel. The light-emitting layer of the virtual sub-pixel and the light-emitting layer of the first sub-pixel are used to emit light of the same color.

[0028] In another aspect, a method for driving an array substrate is provided, for driving the array substrate according to the above aspect, the method comprising:

[0029] A driving signal is provided to the pixel circuit of the dummy sub-pixel. In response to the driving signal, the pixel circuit of the dummy sub-pixel drives the light-emitting layer of the dummy sub-pixel to emit light through the connection electrode of the dummy sub-pixel.

[0030] On the other hand, a control device for an array substrate is provided. The control device is electrically connected to the pixel circuit of the virtual sub-pixel, and the control device is used to execute the driving method of the array substrate as described in the above aspects.

[0031] On the other hand, a display device is provided, comprising: the array substrate as described in the above aspect, and the control device of the array substrate as described in the above aspect.

[0032] The beneficial effects of the technical solution provided by the present disclosure may include at least:

[0033] In summary, the embodiments of the present disclosure provide an array substrate, a method for manufacturing and controlling the same, and a display device. The array substrate includes a first sub-pixel, a second sub-pixel, and a virtual sub-pixel. In the target direction, the brightness attenuation of the first sub-pixel is greater than the brightness attenuation of the second sub-pixel, and the color of the light emitted by the light-emitting layer of the virtual sub-pixel is the same as the color of the light emitted by the first sub-pixel. Since the virtual sub-pixel also includes a connecting electrode electrically connecting its pixel circuit and the light-emitting layer, and the pixel circuit can drive the virtual sub-pixel to emit light through the connecting electrode, the brightness attenuation of the first sub-pixel can be compensated by controlling the light emission of the virtual sub-pixel, that is, the difference in brightness attenuation between the first sub-pixel and the second sub-pixel can be reduced by controlling the light emission of the virtual sub-pixel. The display effect of the display device made of the array substrate is better. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0035] Figure 1 This is a schematic structural diagram of a special-shaped screen provided by an embodiment of the present disclosure;

[0036] Figure 2 This is a structural diagram of a special-shaped screen recorded in related technology;

[0037] Figure 3 This is a schematic diagram of the substrate structure of a special-shaped screen recorded in related technology;

[0038] Figure 4 is a test result schematic diagram provided by an embodiment of the present disclosure;

[0039] Figure 5 is another test result schematic diagram provided by an embodiment of the present disclosure;

[0040] Figure 6This is another test result diagram provided by an embodiment of the present disclosure;

[0041] Figure 7 This is another test result diagram provided by an embodiment of the present disclosure;

[0042] Figure 8 This is another test result diagram provided by an embodiment of the present disclosure;

[0043] Figure 9 This is another test result diagram provided by an embodiment of the present disclosure;

[0044] Figure 10 is a structural schematic diagram of an array substrate provided by an embodiment of the present disclosure;

[0045] Figure 11 is a structural schematic diagram of another array substrate provided by an embodiment of the present disclosure;

[0046] Figure 12 is a structural diagram of another array substrate provided by an embodiment of the present disclosure;

[0047] Figure 13 is a structural schematic diagram of another array substrate provided by an embodiment of the present disclosure;

[0048] Figure 14 is a structural schematic diagram of another array substrate provided by an embodiment of the present disclosure;

[0049] Figure 15 is a structural schematic diagram of another array substrate provided by an embodiment of the present disclosure;

[0050] Figure 16 is a structural schematic diagram of another array substrate provided by an embodiment of the present disclosure;

[0051] Figure 17 is a flow chart of a method for manufacturing an array substrate provided by an embodiment of the present disclosure;

[0052] Figure 18 is a flow chart of another method for manufacturing an array substrate provided by an embodiment of the present disclosure;

[0053] Figure 19 This is a schematic diagram of an array substrate having a pixel circuit structure provided by an embodiment of the present disclosure;

[0054] Figure 20 Schematic diagram of an array substrate provided by an embodiment of the present disclosure having a driving electrode structure;

[0055] Figure 21 This is a schematic diagram of an array substrate having a light-emitting layer structure provided by an embodiment of the present disclosure;

[0056] Figure 22 Schematic diagram of an array substrate having an electrode layer structure provided by an embodiment of the present disclosure;

[0057] Figure 23 This is a flow chart of a driving method for an array substrate provided by an embodiment of the present disclosure;

[0058] Figure 24 This is a flow chart of another driving method of an array substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0059] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0060] The transistors used in all embodiments of the present disclosure can be thin-film transistors, field-effect transistors, or other devices with similar characteristics. Based on their function in the circuit, the transistors used in the embodiments of the present disclosure are primarily switching transistors. Since the source and drain of the switching transistors used here are symmetrical, their source and drain are interchangeable. In the embodiments of the present disclosure, the source is referred to as the first electrode and the drain is referred to as the second electrode, or alternatively, the drain is referred to as the first electrode and the source is referred to as the second electrode. According to the configuration in the accompanying drawings, the middle end of the transistor is defined as the gate, the signal input end as the source, and the signal output end as the drain. Furthermore, the switching transistors used in the embodiments of the present disclosure can include either a P-type switching transistor or an N-type switching transistor. A P-type switching transistor is turned on when the gate is at a low level and turned off when the gate is at a high level, while an N-type switching transistor is turned on when the gate is at a high level and turned off when the gate is at a low level. Furthermore, multiple signals in each embodiment of the present disclosure correspond to a first potential and a second potential. The first potential and the second potential merely represent that the potential of the signal has two different states and do not imply that the first potential or the second potential has a specific value throughout the text.

[0061] Special-shaped screens with a notch on at least one side of the display area have become the mainstream design in the field of display technology. Figure 1 This is a structural diagram of a special-shaped screen provided by an embodiment of the present disclosure. Figure 1 The display area A1 of the special-shaped screen has a gap K1 on one side. The display area A1 includes multiple effective sub-pixels. The display area A1 near the gap K1 and the non-display area away from the gap K1 include multiple dummy sub-pixels.

[0062] Among them, reference Figure 2, the effective sub-pixel may include a red sub-pixel, a green sub-pixel and a blue sub-pixel, and the virtual sub-pixel may include a red virtual sub-pixel, a green virtual sub-pixel and a blue virtual sub-pixel. Moreover, the arrangement of the sub-pixels in each row may be an RGGB arrangement, that is, the sub-pixels in each row may be arranged as a red sub-pixel, two green sub-pixels arranged in parallel and a blue sub-pixel. It should be noted that by setting up multiple virtual sub-pixels, the effective sub-pixels can be protected and the uniformity of the sub-pixel arrangement can be ensured. Optionally, refer to Figure 2 The shapes of the green sub-pixels and the green dummy sub-pixels are both pentagons, the shapes of the blue sub-pixels and the blue dummy sub-pixels are both hexagons, and the shapes of the red sub-pixels and the red dummy sub-pixels are both ellipses. Furthermore, the orthographic projection areas of the two green sub-pixels arranged side by side on the substrate, the orthographic projection areas of the red sub-pixels on the substrate, and the orthographic projection areas of the blue sub-pixels on the substrate are the same. The orthographic projection areas of the two green dummy sub-pixels arranged side by side on the substrate, the orthographic projection areas of the red dummy sub-pixels on the substrate, and the orthographic projection areas of the blue dummy sub-pixels on the substrate are the same.

[0063] In the related art, each effective sub-pixel includes a pixel circuit and a light-emitting layer that are electrically connected, and each effective sub-pixel can be used for display. Each virtual sub-pixel only includes a pixel circuit and a light-emitting layer, and the light-emitting layer is not electrically connected to the pixel circuit, that is, the virtual sub-pixels included in the special-shaped screen display device of the related art are not used for display. For example, Figure 3 Taking adjacent effective green sub-pixels and virtual green sub-pixels as an example, a special-shaped screen array substrate described in the related art is introduced. Figure 3 As shown, the effective green sub-pixel P1 includes: a light-emitting layer P11, a pixel circuit P12, and a connection electrode P13 electrically connecting the pixel circuit P12 and the light-emitting layer P11. The virtual green sub-pixel P2 only includes: a light-emitting layer P21 and a pixel circuit P22, and the light-emitting layer P21 and the pixel circuit P22 are not electrically connected. In addition, referring to Figure 3 , the array substrate also includes multiple insulating layers (not numbered in the figure).

[0064] Furthermore, in order to drive each row of sub-pixels to emit light normally and to ensure uniform arrangement, the special-shaped screen may further include a plurality of effective shift register GOA units, a plurality of effective shift register EOA units, a plurality of dummy GOA units, and a plurality of dummy EOA units located on one side of the display area A1. The effective GOA units and the effective EOA units may be electrically connected to the pixel circuits of the effective sub-pixels and used to provide drive signals to the pixel circuits. The dummy GOA units and the dummy EOA units are not connected to any sub-pixels, i.e., the dummy GOA units and the dummy EOA units are not used for driving and do not contribute to the display.

[0065] In the embodiment of the present disclosure, the following conclusions are drawn through the long range uniformity (LRU) test, that is, the brightness uniformity test: Figure 1 and Figure 2 , in the target direction X1 along the center of the display area A1 close to the notch K1, the brightness of each sub-pixel decays to varying degrees, and accordingly, the display color near the notch K1 becomes abnormal. Figure 2 In the RGGB arrangement shown, along the target direction X1, the green subpixel's brightness attenuation L_G is 31%, the red subpixel's brightness attenuation L_R is 27%, and the blue subpixel's brightness attenuation L_B is 25%. Comparing the brightness attenuation of these three subpixels reveals that, along the target direction X1, the green subpixel's brightness attenuation is greater than that of the blue and red subpixels. Consequently, the display near the gap K1 exhibits color imbalance. For example, testing indicates that the red subpixel's color component Gx near the gap K1 is 0.0018, while the green subpixel's color component Rx is 0.0002, meaning the green subpixel's color component is smaller than the red subpixel's.

[0066] For example, Figures 4 to 9 This embodiment of the present disclosure provides a method for Figure 2 The diagram shows the test results of brightness test and color test of the display screen. The color test is based on the International Illumination Commission (Commission Internationale de L'Eclairage, CIE) as the test standard. Figures 4 to 9 The horizontal coordinate X refers to each sub-pixel point collected along the target direction X1. Figure 4 The Y coordinate of the test result shown is the color component of the red sub-pixel in the X-axis direction of CIE. Figure 5 The vertical coordinate Y of the test results shown refers to the color component of the green sub-pixel in the X-axis direction of CIE. Figure 6 The vertical coordinate Y of the test results shown refers to the color component of the red sub-pixel in the Y-axis direction of CIE. Figure 7 The vertical axis of the test results shown refers to the color component of the green sub-pixel in the Y-axis direction of CIE. Figure 8 The vertical coordinate Y of the test result shown is the brightness value of the red sub-pixel. Figure 9 The vertical axis Y of the test results shown refers to the brightness value of the green sub-pixel. Figures 4 to 9 It can be seen that along the target direction X1, the color component of the red sub-pixel gradually increases in both the X-axis and Y-axis directions of the CIE coordinate system, but the change is relatively gentle. The color component of the green sub-pixel gradually decreases in the X-axis direction of the CIE coordinate system, and gradually increases in the Y-axis direction of the color coordinate system, with the change being more pronounced. The brightness attenuation of the red sub-pixel is significantly less than that of the green sub-pixel. Because the overall display effect will be reddish when the brightness attenuation of the green sub-pixel is greater, the side of the special-shaped screen display device provided by the related art is prone to redness near the gap K1.

[0067] The embodiments of the present disclosure provide an array substrate that can solve the problem of poor display effects of special-shaped screen display devices in related technologies. It should be noted that the non-virtual sub-pixels described in the following embodiments are all valid sub-pixels that can emit light normally, the non-virtual GOA units are all valid GOA units, the non-virtual EOA units are all valid EOA units, and the transistors in the pixel circuit included in the array substrate are all bottom-gate structures. Of course, the transistors in the pixel circuit can also be top-gate structures, which are not introduced in the embodiments of the present disclosure.

[0068] Figure 10 Schematic diagram of the structure of an array substrate provided by an embodiment of the present disclosure. Figure 10 As shown, the array substrate may include: a base substrate 00, and a first sub-pixel 10, a second sub-pixel 20 and a dummy sub-pixel 30 located in a display area A1 of the base substrate 00. Figure 10 The display area A1 of the base substrate 00 has a notch K1, and in a target direction X1 along the center of the display area A1 close to the notch K1, the brightness attenuation of the first sub-pixel 10 is greater than that of the second sub-pixel 20.

[0069] Each sub-pixel may include a pixel circuit, a connecting electrode, a light-emitting layer, and an electrode layer. For each sub-pixel, its light-emitting layer may be electrically connected to its pixel circuit via its connecting electrode, and its light-emitting layer may also be electrically connected to its electrode layer. The pixel circuit may drive the light-emitting layer to emit light via the connecting electrode. Furthermore, the light-emitting layer of the virtual sub-pixel 30 may emit the same color as the light-emitting layer of the first sub-pixel 10. For example, assuming that the first sub-pixel 10 is a green sub-pixel, the light-emitting layer of the virtual sub-pixel 30 may emit green light.

[0070] Optional, reference Figure 11 , which takes the virtual sub-pixel 30 as an example, shows a structural schematic diagram of another array substrate provided by an embodiment of the present disclosure. Figure 11 As shown, the virtual sub-pixel 30 may include: a connecting electrode 301, a pixel circuit 302, a light-emitting layer 303, and an electrode layer 304. The light-emitting layer 303 and the pixel circuit 302 may be electrically connected via the connecting electrode 301, and the light-emitting layer 303 may also be electrically connected to the electrode layer 304. The pixel circuit 302 may drive the light-emitting layer 303 to emit light via the connecting electrode 301.

[0071] contrast Figure 3 and Figure 11 Because the virtual sub-pixel 30 for emitting the same color as the first sub-pixel within the display area A1 of the array substrate provided in the embodiment of the present disclosure further includes a connection electrode 301, and the connection electrode 301 can electrically connect the pixel circuit 302 and the light-emitting layer 303 of the virtual sub-pixel 30, the embodiment of the present disclosure can compensate for the brightness attenuation of the first sub-pixel 10, which has a larger brightness attenuation, by driving the virtual sub-pixel 30 to emit light. In other words, by driving the virtual sub-pixel 30 to emit light, the difference in brightness attenuation between the effective sub-pixels (such as the first sub-pixel 10 and the second sub-pixel 20) is reduced. This results in a better display effect for a display device manufactured using this array substrate.

[0072] For example, assuming that the first sub-pixel 10 is a green sub-pixel, the second sub-pixel 20 is a red sub-pixel, the virtual sub-pixel 30 is a green virtual sub-pixel, and the display area A1 also includes a blue sub-pixel, then by driving the virtual sub-pixel 30 to emit light, the degree of difference in brightness attenuation of the three color sub-pixels can be effectively reduced. Accordingly, the reddening phenomenon caused by the large brightness attenuation of the first sub-pixel can be effectively avoided.

[0073] In summary, an embodiment of the present disclosure provides an array substrate. The array substrate includes a first sub-pixel, a second sub-pixel, and a virtual sub-pixel. In the target direction, the brightness attenuation of the first sub-pixel is greater than the brightness attenuation of the second sub-pixel, and the color of the light emitted by the light-emitting layer of the virtual sub-pixel is the same as the color of the light emitted by the first sub-pixel. Since the virtual sub-pixel also includes a connecting electrode electrically connecting its pixel circuit and the light-emitting layer, and the pixel circuit can drive the virtual sub-pixel to emit light through the connecting electrode, the brightness attenuation of the first sub-pixel can be compensated by controlling the virtual sub-pixel to emit light, that is, the difference in brightness attenuation between the first sub-pixel and the second sub-pixel can be reduced by controlling the virtual sub-pixel to emit light. The display effect of the display device made of the array substrate is better.

[0074] Optionally, in an embodiment of the present disclosure, the connecting electrode and the electrode layer may both be an anode or cathode for driving the light-emitting layer to emit light, and the connecting electrode and the electrode layer may be different. The following embodiments of the present disclosure are described using the example of the connecting electrode being the anode and the electrode layer being the cathode.

[0075] Figure 12 This is a structural diagram of another array substrate provided by an embodiment of the present disclosure. Figure 12 As shown, the connecting electrode 301 of the dummy sub-pixel 30 can be located on the same layer as the connecting electrode 101 of the first sub-pixel 10. Accordingly, the connecting electrode 301 can be formed through a single patterning process as the connecting electrode 101, and the connecting electrode 301 can be the same type of electrode as the connecting electrode 101. That is, if the connecting electrode 101 is an anode, the connecting electrode 301 is also the anode; if the connecting electrode 101 is a cathode, the connecting electrode 301 is also the cathode. This avoids increasing manufacturing costs and complexity of the manufacturing process.

[0076] Alternatively, for each sub-pixel, the luminance of the light-emitting layer is proportional to the effective area of ​​the connecting electrode. The effective area refers to the overlapping area of ​​the orthographic projection of the connecting electrode on the substrate and the orthographic projection of the light-emitting layer on the substrate. That is, for each sub-pixel, the larger the effective area of ​​the connecting electrode, the higher the luminance of the light-emitting layer; and the smaller the effective area of ​​the connecting electrode, the lower the luminance.

[0077] Therefore, in the virtual sub-pixel 30, the area of ​​the orthographic projection of its connecting electrode 301 on the base substrate 00 can be less than or equal to the area of ​​the orthographic projection of its light-emitting layer 303 on the base substrate 00. For example, referring to Figure 12 In the array substrate provided by the embodiment of the present disclosure, the virtual sub-pixel 30 has a connection electrode 301 whose orthographic projection area on the base substrate 00 is smaller than the orthographic projection area of ​​the light-emitting layer 303 on the base substrate 00. Moreover, since the first sub-pixel 10 can emit light itself, it is only necessary to control the brightness of the virtual sub-pixel 30 to compensate for the brightness attenuation of the first sub-pixel 10. Therefore, by Figure 12 The setting method can reduce manufacturing costs while achieving reliable compensation.

[0078] It should be noted that for different sizes and different luminescent materials, the degree of brightness attenuation of the first sub-pixel 10 may vary. Accordingly, the brightness required to be compensated is different, and the brightness required to be emitted by the virtual sub-pixel 30 is also different. For example, after algorithm testing, when the first sub-pixel 10 is a green sub-pixel and the virtual sub-pixel 30 is a green virtual sub-pixel, combined with the luminescent material, film characteristics, and brightness attenuation of the green sub-pixel, it is concluded that the ratio of the area of ​​the orthographic projection of the virtual sub-pixel's connecting electrode 301 on the substrate 00 to the area of ​​the orthographic projection of the luminescent layer 303 of the virtual sub-pixel 30 on the substrate 00 can be within the range of 7% to 15%. In other words, when the area of ​​the orthographic projection of the connecting electrode 301 on the substrate 00 meets this ratio range, effective and reliable compensation for the brightness attenuation of the first sub-pixel 10 can be achieved.

[0079] It should also be noted that the above control of the luminous brightness of the luminous layer 303 of the virtual sub-pixel 30 is achieved by adjusting the effective area of ​​the connection electrode 301 of the virtual sub-pixel 30. In addition, because the luminous brightness of each sub-pixel is also related to the voltage of the signal provided by its pixel circuit (such as the data signal Vdata), for the virtual sub-pixel 30, the luminous brightness of the luminous layer 303 can also be flexibly adjusted by controlling the voltage of the signal provided by its pixel circuit 302.

[0080] Optional, combined Figure 12 Since there may be a certain distance between the pixel circuit 302 and the light emitting layer 303 of the virtual sub-pixel 30, in order to achieve a reliable electrical connection between the pixel circuit 302 and the light emitting layer 303. Figure 12 The array substrate may further include an auxiliary electrode 305. The auxiliary electrode 305 and the connecting electrode 301 may be sequentially arranged in a direction away from the base substrate 00, and the pixel circuit 302, the auxiliary electrode 305, the connecting electrode 301, and the light-emitting layer 303 of the virtual sub-pixel 30 may be electrically connected in sequence.

[0081] Furthermore, in order to further achieve reliable electrical connection between the pixel circuit 302 and the light emitting layer 303, the orthographic projection of the auxiliary electrode 305 on the base substrate 00 may at least partially overlap with the orthographic projection of the connecting electrode 301 on the base substrate 00. For example, Figure 12 The array substrate shown includes an orthographic projection of the auxiliary electrode 305 on the base substrate 00, which completely covers the orthographic projection of the connecting electrode 301 on the base substrate 00. The complete coverage ensures a reliable electrical connection between the auxiliary electrode 305 and the connecting electrode 301, thereby ensuring a reliable electrical connection between the pixel circuit 302 and the light-emitting layer 303.

[0082] Optional, reference Figure 12In the embodiment of the present disclosure, the auxiliary electrode 305 can also be located on the same layer as the source and drain (SD) in the pixel circuit 302 of the virtual sub-pixel 30. Accordingly, the auxiliary electrode 305 and the source and drain SD of the pixel circuit 302 can be formed through a single patterning process, thereby avoiding increasing manufacturing costs and complexity of the manufacturing process.

[0083] Optional, reference Figure 12 The array substrate may further include: a buffer layer (buffer) B1, an active layer (poly) L1, a first gate insulating layer GI1, a gate G1, and a second gate insulating layer GI2, which are located between the base substrate 00 and the source and drain electrodes SD and are stacked in sequence in a direction away from the base substrate; a planar layer (PLN) N1 located between the source and drain electrodes SD and the connecting electrode 301; a pixel defining layer (PDL) D1 and a hole transport layer (HTL) H1, which are located between the connecting electrode 301 and the light-emitting layer 303 and are arranged in sequence along the Y1 direction; and an electron transport layer (ETL) E1 located between the light-emitting layer 303 and the electrode layer 304.

[0084] Figure 13 This is a structural diagram of another array substrate provided in an embodiment of the present disclosure. Figure 14 This is a structural diagram of another array substrate provided by an embodiment of the present disclosure. Figure 13 and Figure 14 ,as well as Figure 12 As can be seen from the cross-sectional view, the array substrate may further include: a data line V1 (connected to the data signal terminal Vdata), a power signal line V2 (connected to the power signal terminal VDD), a first GOA unit and a first EOA unit. Figure 13 and Figure 14 The data line V1 , the power signal line V2 , the first GOA unit, and the first EOA unit may all be electrically connected to the pixel circuit 302 of the virtual sub-pixel 30 .

[0085] For example, reference Figure 13 and Figure 14, the first GOA unit can be connected to the gate signal terminal GATE and the reset signal terminal RST of the pixel circuit 302, and the first EOA unit can be connected to the light-emitting control signal terminal EM of the pixel circuit 302. The data line V1 can provide a data signal to the pixel circuit 302 of the virtual sub-pixel 30, the power signal line V2 can provide a power signal to the pixel circuit 302 of the virtual sub-pixel 30, the first GOA unit can provide a gate drive signal GATE and a reset signal RST to the pixel circuit 302 of the virtual sub-pixel 30, and the first EOA unit can provide a light-emitting control signal EM to the pixel circuit 302 of the virtual sub-pixel 30. The pixel circuit 302 can work under the drive of each signal to drive the light-emitting layer 303 of the virtual sub-pixel 30 to emit light. Optionally, refer to Figure 13 and Figure 14 Each pixel circuit is also electrically connected to an initial power supply terminal Vinit, and the initial power supply terminal Vinit can provide an initial power supply signal to the pixel circuit electrically connected thereto.

[0086] It should be noted that, combined with Figure 12 It can be seen that the data line V1 and the power signal line V2 can be located in the same layer as the source and drain electrodes SD. Accordingly, the data line V1 and the power signal line V2 can be formed with the source and drain electrodes SD through a single patterning process.

[0087] refer to Figure 13 and Figure 14 The array substrate may further include: a virtual GOA unit and a virtual EOA unit, and the virtual GOA unit and the virtual EOA unit may both be electrically connected to the pixel circuit 102 of the first sub-pixel 10, and the first sub-pixel 10 and the virtual sub-pixel 30 may be arranged in sequence and adjacent to each other along the target direction X1.

[0088] Optional, reference Figure 13 , the first EOA unit, the first GOA unit and the first sub-pixel 10 can be arranged in sequence along the gate line scanning direction S1, the virtual GOA unit and the first GOA unit can be arranged in sequence along the target direction X1, and the virtual EOA unit and the first EOA unit can be arranged in sequence along the target direction X1.

[0089] Alternatively, refer to Figure 14 , the virtual EOA unit, the virtual GOA unit and the first sub-pixel 10 can be arranged in sequence along the gate line scanning direction S1, the virtual GOA unit and the first GOA unit can be arranged in sequence along the opposite direction X2 of the target direction X1, and the virtual EOA unit and the first EOA unit can be arranged in sequence along the opposite direction X2 of the target direction X1. It should be noted that, Figure 13 and Figure 14 Only the pixel circuit 102 of the first sub-pixel 10 and the pixel circuit 302 of the dummy sub-pixel 30 are shown.

[0090] contrast Figure 13 and Figure 14 It can be seen from the arrangement and connection method that Figure 13 The arrangement and connection method shown can reduce the wiring length, facilitate the connection between the first GOA unit and the first EOA unit and the pixel circuit 302 of the virtual sub-pixel 30, save manufacturing costs, and facilitate the realization of a narrow frame.

[0091] Optional, Figure 15 FIG. 1 is a structural diagram of another array substrate provided by an embodiment of the present disclosure. Figure 15 As shown, the array substrate may further include: at least one switching circuit 40 corresponding to at least one signal line in the signal line set. Each of the at least one signal line may include two conductive segments, and the two conductive segments may be electrically connected via the switching circuit 40 corresponding to the signal line.

[0092] Optionally, the signal line set may include: a data line V1, a power signal line V2, a signal line electrically connecting the first GOA unit to the pixel circuit 302 of the virtual sub-pixel 30, and a signal line electrically connecting the first EOA unit to the pixel circuit 302 of the virtual sub-pixel 30. The switch circuit 40 may also be electrically connected to the control signal terminal Con1. The switch circuit 40 may control the on / off state of the two electrically connected conductive segments in response to a control signal provided by the control signal terminal Con1.

[0093] Example, reference Figure 15 The at least one switching circuit 40 may include: a switching circuit 40 corresponding to the data line V1, and a switching circuit 40 corresponding to the power signal line V2. The switching circuit 40 corresponding to the data line V1 can control the two conductive segments of the data line V1 to be conductive when the potential of the control signal provided by the control signal terminal Con1 is a valid potential, at which point the data line V1 can input a data signal to the pixel circuit 302; and control the two conductive segments of the data line V1 to be disconnected when the potential of the control signal is an invalid potential. The switching circuit 40 corresponding to the power signal line V2 can also control the two conductive segments of the power signal line V2 to be conductive when the potential of the control signal provided by the control signal terminal Con1 is a valid potential, at which point the power signal line V2 can input a power signal to the pixel circuit 302; and control the two conductive segments of the power signal line V2 to be disconnected when the potential of the control signal is an invalid potential.

[0094] By providing the switch circuit 40, flexible control of the pixel circuit 302 of the virtual sub-pixel 30 can be achieved. Furthermore, since the signal provided by the first GOA unit to the pixel circuit 302 is a gate drive signal, and the signal provided by the first EOA unit to the pixel circuit 302 is a light-emission control signal, and these gate drive signals and light-emission control signals are susceptible to leakage when left floating, by providing only the switch circuits corresponding to the data line V1 and the power signal line V2, flexible control of the pixel circuit 302 can be achieved while avoiding abnormal display effects caused by leakage of the gate drive signals and light-emission control signals. This ensures the display effect while maintaining controllability of the pixel circuit 302 of the virtual sub-pixel 30.

[0095] Optional, reference Figure 15 The switch circuit 40 may include a transistor T1. A gate of the transistor T1 may be electrically connected to the control signal terminal Con1, a first electrode of the transistor T1 may be electrically connected to a conductive segment of a signal line, and a second electrode of the transistor T1 may be electrically connected to another conductive segment of the signal line.

[0096] Example, reference Figure 15 The gate of the transistor T1 corresponding to the data line V1 is electrically connected to the control signal terminal Con1, the first electrode is electrically connected to one conductive segment of the data line V1, and the second electrode is electrically connected to another conductive segment of the data line V1. The gate of the transistor T1 corresponding to the power signal line V2 is electrically connected to the control signal terminal Con1, the first electrode is electrically connected to one conductive segment of the power signal line V2, and the second electrode is electrically connected to another conductive segment of the power signal line V2.

[0097] Optional, Figure 16 FIG. 1 is a structural diagram of another array substrate provided by an embodiment of the present disclosure. Figure 16 As shown, the array substrate may further include a third sub-pixel 50 located in the display area A1. The colors of the first sub-pixel 10, the second sub-pixel 20, and the third sub-pixel 50 may be different, and in the gate line scanning direction S1, two sub-pixels for emitting light of a target color may be arranged side by side between the second sub-pixel 20 and the third sub-pixel 50. The target color is the same as the color of the light emitted by the first sub-pixel.

[0098] Since the color of light emitted by the virtual sub-pixel 30 is the same as that of the first sub-pixel 10, Figure 16 Two first sub-pixels 10 may be arranged in parallel between the second sub-pixel 20 and the third sub-pixel 50; or one first sub-pixel 10 and one dummy sub-pixel 30 may be arranged in parallel between the second sub-pixel 20 and the third sub-pixel 50.

[0099] use Figure 16The arrangement shown allows the second sub-pixel 20 and the third sub-pixel 50 to achieve normal color matching by sharing the two sub-pixels arranged in parallel between them. In other words, normal display is achieved by sharing sub-pixels. Optionally, the first sub-pixel 10 can be a green sub-pixel, the second sub-pixel 20 can be a red sub-pixel, and the third sub-pixel 50 can be a blue sub-pixel.

[0100] Of course, the colors of the first sub-pixel 10, the second sub-pixel 20 and the third sub-pixel 50 are not limited to those described in the specification. That is, for other non-RGB display devices, effective brightness compensation can also be achieved through the array substrate provided by the embodiment of the present disclosure.

[0101] It should be noted that the structures of each sub-pixel (such as the connecting electrodes, pixel circuitry, and light-emitting layer) are all patterned using a fine metal mask (FMM). Since the structure of the effective sub-pixels is not adjusted in this embodiment, the hollowed-out areas of the FMM corresponding to the effective sub-pixels do not need to be modified.

[0102] It should also be noted that the electrical connection described in the embodiments of the present disclosure means that the two ends of the interconnected circuit can transmit signals to each other, and the electrical connection can include direct connection or indirect connection. In the above embodiments, the transistor is an N-type transistor, and the effective potential is a high potential and the invalid potential is a low potential. Of course, the transistor can also be a P-type transistor. When the transistor is a P-type transistor, the effective potential is a low potential and the invalid potential is a high potential.

[0103] In summary, an embodiment of the present disclosure provides an array substrate. The array substrate includes a first sub-pixel, a second sub-pixel, and a virtual sub-pixel. In the target direction, the brightness attenuation of the first sub-pixel is greater than the brightness attenuation of the second sub-pixel, and the color of the light emitted by the light-emitting layer of the virtual sub-pixel is the same as the color of the light emitted by the first sub-pixel. Since the virtual sub-pixel also includes a connecting electrode electrically connecting its pixel circuit and the light-emitting layer, and the pixel circuit can drive the virtual sub-pixel to emit light through the connecting electrode, the brightness attenuation of the first sub-pixel can be compensated by controlling the virtual sub-pixel to emit light, that is, the difference in brightness attenuation between the first sub-pixel and the second sub-pixel can be reduced by controlling the virtual sub-pixel to emit light. The display effect of the display device made of the array substrate is better.

[0104] Figure 17 This is a flow chart of a method for manufacturing an array substrate provided by an embodiment of the present disclosure, which is used to manufacture Figures 10 to 16 Any of the array substrates shown, refer to Figure 17 , the manufacturing method may include:

[0105] Step 170 : forming a pixel circuit structure, a driving electrode structure, a light-emitting layer structure, and an electrode layer structure in sequence in the display area of ​​the base substrate to obtain a first sub-pixel, a second sub-pixel, and a virtual sub-pixel.

[0106] The pixel circuit structure may include: a pixel circuit for each sub-pixel; the driving electrode structure may include a connecting electrode for each sub-pixel; the light-emitting layer structure may include a light-emitting layer for each sub-pixel; and the electrode layer structure may include an electrode layer for each sub-pixel. Furthermore, in each sub-pixel, the light-emitting layer may be electrically connected to the pixel circuit via the connecting electrode, and the light-emitting layer may also be electrically connected to the electrode layer, and the pixel circuit may drive the light-emitting layer to emit light via the connecting electrode.

[0107] In the embodiments of the present disclosure, reference Figure 10 The display area A1 may have a gap K1. In the target direction X1 along the center of the display area A1 close to the gap K1, the brightness attenuation of the first sub-pixel 10 is greater than the brightness attenuation of the second sub-pixel 20, and the light-emitting layer of the virtual sub-pixel and the light-emitting layer of the first sub-pixel are used to emit light of the same color.

[0108] In summary, embodiments of the present disclosure provide a method for manufacturing an array substrate. By forming a virtual sub-pixel within a display region that includes a connecting electrode and emits the same color as the first sub-pixel with the greatest brightness attenuation, the brightness attenuation of the first sub-pixel can be compensated by controlling the brightness of the virtual sub-pixel. In other words, the difference in brightness attenuation between the first and second sub-pixels can be reduced by controlling the brightness of the virtual sub-pixel. The array substrate manufactured using this method provides a display device with improved display quality.

[0109] Optional, reference Figure 12 , the array substrate may further include: an auxiliary electrode 305. Accordingly, Figure 18 This is a flow chart of a method for sequentially forming a pixel circuit structure, a driving electrode structure, a light-emitting layer structure, and an electrode layer structure in a display area of ​​a substrate provided by an embodiment of the present disclosure. Figure 18 As shown, the method may include:

[0110] Step 1701: Form a gate pattern, an active layer pattern, and a source / drain pattern on one side of a base substrate to obtain a pixel circuit structure.

[0111] In the embodiment of the present disclosure, an active layer pattern, a gate pattern, and a source / drain pattern can be sequentially formed in a direction away from the substrate 00 through a patterning process, and the resulting pixel circuit structure is a bottom-gate structure. Alternatively, an active layer pattern, a source / drain pattern, and a gate pattern can be sequentially formed in a direction away from the substrate 00 through a patterning process, and the resulting pixel circuit structure is a top-gate structure. Optionally, the patterning process may include processes such as coating, exposure, development, and etching.

[0112] For example, the base substrate 00 formed with the pixel circuit structure can be as follows Figure 19 Reference Figure 19 The pixel circuit structure shown is a bottom-gate structure, that is, the gate pattern M1 and the source-drain pattern M2 are arranged in sequence in a direction away from the base substrate 00. The gate pattern M1 may include the gate G1 of each sub-pixel to be formed (such as the first sub-pixel 10, the second sub-pixel 20, and the dummy sub-pixel 30), the source-drain pattern M2 may include the source-drain electrode SD of each sub-pixel to be formed and the auxiliary electrode 305, and the active layer pattern M3 may include the active layer L1 of each sub-pixel to be formed.

[0113] Optional, reference Figure 19 , the source-drain pattern M2 may also include Figures 12 to 15 Any of the data lines V1, power signal lines V2 and source and drain electrodes SD (not shown) of the switch circuit 40. The gate pattern M1 may also include Figure 10 The gate of the switching circuit 40 is shown (not shown in the figure).

[0114] It should be noted that Figure 19 Only the gate pattern, source / drain pattern, and active layer pattern corresponding to the first sub-pixel 10 and the dummy sub-pixel 30 to be formed are shown.

[0115] Step 1702 : forming a driving electrode structure on a side of the gate pattern, the active layer pattern, and the source and drain pattern away from the base substrate.

[0116] In the embodiment of the present disclosure, after the pixel circuit is formed, a patterning process may be continued to form a driving electrode structure on a side of the gate pattern, the active layer pattern, and the source and drain pattern away from the base substrate.

[0117] For example, the base substrate 00 formed with the driving electrode structure M4 can be as follows Figure 20 Reference Figure 20 The driving electrode pattern M4 may include: a connecting electrode for each sub-pixel to be formed. Figure 14 Only the connection electrode 101 of the first sub-pixel 10 to be formed and the connection electrode 301 of the dummy sub-pixel 30 to be formed are shown. Optionally, the formed driving electrode structure may be an anode or a cathode.

[0118] It should be noted that the exposure step of the patterning process provided in the embodiments of the present disclosure is performed using a mask including hollowed-out regions of varying shapes and sizes. Since the orthographic projection area of ​​the connection electrode 301 formed on the base substrate 00 for the virtual sub-pixel 30 can be smaller than or equal to the orthographic projection area of ​​the light-emitting layer 303 on the base substrate 00, the area of ​​the hollowed-out region of the mask corresponding to the connection electrode 301 can be smaller than or equal to the area of ​​the hollowed-out region corresponding to the light-emitting layer 303.

[0119] Step 1703: forming a light-emitting layer structure on a side of the driving electrode structure away from the base substrate.

[0120] Similarly, the patterning process may be continued to form a light-emitting layer structure M5 on the side of the driving electrode structure M4 away from the base substrate 00 .

[0121] For example, the base substrate 00 formed with the light emitting layer structure M5 can be as follows Figure 21 Reference Figure 21 , the light emitting layer pattern structure may include the light emitting layer of each sub-pixel to be formed. For example, Figure 21 Only the light emitting layer 103 of the first sub-pixel to be formed and the light emitting layer 303 of the dummy sub-pixel to be formed are shown. Figure 21 The pixel circuit 302 of the virtual sub-pixel and the light-emitting layer 303 can be electrically connected through the connecting electrode 301 , and the pixel circuit 102 of the first sub-pixel and the light-emitting layer 103 can be electrically connected through the connecting electrode 101 of the first sub-pixel.

[0122] Optionally, the materials forming the light-emitting layer patterns corresponding to different sub-pixels may be different. For example, when the first sub-pixel 10 is a green sub-pixel and the dummy sub-pixel 30 is a green dummy sub-pixel, the material of the light-emitting layer structure M5 may be the light-emitting material forming the green sub-pixel.

[0123] Step 1704: forming an electrode layer structure on a side of the light-emitting layer structure away from the base substrate.

[0124] Similarly, the patterning process may be continued to form the electrode layer structure M6 on the side of the light emitting layer structure M5 away from the base substrate 00 .

[0125] For example, the base substrate 00 formed with the electrode layer structure M6 can be as follows Figure 22 Reference Figure 22 The electrode layer structure M6 may include: an electrode layer for each sub-pixel ( Figure 22Only the electrode layer 104 of the first sub-pixel and the electrode layer 304 of the dummy sub-pixel are shown. Optionally, the formed electrode layer may be an anode or a cathode, and the electrode layer structure and the driving electrode structure have different electrodes.

[0126] It should be noted that, combined with Figures 19 to 22 For an array substrate with a bottom-gate structure, the method for forming sub-pixels further includes: forming a buffer layer B1 on one side of the base substrate 00 through a patterning process before forming an active layer L1; forming a first gate insulating layer GI1 on a side of the active layer L1 away from the buffer layer B1 after forming the active layer L1; forming a second gate insulating layer GI2 on a side of the gate G1 away from the first gate insulating layer GI1 after forming the gate G1; forming a planarizing layer N1 on a side of the source and drain SD away from the base substrate 00 after forming the source and drain SD; forming a pixel dielectric layer D1 on a side of the drive electrode structure away from the planarizing layer N1 after forming the drive electrode structure (including the connecting electrode); forming a hole transport layer H1 on a side of the pixel dielectric layer D1 away from the drive electrode structure; and forming an electron transport layer E1 on a side of the light-emitting layer structure away from the hole transport layer H1 after forming the light-emitting layer structure (including the light-emitting layer).

[0127] It should also be noted that a first GOA unit, a first EOA unit, a dummy GOA unit, and a dummy EOA unit may be provided at the edge of the substrate. Each GOA unit and each EOA unit is electrically connected to a pixel circuit of a sub-pixel to control the pixel circuit to drive the sub-pixel to emit light.

[0128] In summary, embodiments of the present disclosure provide a method for manufacturing an array substrate. By forming a virtual sub-pixel within a display region that includes a connecting electrode and emits the same color as the first sub-pixel with the greatest brightness attenuation, the brightness attenuation of the first sub-pixel can be compensated by controlling the brightness of the virtual sub-pixel. In other words, the difference in brightness attenuation between the first and second sub-pixels can be reduced by controlling the brightness of the virtual sub-pixel. The array substrate manufactured using this method provides a display device with improved display quality.

[0129] Figure 23 This is a flow chart of a driving method of an array substrate provided by an embodiment of the present disclosure, which is used to drive Figures 10 to 16 Any of the array substrates shown. Figure 23 As shown, the method may include:

[0130] Step 230 : providing a driving signal to the pixel circuit of the virtual sub-pixel. The pixel circuit of the virtual sub-pixel responds to the driving signal and drives the light-emitting layer of the virtual sub-pixel to emit light through the connecting electrode of the virtual sub-pixel.

[0131] Optional, reference Figure 15 The array substrate may further include: at least one switch circuit 40 corresponding to at least one signal line in the signal line set, and the switch circuit 40 is also electrically connected to the control signal terminal Con1. Figure 24 , the above step 230 may include:

[0132] Step 2301: Provide a control signal to the control signal terminal. The switch circuit responds to the control signal to control the two electrically connected conductive segments to be turned on.

[0133] In the disclosed embodiment, the control device of the array substrate may first provide a control signal at an effective potential to the control signal terminal. Accordingly, the switch circuit may control the two electrically connected conductive segments to be conductive under the control of the control signal.

[0134] For example, for Figure 15 In the array substrate shown, one switch circuit 40 can control the two conductive segments of the data line V1 electrically connected thereto to be conductive under the control of a control signal; another switch circuit 40 can control the power signal line V2 electrically connected thereto to be conductive under the control of a control signal.

[0135] Step 2302: Provide a data signal to the data line, provide a power signal to the power signal line, provide a compensation signal to the first GOA unit, and provide a compensation signal to the first EOA unit.

[0136] In the disclosed embodiment, after providing a control signal at an effective potential to the control signal terminal Con1, the control device can control the circuit connected to the data line V1 (e.g., a source driver circuit) to provide a data signal to the data line V1. The control device can control the circuit connected to the power signal line V2 to provide a power signal to the power signal line V2. The control device can control the circuit connected to the first GOA unit to provide a compensation signal to the virtual GOA unit, and can control the circuit connected to the first EOA unit to provide a compensation signal to the virtual EOA unit.

[0137] Then, the data line V1 can write a data signal to the pixel circuit, the power signal line V2 can write a power signal to the pixel circuit 302, the first GOA unit can output a gate drive signal and a reset signal to the pixel circuit 302, and the first EOA unit can output a light-emitting control signal to the pixel circuit 302. Accordingly, under the control of these multiple signals, the pixel circuit 302 can output a drive signal to the light-emitting layer 303 electrically connected thereto, so as to drive the light-emitting layer 303 electrically connected thereto to emit light.

[0138] It should be noted that the embodiment of the present disclosure does not limit the order of the above steps 2301 and 2302. For example, steps 2301 and 2302 can be performed simultaneously.

[0139] In summary, the embodiments of the present disclosure provide a method for controlling an array substrate. By providing signals to each signal line, the first GOA unit, and the first EOA unit, the pixel circuit of a virtual sub-pixel can reliably drive the light-emitting layer of the virtual sub-pixel to emit light. Because the virtual sub-pixel can emit light of the same color as the first sub-pixel with the greatest brightness attenuation, controlling the illumination of the virtual sub-pixel effectively reduces the difference in brightness attenuation between the first sub-pixel and the second sub-pixel, resulting in a display device fabricated from this array substrate having a better display effect.

[0140] Optionally, the embodiment of the present disclosure further provides a control device for the array substrate, which can be electrically connected to the pixel circuit of the virtual sub-pixel, and can perform the following operations: Figure 23 and Figure 24 Any of the driving methods of the array substrate shown. For example, the control device may be a processor.

[0141] Optionally, the embodiment of the present disclosure further provides a display device, which may include: Figures 10 to 16 Any of the array substrates shown, and a control device for the array substrate. The display device may be a liquid crystal panel, electronic paper, an organic light-emitting diode (OLED) panel, an active-matrix organic light-emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or any other product or component with a display function.

[0142] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the array substrate, each circuit and the control device of the array substrate described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0143] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

[0144] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. An array substrate, characterized in that: The array substrate comprises: a base substrate, a first sub-pixel and a second sub-pixel located in a display area of ​​the base substrate, and a virtual sub-pixel located in the display area and in a non-display area of ​​the base substrate, the virtual sub-pixel being used to protect the first sub-pixel and the second sub-pixel and to arrange the sub-pixels in the array substrate uniformly, the display area having a notch, and in a target direction close to the notch along the center of the display area, the brightness attenuation degree of the first sub-pixel is greater than the brightness attenuation degree of the second sub-pixel; Each of the first sub-pixel, the second sub-pixel and the virtual sub-pixel located in the display area includes: a pixel circuit, a connecting electrode, a light-emitting layer and an electrode layer. The light-emitting layer is electrically connected to the pixel circuit through the connecting electrode, and the light-emitting layer is also electrically connected to the electrode layer. The pixel circuit is used to drive the light-emitting layer to emit light through the connecting electrode, and the light-emitting layer in the virtual sub-pixel located in the display area and the light-emitting layer in the first sub-pixel are used to emit light of the same color; the virtual sub-pixel located in the non-display area does not emit light.

2. The array substrate according to claim 1, characterized in that: The connection electrode of the virtual sub-pixel located in the display area is located in the same layer as the connection electrode of the first sub-pixel.

3. The array substrate according to claim 1, characterized in that: In the virtual sub-pixel located in the display area, an area of ​​an orthographic projection of the connecting electrode on the base substrate is smaller than or equal to an area of ​​an orthographic projection of the light emitting layer on the base substrate.

4. The array substrate according to claim 3, characterized in that: In the virtual sub-pixel located in the display area, the ratio of the area of ​​the orthographic projection of the connecting electrode on the base substrate to the area of ​​the orthographic projection of the light-emitting layer on the base substrate is in a range of 7% to 15%.

5. The array substrate according to any one of claims 1 to 4, characterized in that: The array substrate further comprises: an auxiliary electrode, and the auxiliary electrode and the connecting electrode in the virtual sub-pixel located in the display area are arranged in sequence along a direction away from the base substrate; The pixel circuit of the virtual sub-pixel located in the display area, the auxiliary electrode, the connection electrode of the virtual sub-pixel located in the display area, and the light-emitting layer of the virtual sub-pixel located in the display area are electrically connected in sequence.

6. The array substrate according to claim 5, characterized in that: The auxiliary electrode is located in the same layer as the source and drain in the pixel circuit of the virtual sub-pixel located in the display area.

7. The array substrate according to any one of claims 1 to 4, characterized in that: The array substrate further comprises: a data line, a power signal line, a first GOA unit and a first EOA unit; The data line, the power signal line, the first GOA unit and the first EOA unit are all electrically connected to the pixel circuit of the virtual sub-pixel located in the display area; The data line is used to provide a data signal to the pixel circuit of the virtual sub-pixel located in the display area, the power signal line is used to provide a power signal to the pixel circuit of the virtual sub-pixel located in the display area, the first GOA unit is used to provide a gate drive signal to the pixel circuit of the virtual sub-pixel located in the display area, and the first EOA unit is used to provide a light emitting control signal to the pixel circuit of the virtual sub-pixel located in the display area.

8. The array substrate according to claim 7, characterized in that: The array substrate further includes: a virtual GOA unit and a virtual EOA unit, and the virtual GOA unit and the virtual EOA unit are both electrically connected to the pixel circuit of the first sub-pixel, and the first sub-pixel and the virtual sub-pixel located in the display area are sequentially arranged and adjacent along the target direction; The first EOA unit, the first GOA unit and the first sub-pixel are arranged in sequence along the gate line scanning direction, the virtual GOA unit and the first GOA unit are arranged in sequence along the target direction, and the virtual EOA unit and the first EOA unit are arranged in sequence along the target direction; Alternatively, the virtual EOA unit, the virtual GOA unit and the first sub-pixel are arranged in sequence along the gate line scanning direction, the virtual GOA unit and the first GOA unit are arranged in sequence in the opposite direction of the target direction, and the virtual EOA unit and the first EOA unit are arranged in sequence in the opposite direction of the target direction.

9. The array substrate according to claim 7, characterized in that: The array substrate further comprises: at least one switch circuit corresponding one-to-one to at least one signal line in the signal line set; Each of the signal lines includes two conductive segments, and the two conductive segments are electrically connected through a switch circuit corresponding to the signal line, and the signal line set includes: the data line, the power signal line, a signal line electrically connected to the pixel circuit of the virtual sub-pixel located in the display area by the first GOA unit, and a signal line electrically connected to the pixel circuit of the virtual sub-pixel located in the display area by the first EOA unit; The switch circuit is also electrically connected to the control signal terminal, and is used to control the on-off state of the two conductive segments electrically connected thereto in response to a control signal provided by the control signal terminal.

10. The array substrate according to claim 9, characterized in that: The at least one switch circuit includes: a switch circuit corresponding to the data line, and a switch circuit corresponding to the power signal line.

11. The array substrate according to claim 9, characterized in that: The switch circuit comprises: a transistor; The gate of the transistor is electrically connected to the control signal terminal, the first electrode of the transistor is electrically connected to a conductive segment of a signal line, and the second electrode of the transistor is electrically connected to another conductive segment of the signal line.

12. The array substrate according to any one of claims 1 to 4, characterized in that: The array substrate further includes: a third sub-pixel located in the display area; The colors of light emitted by the first sub-pixel, the second sub-pixel and the third sub-pixel are different, and in the gate line scanning direction, two sub-pixels for emitting light of a target color are arranged side by side between the second sub-pixel and the third sub-pixel, and the target color is the same as the color of the light emitted by the first sub-pixel.

13. The array substrate according to claim 12, characterized in that: The first sub-pixel is a green sub-pixel, the second sub-pixel is a red sub-pixel, and the third sub-pixel is a blue sub-pixel.

14. A method for manufacturing an array substrate, characterized in that: For manufacturing the array substrate according to any one of claims 1 to 13, the method comprises: A pixel circuit structure, a driving electrode structure, a light-emitting layer structure and an electrode layer structure are sequentially formed in the display area of ​​the base substrate to obtain a first sub-pixel, a second sub-pixel and a virtual sub-pixel; The pixel circuit structure includes: a pixel circuit of each sub-pixel, the driving electrode structure includes a connecting electrode of each sub-pixel, the light-emitting layer structure includes a light-emitting layer of each sub-pixel, the electrode layer structure includes an electrode layer of each sub-pixel, and in each of the sub-pixels, the light-emitting layer is electrically connected to the pixel circuit through the connecting electrode, the light-emitting layer is also electrically connected to the electrode layer, and the pixel circuit is used to drive the light-emitting layer to emit light through the connecting electrode; The display area has a notch, and in a target direction close to the notch along the center of the display area, the brightness attenuation of the first sub-pixel is greater than the brightness attenuation of the second sub-pixel, and the light-emitting layer of the virtual sub-pixel and the light-emitting layer of the first sub-pixel are used to emit light of the same color.

15. The method according to claim 14, characterized in that The array substrate further includes: an auxiliary electrode, the auxiliary electrode being electrically connected to the connection electrode of the virtual sub-pixel; the pixel circuit structure, the driving electrode structure, the light-emitting layer structure and the electrode layer structure are sequentially formed in the display area of ​​the base substrate, including: A gate pattern, an active layer pattern and a source-drain pattern are formed on one side of the base substrate to obtain the pixel circuit structure, wherein the source-drain pattern includes the source-drain and the auxiliary electrode of each sub-pixel, the active layer pattern includes the active layer of each sub-pixel, and the gate pattern includes the gate of each sub-pixel; forming the driving electrode structure on a side of the gate pattern, the active layer pattern and the source and drain pattern away from the base substrate; Forming the light-emitting layer structure on a side of the driving electrode structure away from the base substrate; The electrode layer structure is formed on a side of the light emitting layer structure away from the base substrate.

16. A method for driving an array substrate, characterized in that: Used to drive the array substrate according to any one of claims 1 to 13, the method comprising: A driving signal is provided to the pixel circuit of the virtual sub-pixel, and the pixel circuit of the virtual sub-pixel drives the light-emitting layer of the virtual sub-pixel to emit light through the connection electrode of the virtual sub-pixel in response to the driving signal.

17. The method according to claim 16, characterized in that The array substrate further includes: at least one switch circuit corresponding to at least one signal line in the signal line set, and the switch circuit is also electrically connected to the control signal terminal; the providing of a driving signal to the pixel circuit of the virtual sub-pixel includes: A control signal is provided to the control signal terminal, and the switch circuit controls the two electrically connected conductive segments to be turned on in response to the control signal; A data signal is provided to the data line, a power signal is provided to the power signal line, a compensation signal is provided to the first GOA unit, and a compensation signal is provided to the first EOA unit.

18. A control device for an array substrate, characterized in that: The control device is electrically connected to the pixel circuit of the virtual sub-pixel, and the control device is used to execute the driving method of the array substrate as described in claim 16 or 17.

19. A display device, characterized in that: The display device comprises: the array substrate according to any one of claims 1 to 13, and the control device for the array substrate according to claim 18.

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