Memory device

Abstract

A memory device is provided. The memory device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; a word line driving circuit including a plurality of sub word line decoders connected to the plurality of word lines, respectively, wherein each sub word line decoder is configured to input a first driving signal to a word line connected thereto when the word line is selected, and wherein each sub word line decoder is configured to input a predetermined power voltage to the word line connected thereto when the word line is not selected; a sense amplifier circuit including a sense amplifier connected to the bit lines; and a logic circuit configured to determine a failure of at least one of the memory cell array and the word line driving circuit by floating the unselected sub word line decoders while inputting the first driving signal to the selected word line and detecting data of the memory cells connected to the unselected word lines using at least one of the sense amplifiers.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2019-0170409 filed on December 19, 2019, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a memory device. Background Art

[0003] A memory device may provide functions including writing data, reading written data, and / or erasing data. The memory device may include a plurality of memory cells and a memory controller, and the memory cells may be connected to the memory controller via word lines and bit lines. As the integration density of memory devices increases, various faults may occur or potentially occur in the memory cells, the memory controller, and / or the word lines and bit lines. Summary of the Invention

[0004] Aspects of the present disclosure provide a memory device that can effectively detect internal latent failures to improve its quality.

[0005] According to some example embodiments, a memory device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; a word line driver circuit including a plurality of sub-word line decoders respectively connected to the plurality of word lines, wherein each of the plurality of sub-word line decoders is configured to input a first drive signal to the word line when the respective connected word line is selected, and each sub-word line decoder is configured to input a predetermined power supply voltage to the word line when the respective connected word line is unselected; a sense amplifier circuit including sense amplifiers is connected to the plurality of bit lines, and a logic circuit is configured to float unselected sub-word line decoders while inputting the first drive signal to the selected word line and detect data of the memory cells connected to the unselected word lines using at least one of the sense amplifiers to determine a failure of at least one of the memory cell array and the word line driver circuit.

[0006] According to some example embodiments, a memory device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; a word line driving circuit including sub-word line decoders connected to the plurality of word lines, wherein each of the sub-word line decoders is connected to a power line and configured to output a predetermined power supply voltage through a power switch; and a logic circuit configured to control the power switch.

[0007] According to some example embodiments, a memory device includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a connection circuit configured to generate a driving signal to drive the memory cells, a sub word line decoder connected between the connection circuit and the plurality of word lines and configured to determine a selected word line and an unselected word line from the plurality of word lines, and a logic circuit configured to control the sub word line decoder such that a power supply voltage is input to the plurality of word lines during a first time, and configured to control the sub word line decoder such that a driving voltage higher than the power supply voltage is input to the selected word line and the unselected word line is floated during a second time after the first time. BRIEF DESCRIPTION OF DRAWINGS

[0008] The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 And Figure 2 is a schematic diagram of a memory device according to some example embodiments.

[0010] Figure 3 shows a failure of a memory device according to some example embodiments.

[0011] Figure 4 is a flowchart showing an operation of a memory device according to some example embodiments.

[0012] Figure 5 shows an operation of a memory device according to some example embodiments.

[0013] Figure 6 shows an operation of a memory device according to some example embodiments.

[0014] Figures 7 to 12 shows an operation of a memory device according to some example embodiments.

[0015] Figures 13 to 15 is a schematic circuit diagram of a memory device according to some example embodiments.

[0016] Figure 16 shows a manufacturing process of a memory device according to some example embodiments.

[0017] Figure 17 is a schematic block diagram of a mobile system including a memory device according to some example embodiments. DETAILED DESCRIPTION

[0018] Hereinafter, some example embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0019] Figure 1and Figure 2 is a schematic diagram of a memory device 1 according to some example embodiments.

[0020] Figure 1 is a schematic block diagram showing a structure of the memory device 1 according to some examples of the embodiments. In some example embodiments, Figure 1 The memory device 1 of Figure 1 In the example embodiments shown in FIG. 1, the memory device 1 can include a row decoder 20, a pre-decoder (PXI GEN.) 22, a connection circuit 42, a word line drive circuit 32, a cell array 10, a sense amplifier circuit 12, and a drive signal generator (PXID GEN.) 40 and a drive signal generator (PXID GEN.) 50. Other components can be present within the memory device 1 of Figure 1 Discussion of these other components can be omitted herein for the sake of brevity.

[0021] The row decoder 20 can decode an up address MRADD in response to an up address RA2 to RA8 (MRADD) received from the outside, and can select a word line corresponding to the up address MRADD among the word lines WL. For example, the row decoder 20 can determine a selected word line among the word lines WL in response to the up address MRADD. As an example, the row decoder 20 can output a word line enable signal NWEI to the word line drive circuit 32 to enable the selected word line.

[0022] The pre-decoder 22 can output a pre-decode signal PXI in response to a down address RA0 to RA1 (LRADD). For example, the pre-decoder 22 can decode a down address LRADD among the row addresses received from the outside, and can generate a pre-decode signal PXI corresponding to a selected word line. The pre-decode signal PXI can be input to the drive signal generators 40 and 50 included in the connection circuit 42.

[0023] The drive signal generators 40 and 50 can generate drive signals PXID and PXIB for driving the word lines WL in response to the pre-decode signal PXI. For example, the drive signal generators 40 and 50 can include pull-up circuits that can increase the drive signals PXID and PXIB to a predetermined voltage level. The drive signals PXID and PXIB can be output to a sub word line decoder SWD included in the word line drive circuit 32.

[0024] The first sub-wordline decoder SWD can activate and precharge selected word lines connected to the first sub-wordline decoder SWD in response to the wordline enable signal NWEI and the drive signals PXID and PXIB. For example, the drive signal generators 40 and 50 can increase the level of the first drive signal PXID from a first voltage to a second voltage, and the first drive signal PXID is input to the sub-wordline decoder SWD connected to the selected word lines. The level of the drive signal PXIB can be set to a first voltage. The sub-wordline decoder SWD, receiving the first drive signal PXID at the second voltage and the second drive signal PXIB at the first voltage, can input the first drive signal PXID to the selected word line.

[0025] Other sub-wordline decoders SWD connected to unselected wordlines that are not selected and / or not indicated by the wordline enable signal NWEI may input a predetermined power supply voltage to the unselected wordlines. In some example embodiments, the power supply voltage input to the unselected wordlines may be lower than the second voltage. As an example, the power supply voltage may be a negative constant voltage lower than 0V (volts).

[0026] In some example embodiments, the sub-word line decoder SWD connected to the unselected word line may be separated from the power supply voltage while the first sub-word line decoder SWD connected to the selected word line inputs the first drive signal PXID to the selected word line. Therefore, the sub-word line decoder SWD connected to the unselected word line and the unselected word line may be floated.

[0027] The present disclosure recognizes that, in some cases, the voltage on an unselected word line may not be maintained. As an example, when a bridging fault exists between a selected word line and a floating unselected word line, the voltage on the floating unselected word line may not be maintained at the power supply voltage level and may change due to the first drive signal PXID input to the selected word line. As another example, due to a fault in a sub-word line decoder SWD connected to the unselected word line, the voltage on the unselected word line may not be maintained at the power supply voltage level and may change.

[0028] In some example embodiments, data of memory cells MC connected to unselected word lines may be detected to detect a fault that may exist in the memory device 1. If the voltage on the unselected word lines is not maintained at the power supply voltage level and is changed, the data of the memory cells MC connected to the unselected word lines may be affected. Therefore, the data of the memory cells MC connected to the unselected word lines can be used to detect a fault that exists in the memory device 1.

[0029] The data of the memory cells MC may be detected by the sense amplifier SA included in the sense amplifier circuit 12. The sense amplifier SA may be connected to at least one of the memory cells MC through the bit line pair BL / BLB and may read the data of at least one of the memory cells MC in response to a column address received from the outside.

[0030] In the cell array 10, memory cells MC may be connected to word lines WL and bit lines BL. Each of the memory cells MC may include a storage capacitor and a switching element. Figure 2 The memory cell MC is described in further detail.

[0031] Reference Figure 2 Each memory cell MC may include a storage capacitor CC and a switching element SW. The switching element SW may have a control terminal connected to the word lines WL0 to WLn and an input terminal connected to the bit lines BL0 to BLm and BL0B to BLmB. The word lines WL0 to WLn may be connected to a sub-word line decoder SWD, and the bit lines BL0 to BLm and BL0B to BLmB may be connected to a sense amplifier BLSA.

[0032] Figure 3 is a circuit diagram of a sub-word line decoder 100 included in a memory device according to some example embodiments. Figure 3 The aspects of FIG. 1 illustrate a failure of a memory device according to some example embodiments. Figure 3 The sub wordline decoder 100 may include switching elements PM1, NM1, and NM2. As an example, the sub wordline decoder 100 may include a first switching element PM1 and a second switching element NM1 connected in series to each other and turned on and off by a wordline control signal NWEIB.

[0033] The first switching element PM1 may be a PMOS transistor, and the second switching element NM1 may be an NMOS transistor. In some example embodiments, a first drive signal PXID may be input to an input terminal of the first switching element PM1, and a power supply voltage VBB2 may be input to an input terminal of the second switching element NM1. The first drive signal PXID may have different levels depending on whether the first word line WL1 connected to the sub-word line decoder 100 is selected. The power supply voltage VBB2 may be a constant voltage. In example embodiments, the power supply voltage VBB2 may be a negative constant voltage lower than 0V.

[0034] The sub-wordline decoder 100 may include a third switching element NM2 . The third switching element NM2 may be turned on and off by the second driving signal PXIB and may receive a power supply voltage VBB2 .

[0035] Reference Figure 3 Faults 101 to 104 may occur in various locations, including between word lines WL1 and WL2 and within sub-word line decoder 100. For example, first fault 101 may occur between word lines WL1 and WL2. Word lines WL1 and WL2 may extend in a predetermined direction, and insulating material may be located between word lines WL1 and WL2. Although the distance between word lines WL1 and WL2 is ideally constant, when an electrical path is formed between word lines WL1 and WL2, first fault 101 may occur due to, for example, a decrease in the distance between word lines WL1 and WL2 in at least one region due to a process error.

[0036] When the first fault 101 is present, a problem may occur when one of the word lines WL1 and WL2 is selected. For example, when the first word line WL1 is not selected and the second word line WL2 is selected, the voltage on the second word line WL2 may increase from a first voltage to a second voltage due to the first drive signal PXID. The power supply voltage VBB2 may be input to the first word line WL1 through the sub-word line decoder 100. In this case, the voltage on at least one of the first word line WL1 and the second word line WL2 may change unintentionally due to the first fault 101.

[0037] Second to fourth faults 102 through 104 may occur in the switching elements PM1, NM1, and NM2 included in the sub-wordline decoder 100. For example, second fault 102 may be a bridge fault in which an electrical path is formed between a common node and an input node. First switching element PM1 and second switching element NM1 are connected to first wordline WL1 via the common node, and wordline control signal NWEIB is input to the input node. When second fault 102 occurs and first wordline WL1 is unselected, power supply voltage VBB2 is input to first wordline WL1. In this case, wordline control signal NWEIB and the common node may affect each other due to second fault 102, and the voltage on first wordline WL1 may unintentionally change, or a fault may occur in sub-wordline decoder 100.

[0038] The third fault 103 may be a bridge fault occurring in the third switching element NM2. When the third fault 103 occurs and the first word line WL1 is not selected, the second driving signal PXIB affects the first word line WL1. As a result, the voltage on the first word line WL1 may be unstable.

[0039] Fourth fault 104 may be a bridge fault occurring in second switching element NM1. When fourth fault 104 occurs and first word line WL1 is unselected, word line control signal NWEIB and power supply voltage VBB2 may affect each other. Consequently, the voltage of first word line WL1 may become unstable or the level of word line control signal NWEIB may change, causing a fault in sub-word line decoder 100.

[0040] Aspects of the present disclosure provide for early detection of reference Figure 3 The method of describing the failures 101 to 104. However, referring to Figure 3 The described faults 101 to 104 are examples, and other faults that may be detected in a memory device according to some embodiments are not necessarily limited to Figure 3 Faults 101 to 104 are shown.

[0041] Figure 4 is a flowchart illustrating the operation of a memory device according to some example embodiments, and more particularly, a flowchart illustrating a test operation of the memory device. Reference may be performed before and / or after packaging for the memory device. Figure 4 Describes the test operation. Figure 4 The operation of the memory device according to some example embodiments may begin by inputting a power supply voltage to a word line (S10). The power supply voltage may be input through a sub-word line decoder connected to the word line. As an example, the power supply voltage may be a negative constant voltage lower than 0V.

[0042] A row decoder included in the memory device may determine a selected word line and one or more unselected word lines among the word lines. When the selected word line is determined, a sub-word line decoder connected to the selected word line may input a first drive signal to the selected word line (S20). The first drive signal input to the selected word line may have a level higher than 0V.

[0043] The memory device may float unselected sub-wordline decoders connected to one or more unselected wordlines (S30). The sub-wordline decoders may be connected to a power line providing a power supply voltage via a predetermined power switch. The unselected sub-wordline decoders may be floated by disconnecting the power switch between the unselected sub-wordline decoders and the power line in the memory device.

[0044] In operation S30, the unselected word lines may be floated. Since a power line transmitting a power supply voltage is connected to the unselected word lines through the unselected sub word line decoders, the unselected word lines may be floated by separating the unselected sub word line decoders and the power line from each other.

[0045] When a bridge failure exists between the selected word line and the unselected word line and / or in the unselected sub word line decoder, the voltage on the unselected word line can increase through the first driving signal input to the selected word line, the word line control signal input to the unselected sub word line decoder, etc. Accordingly, the data of the memory cell connected to the unselected word line can be unintentionally changed.

[0046] The memory device can detect the data of the memory cell connected to the unselected word line (S40). As an example, the memory device can detect the data of the memory cell during the time when the word line determined as the unselected word line in S20 and S30 is determined as the selected word line.

[0047] The memory device can determine whether the data detected in step S40 is changed (S50). When the determination result in step S50 is that the data is changed, it can be determined that a failure exists in the word line connected to the memory cell in which the data is changed and / or a failure exists in the sub word line decoder connected to the corresponding word line (S60). In contrast, when the determination result in step S50 is that the data is not changed, it can be determined that no failure exists in the word line connected to the memory cell in which the data is not changed and / or no failure exists in the sub word line decoder connected to the corresponding word line (S70). In some example embodiments, when it is determined that a failure exists in the word line and / or the sub word line decoder, the memory device can perform a repair operation to replace the word line with a redundant word line.

[0048] Figure 5 An operation of a memory device according to some example embodiments is illustrated.

[0049] Referring to Figure 5 The memory device 200 according to some example embodiments can include a first sub word line decoder 210 connected to a first word line WL1, a second sub word line decoder 220 connected to a second word line WL2, a first sense amplifier SA1 connected to a first bit line BL1, and a second sense amplifier SA2 connected to a second bit line BL2. Memory cells MC1 to MC4 can be connected to the word lines WL1 and WL2 and the bit lines BL1 and BL2.

[0050] The first sub word line decoder 210 and the second sub word line decoder 220 can have the same structure, and can be referred to with reference to the description of the first sub word line decoder 210. Figure 3The first sub word line decoder 210 can be activated or deactivated by a first word line control signal NWEIB1, and the second sub word line decoder 220 can be activated or deactivated by a second word line control signal NWEIB2. As an example, when one of the first sub word line decoder 210 and the second sub word line decoder 220 is activated, the other one of the first sub word line decoder 210 and the second sub word line decoder 220 can be deactivated and / or can not be activated.

[0051] In some example embodiments, as shown in FIG. 2, the memory device 200 further includes a power line 205 for supplying a power supply voltage VBB2 to the first sub word line decoder 210 and the second sub word line decoder 220. A first power switch PW1 can be connected between the first sub word line decoder 210 and the power line 205, and a second power switch PW2 can be connected between the second sub word line decoder 220 and the power line 205. The first power switch PW1 can be controlled by a first power control signal CTR1, and the second power switch PW2 can be controlled by a second power control signal CTR2. Figure 5

[0052] In the following, a test operation for detecting a fault that can exist in the memory device 200 will be described with reference to FIG. 3. Figure 5

[0053] When the word lines WL1 and WL2 are not selected, the first sub word line decoder 210 and the second sub word line decoder 220 are not activated, and / or can be deactivated by the first word line control signal NWEIB1 and the second word line control signal NWEIB2. In addition, both the first power switch PW1 and the second power switch PW2 can be on. The first sub word line decoder 210 can input the power supply voltage VBB2 to the first word line WL1 using the first word line control signal NWEIB1, and the second sub word line decoder 220 can input the power supply voltage VBB2 to the second word line WL2 using the second word line control signal NWEIB2.

[0054] When the first word line WL1 is determined to be the selected word line, the first sub word line decoder 210 can input the first drive signal PXID1 to the first word line WL1 using the first word line control signal NWEIB1. In some example embodiments, in the first sub word line decoder 210, the first switch element PM1 can be on, and the second switch element NM1 and the third switch element NM2 can be off.

[0055] ​​In some example embodiments, the levels of the first drive signal PXID1 and the second drive signal PXIB1 may be greater than or equal to the level of the first voltage and less than or equal to the level of the second voltage, and the second voltage may be greater than the first voltage. When the first word line WL1 is selected, the level of the first drive signal PXID1 input to the first sub-word line decoder 210 may be set to the level of the second voltage. Simultaneously, the level of the second drive signal PXIB1 may be set to the level of the first voltage to turn off the third switching element NM2. In addition, the first power switch PW1 connected to the first sub-word line decoder 210 may remain in the on state. However, according to some example embodiments, the first power switch PW1 may be turned off.

[0056] When the first word line WL1 is determined as the selected word line, the second word line WL2 may be determined as the unselected word line. Therefore, the second sub word line decoder 220 may be kept in the deactivated state by the second word line control signal NWIEB2, and in the second sub word line decoder 220, the first switching element PM1 may be turned off, while the second switching element NM1 and the third switching element NM2 may be turned on.

[0057] In some example embodiments, when the first word line WL1 is determined as a selected word line and the second word line WL2 is determined as an unselected word line, the second power switch PW2 connected between the second sub-word line decoder 220 and the power line 205 may be turned off. Thus, the power supply voltage VBB2 may not be continuously supplied to the second word line WL2, and the second word line WL2 may be floated. In addition, a portion of the node included in the second sub-word line decoder 220 (e.g., the input terminal of the first switching element NM1 and the second switching element NM2) may be floated.

[0058] As an example, when there is no fault between the word lines WL1 and WL2 and in the second sub-word line decoder 220, the voltage on the second word line WL2 may be maintained at the level of the power supply voltage VBB2, which may be input to the second word line WL2 before the first word line WL1 is selected. Meanwhile, when there is a fault between the word lines WL1 and WL2 and / or in the second sub-word line decoder 220, the voltage on the second word line WL2 does not remain at the level of the power supply voltage VBB2 and may change.

[0059] When the voltage of the second word line WL2 changes in a state where the second word line WL2 is an unselected word line, data of the memory cells MC3 and MC4 connected to the second word line WL2 may change. In some example embodiments, the second word line WL2 may be selected and the data changes of the memory cells MC3 and MC4 connected to the second word line WL2 may be detected to determine whether there is a fault between the word lines WL1 and WL2 and / or in the second sub-word line decoder 220.

[0060] According to some example embodiments, the turn-off time of the second power switch PW2 may vary. For example, while the first word line WL1 is selected and the first drive signal PXID1 is input to the first word line WL1, the second power switch PW2 may remain in an off state. Alternatively, the second power switch PW2 may be turned off after a predetermined delay time has passed since the first drive signal PXID1 was input to the first word line WL1.

[0061] Figure 6 The operation of the memory device according to the example embodiment is shown. Figure 6 as well as Figure 5 The operation of the memory device 200 will be described.

[0062] Reference Figure 6 During a first time period before the first time point T1, both the first word line control signal NWEIB1 and the second word line control signal NWEIB2 may be set to a high level H, and the first power supply signal CTR1 and the second power supply signal CTR2 may also be set to a high level H. Therefore, in the first sub word line decoder 210, the first switching element PM1 may be turned off, while the second switching element NM1 and the third switching element NM2 may be turned on, and the power supply voltage VBB2 may be input to the first word line WL1. Since the second sub word line decoder 220 operates similarly to the first sub word line decoder 210, the power supply voltage VBB2 may be input to the second word line WL2.

[0063] In some example embodiments, Figure 6 As shown in , during the second time period between the first time point T1 and the second time point T2, the first word line WL1 can be operated as a selected word line, and the second word line WL2 can be operated as an unselected word line. In the first sub-word line decoder 210, the first word line control signal NWEIB1 can be turned into a low level L, the level of the first drive signal PXID1 can be increased from the level of the first voltage VSS to the level of the second voltage VPP, and the level of the second drive signal PXIB1 can be reduced from the level of the second voltage VPP to the level of the first voltage VSS. Figure 6, the first power switch PW1 is shown to be maintained in the on state. However, according to some example embodiments, the first power switch PW1 may be switched to an off state.

[0064] After time T1, the second power switch PW2 can be turned off, and the second sub-wordline decoder 220 can be separated from the power line 205. Thus, the second sub-wordline decoder 220 and the second wordline WL2 can be floated. When a bridge fault exists between the first wordline WL1 and the second wordline WL2 and / or in the second sub-wordline decoder 220, the voltage on the second wordline WL2 increases from the power supply voltage VBB2 via at least one of the voltage on the first wordline WL, the second wordline control signal NWEIB2, and the second drive signal PXIB2. As the voltage on the second wordline WL increases, the data of the memory cells MC3 and MC4 connected to the second wordline changes.

[0065] After the second time point T2, the voltages on the word lines WL1 and WL2 may be restored. After the third time point T3, the second word line WL2 may be determined as the selected word line. When the second word line WL2 is determined as the selected word line, in the second sub-word line decoder 220, the level of the second word line control signal NWEIB2 may be set to a low level L, and the level of the first drive signal PXID2 may be increased from the level of the first voltage VSS to the level of the second voltage VPP, and the level of the second drive signal PXIB2 may be decreased from the level of the second voltage VPP to the level of the first voltage VSS.

[0066] After the third time point T3, the memory device may control the sense amplifiers SA1 and SA2 to read data of the memory cells MC3 and MC4 connected to the second word line WL2. When it is determined that the data read from the memory cells MC3 and MC4 are unintentionally changed, the memory device may determine that there is a bridge failure between the word lines WL1 and WL2 and / or in the second sub-word line decoder 220. In some example embodiments, the memory device may perform a repair operation to replace the second word line WL2 with one of the redundant word lines.

[0067] In some example embodiments, Figure 6 As shown in FIG, it is assumed that the time point when the first drive signal PXID1 is input to the first word line WL1 and the time point when the second word line WL2 is floated are the same as the first time point T1. However, the present disclosure is not necessarily limited thereto. For example, the time point when the second word line WL2 is floated may be before the time point when the first drive signal PXID1 is input to the first word line WL1 or may be after the time point when the first drive signal PXID1 is input to the first word line WL1 by a predetermined delay time DT.

[0068] Figures 7 to 12 The operation of the memory device according to some example embodiments is shown. Figures 7 to 12 as well as Figure 5 To describe the operation of the memory device.

[0069] Figure 7 and Figure 8 is a graph showing a voltage change occurring on the second word line WL2 depending on whether a fault exists between the first word line WL1 and the second word line WL2. Figure 7 and Figure 8 In the example embodiment shown in , the first word line WL1 may be a selected word line, and the second word line WL2 may be an unselected word line.

[0070] The voltages on the first and second word lines WL1 and WL2 may be initially set to a power supply voltage VBB2. The first sub-word line decoder 210 may supply a second voltage VPP to the first (selected) word line WL1. In some example embodiments, the second (unselected) word line WL2 may be floated.

[0071] like Figure 7 As shown in , when there is no bridge failure or the like between the first word line WL1 and the second word line WL2, the level of the second word line WL2 can be maintained at the level of the power supply voltage VBB2. Figure 8 As shown in FIG, when a bridge fault occurs between a first word line WL1 and a second word line WL2, the level of the floating second word line WL2 is increased by a second voltage VPP input to the first word line WL1. When the level of the floating second word line WL2 increases, the data of the memory cells MC3 and MC4 connected to the second word line WL2 changes. The memory device can detect the change in the data of the memory cells MC3 and MC4 to determine the bridge fault.

[0072] Figures 9 to 12 is a graph showing a change in voltage on the second word line WL2 , which is an unselected word line, according to whether a malfunction occurs in the second sub-word line decoder 220 connected to the second word line WL2 .

[0073] First refer to Figure 9 and Figure 10As described above, the voltage of word lines WL1 and WL2 can be initially set to the power supply voltage VBB2. The second word line control signal NWEIB2 input to the second sub-word line decoder 220 is maintained at a high level H, so that in the second sub-word line decoder 220, the first switching element PM1 can be turned off and the second switching element NM1 and the third switching element NM2 can be turned on. At a time point between the first time point T1 and the second time point T2, the second power switch PW2 can be turned off by the second control signal CTR2, and the power supply voltage can be prevented from being input to the second word line WL2.

[0074] Figure 9 It may be the case that there is no failure in the second sub-word line decoder 220. In this case, the level of the second word line WL2 may be maintained at the level of the power supply voltage VBB2. On the other hand, Figure 10 It may be the case that there is a fault in the second sub-wordline decoder 220. As an example, Figure 10 This may correspond to an example embodiment in which a bridge fault exists in the second sub-wordline decoder 220. For example, the node between the first switching element PM1 and the second switching element NM1 may be electrically connected to the node receiving the second wordline control signal NWEIB2. Therefore, the level of the second wordline WL2 may be increased by the second wordline control signal NWEIB2 having a high level H.

[0075] As an example, after the second time point T2, as the second power switch PW2 turns on, the level of the second word line WL2 decreases again to the level of the power supply voltage VBB2. However, the change in the level of the second word line WL2 that occurs between the first time point T1 and the second time point T2 may affect the data of the memory cells MC3 and MC4. The memory device can detect the change in the data of the memory cells MC3 and MC4 connected to the second word line WL2 to determine a failure.

[0076] Reference Figure 11 and Figure 12 As described above, the voltage on word lines WL1 and WL2 can be initially set to the power supply voltage VBB2. In the second sub-word line decoder 220, the second drive signal PXIB2 input to the third switching element NM2 can be maintained at a high level H. Therefore, the third switching element NM2 can be turned on to input the power supply voltage VBB2 to the second word line WL2. When the second power switch PW2 is turned off at the first time point T1 by the second control signal CTR2, the power supply voltage VBB2 can be prevented from being input to the second word line WL2, regardless of whether the third switching element NM2 is turned on.

[0077] Figure 11It may be the case that there is no failure in the second sub-word line decoder 220. In this case, the level of the second word line WL2 can be maintained at the level of the power supply voltage VBB2 even after the first time point T1. In contrast, Figure 12 It may be the case that there is a fault in the second sub-wordline decoder 220. As an example, Figure 12 This corresponds to an example embodiment in which a bridge fault occurs between the control terminal and the output terminal of the third switching element NM2. The second drive signal PXIB2 may be input to the control terminal of the third switching element NM2, and the second word line WL2 may be connected to the output terminal of the third switching element NM2. Therefore, when a bridge fault occurs, the level of the second word line WL2 is increased by the second drive signal PXIB2 having a high level H.

[0078] Figures 13 to 15 is a schematic circuit diagram of a memory device according to some example embodiments.

[0079] First refer to Figure 13 , the memory device 300 according to some example embodiments may include sub-word line decoders 311 to 313 and 321 to 323 connected to the word lines WL0 to WL5. The word lines WL0 to WL5 and the sub-word line decoders 311 to 313 and 321 to 323 may vary in number.

[0080] The word lines WL0 to WL5 may include odd word lines WL1, WL3, and WL5 and even word lines WL0, WL2, and WL4. Sub-word line decoders 311 to 313 and 321 to 323 may include odd sub-word line decoders 311 to 313 and even sub-word line decoders 321 to 323. Each of the sub-word line decoders 311 to 313 and 321 to 323 may be connected to a power line 305 for supplying a predetermined power supply voltage. The power supply voltage may be a negative constant voltage lower than 0V.

[0081] In some example embodiments, Figure 13 As shown in FIG, power switches PW0 to PW5 connecting the sub-word line decoders 311 to 313 and 321 to 323 to the power line 305 may be included in the sub-word line decoders 311 to 313 and 321 to 323, respectively. As an example, when the first even-numbered sub-word line decoder 321 is activated to input the first driving signal PXID0 to the first even-numbered word line WL0, the power switches PW1 to PW5 included in the other sub-word line decoders 311 to 313 and 322 to 323 may be turned off to float the other word lines WL1 to WL5.

[0082] However, the above is merely an example, and only a portion of the power switches PW0 to PW5 included in the sub word line decoders 311 to 313 and 321 to 323 can be turned off. As an example, among the power switches PW0 to PW5, the power switch to be turned off can vary according to the unselected word line adjacent to the selected word line. For example, the even word lines WL0, WL2, WL4 and the odd word lines WL1, WL3, and WL5 can be alternately arranged. When the first even word line WL0 is selected, only the first power switch PW1 connected to the first odd word line WL1 adjacent to the first even word line WL0 can be selectively turned off.

[0083] Referring to Figure 14 The memory device 400 according to some example embodiments can include sub word line decoders 411 to 413 and 421 to 423 connected to the word lines WL0 to WL5. The word lines WL0 to WL5 can include odd word lines WL1, WL3, and WL5 and even word lines WL0, WL2, and WL4, and the sub word line decoders 411 to 413 and 421 to 423 can include odd sub word line decoders 411 to 413 and even sub word line decoders 421 to 423.

[0084] Each of the sub word line decoders 411 to 413 and 421 to 423 can be connected to a power line 405 for supplying a predetermined power supply voltage. In some example embodiments, as shown in Figure 14 The first power switch PW1 can be commonly connected to the odd sub word line decoders 411 to 413, and the second power switch PW2 can be commonly connected to the even sub word line decoders 421 to 423.

[0085] As an example, when the first odd sub word line decoder 411 is activated, the first power switch PW1 can be maintained in an on state, and the second power switch PW2 can be turned off. Accordingly, the even word lines WL0, WL2, and WL4 can be separated from the power line 405 to be floated, and a bridge fault between the first odd word line WL1 and the other even word lines WL0, WL2, and WL4 adjacent to the first odd word line WL1 can be determined. In addition, a fault of each of the even sub word line decoders 421 to 423 can also be determined.

[0086] According to some example embodiments, the first power switch PW1 can also be turned off while the first odd sub word line decoder 411 is activated. As the first power switch PW1 is turned off, a fault of the other odd sub word line decoders 412 to 413 that are not activated can be determined.

[0087] In some example embodiments, as shown in Figure 14As shown in FIG, since a plurality of sub-word line decoders 411 to 413 and 421 to 423 are connected to the power switches PW1 and PW2, respectively, Figure 13 Compared with the example shown in , the number of power switches PW1 and PW2 can be reduced. Figure 14 In the example shown in , power switches PW1 and PW2 may be provided in a connection circuit that outputs drive signals PXID0 to PXID5 and PXIB0 to PXIB5 .

[0088] Reference Figure 15 , the memory device 500 according to some example embodiments may include sub-word line decoders 511 to 513 and 521 to 523 connected to word lines WL0 to WL5. The word lines WL0 to WL5 may include odd word lines WL1, WL3, and WL5 and even word lines WL0, WL2, and WL4, and the sub-word line decoders 511 to 513 and 521 to 523 may include odd sub-word line decoders 511 to 513 and even sub-word line decoders 521 to 523.

[0089] Each of the sub word line decoders 511 to 513 and 521 to 523 may be connected to a power line 505 for supplying a predetermined power supply voltage. Figure 15 In the example shown in , a single power switch PW may be connected between the sub-word line decoders 511 to 513 and 521 to 523 and the power line 505. For example, the power switch PW may be provided in a row decoder of the memory device 500.

[0090] As an example, when the second odd sub-wordline decoder 512 is activated, the power switch PW may be turned off. The first drive signal PXID3 may be input to the second odd wordline WL3 by the second odd sub-wordline decoder 512. The other sub-wordline decoders 511, 513, and 521 to 523 may all be separated from the power line 405 and the other wordlines WL0 to WL2, WL4, and WL5. Therefore, a bridge failure between the second odd wordline WL3 and the other wordlines WL0 to WL2, WL4 to WL5, and / or a failure of each of the deactivated sub-wordline decoders 511, 513, and 521 to 523 may be determined.

[0091] Figure 16 A manufacturing process of a memory device according to some example embodiments is illustrated.

[0092] Reference Figure 16 , a plurality of semiconductor dies may be produced by applying a semiconductor process to the wafer W, and the wafer W may be manufactured. In some example embodiments, the plurality of semiconductor dies included in the wafer W may be manufactured according to the reference Figures 1 to 15The memory device of the example embodiment described above. When a wafer W is manufactured, a first test 601 may be performed to select one word line among the word lines included in the memory device and float the unselected word lines. For example, the first test 601 may be performed at the wafer level, and a word line determined to be faulty by the first test 601 may be replaced with a redundant word line.

[0093] Upon completion of the first test 601, a dicing process 602 and a packaging process 603 may be performed to separate the semiconductor dies. Upon completion of the packaging process 603, a second test 604 may be performed. The second test 604 may be performed at the package level and may include operations similar to those of the first test 601. For example, in the second test 604, data changes may be determined by: selecting a selected word line and unselected word lines among the word lines; floating the unselected word lines while inputting a drive signal to the selected word line; and reading data from memory cells connected to the unselected word lines. When data changes are detected in memory cells connected to the unselected word lines, it may be determined that a fault exists in the sub-word line decoder and / or the unselected word lines connected to the unselected word lines, and a repair operation may be performed.

[0094] According to some example embodiments, one of the first test 601 and the second test 604 may be omitted. For example, the test operation according to the example embodiments may be performed at only one of the wafer level and the package level. Alternatively, the test operation according to the example embodiments may be performed while the memory device is installed in an electronic device after shipping and the memory device is operated. As an example, the memory device may perform the test operation according to the example embodiment for each predetermined period while operating in combination with the electronic device, and may perform a repair operation when a failure is determined to have occurred.

[0095] Figure 17 is a schematic block diagram of a mobile system including a memory device according to some example embodiments.

[0096] Reference Figure 17 , the mobile system 1000 may include a camera 1100, a display 1200, an audio processor 1300, a modem 1400, DRAMs 1500a and 1500b, flash memory devices 1600a and 1600b, input / output (I / O) devices 1700a and 1700b, and an application processor (hereinafter, referred to as “AP”) 1800.

[0097] The mobile system 1000 may be implemented as a laptop computer, a portable terminal, a smart phone, a tablet personal computer (tablet PC), a wearable device, a healthcare device, or an Internet of Things (IoT) device. In addition, the mobile system 1000 may be implemented as a server or a PC.

[0098] Camera 1100 can capture still images or videos under user control. Mobile system 1000 can use the still images / videos captured by camera 1100 to obtain specific information, or can convert and store the still images / videos into other types of data, such as text. Optionally, mobile system 1000 can recognize strings included in the still images / videos captured by camera 1100 and can provide text or audio translations corresponding to the strings. As described above, camera 1100 in mobile system 1000 can be used in various application areas. In some example embodiments, camera 1100 can transmit data, such as still images / videos, to AP 1800 according to the D-PHY or C-PHY interface in the MIPI standard.

[0099] The display 1200 may be implemented in various forms, such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display, an active matrix organic light emitting diode (AMOLED) display, a plasma display panel (PDP), a field emission display (FED), electronic paper, etc. In some example embodiments, the display 1200 may provide a touch screen function, thereby also serving as an input device for the mobile system 1000. In addition, the display 1200 may be integrated with a fingerprint sensor, etc., to provide a security function for the mobile system 1000. In some example embodiments, the AP 1800 may transmit image data to the display 1200 to be displayed on the display 1200 according to the D-PHY or C-PHY interface in the MIPI standard.

[0100] The audio processor 1300 may process audio data stored in the flash memory devices 1600a and 1600b or audio data included in content received from the outside through the modem 1400 or the I / O devices 1700a and 1700b. For example, the audio processor 1300 may perform various processes such as encoding / decoding, amplification, and noise filtering on the audio data.

[0101] The modem 1400 can modulate a signal and transmit the modulated signal to transmit and receive wired / wireless data, and can demodulate a signal received from the outside to restore the original signal. The I / O devices 1700a and 1700b can provide digital input and output, and can include input devices such as ports that can be connected to external recording media, touch screens or mechanical buttons (keys), and output devices that can output vibrations in a tactile manner. In some examples, the I / O devices 1700a and 1700b can be connected to external recording media via ports such as USB, lightning cables (lightning data cables), SD cards, micro SD cards, DVDs, network adapters, etc.

[0102] The AP 1800 may control the overall operation of the mobile system 1000. Specifically, the AP 1800 may control the display 1200 to display a portion of the content stored in the flash memory devices 1600a and 1600b on the screen. When a user input is received through the I / O devices 1700a and 1700b, the AP 1800 may perform a control operation corresponding to the user input.

[0103] The AP 1800 may be provided as a system on chip (SoC) that drives an application program, an operating system (OS), or the like. Furthermore, the AP 1800 may be included in a single semiconductor package along with other devices included in the mobile system 1000 (e.g., the DRAM 1500a, the flash memory 1620, and / or the memory controller 1610). For example, the AP 1800 and at least one device may be provided in a package form (such as a package on package (PoP), a ball grid array (BGA), a chip scale package (CSP), a system in package (SIP), a multi-chip package (MCP), a wafer-level fabrication package (WFP), or a wafer in a package form such as a process-level stacked package (WSP)). The kernel of the operating system driven on the AP 1800 may include an input / output scheduler and a device driver for controlling the flash memory devices 1600a and 1600b. The device driver may control access performance of the flash memory devices 1600a and 1600b with reference to the number of synchronization queues managed by the input / output scheduler, or may control a CPU mode, a dynamic voltage and frequency scaling (DVFS) level, etc. inside the SoC.

[0104] In some example embodiments, the AP 1800 may include a processor block that executes operations or drives an application program and / or an operating system, and various other peripheral components connected via a system block and a system bus. The peripheral components may include a memory controller, internal memory, a power management block, an error detection block, a monitoring block, and the like. The processor block may include one or more cores. When a processor block includes multiple cores, each core includes a cache memory, and a common cache shared by the cores may be included in the processor block.

[0105] In some embodiments, the AP 1800 may include an accelerator block 1820, a dedicated circuit for AI data operations. Alternatively, according to some example embodiments, a separate accelerator chip may be provided separate from the AP 1800, and the DRAM 1500b may be additionally connected to the accelerator block 1820 or the accelerator chip. The accelerator block 1820 may be a functional block dedicated to performing a specific function of the AP 1800, and may include a graphics processing unit (GPU) serving as a functional block dedicated to processing graphics data, a neural processing unit (NPU) serving as a functional block dedicated to performing AI calculations and interference, a data processing unit (DPU) serving as a functional block dedicated to transmitting data, and the like.

[0106] According to an example embodiment, the mobile system 1000 may include a plurality of DRAMs 1500a and 1500b. In an example embodiment, the AP 1800 may include a controller 1810 for controlling the DRAMs 1500a and 1500b, and the DRAM 1500a may be directly connected to the AP 1800.

[0107] The AP 1800 may set commands and mode register set (MRS) commands to control the DRAM according to the JEDEC standard, or may set the specifications and functions (such as low voltage, high speed, and reliability) required by the mobile system 1000, as well as an interface protocol for the DRAM used for CRC / ECC communication. For example, the AP 1800 may set a new DRAM interface protocol to control the DRAM 1500b for accelerator communication, where the accelerator chip or accelerator block 1820 provided independently of the AP 1800 has a higher bandwidth than the DRAM 1500a.

[0108] Figure 17Only DRAMs 1500a and 1500b are shown, but the configuration of mobile system 1000 is not necessarily limited thereto. Depending on the bandwidth and response speed of AP 1800 and accelerator block 1820, as well as voltage conditions, memories other than DRAMs 1500a and 1500b may be included in mobile system 1000. For example, controller 1810 and / or accelerator block 1820 may control various memories such as PRAM, SRAM, MRAM, RRAM, FRAM, hybrid RAM, etc. DRAMs 1500a and 1500b have relatively low latency and relatively high bandwidth compared to input / output devices 1700a and 1700b or flash memory devices 1600a and 1600b. DRAMs 1500a and 1500b may be initialized at power-on of mobile system 1000. When an operating system and application data are loaded, the DRAMs 1500a and 1500b may be used as a location to temporarily store the operating system and application data, or as a space to execute various software codes.

[0109] The four basic arithmetic operations such as addition, subtraction, multiplication and division, as well as vector operations, address operations or FFT operation data can be stored in DRAM 1500a and 1500b. In some example embodiments, DRAM 1500a and 1500b can be provided as in-memory processing (PIM) with operation functions. For example, a function for performing inference in DRAM 1500a and 1500b can be executed. In this case, an artificial neural network can be used to perform inference in a deep learning algorithm. The deep learning algorithm may include a training step of learning a model through various data and an inference step of identifying data using the trained model. For example, the function used in the inference may include a hyperbolic tangent function, a sigmoid function, a rectified linear unit (ReLU) function, etc.

[0110] exist Figure 17 In the example shown in FIG, each of DRAMs 1500a and 1500b may be based on the reference Figures 1 to 16 Before and / or after the DRAMs 1500a and 1500b are mounted on the mobile system 1000, they may perform a test operation to determine bridge failures in word lines and / or sub-word line decoders connected to the word lines.

[0111] As an example, the DRAMs 1500a and 1500b can float unselected word lines while inputting a predetermined driving signal to a selected word line. When there is a failure in an unselected word line and / or an unselected sub word line decoder connected to the unselected word line, a voltage on the unselected word line can change, and data of a memory cell connected to the unselected word line can also change. The memory device can detect a change in the data of the memory cell connected to the unselected word line to determine whether there is a failure and can perform a repair operation.

[0112] As an example, an image captured by the user through the camera 1100 can be signal-processed and stored in the DRAM 1500b, and the accelerator block 1820 or the accelerator chip can perform an AI data operation using data stored in the DRAM 1500b and a function used in an inference, thereby recognizing the data.

[0113] According to some example embodiments, the mobile system 1000 can include a plurality of memories or a plurality of flash memory devices 1600a and 1600b having a capacity higher than that of the DRAMs 1500a and 1500b. The flash memory devices 1600a and 1600b can include a controller 1610 and a flash memory 1620. The controller 1610 can receive a control command and data from the AP 1800, and can write data to the flash memory 1620 in response to the control command, or can read data stored in the flash memory 1620 and transmit the read data to the AP 1800.

[0114] According to some example embodiments, the accelerator block 1820 or the accelerator chip can use the flash memory devices 1600a and 1600b to perform a training step and an AI data operation. In some example embodiments, operation logic capable of performing a predetermined operation in the flash memory devices 1600a and 1600b can be implemented in the controller 1610. Instead of the AP 1800 and / or the accelerator block 1820, the operation logic can use data stored in the flash memory 1620 to perform at least a part of a training step and an inference performed by the AP 1800 and / or the accelerator block 1820.

[0115] In some example embodiments, the AP 1800 can include an interface 1830. Accordingly, the flash memory devices 1600a and 1600b can be directly connected to the AP 1800. For example, the AP 1800 can be implemented as an SoC, the flash memory device 1600a can be implemented as a chip independent of the AP 1800, and the AP 1800 and the flash memory device 1600a can be mounted in a single package. However, example embodiments are not limited thereto, and a plurality of flash memory devices 1600a and 1600b can be electrically connected to the mobile system 1000 through a connection.

[0116] The flash memory devices 1600a and 1600b may store data such as still images / videos captured by the camera 1100 and / or data received via a communication network and / or ports included in the input and output devices 1700a and 1700b. For example, the flash memory devices 1600a and 1600b may store augmented reality / virtual reality, high definition (HD), or ultra high definition (UHD) content.

[0117] As described above, a failure in a memory device can be determined by separating a sub-wordline decoder connected to an unselected wordline from a power supply voltage to float and detecting data of an unselected memory cell connected to the unselected wordline. According to example embodiments, potential failures in a memory device can be determined in advance to improve the quality of the memory device.

[0118] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept as defined by the appended claims.

Claims

1. A memory device, comprising: a memory cell array comprising a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; a word line driving circuit comprising a plurality of sub-word line decoders respectively connected to the plurality of word lines, wherein each sub-word line decoder is configured to input a first driving signal to the word line when the respectively connected word line is selected, and wherein each sub-word line decoder is configured to input a predetermined power supply voltage to the word line when the respectively connected word line is not selected; a sense amplifier circuit comprising sense amplifiers connected to the plurality of bit lines; and a logic circuit configured to determine a failure of at least one of the memory cell array and the word line driving circuit by floating unselected sub word line decoders while inputting a first driving signal to a selected word line and detecting data of memory cells connected to the unselected word line using at least one of the sense amplifiers, wherein the first driving signal has a level greater than or equal to the level of the first voltage and less than or equal to the level of the second voltage, wherein the level of the second voltage is higher than the level of the first voltage, and The first driving signal input to the selected word line has the same level as the second voltage.

2. The memory device according to claim 1, wherein The fault is a bridge fault between a selected word line and a first unselected word line, and wherein the logic circuit determines the bridge fault by detecting data of a first unselected memory cell connected to the first unselected word line adjacent to the selected word line.

3. The memory device according to claim 1, wherein Each of the plurality of sub-wordline decoders includes: a first switching element configured to receive a first driving signal; and a second switching element and a third switching element each configured to receive a power supply voltage, and The first switching element and the second switching element are commonly controlled by a word line control signal, and the third switching element is controlled by a second driving signal different from the first driving signal.

4. The memory device according to claim 3, wherein The logic circuit is configured to float the second and third switching elements of unselected sub word line decoders while inputting the first drive signal to the selected word line by blocking the second and third switching elements from the power supply voltage.

5. The memory device according to claim 4, wherein The logic circuit is configured to determine that a bridge failure occurs in at least one of the first to third switching elements when a data change is detected in at least one of the memory cells connected to an unselected word line. The memory device according to claim 1 , wherein: The power supply voltage is a negative constant voltage.

7. The memory device according to claim 1, wherein The second voltage is greater than the power supply voltage.

8. A memory device, comprising: a memory cell array comprising a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; a word line driving circuit comprising sub word line decoders connected to the plurality of word lines, wherein each of the sub word line decoders is connected to a power line and configured to output a predetermined power supply voltage through a power switch; and a logic circuit configured to control the power switch, wherein the sub-wordline decoder is configured to be connected to the power line during a first time and input a power supply voltage to the plurality of wordlines, and wherein the selected sub-word line decoder connected to the selected word line is configured to input a driving voltage higher than a power supply voltage to the selected word line during a second time after the first time, and The unselected sub-word line decoders connected to the unselected word lines are configured to be separated from the power line to be floated during the second time.

9. The memory device according to claim 8, wherein Each of the sub-wordline decoders includes a power switch.

10. The memory device of claim 8, further comprising: a connection circuit configured to generate a power supply voltage and a driving signal input to a sub-word line decoder, Wherein, the power switch is included in the connecting circuit.

11. The memory device of claim 8, further comprising: A row decoder configured to control a word line driver circuit, The power switch is included in the row decoder.

12. The memory device according to claim 8, wherein The logic circuit is configured to turn on the power switch during a first time and to turn off the power switch during a second time.

13. The memory device according to claim 8, wherein The power switch includes a first power switch connected to the odd word line and a second power switch connected to the even word line, and The logic circuit is configured to turn on the first power switch and the second power switch during a first time, and is configured to turn on one of the first power switch and the second power switch and turn off the other of the first power switch and the second power switch during a second time.

14. The memory device according to claim 13, wherein: The logic circuit is configured to turn on the first power switch and turn off the second power switch when a selected word line is determined among odd word lines, and The logic circuit is configured to turn off the first power switch and turn on the second power switch when a selected word line is determined among the even word lines.

15. The memory device according to claim 8, wherein Each of the sub-wordline decoders includes a power switch, and The logic circuit is configured to turn on a power switch included in each of the sub-word line decoders during a first time, and to turn off a power switch included in each of the unselected sub-word line decoders during a second time.

16. A memory device, comprising: a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines; a connecting circuit configured to generate a driving signal to drive the plurality of memory cells; a sub-wordline decoder connected between the connection circuit and the plurality of wordlines and configured to determine a selected wordline and unselected wordlines from the plurality of wordlines; as well as a logic circuit configured to control the sub wordline decoder so that a power supply voltage is input to the plurality of word lines during a first time, and configured to control the sub wordline decoder so that a driving voltage higher than the power supply voltage is input to the selected word line and unselected word lines are floated during a second time after the first time, The unselected sub-word line decoders connected to the unselected word lines are configured to be separated from the power line to be floated during the second time.

17. The memory device of claim 16, further comprising: a sense amplifier circuit including sense amplifiers connected to the plurality of bit lines and configured to read data from the plurality of memory cells, The logic circuit is configured to detect a failure of at least one of the plurality of word lines and the sub-word line decoder based on data read from the memory cell by the sense amplifier circuit after a second time.

18. The memory device of claim 16, further comprising: The power switch is connected between the sub-word line decoder and the power line and is configured to supply and cut off the power supply voltage in response to the control of the logic circuit.

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