Semiconductor device manufacturing method

Abstract

This invention discloses a semiconductor device and a method for manufacturing the semiconductor device, specifically for forming source / drain contact plugs for adjacent fin field-effect transistors (FFETs). The source / drain regions of the adjacent fin field-effect transistors are embedded in an interlayer dielectric and separated by an isolation region isolating the cut-metal gate (CMG) structure of the gate electrode of the adjacent fin field-effect transistor. The method includes recessing the isolation region; and forming a contact plug opening through the interlayer dielectric to expose a portion of a contact etch stop layer disposed above the source / drain regions, wherein the contact etch stop layer is made of a different material than the isolation region. Once exposed, a portion of the contact etch stop layer is removed, and a conductive material is formed in the contact plug opening. The conductive material contacts the source / drain regions of the adjacent fin field-effect transistor and the isolation region.

Description

Technical Field

[0001] This invention relates to semiconductor devices, and more particularly to semiconductor devices for source / drain contact plugs for adjacent finFETs and methods of manufacturing the same. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate, and then using photolithography to pattern these material layers to form circuit components and elements on the semiconductor substrate.

[0003] The semiconductor technology field has continuously improved the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly reducing the size of the smallest feature, allowing more components to be integrated into a given area. However, as the size of the smallest feature shrinks, other problems arising from this need to be addressed. Summary of the Invention

[0004] One embodiment relates to a method. The method includes: etching an isolation region. The isolation region includes a first dielectric material and is embedded in a dielectric layer. An etch opening is formed in the dielectric layer, exposing a first portion of a contact etch stop layer and a second portion of the contact etch stop layer via the opening. The isolation region is disposed between the first and second portions of the contact etch stop layer. The first portion of the contact etch stop layer is removed, exposing a first source / drain region via the opening. The contact etch stop layer includes a second dielectric material. The second dielectric material is different from the first dielectric material. The second portion of the contact etch stop layer is removed, exposing a second source / drain region via the opening. A contact is formed in the opening connecting the first source / drain region and the second source / drain region.

[0005] Another embodiment relates to a method. The method includes: forming a cavity in an interlayer dielectric to expose an isolation structure, and exposing a second dielectric material via the cavity. The exposed second dielectric material is located on the exposed isolation structure within the cavity. The second dielectric material is different from the dielectric material of the isolation structure. After exposing the isolation structure, first and second portions of the second dielectric material are removed to expose a first source / drain region of a first FinFET and a second source / drain region of a second FinFET via the cavity. A conductive material is deposited in the cavity to form a plug connecting the first source / drain regions and the second source / drain regions.

[0006] Another embodiment relates to a semiconductor device. The semiconductor device includes an interlayer dielectric, a first source / drain region of a first device, a second source / drain region of a second device, an isolation region, and contacts. The interlayer dielectric includes a first dielectric material. The first source / drain region of the first device is embedded in the interlayer dielectric. The second source / drain region of the second device is embedded in the interlayer dielectric. The isolation region includes a second dielectric material embedded in the interlayer dielectric and is disposed between the first device and the second device. The contacts are connected to the first source / drain region via a first portion of a contact etch stop layer and to the second source / drain region via a second portion of the contact etch stop layer. The contact etch stop layer includes a third dielectric material different from the second dielectric material. Attached Figure Description

[0007] The best understanding of all aspects of this disclosure can be obtained from the following detailed description and the accompanying drawings. It should be noted that, in accordance with the general practice in this art, the various components are not necessarily drawn to scale. In fact, the dimensions of various components may be arbitrarily enlarged or reduced for clarity of illustration.

[0008] Figure 1 This is a three-dimensional view depicting an example of FinFET based on some embodiments.

[0009] Figures 2 to 7 8A, 8B, 9A, 9B, 10A to 10C, 11A to 11C, 12A, 12B, 13A, 13B, 14A to 14C, 15A to 15D, 16A to 16D, 17, 18, and 19A to 19C are cross-sectional views of intermediate stages in the manufacture of a FinFET according to some embodiments.

[0010] The annotations in the attached figures are explained as follows:

[0011] 50:Substrate

[0012] 50N, 50P: Area

[0013] 52: Fins

[0014] 54: Insulating materials

[0015] 56: Shallow trench isolation area

[0016] 58: Passage Area

[0017] 60: Dummy dielectric layer

[0018] 62: Dummy gate layer

[0019] 64,163: Mask layer

[0020] 72: Dummy gate

[0021] 74: Mask

[0022] 80: Gate sealing spacer

[0023] 82: Source / Drain Region

[0024] 86: Gate interstitial material

[0025] 87: Contact Etching Stop Layer

[0026] 88: First interlayer dielectric

[0027] 89: Area

[0028] 90: concave part

[0029] 92: Gate dielectric layer

[0030] 94, 106: Gate electrode

[0031] 94A: Liner

[0032] 94B: Work Function Adjustment Layer

[0033] 94C: Filler material

[0034] 95, 95A, 95B: Metal gate stacks

[0035] 96: Gate Mask

[0036] 108: Interlayer dielectric

[0037] 110: Gate contact

[0038] 112: Source / Drain Contact

[0039] 156: Cutting the metal gate opening

[0040] 160: Isolation layer

[0041] 162: Dielectric isolation region

[0042] 164: First Opening

[0043] 166: Second opening

[0044] 170: Contact guide hole opening

[0045] 182: Epitaxial growth

[0046] D1: First Depth

[0047] D2: Second Depth

[0048] D3: Third Depth

[0049] H1: First Height

[0050] H2: Second Altitude

[0051] H3: Third Height

[0052] H4: Fourth Height

[0053] H5: Fifth Height

[0054] L1: First Length

[0055] L2: Second Length

[0056] R1: First proportion

[0057] R2: Second proportion

[0058] W1: First width

[0059] W2: Second width

[0060] W3: Third width Detailed Implementation

[0061] The following disclosure provides numerous different embodiments or examples for implementing the various features of this disclosure. The following disclosure describes specific examples of components and arrangements to simplify the disclosure. Of course, these specific examples are merely illustrative and not intended to be limiting. For example, if the disclosure describes a first component formed over or on a second component, it may include embodiments where the first and second components are in direct contact, and may also include embodiments where other components are formed between the first and second components, so that the first and second components may not be in direct contact. Furthermore, the same reference numerals and / or designations may be repeated in different examples of this disclosure. These repetitions are for simplification and clarity and are not intended to limit any specific relationship between the different embodiments and / or configurations discussed.

[0062] Furthermore, spatial terms used herein, such as “beneath,” “below,” “lower,” “above,” “upper,” and similar terms, are used to facilitate the description of the relationship between one element or component and another element(s) in the accompanying drawings. In addition to the orientations shown in the drawings, these spatial terms are intended to cover different orientations of the device in use or operation. The device may be rotated to different orientations (90 degrees or other orientations), and the spatial terms used herein may be interpreted in the same way.

[0063] Figure 1 An example of a Fin Field-Effect Transistor (finFET) according to some embodiments is shown in a three-dimensional view. The FinFET includes fins 52 on a substrate 50 (e.g., a semiconductor substrate). Shallow Trench Isolation (STI) regions 56 are disposed in the substrate 50, and the fins 52 protrude from and above the adjacent STI regions 56. Although the STI regions 56 are described / shown as separated from the substrate 50, the term "substrate" as used herein can be used to refer only to a semiconductor substrate or a semiconductor substrate including the isolation regions. Additionally, although the fins 52 are described as being made of the same single continuous material as the substrate 50, the fins 52 and / or the substrate 50 may comprise a single material or multiple materials. In this case, the fins 52 refer to the portion extending between adjacent STI regions 56.

[0064] The gate dielectric layer 92 runs along the sidewall of the fin 52 and is above the top surface of the fin 52, and the gate electrode 94 is above the gate dielectric layer 92. The source / drain region 82 is disposed on the opposite side of the fin 52 relative to the gate dielectric layer 92 and the gate electrode 94. Figure 1 The reference cross-sectional views used in the following figures are further illustrated. Cross-section AA is along the longitudinal axis of the gate electrode 94 and, for example, perpendicular to the current direction between the source / drain regions 82 of the FinFET. Cross-section BB is perpendicular to cross-section AA, along the longitudinal axis of the fin 52, and, for example, between the source / drain regions 82 of the FinFET. Cross-section CC is parallel to cross-section AA and extends through the source / drain regions of the FinFET. For clarity, the following figures refer to these reference cross-sectional views.

[0065] Some embodiments discussed herein are presented in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate use in planar devices such as planar FETs.

[0066] Figures 2 to 19C This is a cross-sectional view of a FinFET fabrication process at an intermediate stage, according to some embodiments. In addition to multiple fins / FinFETs, Figures 2 to 7 Displayed Figure 1 The reference cross-section AA is shown in the image. In addition to multiple fins / FinFETs, Figure 8A , 9A 10A, 11A, 12A, 13A, 14A, 15A, 15C, 16A, 16C and 19A display along Figure 1 The reference section AA shown is... Figure 8B , 9B Models 10B, 11B, 12B, 13B, 14B, 14C, 15B, 16B, and 19B are displayed along... Figure 1 A similar reference cross-section BB is shown. In addition to multiple fins / FinFETs, Figure 10C , 11C 15D, 16D, 17, 18 and 19C display along Figure 1 The reference section CC is shown.

[0067] exist Figure 2In this embodiment, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or a similar substrate, and the substrate 50 may be doped (e.g., having p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a semiconductor material layer formed on an insulating layer. The aforementioned insulating layer may, for example, be a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is disposed on the substrate, which is typically a silicon substrate or a glass substrate. Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0068] The substrate 50 has regions 50N and 50P. Region 50N can be used to form n-type devices, such as n-type metal-oxide-semiconductor field-effect transistors (n-type MOS, NMOS), for example, n-type FinFETs. Region 50P can be used to form p-type devices, such as p-type metal-oxide-semiconductor field-effect transistors (p-type MOS, PMOS), for example, p-type FinFETs. However, it should be understood that regions 50N and 50P can be used to form any type of device (e.g., n-type devices, p-type devices, passive devices, active devices, combinations thereof, or similar devices). Furthermore, regions 50N and 50P can be adjacent to each other, or regions 50N and 50P can be physically separated from each other. In addition, any number of device components (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between regions 50N and 50P.

[0069] exist Figure 3 In this embodiment, fins 52 are formed in the substrate 50. Fins 52 are semiconductor strips. In some embodiments, fins 52 can be formed in the substrate 50 by etching trenches in the substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), similar processes, or combinations thereof. Etching can be anisotropic.

[0070] The fin 52 can be patterned by any suitable method. For example, one or more photolithography processes can be used to pattern the fin 52, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography with self-alignment processes to allow the production of patterns with, for example, a pitch smaller than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using photolithography. A spacer is formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacer can then be used to pattern the fin 52. In some embodiments, a mask (or other layer) may be retained on the fin 52.

[0071] exist Figure 4In this embodiment, insulating material 54 is formed above substrate 50 and between adjacent fins 52. Insulating material 54 can be an oxide, nitride, or a combination thereof, such as silicon oxide, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD) (for example, depositing CVD-based materials in a remote plasma system and performing post-curing to transform the CVD-based materials into another material such as oxide), similar processes, or combinations thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, insulating material 54 is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, insulating material 54 is formed such that excess material of insulating material 54 covers the fins 52. Although insulating material 54 is shown as a single layer, some embodiments may use multiple layers. For example, in some embodiments, an optional liner (not shown) may be formed first along the surface of the substrate 50 and the fins 52. A filler material, such as that described above, may then be formed over the optional liner.

[0072] exist Figure 5 In this process, a removal process is applied to the insulating material 54 to remove excess material from the insulating material 54 above the fin 52. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), etch-back, a combination thereof, or similar processes may be used. The planarization process exposes the fin 52 such that, after the planarization process is completed, the top surfaces of the fin 52 and the insulating material 54 are flush. In embodiments where the mask remains on the fin 52, the planarization process may expose or remove the mask such that, after the planarization process is completed, the mask or the fin 52 is flush with the top surface of the insulating material 54, respectively.

[0073] exist Figure 6In this process, the insulating material 54 is recessed to form shallow trench isolation (STI) regions 56. The insulating material 54 is recessed such that the upper portions of the fins 52 in regions 50N and 50P protrude between adjacent STI regions 56. Furthermore, the top surface of the STI region 56 can have a flat surface, a convex surface, a concave surface, or a combination thereof, as shown. The top surface of the STI region 56 can be formed as flat, convex, and / or concave by appropriate etching. Acceptable etching processes can be used to recess the STI region 56, such as processes that are selective for the material of the insulating material 54 (e.g., etching the material of the insulating material 54 at a faster rate than etching the material of the fins 52). For example, oxide removal can be used, and the aforementioned oxide removal can use, for example, diluted hydrofluoric acid (dHF).

[0074] about Figures 2 to 6 The described process is merely one example of how fin 52 can be formed. In some embodiments, fin 52 can be formed using an epitaxial growth process. For example, a dielectric layer can be formed above the top surface of substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Homoepitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form a fin. Additionally, in some embodiments, heteroepitaxial structures can be used for fin 52. For example, in... Figure 5 The fins 52 can be recessed, and a material different from the fins 52 can be epitaxially grown on the recessed fins 52. In such an embodiment, the fins 52 include the recessed material and the epitaxially grown material disposed above the recessed material. In another embodiment, a dielectric layer can be formed on the top surface of the substrate 50, and trenches can be etched through the dielectric layer. A heteroepitaxial structure can then be epitaxially grown in the trenches using a material different from the substrate 50, and the dielectric layer can be recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fins 52. In some embodiments of epitaxially growing homoepitaxial or heteroepitaxial structures, although in-situ doping and implantation doping can be used together, the epitaxially grown material can be in-situ doped during growth, and the in-situ doping can obviate the implantation before and after.

[0075] Furthermore, it may be advantageous to epitaxially grow a different material in region 50N (for example, the NMOS region) than in region 50P (for example, the PMOS region). In various embodiments, the upper portion of fin 52 may be made of silicon-germanium (Si... x Ge 1-x The semiconductor can be formed from silicon carbide, pure or substantially pure germanium, III-V compound semiconductors, II-VI compound semiconductors, or the like. For example, usable materials for forming III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, or the like.

[0076] In addition, Figure 6 Suitable wells (not shown) may be formed in the fins 52 and / or the substrate 50. In some embodiments, a P-well may be formed in region 50N and an N-well may be formed in region 50P. In some embodiments, either a P-well or an N-well may be formed in both region 50N and region 50P.

[0077] In embodiments with different types of wells, photoresist or other masks (not shown) can be used to implement different implantation steps for regions 50N and 50P. For example, photoresist can be formed over fins 52 and STI regions 56 in region 50N. The photoresist is patterned to expose regions 50P of the substrate 50, such as PMOS regions. The photoresist can be formed using spin coating techniques, and the photoresist can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type dopant implantation is performed in region 50P, and the photoresist can act as a mask to substantially prevent n-type dopant implantation into regions 50N, such as NMOS regions. The n-type dopant can be phosphorus, arsenic, antimony, or the like implanted into the region, with a concentration equal to or less than 10. 18 cm -3 Such as in between about 10 16 cm -3 and about 10 18 cm-3 Between. After injection, the photoresist is removed, for example, through an acceptable ashing process.

[0078] Next, photoresist is implanted into region 50P, and photoresist is formed over fin 52 and STI region 56 in region 50P. The photoresist is patterned to expose region 50N of substrate 50, such as an NMOS region. The photoresist can be formed using spin coating technology, and the patterned photoresist can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type dopant implantation can be performed in region 50N, and the photoresist can be used as a mask to substantially prevent p-type dopant implantation into region 50P, such as a PMOS region. The p-type dopant can be boron, boron fluoride, indium, or the like implanted into the region, and the concentration of the p-type dopant is equal to or less than 10. 18 cm -3 Such as in between about 10 16 cm -3 Up to approximately 10 18 cm -3 After injection, the photoresist can be removed, for example, through an acceptable ashing process.

[0079] Following implantation in regions 50N and 50P, an annealing process can be performed to repair implantation damage and activate the implanted p-type and / or n-type dopants. In some embodiments, although in-situ doping and implantation doping can be used together, the growth material of the epitaxial fin can be in-situ doped during growth, and the aforementioned in-situ doping can eliminate implantation.

[0080] exist Figure 7In this process, a dummy dielectric layer 60 is formed on the fin 52. The dummy dielectric layer 60 can be, for example, silicon oxide, silicon nitride, combinations thereof, or the like, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 62 is formed on the dummy dielectric layer 60, and a mask layer 64 is formed on the dummy gate layer 62. The dummy gate layer 62 can be deposited on the dummy dielectric layer 60 and then planarized by means such as CMP. The mask layer 64 can be deposited on the dummy gate layer 62. The dummy gate layer 62 can be a conductive or non-conductive material and can be selected from the group consisting of amorphous silicon, polycrystalline silicon, polycrystalline silicon-germanium, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 62 can be deposited using physical vapor deposition (PVD), CVD, sputter deposition, or other techniques known in the art and used for depositing selected materials. The dummy gate layer 62 can be formed of other materials that have a higher etch selectivity than the etch isolation region. The mask layer 64 can include, for example, silicon nitride, silicon oxynitride, or the like. In this example, the dummy gate layer 62 and the mask layer 64 are formed across regions 50N and 50P. It should be noted that, for illustrative purposes only, a dummy dielectric layer 60 covering only the fin 52 is shown. In some embodiments, the dummy dielectric layer 60 can be deposited such that it covers the STI region 56 and extends between the dummy gate layer 62 and the STI region 56.

[0081] Figures 8A to 19C Various other steps are shown in the apparatus of the manufacturing embodiment. Figures 8A to 19C The component displayed in either area 50N or area 50P. For example, Figures 8A to 19C The structure shown is applicable to both region 50N and region 50P. The differences in the structure between region 50N and region 50P (if any) are described in the relevant content of each figure.

[0082] exist Figure 8A and Figure 8BIn this process, acceptable photolithography and etching processes can be used to pattern the mask layer 64 (see reference). Figure 7 A mask 74 is formed. The pattern of the mask 74 can then be transferred to the dummy gate layer 62. In some embodiments (not shown), the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 by an acceptable etching process to form the dummy gate 72. The dummy gate 72 covers the corresponding channels of the channel region 58 of the fin 52. The pattern of the mask 74 can be used to physically separate each dummy gate 72 from adjacent dummy gates. The dummy gate 72 can also have a length direction that is substantially perpendicular to the lengthwise direction of the fin 52.

[0083] Furthermore, in Figure 8A and Figure 8B In this process, gate seal spacers 80 can be formed on the exposed surfaces of the dummy gate 72, mask 74, and / or fin 52. Subsequent anisotropic etching, thermal oxidation, or deposition can form the gate seal spacers 80. The gate seal spacers 80 can be formed from silicon oxide, silicon nitride, silicon oxynitride, or similar materials.

[0084] After the gate seal spacer 80 is formed, implantation for the lightly doped source / drain (LDD) region (not explicitly shown) can be performed. In embodiments with different device types, similar to the above description... Figure 6 The implantation discussed earlier can form a mask, such as a photoresist, over region 50N, while exposing region 50P, allowing appropriate type (e.g., p-type) dopants to be implanted into the exposed fin 52 in region 50P. The mask can then be removed. The n-type dopant can be any n-type dopant discussed previously, and the p-type dopant can be any p-type dopant discussed previously. The lightly doped source / drain regions can have a dopant size of approximately 10. 15 cm -3 up to about 10 19 cm -3 The dopant concentration. Annealing can be used to repair implantation damage and reactivate the implanted dopants.

[0085] exist Figure 9A and Figure 9BIn this process, a gate spacer 86 is formed on the gate sealing spacer 80 along the sidewalls of the dummy gate 72 and the mask 74. The gate spacer 86 can be formed by conformally depositing an insulating material and then anisotropically etching the insulating material. The insulating material of the gate spacer 86 can be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, combinations thereof, or the like.

[0086] It should be noted that the above disclosure generally describes the process for forming the spacer and LDD region. Other processes and sequences can be used. For example, fewer or additional spacers can be used; steps in a different sequence can be used (e.g., the gate seal spacer 80 may not be etched before forming the gate spacer 86 to obtain an "L-shaped" gate seal spacer); and / or similar processes and sequences. Furthermore, different structures and steps can be used to form n-type and p-type devices. For example, the LDD region for an n-type device can be formed before forming the gate seal spacer 80, while the LDD region for a p-type device can be formed after forming the gate seal spacer 80.

[0087] exist Figure 10A and Figure 10B In this process, source / drain regions 82 are formed in fin 52 to exert stress in each channel of channel region 58, thereby improving performance. The source / drain regions 82 are formed in fin 52 such that each dummy gate 72 is disposed between its respective neighboring pairs of source / drain regions 82. In some embodiments, the source / drain regions 82 may extend into and penetrate through fin 52. In some embodiments, gate spacers 86 are used to separate the source / drain regions 82 from the dummy gates 72 by an appropriate lateral distance, such that the source / drain regions 82 do not short-circuit the gate of the subsequently formed FinFET.

[0088] Figure 10C According to some embodiments, in a cross-section CC extending through the source / drain region 82, the source / drain region 82 in the fin 52 formed in region 50N of the NMOS FinFET device and region 50P of the adjacent PMOS FinFET device is shown. Although Figure 10C FinFET devices in region 50N are shown as n-type devices (e.g., NMOS devices), and FinFET devices in region 50P are shown as p-type devices (e.g., PMOS devices). However, it should be understood that n-type devices, p-type devices, or any combination of these devices may be formed in either region 50N or region 50P. Figure 10C The embodiments shown are for illustrative purposes only. Furthermore, it should be understood that although... Figure 10C Only displayed Figure 7 One of the two fins 52 in region 50P shown can be formed using any appropriate number of fins 52. Figure 10C The p-type device formed in region 50P is shown.

[0089] For example, the source / drain region 82 in region 50N of an NMOS region can be formed by initial masking, for example, region 50P of a PMOS region. According to some embodiments, the etch mask can be formed from materials such as photoresist, dielectric materials, or the like via spin-on processes, chemical vapor deposition (CVD) (e.g., plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, or similar processes), using materials such as photoresist, dielectric materials, or the like. However, any suitable material and any suitable deposition process can be used. The etch material can then be patterned via appropriate exposure and development and / or etching processes.

[0090] Once region 50P has been masked, the source / drain regions 82 of the fin 52 in region 50N are etched to form recesses in the fin 52. In some embodiments, a gate spacer 86 is formed covering a portion of the sidewall of the fin 52, which extends over the STI region 56, to prevent the source / drain regions 82 from growing near the surface of the STI region 56. However, in other embodiments, the spacer etching used to form the gate spacer 86 can be adjusted to remove spacer material, allowing the epitaxial growth region to extend to the surface of the STI region 56.

[0091] Once the recess is formed in the fin 52, and if necessary, once a portion of the spacer material of the gate spacer 86 has been removed, the source / drain region 82 in region 50N is epitaxially grown in the recess. The source / drain region 82 may comprise any acceptable material, such as materials suitable for n-type FinFETs. For example, if the fin 52 is silicon, the source / drain region 82 in region 50N may comprise a material to which tensile strain is applied in the channel region 58, such as silicon, silicon carbide, phosphorous doped silicon carbide, silicon phosphide, or similar materials. The source / drain region 82 in region 50N may have raised surfaces from the respective surfaces of the fin 52 and may have facets. Once the source / drain regions 82 have been formed in region 50N, the mask formed in region 50P can be removed (e.g., via an ashing or etching process) to expose the fins 52 in region 50P.

[0092] As a result of the epitaxial process used to form the source / drain region 82 in region 50N, the upper surface of the source / drain region 82 has a facet that extends laterally outward beyond the sidewall of the fin 52. In some embodiments, such as by Figure 10C As shown on the left side of region 50N, the two source / drain regions 82 are faceted to cause adjacent source / drain regions 82 of the same FinFET to merge.

[0093] For example, the source / drain region 82 in region 50P of a PMOS region can be formed by masking, for example, region 50N of an NMOS region. A masking process for forming a mask over region 50P can be used to form a mask over region 50N. However, any suitable mask material and any suitable masking process can be used.

[0094] Once region 50N has been shielded, the source / drain regions 82 of the fin 52 in region 50P are etched to form recesses in the fin 52. Furthermore, a portion of the spacer material of the gate spacer 86 may be retained to cover a portion of the sidewall of the fin 52. However, in other embodiments, a portion of the spacer material of the source / drain regions may be removed. The source / drain regions 82 in region 50P are then epitaxially grown in the recesses. The source / drain regions 82 may comprise any acceptable material, such as materials suitable for p-type FinFETs. For example, if the fin 52 is silicon, the source / drain regions 82 in region 50P may comprise materials that apply compressive strain to the channel region 58, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, or similar materials. The source / drain regions 82 in region 50P may also have surfaces protruding from the respective surfaces of the fins 52 and may have facets. Once the source / drain regions 82 have been formed in region 50P, the mask formed in region 50N may be removed (e.g., via an ashing or etching process) to expose the source / drain regions 82 in region 50N for further processing.

[0095] As a result of the epitaxial process used to form the source / drain region 82 in region 50P, the upper surface of the epitaxial source / drain region 82 has a facet that extends laterally outward beyond the sidewall of the fin 52. In some embodiments, such as by Figure 10C As shown in the source / drain region 82 in region 50P on the right, adjacent source / drain regions of the finFET device remain separated after the epitaxial process is completed.

[0096] The source / drain regions 82 and / or fins 52 can be implanted with dopants to form source / drain regions, and the aforementioned process is similar to the previously discussed process for forming lightly doped source / drain regions followed by annealing. The source / drain regions can have a density between approximately 10... 19 cm -3 and about 10 21 cm -3 The dopant concentrations between these values. The n-type and / or p-type dopants used for the source / drain regions can be any of the dopants previously discussed. In some embodiments, the source / drain regions 82 can be doped in situ during growth.

[0097] exist Figures 11A to 11C In the middle, the deposited contact etch stop layer (CESL) 87 is in Figures 10A to 10CThe structure shown is above. According to the embodiments disclosed herein, the dielectric material of CESL 87 has a first etch rate compared to the second etch rate of the dielectric material of the subsequently formed cut metal gate (CMG) isolation structure, referred to herein as dielectric isolation region 162 and discussed in detail below. In some specific embodiments, CESL 87 may include elements similar to those of dielectric isolation region 162, but with additional elements added. For example, in embodiments where dielectric isolation region 162 includes a material such as silicon nitride, CESL 87 may include a material having silicon and nitride and having other elements such as carbon, such as silicon carbonitride (SiCN), also added to the material. In some embodiments, the material of CESL 87 comprises between about 15% and about 50% (by volume) of carbon (C), and in some embodiments, the material of CESL 87 comprises between about 5% and about 20% (by weight) of carbon (C).

[0098] However, in other embodiments, CESL 87 may include materials unrelated to the material of dielectric isolation region 162, while still maintaining the desired separation in terms of etch rate and etch selectivity. For example, in other embodiments, CESL 87 includes a dielectric material such as silicon oxide, any other suitable dielectric material, or the like. However, any suitable material may be used.

[0099] The dielectric material (e.g., SiCN) of CESL 87 can be compliantly deposited on the source / drain regions 82, mask 74, and gate spacer 86. According to some embodiments, a chemical vapor deposition (CVD) process can be used to form CESL 87 to enable… Figures 10A to 10C The structure shown is exposed to one or more precursors and subjected to a plasma activation process performed in a deposition chamber. The CVD process can be atomic layer deposition (ALD), plasma-assisted chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or similar processes.

[0100] In some embodiments, precursors may be introduced into the structure as first and second precursors, respectively, wherein a plasma activation process is performed on one of the introduced precursors in a repeated series of depositions of the respective materials. In other embodiments, precursors may be introduced in the form of a mixture in a repeated series of depositions of the mixture, wherein a plasma activation process is performed after each deposition in the repeated series of depositions of the mixture until the desired thickness of CESL 87 has been formed.

[0101] According to some embodiments, the first precursor includes silane (e.g., dichlorosilane, SiH2Cl, DCS), and the first precursor flows into the cavity at a flow rate between about 1500 sccm and about 2500 sccm, such as about 2000 standard cubic centimeters per minute (sccm). The second precursor includes nitrogen (e.g., ammonia, NH3), and the second precursor flows into the cavity at a flow rate between about 4500 sccm and about 5500 sccm, such as about 5000 sccm. During the deposition process, the process conditions are maintained at a pressure between about 3.5 torr and about 4.5 torr, such as about 4 torr; and at a temperature between about 520°C and about 590°C, such as about 550°C. The plasma generator for the second precursor (e.g., NH3) used to initiate the deposition process is maintained at a power between approximately 100W and approximately 120W, such as approximately 110W; at a frequency between approximately 13MHz and approximately 14GHz; and for a duration between approximately 25 seconds and approximately 35 seconds, such as approximately 30 seconds. However, any suitable precursor material and any suitable process conditions can be used to deposit CESL 87.

[0102] According to some embodiments, the dielectric material of CESL 87 is compliantly deposited as a coordination compound containing SiN (e.g., SiCN, SiOCN, or similar compounds), or other suitable compounds such as SiOC, and formed having a dielectric material with a dielectric material ... up to approximately The thickness, such as approximately However, any suitable process conditions can be used. Furthermore, the coverage and conformity of CESL87 can be controlled based on the deposition process used (e.g., ALD, CVD, furnace, or the like) and process conditions. For example, ALD deposition provides better stepped coverage and conformity than CVD. Moreover, considering the controllability of the deposition process used (e.g., ALD, CVD, furnace, or the like), the thickness uniformity of CESL 87 can be controlled within approximately ±20%.

[0103] Figures 11A to 11CThe first interlayer dielectric (ILD) 88 deposited on CESL 87 is further shown. The first ILD 88 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-assisted CVD (PECVD), or flow-through chemical vapor deposition (FCVD). The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may be used.

[0104] exist Figure 12A and Figure 12B In this process, a planarization process such as CMP can be performed to make the top surface of the first ILD 88 flush with the top surface of the dummy gate 72 or the mask 74. The planarization process may also remove the mask 74 on the dummy gate 72, and a portion of the gate sealing spacers 80 and 86 along the sidewalls of the mask 74. After the planarization process, the dummy gate 72, the gate sealing spacers 80, the gate spacers 86, and the top surface of the first ILD 88 are flush. Accordingly, the top surface of the dummy gate 72 is exposed via the first ILD 88. In some embodiments, the mask 74 may be retained, in which case the planarization process makes the top surface of the first ILD 88 flush with the top surface of the mask 74.

[0105] exist Figure 13A and Figure 13BIn the etching step, the dummy gate 72 is removed, and if a mask 74 is present, the mask 74 is also removed, thereby forming a recess 90. A portion of the dummy dielectric layer 60 in the recess 90 may also be removed. In some embodiments, only the dummy gate 72 is removed, leaving the dummy dielectric layer 60 exposed through the recess 90. In some embodiments, the dummy dielectric layer 60 is removed from the recess 90 in a first region of the die (e.g., a core logic region) and left in the recess 90 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gate 72 is removed by an isotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 72 without etching the first ILD 88 or the gate spacer 86. Each recess 90 exposes and / or overlies a channel region 58 of the fin 52. Each channel region 58 is disposed between adjacent source / drain regions 82. During removal, the dummy dielectric layer 60 can be used as an etch stop layer when the dummy gate 72 is etched. After the dummy gate 72 is removed, the dummy dielectric layer 60 can then optionally be removed.

[0106] exist Figure 14A and Figure 14B In this process, a gate dielectric layer 92 and a gate electrode 94 are formed as replacement gates. Figure 14C show Figure 14BA detailed view of region 89. A gate dielectric layer 92 is compliantly deposited in the recess 90, such as on the top surface and sidewalls of fin 52, and on the sidewalls of gate seal spacer 80 / gate spacer 86. The gate dielectric layer 92 may also be formed on the top surface of the first ILD 88. According to some embodiments, the gate dielectric layer 92 comprises silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric layer 92 comprises a high dielectric constant (high k) dielectric material, and in these embodiments, the gate dielectric layer 92 may have a k value greater than about 7.0, and may comprise metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Methods for forming the gate dielectric layer 92 may include molecular beam deposition (MBD), ALD, PECVD, and similar processes. In embodiments where a portion of the dummy dielectric layer 60 is retained in the recess 90, the gate dielectric layer 92 comprises the material of the dummy dielectric layer 60 (e.g., SiO2).

[0107] Gate electrodes 94 are deposited on the gate dielectric layer 92 and fill the remaining portion of the recess 90. Gate electrodes 94 may comprise metal-containing materials such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiples thereof. For example, although in… Figure 14B The image shows a single-layer gate electrode, but gate electrode 94 may include, for example, Figure 14C The diagram shows any number of optional substrates 94A, any number of work function adjustment layers 94B, and fill material 94C. After filling the recess 90, a planarization process such as CMP can be performed to remove excess material from the gate dielectric layer 92 and the gate electrode 94, which lies on the top surface of the first ILD 88. The combination of the material of the gate electrode 94 and the remaining portion of the gate dielectric layer 92 is referred to as the resulting FinFET replacement gate stacks or metal gate stacks 95. Thus, as... Figures 15A to 15D As shown, the metal gate stack 95 extends along the sidewall of the channel region 58 of the fin 52.

[0108] Furthermore, the metal gate stack 95 of the p-type FinFET and the metal gate stack 95 of the n-type FinFET can be different from each other, such that the work function of the metal gate stack 95 is suitable for the corresponding p-type FinFET or n-type FinFET. The filler material 94C used to form the metal gate stack 95 may include aluminum, copper, tungsten, cobalt, or the like.

[0109] The formation of the gate dielectric layer 92 in regions 50N and 50P may occur simultaneously, such that the gate dielectric layer 92 in each region is formed of the same material, and the formation of the gate electrode 94 may occur simultaneously, such that the gate electrode 94 in each region is formed of the same material. In some embodiments, the gate dielectric layer 92 in each region may be formed using different processes, such that the gate dielectric layer 92 may be made of different materials, and / or the gate electrode 94 in each region may be formed using different processes, such that the gate electrode 94 may be made of different materials. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0110] exist Figures 15A to 15D In some embodiments, the metal gate stack 95 is recessed, thereby forming a recess directly above the metal gate stack 95 and between opposing portions of the gate spacer 86. A gate mask 96, comprising one or more layers of dielectric material such as silicon nitride, silicon oxynitride, or the like, is filled in the recess, followed by a planarization process to remove excess dielectric material extending over the first ILD 88. The material of the gate mask 96 may be the same as or different from the material of the gate dielectric layer 92, the first ILD 88, and / or the gate spacer 86. According to some embodiments of this disclosure, the formation of the gate mask 96 includes recessing the metal gate stack 95 by etching to form the recess; filling the recess with dielectric material; and performing planarization to remove excess dielectric material. In this way, the remaining portion of the dielectric material forms the gate mask 96, which, along with the gate sealing spacer 80, the gate spacer 86, the CESL 87, and the first ILD 88, is surface-planarized. According to some embodiments of this disclosure, the gate mask 96 is formed of silicon nitride, silicon oxynitride, silicon oxycarbide, silicon oxycarbonitride, or the like.

[0111] Once the gate mask 96 has been formed, an etch mask for the metal gate dicing process can be deposited on the surfaces of the gate mask 96, gate seal spacer 80, gate spacer 86, and CESL 87, which are planarized together with the first ILD 88. The etch mask is then patterned to form openings within it. According to some embodiments, the etch mask can be formed from materials such as photoresist, titanium nitride, boron nitride, silicon nitride, or the like, and the material of the etch mask differs from the material of the underlying components of the gate mask 96, gate seal spacer 80, gate spacer 86, CESL 87, first ILD 88, gate dielectric layer 92, and gate electrode 94. When the etch mask is formed from a non-photoresist material, a patterned photoresist can be formed on the etch mask, and the patterned photoresist can be used as the etch mask to transfer the desired pattern into the etch mask, forming openings through the aforementioned etch mask. According to some embodiments, the opening formed in the etch mask not only exposes a portion of the gate electrode 94, but also extends in a region and exposes a material surface planarized together with the first ILD 88. The aforementioned region extends between regions 50N and 50P and extends between source / drain regions 82 disposed on opposite sides of the gate electrode 94 in a direction substantially perpendicular to the gate electrode 94.

[0112] Once the desired pattern has been formed in the etching mask, an etching process is performed using the patterned etching mask to remove areas of underlying material exposed through openings in the etching mask (e.g., the material of the gate electrode 94 and the exposed portion of the first ILD 88). According to some embodiments, during the CMG process, etching of the material is performed using process gases selected from, but not limited to, SiCl4, O2, C4F6, HBr, He, and combinations thereof. Etching can be performed at pressures ranging from approximately 3 mTorr to approximately 10 mTorr, for durations ranging from approximately 500 seconds to approximately 900 seconds, such as approximately 700 seconds. Radio frequency (RF) power is applied during etching, and the RF power can be in the range of approximately 500 watts to approximately 900 watts. A bias voltage is also applied.

[0113] Figure 15C and Figure 15DAccording to some embodiments, the formation of a cut metal gate (CMG) opening 156 using an etching process is shown. According to some embodiments, the CMG opening 156 may be formed between regions 50N and 50P of adjacent devices to cut the metal gate stack 95 into partitioned portions, each of these partitioned portions serving as a metal gate stack 95A for an n-type device in region 50N and a metal gate stack 95B for a p-type device in region 50P. Accordingly, dividing the metal gate stack 95 into partitioned portions can be referred to as a CMG process.

[0114] In some embodiments, the etching used to form the CMG opening 156 is anisotropic, so the sidewalls of the CMG opening 156 are substantially vertical. During etching in the CMG process, as in Figures 14A to 15D As seen, the desired portions of the gate mask 96, gate seal spacer 80, gate spacer 86, CESL 87, first ILD 88, gate dielectric layer 92, and gate electrode 94 between region 50N and region 50P are removed. Accordingly, the lower portion of STI region 56 is exposed. Etching can be stopped at the desired intermediate level between the top and bottom surfaces of STI region 56. An etching gas is selected to primarily erode the metal in the metal gate stack 95 to ensure removal of this metal. Accordingly, the etching rate of first ILD 88, CESL 87, gate spacer 86, and STI region 56 can be lower than the etching rate of metal gate stack 95. Thus, CMG opening 156 is located in the first region of the AA cut line between the separating portions of metal gate stack 95 (e.g., ...). Figure 15C The CMG opening 156 extends to a first depth D1 in the second region (as shown in the diagram) between the source / drain regions 82 of the adjacent device. Figure 15D (as shown) extends to a second depth D2, and the first depth D1 is greater than the second depth D2.

[0115] According to some embodiments, the CMG opening 156 may be formed at the planarized surface of the first ILD 88 having a first width W1 between about 10 nm and about 40 nm, such as about 26 nm, and a first length L1 between about 5 nm and about 25 nm, such as about 15 nm. Furthermore, in some embodiments, the CMG opening 156 may extend from the planarized surface of the first ILD 88 to a first depth D1 of the STI region 56 between about 70 nm and about 210 nm, such as about 140 nm, and the CMG opening 156 may extend from the planarized surface to a second depth D2 of the first ILD 88 between about 50 nm and about 110 nm, such as about 80 nm. However, any suitable width and any suitable depth may be used for the CMG opening 156. In some embodiments, in the second region of the CC cleavage line between the source / drain regions 82 of adjacent devices in regions 50N and 50P, the CMG opening 156 substantially extends through but not completely through the first ILD 88, and the distance from the first ILD 88 to the second depth D2 is between approximately 70 nm ± 20 nm. Figure 15D (As shown). In other embodiments, the CMG opening 156 in the second region of the CC cut line between the source / drain regions 82 of adjacent devices in regions 50N and 50P can extend completely through the first ILD 88 and to the STI region 56 (not shown). Figure 15D As shown in the image, the distance to the second depth D2 is reduced to approximately 120 nm ± 20%. Once a CMG opening 156 has been formed, the etch mask can be removed, for example, by a CMP process or an etching process.

[0116] Figures 16A to 16D Displayed at CMG opening 156 ( Figure 15C A dielectric isolation region 162 is formed within the first ILD 88, and an isolation layer 160 is formed on the flat surface of the first ILD 88. Figures 16A to 16D Further, a second ILD 108 is formed on the isolation layer 160; a mask layer 163 is formed on the second ILD 108, and then patterning for further processes is prepared.

[0117] Reference Figure 16C and Figure 16D A dielectric isolation region 162 is formed at the CMG opening 156 ( Figure 15CIn this configuration, the metal gate stack 95 is divided into metal gate stacks 95A and 95B, which are adjacent devices located in regions 50N and 50P, respectively. According to some embodiments, dielectric filler material is deposited to fill or overfill the metal gate stack. Figure 15C and Figure 15D The CMG opening 156 is used to form a dielectric isolation region 162. According to some embodiments, such as... Figure 16C As shown, in the channel region, a dielectric isolation region 162 is formed to have a first height H1 between approximately 120 nm ± 20%, and as Figure 16D As shown, in the embodiment where the CMG opening 156 extends into the STI region 56 of the source / drain region, a dielectric isolation region 162 is formed to have a second height H2 between approximately 120 nm ± 20%. In embodiments where the second depth D2 of the CMG opening 156 in the source / drain region remains above the STI region 56 (e.g., ...), a dielectric isolation region 162 is formed to have a second height H2 between approximately 120 nm ± 20%. Figure 15D As shown), the dielectric isolation region 162 in the source / drain region is also retained above the STI region 56 (not shown). Figure 16D In this way, the second height H2 of the dielectric isolation region 162 in the source / drain region can be smaller than the first height H1 of the dielectric isolation region 162 in the channel region. For example, the second height H2 can be between approximately 70 nm ± 20%. Deposition methods can include plasma-assisted chemical vapor deposition (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), spin coating, or similar methods, and the dielectric filling material is compatible with CESL 87 (…). Figure 16B The materials used vary. According to some embodiments, the dielectric filling material includes silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon carbide, or the like. However, any suitable deposition method and any suitable dielectric filling material can be used.

[0118] Once deposited, the dielectric filler is planarized using processes such as CMP or grinding to remove excess material. In some embodiments, such a planarization process is performed so that a portion of the dielectric filler remains as an isolation layer 160 over the dielectric isolation region 162 and over the remaining flat surfaces of the gate mask 96, the first ILD 88, CESL 87, the gate spacer 86, and the gate seal spacer 80. According to some embodiments, the isolation layer 160 may be formed as a layer between approximately up to approximately The thickness between, such as approximately However, any suitable thickness can be used for the isolation layer 160.

[0119] Figures 16A to 16D Further illustration shows the deposition of a second ILD 108 on the insulating layer 160 using any material and method used to form the first ILD 88. In some embodiments, the material of the second ILD 108 may be the same as the material of the first ILD 88. However, the material of the second ILD 108 may differ from the material of the first ILD 88. Nevertheless, any suitable material and any suitable deposition method can be used to form the second ILD 108. In some embodiments, the second ILD 108 may be formed as if at a depth between approximately up to approximately The thickness between, such as approximately However, any suitable thickness can be used for the second ILD 108.

[0120] Figures 16A to 16D The photolithography process for depositing and patterning the mask layer 163 over the second ILD 108 is further illustrated. According to some embodiments, the mask layer 163 can be deposited using any suitable deposition process, can be formed to any suitable thickness, and can be patterned using any suitable photolithography method to form openings through the mask layer 163 and expose the surface of the second ILD 108 in the regions overlying the source / drain regions 82 and / or overlying the metal gate stack 95.

[0121] According to some embodiments, Figure 16A and Figure 16B A deposition mask layer 163 is shown, and a first opening 164 is formed through the mask layer 163 to expose the region of the source / drain region 82 overlaid on the second ILD 108. According to some embodiments, the first opening 164 may be formed with a second width W2 between approximately 12 nm and approximately 18 nm, such as approximately 15 nm, and as in... Figure 16D As shown, the first opening 164 can be formed to have a second length L2 between approximately 60 nm and approximately 120 nm, such as approximately 90 nm. According to some embodiments, Figure 16C This illustrates the formation of a second opening 166 through the mask layer 163 to expose one or more regions of the second ILD 108 overlying the metal gate stack 95, for example, in regions 50N and 50P. According to some embodiments, the second opening 166 may be formed with a third width W3 between approximately 8 nm and approximately 20 nm, such as approximately 14 nm. Once patterned with the first opening 164 and / or the second opening 166, the mask layer 163 can be used as a mask to form contact plugs through the second ILD 108, which are used for the metal gate stack 95 and for the source / drain regions 82.

[0122] Figure 17 The formation of contact via openings 170 is shown above the source / drain regions 82 of adjacent devices in regions 50N and 50P. In this way, the surface of the CESL 87 surrounding the source / drain regions 82 of adjacent devices in regions 50N and 50P is exposed via the contact via openings 170.

[0123] Once the mask layer 163 has been patterned, during the etching process, an isolation layer 160 is used as an etch stop layer to transfer the pattern of the mask layer 163 through the first opening 164 and / or the second opening 166 of the second ILD 108. This allows the formation of contact via openings through the second ILD 108. In some embodiments, the mask layer 163 is applied and patterned such that the first opening 164 and the second opening 166 are simultaneously etched through the second ILD 108 to transfer the pattern of the mask layer 163 into the second ILD 108. In other embodiments, the pattern of the first opening 164 in the mask layer 163 is transferred to the second ILD 108 separately from the pattern of the second opening 166 in the mask layer 163.

[0124] According to some embodiments, an etchant having a high selectivity for the material of the second ILD 108 and a low selectivity for the material of the insulating layer 160 can be used to remove the material of the second ILD 108. This forms a contact via opening 170 through the second ILD 108, exposing the surface of the insulating layer 160 via the contact via opening. According to some embodiments, the etchant used to form the contact via opening through the second ILD 108 includes, but is not limited to, carbon-and-fluorine-containing gases, such as CF4, CH2F2, CHF3, or the like. However, any suitable gas can be used.

[0125] In some embodiments, an isotropic reactive ion etching (RIE) process is used to form the contact via opening 170 in the second ILD 108. The RIE process uses one or more carbon- and fluorine-containing gases and is performed at a pressure ranging from approximately 3 mTorr to approximately 10 mTorr for a time period ranging from approximately 300 seconds to approximately 1200 seconds, such as approximately 750 seconds. RF power is applied during etching, and the RF power can be in the range of approximately 500 watts to approximately 900 watts. A bias voltage is also applied.

[0126] Once the surface area of ​​the isolation layer 160 is exposed via the contact via opening 170 in the second ILD 108, another etching process is used to extend the contact via opening 170 through the isolation layer 160. Additionally, during the etching process, the material of the isolation layer 160 is etched faster than the material of the underlying first ILD 88, thus causing the material (e.g., SiN) of the dielectric isolation region 162 to recess faster than that of the first ILD 88, resulting in a pullback of the dielectric isolation region 162 (e.g., SiN pullback).

[0127] During this pullback, a portion of one or more exposed isolation layers 160 is removed via the first opening 164 and / or the second opening 166, and the dielectric isolation region 162 is recessed in the source / drain region. In some embodiments, the dielectric isolation region 162 may be recessed from a second height H2 (e.g., between approximately 120 nm ± 20%) in the source / drain region. Figure 16D (As shown), the height is reduced to, for example, a third height H3 between approximately 30 nm ± 20%, or, for example, a third height H3 between approximately 40 nm ± 10%. Furthermore, a portion of the dielectric isolation region 162 is embedded in the STI region 56. According to some embodiments, the embedded portion of the dielectric isolation region 162 may have a fourth height H4 between approximately 80 nm ± 20% or between approximately 60 nm and approximately 100 nm, such as approximately 80 nm. A first ratio R1 of the fourth height H4 to the second height H2 can be defined using the following formula: R1 = H4 / H2, where R1 is between approximately 1:1 and approximately 1:2, such as approximately 1:1.5. Once the dielectric isolation region 162 has been recessed, the area on the surface of the first ILD 88 of the underlying layer is exposed via an opening in the isolation layer 160. According to some embodiments, pull-back etch uses an etchant that has a high selectivity for the material of the isolation layer 160 and the dielectric isolation region 162, and a relatively low selectivity for the material of the first ILD 88 in the planarized surface of the lower isolation layer 160.

[0128] According to some embodiments, the pull-back etching process can be an isotropic reactive ion etching (RIE) process, which uses one or more carbon- and fluorine-containing gases and is performed at a pressure between about 3 mTorr and about 10 mTorr for a time period between about 200 seconds and about 1200 seconds, such as about 750 seconds. However, any suitable pressure and any suitable time period can be used. RF power is applied during etching, and the RF power can be in the range between about 500 watts and about 900 watts. A bias voltage is also applied. However, any suitable RF power and any suitable bias voltage can be used. In this way, a surface area of ​​the planarized surface of the underlying isolation layer 160 is exposed through one or more of the first opening 164 and / or the second opening 166, and the isolation layer 160 is recessed to a depth between about 40 nm and about 100 nm, such as about 70 nm. However, the isolation layer 160 can be recessed to any suitable depth.

[0129] Once the pull-back etching is complete, a timed etch can be performed to recess a portion of the first ILD 88 and expose the surface of the CESL 87 via the contact via opening 170. According to some embodiments, one or more etching processes (e.g., dry etch, physical etching process, bombardment etch, or similar processes) are used to recess the first ILD 88 to a third depth D3 between approximately 40 nm and approximately 60 nm, such as up to approximately 50 nm. In some embodiments, the first ILD 88 is recessed to a third depth D3 between approximately 80 nm ± 20%. However, any suitable depth can be utilized.

[0130] In some embodiments, timed etching may be used to recess the first ILD 88 using a physical etching process (e.g., ion beam etching (IBE), reactive ion beam etching (RIBE), bombardment etching, sputtering etching, or similar processes). The physical etching process uses a process gas, such as an inert gas (e.g., argon (Ar)), to accelerate ions at the exposed material in the contact via opening 170 and to recess the exposed portion of the first ILD 88 to a third depth D3. However, any suitable process gas and any suitable depth may be used to recess the first ILD 88.

[0131] Figure 18As shown, once the first ILD 88 has been recessed, an etch-stop removal process is used to remove a portion of CESL 87, exposing the surface of the epitaxial growth 182 of the source / drain regions 82 of adjacent devices in regions 50N and 50P. According to some embodiments, one or more etching processes (e.g., dry etching, wet etching, physical etching, bombardment etching, or similar processes) are used to remove a portion of CESL 87 using an etchant having a material selectivity ratio for CESL 87 and a relatively low selectivity ratio for the epitaxial growth 182 of the source / drain regions 82. In this way, CESL 87 prevents the removal of the epitaxial growth 182 during the etching of the first ILD 88, and due to the relative selectivity of CESL 87 relative to the epitaxial growth 182 during the removal of CESL 87, the percentage loss of the epitaxial growth 182 is limited to between approximately 5% and approximately 20% (by volume). For example, in embodiments where the source / drain regions 82 comprise silicon-based materials (e.g., SiGe, SiP, SiCP, or the like) and where the epitaxial growth 182 comprises a critical dimension (CD) between approximately 30 nm and approximately 80 nm, the material loss of the epitaxial growth 182 is limited to between approximately 5 nm and approximately 10 nm during the removal of CESL 87. Figure 18 Furthermore, once a portion of CESL 87 has been removed, the topmost portion of the epitaxial growth 182 remains above the topmost portion of the dielectric isolation region 162 at a fifth height H5. In some embodiments, the fifth height H5 is between approximately 30 nm ± 20%, or between approximately 20 nm and approximately 40 nm, such as approximately 30 nm. According to some embodiments, a second ratio R2 of the fifth height H5 to the second height H2 can be defined using the following formula: R2 = H5 / H2, where R2 is between approximately 1:6 and approximately 1:3, such as approximately 1:4. However, any suitable height and any suitable ratio can be used.

[0132] According to one embodiment, etch stop removal includes a wet etching process to remove the exposed portions of CESL 87. While other etchants such as gaseous H2 can be used, wet etching is performed, for example, using an etchant such as HF. According to some embodiments, wet etching can be performed at a process temperature between about 20°C and about 100°C, such as about 60°C, and for a duration between about 10 seconds and about 90 seconds, such as about 50 seconds, to perform etch stop removal. However, etch stop removal can be performed at any suitable temperature and for any suitable period of time. Furthermore, any other suitable method, such as reactive ion etching (RIE) or dry etching using an etchant such as NH3 / NF3, can be used to remove the exposed portions of CESL 87.

[0133] In other embodiments, as described above, etch stop removal can be performed using physical etching processes (e.g., ion beam etching (IBE), reactive ion beam etching (RIBE), bombardment etching, sputtering etching, or similar processes) to remove the exposed portions of CESL 87. According to some embodiments, an inert process gas (e.g., Ar, Xe, Ne, or Kr) and process beam energy (e.g., voltage VB) can be used to perform the physical etching process for etch stop removal.

[0134] In one specific embodiment, although different etching parameters are used, the physical etching process (e.g., ion beam etching (IBE)) used to recess the first ILD 88 can also be used to perform the etch-stop removal for CESL 87. For example, the first physical etching process can be performed using a first process gas with a first flow rate and a first beam energy for a first duration to recess the first ILD 88. After the first duration, a second physical etching process can be performed using a second process gas with a second flow rate and a second beam energy for a second duration to remove the exposed portion of CESL 87. In some embodiments, the second process gas can be the same as the first process gas (e.g., Ar), and the second physical etching process can be performed by increasing the beam energy used in the first physical etching process from the first beam energy to the second beam energy.

[0135] According to the embodiments described herein, during the etching process, the dielectric material of CESL 87 has a first etching rate, and the material of the dielectric isolation region 162 has a second etching rate, the second etching rate being less than the first etching rate of CESL 87. While specific embodiments have disclosed physical etching processes for recessing the first ILD 88 and for removing exposed portions of CESL 87, it should be understood that any combination of a first etching process suitable for selectively removing the material of the first ILD 88 and a second etching process suitable for selectively removing exposed portions of CESL 87 can be used. Furthermore, based on the material composition of the first ILD 88 and CESL 87 and their respective etching rates, the required recess depth of the first ILD 88 and the thickness of the CESL 87, as well as the process parameters (e.g., temperature, process gas, flow rate, beam energy, and / or time period) for recessing the first ILD 88 and for removing a portion of CESL 87, may be the same or different. According to some embodiments, during the etching process, the selectivity of the dielectric layers (e.g., in the second ILD 108, the isolation layer 160, the dielectric isolation region 162, the first ILD 88, and CESL 87) can be adjusted by changing process conditions (e.g., gas type, gas ratios, power, frequency, pressure, combinations thereof, or similar conditions). For example, in some embodiments, wet etching utilizing HF can be used, resulting in an etching selectivity ratio of approximately 3:1 between the first ILD 88 and CESL 87.

[0136] Figures 19A to 19C The figure illustrates the formation of source / drain contacts 112 in the contact via opening 170 of the first opening 164 and the formation of gate contacts 110 in the contact via opening 170 of the second opening 166. According to some embodiments, once the contact via opening 170 has been formed, the mask layer 163 can be removed, for example, via an ashing process. In other embodiments, the mask layer 163 can be removed during a planarization process (e.g., chemical mechanical planarization, CMP) during contact formation. However, any suitable process (e.g., CMP) can be used to remove the mask layer 163.

[0137] Furthermore, an optional residue clean process can be performed using a relatively weak solution to minimize surface damage. For example, before forming the gate contact 110 and / or the source / drain contact 112, any unwanted residues can be removed from the contact via opening 170 using a weak solution such as deionized (DI) water, Standard Cleaning Solution-1 / Standard Cleaning Solution-2 (SC1 / SC2), ozone, or the like. By using a weak solution, minimal or no damage is caused to the material of the exposed portion of the epitaxial growth 182 in the source / drain region 82.

[0138] According to some embodiments, an optional liner, such as a diffusion barrier layer, an adhesion layer, or a similar layer, and a conductive material are formed in the contact via opening 170. The optional liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be tungsten, copper, a copper alloy, silver, gold, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from the surface of the second ILD 108. The remaining portion of the optional liner and conductive material forms source / drain contacts 112 and gate contacts 110 in the opening. An annealing process may be performed to form silicide at the interface between the source / drain region 82 and the source / drain contact 112. The source / drain contact 112 is physically coupled and electrically coupled to the exposed portion of the source / drain region 82 of the epitaxial growth 182, and the gate contact 110 is physically coupled and electrically coupled to the gate electrode 106. The source / drain contacts 112 and the gate contact 110 can be formed in different processes or in the same process. Although shown as having the same cross-section, it should be understood that each of the source / drain contacts 112 and the gate contact 110 can be formed with a different cross-section to avoid short circuits in the contacts.

[0139] By utilizing the embodiments described herein, less etch damage occurs to the source / drain region 82, which would increase the series resistance of the device. Specifically, during the material pull-back of the dielectric isolation region 162 (e.g., during SiN pull-back), CESL 87 is retained to protect the source / drain region 82 by separating the etch selectivity of CESL 87 and the dielectric isolation region 162. With such protection, damage to the source / drain region 82 is minimized, and both the size and shape of the source / drain region 82 are preserved before and after the pull-back etching.

[0140] According to some embodiments, the method includes: etching an isolation region. The isolation region includes a first dielectric material and is embedded in a dielectric layer. An etching opening is formed in the dielectric layer, exposing a first portion of a contact etch stop layer and a second portion of the contact etch stop layer via the opening. The isolation region is disposed between the first and second portions of the contact etch stop layer. The first portion of the contact etch stop layer is removed, exposing a first source / drain region via the opening. The contact etch stop layer includes a second dielectric material. The second dielectric material is different from the first dielectric material. The second portion of the contact etch stop layer is removed, exposing a second source / drain region via the opening. A contact is formed in the opening connecting the first and second source / drain regions. In one embodiment, etching the isolation region includes recessing the isolation region to a depth below the first and second portions of the contact etch stop layer. In one embodiment, etching the opening in the dielectric layer includes performing a timed etch of the dielectric layer after recessing the isolation region. In one embodiment, performing timed etching includes: using a first beam energy and continuing for a first time period while using a process gas to perform a physical etching process. In one embodiment, removing the first and second portions of the contact etch stop layer includes: after the first time period, using a second beam energy and continuing for a second time period while using a process gas to continue performing the physical etching process. The second beam energy is greater than the first beam energy. In one embodiment, continuing the physical etching process further includes using argon (Ar) as the process gas, and the material of the contact etch stop layer is silicon carbon nitride. In one embodiment, removing the first and second portions of the contact etch stop layer includes performing wet etching after the first time period.

[0141] According to one embodiment, the method includes: forming a cavity in an interlayer dielectric to expose an isolation structure, and exposing a second dielectric material via the cavity. The exposed second dielectric material is on the exposed isolation structure within the cavity. The second dielectric material is different from the dielectric material of the isolation structure. After exposing the isolation structure, a first portion and a second portion of the second dielectric material are removed to expose a first source / drain region of a first finFET and a second source / drain region of a second finFET via the cavity. A conductive material is deposited in the cavity to form a plug connecting the first source / drain region and the second source / drain region. In one embodiment, forming the cavity includes performing timed physical etching on the interlayer dielectric using an inert process gas for timed physical etching. In one embodiment, the isolation structure includes a material having a first set of elements, and the second dielectric material includes the first set of elements and at least one other element. In one embodiment, performing physical etching includes performing ion beam etching using a first process voltage to form the cavity. In one embodiment, removing the first and second portions of the second dielectric material further includes performing ion beam etching using a second process voltage to remove the first and second portions of the second dielectric material, wherein the second process voltage is greater than a first process voltage. In one embodiment, removing the first and second portions of the second dielectric material further includes using wet etching. In one embodiment, performing wet etching includes using an etchant with a selective ratio to silicon carbonitride. In one embodiment, the method further includes using an etchant with a selective ratio to silicon nitride to recess the isolation structure.

[0142] According to one embodiment, a semiconductor device includes: an interlayer dielectric, a first source / drain region of a first device, a second source / drain region of a second device, an isolation region, and a contact. The interlayer dielectric includes a first dielectric material. The first source / drain region of the first device is embedded in the interlayer dielectric. The second source / drain region of the second device is embedded in the interlayer dielectric. The isolation region includes a second dielectric material embedded in the interlayer dielectric and is disposed between the first device and the second device. The contact is connected to the first source / drain region via a first portion of a contact etch stop layer and to the second source / drain region via a second portion of the contact etch stop layer. The contact etch stop layer includes a third dielectric material different from the second dielectric material. In one embodiment, the second dielectric material includes silicon nitride. In one embodiment, the third dielectric material includes silicon carbonitride. In one embodiment, the first device is an NMOS finFET device. In one embodiment, the second device is a PMOS finFET device.

[0143] The foregoing description outlines components of various embodiments, enabling those skilled in the art to better understand this disclosure from all aspects. Those skilled in the art will understand that they can readily design or modify other processes and structures based on this disclosure to achieve the same purpose and / or the same advantages as the various embodiments described herein. Those skilled in the art will also understand that these equivalent configurations do not depart from the inventive spirit and scope of this disclosure, and that various changes, substitutions, or modifications can be made to this disclosure without departing from its inventive spirit and scope.

Claims

1. A method for manufacturing a semiconductor device, comprising: A gate electrode is formed, and a first dielectric material is adjacent to the gate electrode; A gap is formed in the gate electrode and in the first dielectric material, the gap separating the gate electrode into a first cleaved gate electrode and a second cleaved gate electrode; The gap is filled with an isolation region having a first portion that electrically isolates the first diced gate electrode from the second diced gate electrode, and the isolation region also having a second portion embedded in the first dielectric material. The isolation region has a third portion below a bottom surface of the first dielectric material and has a non-uniform width; An opening is etched in the first dielectric material, and a first portion of a contact etch stop layer is exposed through the opening, and a second portion of the contact etch stop layer is exposed through the opening. A sidewall of the isolation region physically contacts the contact etch stop layer. The isolation region is disposed between the first portion and the second portion of the contact etch stop layer. The step of etching the opening in the first dielectric material also etches the second portion of the isolation region so that a top surface of the first portion of the isolation region is below the first portion of the contact etch stop layer. Remove the first portion of the contact etch stop layer and expose a first source / drain region through the opening. The contact etch stop layer includes a second dielectric material that is different from the first dielectric material. Remove the second portion of the contact etch stop layer and expose a second source / drain region through the opening; as well as A contact is formed in the opening that connects the first source / drain region and the second source / drain region.

2. The manufacturing method of claim 1, wherein etching the isolation region includes recessing the isolation region to a depth below the first portion and the second portion of the contact etch stop layer.

3. The manufacturing method of claim 2, wherein etching the opening in the first dielectric material comprises: After the isolation area is recessed, the first dielectric material is etched at a certain time.

4. The manufacturing method of claim 3, wherein performing the timing etching comprises: A physical etching process is performed using a first beam energy and sustained for a first time period and with a process gas.

5. The manufacturing method of claim 4, wherein removing the first portion and the second portion of the contact etch stop layer comprises: After the first time period, a second beam energy is used and sustained for a second time period with the process gas to continue the physical etching process, and the second beam energy is greater than the first beam energy.

6. The manufacturing method of claim 5, wherein continuing the physical etching process further includes using argon as the process gas, and the second dielectric material of the contact etch stop layer is silicon carbonitride.

7. The manufacturing method of claim 4, wherein removing the first portion and the second portion of the contact etch stop layer includes performing a wet etching after the first time period.

8. A method for manufacturing a semiconductor device, comprising: A layer of inter-dielectric material is deposited over a first source / drain region of a first fin field-effect transistor and a second source / drain region of a second fin field-effect transistor; A gate electrode is formed, and the gate electrode is adjacent to the first source / drain region of the first fin field-effect transistor. An opening is formed that extends through the gate electrode and at least partially through the interlayer dielectric, and the opening is filled with an isolation structure; A cavity is formed in the interlayer dielectric to expose the isolation structure and a second dielectric material is exposed through the cavity. One sidewall of the isolation structure is physically in contact with the interlayer dielectric, and the exposed second dielectric material is above the exposed isolation structure in the cavity, and the second dielectric material is different from a dielectric material of the isolation structure. After exposing the isolation structure, a first portion and a second portion of the exposed second dielectric material are removed to expose the first source / drain region of the first fin field-effect transistor and the second source / drain region of the second fin field-effect transistor via the cavity. The top surface of the exposed isolation structure is below the top surface of the first source / drain region and the top surface of the second source / drain region. and A conductive material is deposited in the cavity to form a contact plug connecting the first source / drain region and the second source / drain region.

9. The manufacturing method of claim 8, wherein forming the cavity comprises performing the timed physical etching of the interlayer dielectric using an inert process gas for timed physical etching.

10. The manufacturing method of claim 9, wherein the isolation structure comprises a material having a first group of elements, and the second dielectric material comprises the first group of elements and at least one other element.

11. The manufacturing method of claim 9, wherein performing the timing physical etching includes performing an ion beam etching using a first process voltage to form the cavity.

12. The manufacturing method of claim 11, wherein removing the first portion and the second portion of the second dielectric material further comprises performing an ion beam etching using a second process voltage to remove the first portion and the second portion of the second dielectric material, wherein the second process voltage is greater than the first process voltage.

13. The manufacturing method of claim 11, wherein removing the first portion and the second portion of the second dielectric material further comprises using a wet etching process.

14. The manufacturing method of claim 13, wherein performing the wet etching includes using an etchant having a selective ratio to silicon carbonitride.

15. The manufacturing method of claim 14, further comprising using an etchant having a selective ratio to silicon nitride to recess the isolation structure.

16. A method for manufacturing a semiconductor device, comprising: A first source / drain region of a first device is formed on a substrate; Forming a second source / drain region for a second device; An interlayer dielectric is formed, the interlayer dielectric comprising a first dielectric material surrounding the first source / drain region and surrounding the second source / drain region; An opening is formed in the interlayer dielectric, and the opening is filled with an isolation region comprising a second dielectric material, wherein the isolation region extends from a top surface of the first dielectric material through a bottom surface of the first dielectric material, and a sidewall of the isolation region physically contacts the interlayer dielectric; and A contact is formed, which is connected to the first source / drain region via a first portion of a contact etch stop layer and to the second source / drain region via a second portion of the contact etch stop layer. The contact etch stop layer includes a third dielectric material different from the second dielectric material. One sidewall of the isolation region physically contacts the contact etch stop layer. At a first plane, the contact directly covers and contacts the isolation region. The top surface of the first source / drain region is located on a second plane; The topmost surface of the second source / drain region is located in the second plane; or The topmost surface of the first source / drain region and the topmost surface of the second source / drain region are located on the second plane. Furthermore, the first plane is closer to the substrate than the second plane.

17. The manufacturing method of claim 16, wherein the second dielectric material comprises silicon nitride.

18. The manufacturing method of claim 17, wherein the third dielectric material comprises silicon carbonitride.

19. The manufacturing method of claim 16, wherein the first device is an N-type metal-oxide-semiconductor fin field-effect transistor device.

20. The manufacturing method of claim 19, wherein the second device is a P-type metal-oxide-semiconductor fin field-effect transistor device.

21. A semiconductor device, comprising: An interlayer dielectric, including a first dielectric material; A first source / drain region of a first device is embedded in the interlayer dielectric; A second source / drain region of a second device is embedded in the interlayer dielectric; An isolation region, including a second dielectric material embedded in the interlayer dielectric, and disposed between the first device and the second device; and A contact material is connected to the first source / drain region via a first portion of a contact etch stop layer and to the second source / drain region via a second portion of the contact etch stop layer, wherein the contact etch stop layer comprises a third dielectric material different from the second dielectric material. The isolation region extends through the bottom surface of the contact etch stop layer.

22. The semiconductor device of claim 21, wherein the second dielectric material comprises silicon nitride.

23. The semiconductor device of claim 22, wherein the third dielectric material comprises silicon carbonitride.

24. The semiconductor device of claim 21, wherein the first device is an N-type metal-oxide-semiconductor fin field-effect transistor device.

25. The semiconductor device of claim 24, wherein the second device is a P-type metal-oxide-semiconductor fin field-effect transistor device.

26. The semiconductor device of claim 21, wherein, in a cross-sectional view, a lowermost surface of the contact contacts an upper surface of the isolation region.

27. The semiconductor device of claim 21, wherein a height of the isolation region has a height in the range between 24 nm and 36 nm.

28. A semiconductor device, comprising: A first source / drain region is located above a substrate; A second source / drain region is located above the substrate; A contact etch stop layer is placed above the first source / drain region and the second source / drain region; A first dielectric layer is located above the first source / drain region and the second source / drain region, and the first dielectric layer includes a first material; A conductive component extends through the first dielectric layer to the first source / drain region and the second source / drain region; and A second dielectric layer extends from the conductive component through the first dielectric layer, and the second dielectric layer includes a second material; The second dielectric layer extends through the bottom surface of the contact etch stop layer.

29. The semiconductor device of claim 28, further comprising a third dielectric layer inserted between the first dielectric layer and the substrate, wherein the second dielectric layer extends only partially through the third dielectric layer.

30. The semiconductor device of claim 29, further comprising a fourth dielectric layer along the sidewalls of the first source / drain region and the second source / drain region, wherein the fourth dielectric layer contacts the third dielectric layer.

31. The semiconductor device of claim 30, wherein the second dielectric layer extends into the third dielectric layer by a distance between 36 nm and 44 nm.

32. The semiconductor device of claim 30, wherein the fourth dielectric layer and the third dielectric layer are made of different materials.

33. The semiconductor device of claim 30, wherein the second dielectric layer directly contacts the conductive component, the first dielectric layer, the third dielectric layer, and the fourth dielectric layer.

34. The semiconductor device of claim 28, wherein the first source / drain region is an n-type region and the second source / drain region is a p-type region.

35. A semiconductor device, comprising: A first source / drain region of a first device; A second source / drain region of a second device; A contact etch stop layer is provided above the first source / drain region and the second source / drain region, and the contact etch stop layer includes a first dielectric material; An interlayer dielectric includes a second dielectric material surrounding the first source / drain region and surrounding the second source / drain region; An isolation region comprising a third dielectric material embedded in the interlayer dielectric and disposed between the first device and the second device, wherein a sidewall of the isolation region physically contacts the interlayer dielectric and the contact etch stop layer, wherein the third dielectric material is different from the first dielectric material; and A contact extends through the contact etch stop layer and is electrically connected to the first source / drain region and the second source / drain region. In a cross-sectional view, the bottom surface of the contact is below a top surface of the first source / drain region and a top surface of the second source / drain region. In the cross-sectional view, the bottom surface of the contact is above a top surface of the isolation region and physically contacts the top surface of the isolation region. The isolation region extends through the bottom surface of the contact etch stop layer.

36. The semiconductor device of claim 35, wherein the third dielectric material comprises silicon nitride.

37. The semiconductor device of claim 36, wherein the first dielectric material comprises silicon carbonitride.

38. The semiconductor device of claim 35, wherein the first device is an N-type metal-oxide-semiconductor fin field-effect transistor.

39. The semiconductor device of claim 38, wherein the second device is a P-type metal-oxide-semiconductor fin field-effect transistor.

40. The semiconductor device of claim 35, further comprising a trench isolation overlying the interlayer dielectric, wherein the isolation region extends partially into the trench isolation.

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