Semiconductor structure and method for manufacturing the same

Abstract

The semiconductor structure and manufacturing method disclosed herein first form electrical connectors on a circuit substrate, then define predetermined locations for vias on a printed layer on a redistribution layer by transfer printing. The electrical connection layer is then repositioned at these predetermined locations. The circuit substrate containing the electrical connectors is then joined to the redistribution layer containing the electrical connection layer. The electrical connection layer is then electrically connected to the electrical connectors via reflow soldering. By accurately defining the electrical contact points between the redistribution layer and the circuit substrate, the electrical connection between the redistribution layer and the circuit substrate is achieved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] Embedded semiconductor chip structures are increasingly being used in system-on-package (SIP) applications, such as a-EASI (Advanced Embedded Active System Integration) in PMIC (Power Management IC) applications. Currently, in the embedded chip structure manufacturing process, the chip is embedded in a dielectric material, then a laser process is used to expose the chip's pads. A redistribution layer (RDL) is then electroplated, and vias are used to connect the RDL to the embedded chip structure.

[0003] When making via holes, laser drilling can be used, but due to the difficulty in controlling the laser energy, inconsistent hole depth may occur, such as Figure 1 As shown ( Figure 1 Schematic diagram of the phenomenon of inconsistent hole depth in the prior art. The inconsistent hole depth will affect the electrical connection performance between the redistribution layer and the embedded chip structure, reducing the product yield. Summary of the Invention

[0004] The present disclosure provides a semiconductor structure and a method for manufacturing the same.

[0005] In a first aspect, the present disclosure provides a semiconductor structure, which includes: a redistribution layer; an insulating connection layer, arranged on the redistribution layer, the insulating connection layer is provided with a via, and an electrical connection layer is provided on the via; a circuit substrate, arranged on the insulating connection layer, the circuit substrate includes a circuit layer, an electronic component, a first electrical connector, and a second electrical connector, the electronic component is arranged on the first electrical connector, the circuit layer is arranged on the second electrical connector, and the circuit layer is arranged on the electronic component; the circuit substrate is embedded in the adhesive layer, the adhesive layer is embedded in the insulating connection layer, the first electrical connector is electrically connected to the electrical connection layer, and the second electrical connector is electrically connected to the electrical connection layer.

[0006] In some optional embodiments, the electrical connection layer includes an adhesive layer, a welding layer, and a solder layer arranged in sequence from bottom to top.

[0007] In some optional embodiments, the second electrical connector includes a conductive layer, a barrier layer, and a second conductive column arranged in sequence from bottom to top.

[0008] In some optional embodiments, the conductive hole is a second conductive hole, and the second conductive hole includes a first inverted truncated cone hole and a second inverted truncated cone hole arranged in sequence from bottom to top.

[0009] In some optional embodiments, the diameter of the second conductive pillar is between 200 micrometers and 500 micrometers.

[0010] In some optional embodiments, the second conductive pillar is an inverted truncated cone conductive pillar; and the ratio of the diameter of the lower surface of the second conductive pillar to the aperture of the lower opening of the second inverted truncated cone hole is between 0.8 and 1.

[0011] In some optional embodiments, the ratio of the diameter of the first plane of the lower surface of the second conductive pillar at the height of the second inverted truncated cone hole to the aperture of the upper opening of the second inverted truncated cone hole is between 0.8 and 1.

[0012] In some optional embodiments, the ratio of the sidewall angle of the second conductive pillar to the sidewall angle of the second frustum-cone hole is between 0.8 and 1.2.

[0013] In some optional embodiments, the first electrical connector includes a conductive layer, a barrier layer, a first conductive column, and a pad arranged in sequence from bottom to top.

[0014] In some optional embodiments, the conductive hole is a first conductive hole, and the first conductive hole includes a third inverted frustum hole and a cylindrical hole arranged in sequence from bottom to top.

[0015] In some optional embodiments, the diameter of the first conductive pillar is between 20 micrometers and 200 micrometers.

[0016] In some optional embodiments, the first conductive pillar is a cylindrical conductive pillar; and a ratio of a diameter of the first conductive pillar to a diameter of the cylindrical hole is between 0.8 and 1.

[0017] In some optional embodiments, the lower surface of the first electrical connector and the lower surface of the second electrical connector are at different horizontal positions.

[0018] In some optional embodiments, the semiconductor structure further includes: an external electrical connector, and the redistribution layer is disposed on the external electrical connector.

[0019] In a second aspect, the present disclosure provides a method for manufacturing a semiconductor structure, the method comprising: etching a metal layer to form a circuit layer and a second conductive column; placing electronic components and pads on the circuit layer; forming a first conductive column on the pad; forming a release film covering the circuit layer, the second conductive column, the electronic components and the first conductive column to obtain a transfer mold; forming a redistribution layer on a carrier, and forming a printing layer on the redistribution layer; transferring a transfer pattern of the transfer mold to the printing layer to form an insulating connection layer, the transfer pattern being used to define a predetermined position of a via; forming a via on the insulating connection layer, and forming an electrical connection layer on the via; removing the release film of the transfer mold, and sequentially forming a barrier layer and a conductive layer on the first conductive column and the second conductive column to obtain a circuit substrate; the circuit substrate is bonded to the insulating connection layer through an adhesive layer; the electrical connection layer is electrically connected to the first electrical connector and the second electrical connector through reflow soldering.

[0020] In some optional embodiments, forming an electrical connection layer on the via hole includes: sequentially forming an adhesive layer, a welding layer, and a solder layer on the via hole; the adhesive layer, the welding layer, and the solder layer together form the electrical connection layer.

[0021] In some optional embodiments, the thickness of the release film is equal to the thickness of the electrical connection layer.

[0022] In some optional embodiments, the method further includes: removing the carrier; and forming external electrical connections on the redistribution layer.

[0023] How to ensure that the redistribution layer can be electrically connected to the chips and circuit layers in the circuit substrate is a technical problem to be solved by the present disclosure. The semiconductor structure and manufacturing method provided by the present disclosure first form electrical connectors on the circuit substrate, then define the predetermined positions of the vias on the printing layer on the redistribution layer by transfer printing, and reconfigure the electrical connection layer at this predetermined position. The electrical connector including the conductive column is joined to the redistribution layer including the electrical connection layer, and the electrical connection layer is electrically connected to the electrical connector by reflow soldering. By accurately defining the electrical contact points between the redistribution layer and the circuit substrate, the electrical connection between the redistribution layer and the circuit substrate is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Other features, objects and advantages of the present disclosure will become more apparent from a reading of the detailed description of non-limiting embodiments made with reference to the following drawings:

[0025] Figure 1 This is a schematic diagram of the phenomenon of inconsistent hole depth in the prior art;

[0026] Figure 2 is a schematic structural diagram of an embodiment of a semiconductor structure according to the present disclosure;

[0027] Figure 3 is a schematic structural diagram of a second via and a second electrical connector according to the present disclosure;

[0028] Figure 4 is a schematic structural diagram of a first via and a first electrical connector according to the present disclosure;

[0029] Figure 5 is a schematic diagram of horizontal positions of the lower surface of the first electrical connector and the lower surface of the second electrical connector according to the present disclosure;

[0030] Figure 6 is a schematic structural diagram of another embodiment of a semiconductor structure according to the present disclosure;

[0031] Figure 7 is a schematic structural diagram of another embodiment of a semiconductor structure according to the present disclosure;

[0032] Figures 8A to 8K A schematic structural diagram of a semiconductor structure during fabrication according to the present disclosure.

[0033] Explanation of symbols:

[0034] 1-rewiring layer, 2-insulating connection layer, 21-conductive hole, 211-second conductive hole, 2111-first inverted truncated cone hole, 2112-second inverted truncated cone hole, 212-first conductive hole, 2121-third inverted truncated cone hole, 2122-cylindrical hole, 22-electrical connection layer, 221-adhesive layer, 222-soldering layer, 223-soldering layer, 3-circuit substrate, 31-circuit layer, 32-electronic component, 33-first electrical connector, 331-conductive layer, 332-barrier layer, 333-first conductive column, 334-pad, 34-second electrical connector, 341-second conductive column, 4-bonding Layer, 5-external electrical connector, 6-metal layer, 7-printing layer, 71-predetermined position of the via, 8-transfer mold, 81-release film, 9-carrier, 10-passive component, H-height of the second inverted frustum hole, D1-diameter of the lower surface of the second conductive column, D2-aperture of the lower opening of the second inverted frustum hole, D3-diameter of the first plane, D4-aperture of the upper opening of the second inverted frustum hole, D5-diameter of the first conductive column, D6-aperture of the cylindrical hole, α-sidewall angle of the second conductive column, β-sidewall angle of the second inverted frustum hole, A-sidewall angle of the second inverted frustum hole, B-lower surface of the second electrical connector. DETAILED DESCRIPTION

[0035] The following describes specific embodiments of the present disclosure in conjunction with the accompanying drawings and examples. Those skilled in the art will readily understand the technical problems solved by the present disclosure and the technical effects produced by the present disclosure through the contents of this specification. It should be understood that the specific embodiments described herein are merely for the purpose of explaining the relevant invention and are not intended to limit the invention. Furthermore, for ease of description, only portions relevant to the relevant invention are shown in the accompanying drawings.

[0036] It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of the specification are only used to match the contents recorded in the specification for the understanding and reading of those skilled in the art, and are not used to limit the limiting conditions for the implementation of the present disclosure. Therefore, they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed in the present disclosure without affecting the efficacy and purpose that can be achieved by the present disclosure. At the same time, terms such as "on", "first", "second" and "one" quoted in this specification are only for the convenience of description and are not used to limit the scope of the implementation of the present disclosure. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present disclosure without substantially changing the technical content.

[0037] In addition, the embodiments and features of the embodiments of the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0038] Please refer to Figure 2 , Figure 2 FIG. 1 shows a schematic structural diagram of an embodiment of a semiconductor structure according to the present disclosure. Figure 2 As shown, the semiconductor structure may include: a redistribution layer 1, an insulating connection layer 2, a circuit substrate 3, and an adhesive layer 4. The insulating connection layer 2 is provided on the redistribution layer 1, the circuit substrate 3 is provided on the insulating connection layer 2, the circuit substrate 3 is embedded in the adhesive layer 4, the adhesive layer 4 is embedded in the insulating connection layer 2, the first electrical connector 33 is electrically connected to the electrical connection layer 22, and the second electrical connector 34 is electrically connected to the electrical connection layer 22.

[0039] Various wires, through-holes, buried vias or blind vias can be provided in the redistribution layer 1 to achieve circuit connection. It should be noted that the size or direction of the through-holes, buried vias or blind vias is not specifically limited here. If through-holes, buried vias or blind vias are provided, the through-holes, buried vias or blind vias can be filled with conductive materials such as metals or metal alloys, or contain conductive materials such as metals or metal alloys. Here, the metal can be, for example, gold (Au), silver (Ag), aluminum (Al), copper (Cu) or their alloys.

[0040] The insulating connection layer 2 may include a dielectric material. The dielectric material may be an organic material, such as polyamide (PA), polyimide (PI), epoxy resin, FR-4 epoxy glass cloth laminate, PP (PrePreg, prepreg material or semi-cured resin, prepreg), ABF (Ajinomoto Build-up Film), etc. The dielectric material may also be an inorganic material, such as silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc.

[0041] The insulating connection layer 2 may be provided with a via hole 21, and an electrical connection layer 22 is provided on the via hole 21. The electrical connection layer 22 may be used for electrical connection and may include a welding material.

[0042] The circuit substrate 3 may include a circuit layer 31, an electronic component 32, a first electrical connector 33, and a second electrical connector 34. The electronic component 32 may be disposed on the first electrical connector 33, the circuit layer 31 may be disposed on the second electrical connector 34, and the circuit layer 31 may be disposed on the electronic component 32. The circuit layer 31 may be, for example, a lead frame. The electronic component 32 may be a chip with various functions, such as a PMIC chip. The first electrical connector 33 and the second electrical connector 34 may be used for electrical connection.

[0043] The adhesive layer 4 may be a structural layer that acts as an adhesive between the circuit substrate 3 and the redistribution layer 1 , and may be made of an adhesive material such as ABF glue.

[0044] In some optional embodiments, such as Figure 2 As shown, the electrical connection layer 22 may include an adhesive layer 221 , a welding layer 222 and a welding layer 223 arranged in sequence from bottom to top.

[0045] The adhesive layer 221 can provide better adsorption, and can be made of titanium, for example.

[0046] The soldering layer 222 may have the function of providing conductivity so that the electroplating of the soldering layer 223 can proceed smoothly, and may be made of copper, for example.

[0047] The solder layer 223 can be used for soldering and connection, for example, solder material can be used.

[0048] Please refer to Figure 3 , Figure 3 A schematic structural diagram of the first via 211 and the second electrical connector 34 according to the present disclosure is shown.

[0049] In some optional embodiments, such as Figure 3As shown, the second electrical connection member 34 may include a conductive layer 331 , a barrier layer 332 , and a second conductive column 341 arranged in sequence from bottom to top.

[0050] The conductive layer 331 can be used for electrical connection, and for example, can be made of conductive materials such as metal or metal alloy.

[0051] The barrier layer 332 may be used to prevent diffusion between the conductive layer 331 and the second conductive pillar 341 , and may be made of titanium, for example.

[0052] The second conductive pillar 341 can provide a better conductive function and the position of the electrical contact point can be defined by defining the height of the second conductive pillar 341 .

[0053] In some optional embodiments, such as Figure 3 As shown, the conductive hole 21 is a first conductive hole 211 , and the first conductive hole 211 may include a first inverted truncated cone hole 2111 and a second inverted truncated cone hole 2112 sequentially arranged from bottom to top.

[0054] Here, the aperture D2 of the lower opening of the second frustum-shaped hole may be larger than the aperture of the upper opening of the first frustum-shaped hole 2111 .

[0055] In some optional embodiments, the diameter of the second conductive pillar 341 may be between 200 micrometers and 500 micrometers.

[0056] The circuit layer 31 may be disposed on the second electrical connector 34 , that is, the diameter of the second conductive pillar 341 may be set according to the size of the circuit layer 31 . Generally, the diameter of the second conductive pillar 341 may be smaller than the line width of the circuit layer 31 .

[0057] In some optional embodiments, such as Figure 3 As shown, the second conductive pillar 341 may be an inverted truncated cone conductive pillar; and the ratio of the diameter D1 of the lower surface of the second conductive pillar to the aperture D2 of the lower opening of the second inverted truncated cone hole is between 0.8 and 1.

[0058] In some optional embodiments, such as Figure 3 As shown, the ratio of the diameter D3 of the first plane of the lower surface of the second conductive pillar 341 at the height of the second frustum-conical hole 211 to the aperture D4 of the upper opening of the second frustum-conical hole can be between 0.8 and 1.

[0059] In some optional embodiments, such as Figure 3 As shown, the ratio of the sidewall angle α of the second conductive pillar to the sidewall angle β of the second frustum-cone hole may be between 0.8 and 1.2.

[0060] Here, the second conductive pillar 341 and the first conductive hole 211 can be a matching combination to achieve a tight connection between the two. The sizes and shapes of the matching parts of the two can correspond. Specifically, the size of the lower surface of the second conductive pillar 341 can match the size of the lower opening of the second inverted frustum conical hole 2112. The size of the first plane of the lower surface of the second conductive pillar 341 at the height of the second inverted frustum conical hole 2112 can match the size of the upper opening of the second inverted frustum conical hole 2112. The sidewall angle α of the second conductive pillar can match the sidewall angle β of the second inverted frustum conical hole.

[0061] Please refer to Figure 4 , Figure 4 2 is a schematic structural diagram of the first via 212 and the first electrical connector 33 according to the present disclosure.

[0062] In some optional embodiments, such as Figure 4 As shown, the first electrical connection member 33 may include a conductive layer 331 , a barrier layer 332 , a first conductive column 333 and a pad 334 arranged in sequence from bottom to top.

[0063] The conductive layer 331 can be used for electrical connection, and for example, can be made of conductive materials such as metal or metal alloy.

[0064] The barrier layer 332 may be used to prevent diffusion between the conductive layer 331 and the first conductive pillar 333 , and may be made of titanium, for example.

[0065] The first conductive pillar 333 can provide better electrical conductivity and the position of the electrical contact point can be defined by defining the height of the first conductive pillar 333 .

[0066] The pad 334 can be used to achieve electrical connection between the electronic component 32 and the first conductive pillar 333 , and can be made of aluminum, for example.

[0067] In some optional embodiments, such as Figure 4 As shown, the conductive hole 21 may be a first conductive hole 212 , and the first conductive hole 212 may include a third inverted frustum hole 2121 and a cylindrical hole 2122 sequentially arranged from bottom to top.

[0068] In some optional embodiments, the diameter D5 of the first conductive pillar may be between 20 micrometers and 200 micrometers.

[0069] The pad 334 may be disposed on the first conductive column 333 , that is, the diameter of the first conductive column 333 may be set according to the size of the pad 334 . Generally, the diameter of the first conductive column 333 may be smaller than the width of the pad 334 .

[0070] In some optional embodiments, such as Figure 4As shown, the first conductive pillar 333 may be a cylindrical conductive pillar; and the ratio of the diameter D5 of the first conductive pillar to the aperture D6 of the cylindrical hole may be between 0.8 and 1.

[0071] Here, the first conductive pillar 333 and the first conductive hole 212 can be a matching combination to achieve a tight combination of the two. The sizes and shapes of the matching parts of the two can correspond to each other. Specifically, the diameter D5 of the first conductive pillar matches the aperture D6 of the cylindrical hole.

[0072] Please refer to Figure 5 , Figure 5 3 is a schematic diagram illustrating horizontal positions of the lower surface of the first electrical connector 33 and the lower surface of the second electrical connector 34 according to the present disclosure.

[0073] In some optional embodiments, such as Figure 5 As shown, the horizontal positions of the lower surface A of the first electrical connector and the lower surface B of the second electrical connector may be different.

[0074] Because the lower surfaces of the circuit layer 31 and the electronic components 32 in the circuit substrate 3 are at different horizontal positions, and the first electrical connector 33 and the second electrical connector 34 are at different heights, the lower surfaces of the first electrical connector 33 and the second electrical connector 34 are at different horizontal positions. Correspondingly, the electrical connection layer 22 disposed above the first conductive via 212 in the insulating interposer and the electrical connection layer 22 disposed above the first conductive via 211 are also at different horizontal positions. By accurately defining the positions of the electrical contacts, the semiconductor structure can have electrical contacts at different horizontal positions, ensuring electrical connection between the redistribution layer 1 and the circuit substrate 3.

[0075] In some optional embodiments, the semiconductor structure may further include an external electrical connection 5 . The redistribution layer 1 may be provided on the external electrical connection 5 .

[0076] The external electrical connector 5 can be used to realize electrical connection between the semiconductor structure and the outside, and can be, for example, a solder ball.

[0077] Please refer to Figure 6 , Figure 6 is a structural schematic diagram of yet another embodiment of a semiconductor structure according to the present disclosure.

[0078] In some optional embodiments, such as Figure 6 As shown, the semiconductor structure may further include passive components 10. The passive components 10 may be embedded in the adhesive layer 4 and / or disposed on the redistribution layer 1. This allows embedding of electronic components with greater functionality and quantity, thereby integrating a high-density semiconductor structure.

[0079] Please refer to Figure 7 , Figure 7is a structural schematic diagram of yet another embodiment of a semiconductor structure according to the present disclosure.

[0080] In some optional embodiments, such as Figure 7 As shown, the semiconductor structure may be a double-sided package module structure (Double Side Module, DSM).

[0081] The semiconductor structure provided by the present disclosure first forms a second electrical connector 34 on the circuit layer 31 and a first electrical connector 33 on the electronic component 32. The predetermined location of the via 21 is then defined on the printing layer 7 on the redistribution layer 1 by transfer printing. The electrical connection layer 22 is then repositioned at this predetermined location. The circuit substrate 3 containing the circuit layer 31 and the electronic component 32 is then bonded to the redistribution layer 1. The electrical connection layer 22 is then electrically connected to the first electrical connector 33 and the second electrical connector 34 via reflow soldering. The electrical connection between the redistribution layer 1 and the circuit substrate 3 is achieved by accurately defining the electrical contact points between the redistribution layer 1 and the circuit substrate 3 on the insulating connection layer 2.

[0082] Figures 8A to 8K Schematic diagram of the structure during the manufacturing process of the semiconductor structure according to the present disclosure. In order to better understand the various aspects of the present disclosure, the figures have been simplified.

[0083] Please refer to Figure 8A , providing a metal layer 6.

[0084] Please refer to Figure 8B , the metal layer 6 is etched to form a circuit layer 31 and a second conductive column 341 , an electronic component 32 and a pad 334 are placed on the circuit layer 31 , and a first conductive column 333 is formed on the pad 334 .

[0085] Please refer to Figure 8C , forming a release film 81 covering the circuit layer 31 , the second conductive pillar 341 , the electronic component 32 and the first conductive pillar 333 , and obtaining a transfer mold 8 .

[0086] In some optional embodiments, the thickness of the release film 81 is equal to the thickness of the electrical connection layer 22 .

[0087] Please refer to Figure 8D , a redistribution layer 1 is formed on the carrier 9 , and a printing layer 7 is formed on the redistribution layer 1 .

[0088] Please refer to Figure 8E , the transfer pattern of the transfer mold 8 is transferred to the printing layer 7 to form the insulating connection layer 2 , the transfer pattern is used to define the predetermined position of the conductive hole 21 , and the conductive hole 21 is formed on the insulating connection layer 2 .

[0089] Please refer to Figure 8F, an electrical connection layer 22 is formed on the via hole 21 .

[0090] In some optional embodiments, an electrical connection layer 22 is formed on the via 21 , including: sequentially forming an adhesive layer 221 , a welding layer 222 , and a welding layer 223 on the via 21 ; the adhesive layer 221 , the welding layer 222 , and the welding layer 223 together form the electrical connection layer 22 .

[0091] Please refer to Figure 8G , remove the release film 81 of the transfer mold 8.

[0092] Please refer to Figure 8H A barrier layer 332 and a conductive layer 331 are sequentially formed on the first conductive pillar 333 and the second conductive pillar 341 to obtain a circuit substrate 3 .

[0093] Please refer to Figure 8I , the circuit substrate 3 is bonded to the insulating connection layer 2 through the adhesive layer 4.

[0094] Please refer to Figure 8J The electrical connection layer 22 is electrically connected to the first electrical connection member 33 and the second electrical connection member 34 by reflow soldering.

[0095] Please refer to Figure 8K In some optional embodiments, the method may further include first removing the carrier 9 and then forming an external electrical connection 5 on the redistribution layer 1 .

[0096] The method for manufacturing a semiconductor structure provided by the present disclosure avoids the use of laser drilling to form via holes, thereby avoiding the phenomenon of electrical disconnection between the redistribution layer 1 and the circuit substrate 3 due to inconsistent hole depths of the via holes.

[0097] By first forming a second electrical connector 34 on the circuit layer 31 and a first electrical connector 33 on the electronic component 32, and then defining the predetermined position of the conductive hole 21 on the printing layer 7 on the redistribution layer 1 by transfer, the electrical contacts between the redistribution layer 1 and the circuit layer 31 in the circuit substrate 3, and the electrical contacts between the redistribution layer 1 and the electronic component 32 in the circuit substrate 3 are accurately defined on the insulating connection layer 2, respectively, to achieve electrical connection between the redistribution layer 1 and the circuit substrate 3.

[0098] Although the present disclosure has been described and illustrated with reference to specific embodiments of the present disclosure, these descriptions and illustrations do not limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalent components may be substituted within the embodiments without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. Due to variables in the manufacturing process, etc., there may be differences between the technical reproduction in the present disclosure and the actual implementation. There may be other embodiments of the present disclosure that are not specifically described. The description and illustrations should be regarded as illustrative, not restrictive. Modifications may be made to adapt specific circumstances, materials, compositions of matter, methods or processes to the objectives, spirit and scope of the present disclosure. All such modifications fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a specific order, it should be understood that these operations can be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the present disclosure.

Claims

1. A semiconductor structure comprising: Rewiring layer; an insulating connection layer, disposed on the redistribution layer, the insulating connection layer being provided with a conducting hole, and an electrical connection layer being provided on the conducting hole; a circuit substrate, disposed on the insulating connection layer, the circuit substrate comprising a circuit layer, an electronic component, a first electrical connector, and a second electrical connector, the electronic component being disposed on the first electrical connector, the circuit layer being disposed on the second electrical connector, and the circuit layer being disposed on the electronic component; The circuit substrate is embedded in the adhesive layer, the adhesive layer is embedded in the insulating connection layer, the first electrical connector is electrically connected to the electrical connection layer, and the second electrical connector is electrically connected to the electrical connection layer.

2. The semiconductor structure according to claim 1, wherein The electrical connection layer includes an adhesive layer, a welding layer and a solder layer which are sequentially arranged from bottom to top.

3. The semiconductor structure according to claim 1 or 2, wherein: The second electrical connection member includes a conductive layer, a barrier layer, and a second conductive column arranged in sequence from bottom to top.

4. The semiconductor structure according to claim 3, wherein: The conductive hole is a second conductive hole, and the second conductive hole includes a first inverted truncated cone hole and a second inverted truncated cone hole arranged in sequence from bottom to top.

5. The semiconductor structure according to claim 3, wherein The first electrical connection member includes the conductive layer, the barrier layer, a first conductive column, and a pad arranged in sequence from bottom to top. The semiconductor structure according to claim 5 , wherein: The conductive hole is a first conductive hole, and the first conductive hole includes a third inverted frustum hole and a cylindrical hole arranged in sequence from bottom to top.

7. The semiconductor structure according to claim 1, wherein The lower surface of the first electrical connector and the lower surface of the second electrical connector are at different horizontal positions.

8. The semiconductor structure according to claim 1, wherein The semiconductor structure further comprises: An external electrical connector, the redistribution layer is disposed on the external electrical connector.

9. A method of manufacturing a semiconductor structure, comprising: Etching the metal layer to form a circuit layer and a second conductive pillar; placing electronic components and pads on the circuit layer; forming a first conductive column on the pad; forming a release film covering the circuit layer, the second conductive pillar, the electronic component, and the first conductive pillar to obtain a transfer mold; forming a redistribution layer on a carrier, and forming a printing layer on the redistribution layer; Transferring the transfer pattern of the transfer mold onto the substrate to form an insulating connection layer, wherein the transfer pattern is used to define a predetermined position of a via hole; forming a via hole on the insulating connection layer, and forming an electrical connection layer on the via hole; removing the release film of the transfer mold, and sequentially forming a barrier layer and a conductive layer on the first conductive pillar and the second conductive pillar to obtain a circuit substrate; The circuit substrate is bonded to the insulating connection layer via an adhesive layer; The electrical connection layer is electrically connected to the first electrical connection member and the second electrical connection member through reflow soldering.

10. The method according to claim 9, wherein: The step of forming an electrical connection layer on the via hole comprises: forming an adhesive layer, a welding layer and a solder layer in sequence on the via hole; The adhesive layer, the welding layer and the solder layer together form the electrical connection layer; removing the carrier; External electrical connections are formed on the redistribution layer.

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