Semiconductor package device and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor package device and a manufacturing method thereof, by setting a spacer between the substrate and the FO layer, the connection possibility between the FO layer and the substrate can be improved in the case of large height variation (for example, uniformity greater than 20%) of the solder pad on the substrate surface and possible warping. And by connecting the FO layer and the substrate by using conductive holes instead of conductive pillars, since the fineness of the conductive holes (Conductive) is easier to control in the process than the conductive pillars (Pillar), the problems of cold welding, damage or deformation of the conductive pillars and reduction of the bonding area that may occur in the prior art by using conductive pillars are avoided. That is, the overall product yield can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor packaging technology, and more specifically to semiconductor packaging apparatus and manufacturing methods thereof. Background Technology

[0002] Currently, high-end products require an increasing number of substrate layers. For example, the FCBGA (Flip Chip Ball Grid Array) used in 5G (5th generation mobile networks) applications may have more than 12 substrate layers. To address this, FOSub (Fan-Out Substrate) substrates have emerged. These substrates primarily reduce the number of substrate layers by replacing some of the substrate circuitry layers with FO (Fan-Out) layers (also known as redistribution layers or fine-line layers). The FO layers are typically bonded to the substrate circuitry structure using adhesive. Summary of the Invention

[0003] This disclosure presents a semiconductor packaging apparatus and a method for manufacturing the same.

[0004] In a first aspect, this disclosure provides a semiconductor packaging apparatus, comprising:

[0005] A substrate having a first surface and a second surface opposite to the first surface, wherein an electrical connector disposed on the first surface is electrically connected to a lower electrical connector disposed on the second surface;

[0006] At least two spacers are disposed on the first surface, and the height of the spacers is greater than or equal to the height of the electrical connectors on each of the substrates;

[0007] An adhesive layer surrounds the first surface, the electrical connectors on the substrate, and each of the spacers;

[0008] A substrate redistribution layer is disposed on the adhesive layer and the spacer.

[0009] A conductive via is exposed on the upper surface of the redistribution layer of the substrate, extends toward the substrate, and contacts an electrical connector on the substrate.

[0010] In some alternative embodiments, the spacer has a material strength of 10 to 100 megapascals.

[0011] In some alternative embodiments, the spacer is bonded to the first surface by a non-conductive adhesive or a non-conductive film.

[0012] In some alternative implementations, the spacer is a cylindrical spacer or a cuboid spacer.

[0013] In some alternative implementations, the height of the cylindrical spacer is greater than twice the horizontal cross-sectional diameter of the cylindrical spacer, and the height of the cuboid spacer is greater than twice the side length of any horizontal cross-section of the rectangular spacer.

[0014] In some alternative embodiments, the horizontal cross-sectional diameter of the cylindrical spacer or the side length of any horizontal cross-section of the cuboid spacer is greater than twice the sum of the linewidth and spacing of the lines in the substrate redistribution layer, or greater than twice the sum of the linewidth and spacing of the electrical connectors on the substrate.

[0015] In some alternative implementations, the linewidth / spacing of the substrate redistribution layer is less than 2 / 2 micrometers, and the uniformity of the substrate redistribution layer is less than 5%.

[0016] In some alternative embodiments, the linewidth / spacing of the electrical connectors on the substrate is greater than 10 / 10 micrometers, and the uniformity of the height of the first surface is greater than 20%.

[0017] In some alternative embodiments, the semiconductor packaging device further includes a first bonding pad disposed on the upper surface of the substrate redistribution layer away from the substrate and electrically connected to the substrate redistribution layer.

[0018] In some alternative embodiments, the semiconductor packaging device further includes a chip disposed on the upper surface of the substrate redistribution layer and electrically connected to the first bonding pad.

[0019] In some alternative embodiments, a chip redistribution layer is provided in the direction of the chip near the substrate redistribution layer, and the chip is electrically connected to the first pad through the chip redistribution layer.

[0020] In some alternative implementations, the distance between the substrate redistribution layer and the first surface is less than 20 micrometers.

[0021] In some alternative embodiments, the adhesive layer is a stage B dielectric material.

[0022] In some alternative embodiments, the minimum horizontal distance between the spacer and the electrical connection on the substrate is greater than or equal to 5 micrometers, and the minimum horizontal distance between the spacer and the circuit pattern in the redistribution layer on the substrate is greater than or equal to 2 micrometers.

[0023] In some alternative embodiments, the number of spacers in the semiconductor packaging device, the yield strength and material strength of the spacers, the horizontal cross-sectional area of ​​the spacers, and the bonding force for bonding the substrate redistribution layer to the substrate satisfy the following formula:

[0024] Sy≤Fm / A(Formula 1)

[0025] Fm / (nA)≤Sp(Formula 2)

[0026] Wherein, Sy and Sp are the yield strength and material strength of the spacer, respectively, Fm is the bonding force for bonding the substrate redistribution layer to the substrate, n is the number of spacers in the semiconductor packaging device, and A is the horizontal cross-sectional area of ​​the spacer.

[0027] In some alternative embodiments, the bonding force for bonding the substrate redistribution layer to the substrate is 5 to 50 Newtons.

[0028] In some alternative implementations, the substrate redistribution layer includes at least one layer of wiring.

[0029] In some alternative embodiments, the semiconductor packaging device further includes a circuit pattern disposed on the upper surface of the substrate redistribution layer and electrically connected to the substrate redistribution layer.

[0030] In some alternative embodiments, the semiconductor packaging device further includes at least one of the following disposed on the adhesive layer: passive components, wire bonding.

[0031] In some alternative embodiments, the spacer includes a spacer core and a spacer coating surrounding the spacer core, the spacer coating being a metallic coating or a non-metallic coating.

[0032] In some alternative implementations, the height of the spacer is greater than or equal to 20 micrometers.

[0033] Secondly, this disclosure provides a method for manufacturing a semiconductor packaging device, comprising:

[0034] A substrate redistribution layer is bonded to a substrate via an adhesive layer to electrically connect the substrate redistribution layer to the substrate electrical connectors. The substrate has a first surface and a second surface opposite to the first surface. The substrate electrical connectors disposed on the first surface are electrically connected to the substrate lower electrical connectors disposed on the second surface. At least two spacers are disposed on the first surface, and the height of the spacers is greater than or equal to the height of each substrate electrical connector. A seed layer and a carrier are disposed on the upper surface of the substrate redistribution layer.

[0035] Remove the carrier board on the substrate redistribution layer and etch away the seed layer on the substrate redistribution layer;

[0036] Drill holes from the upper surface of the substrate redistribution layer toward the substrate to form through holes that penetrate the substrate redistribution layer and the adhesive layer and contact electrical connectors on the substrate;

[0037] A seed layer is formed on the upper surface of the substrate redistribution layer and the via;

[0038] After applying photoresist, photolithography is performed to expose the vias, and after forming a metal layer in the vias, the photoresist is removed to obtain the semiconductor packaging device.

[0039] In some alternative embodiments, the substrate redistribution layer is obtained through the following process:

[0040] A seed layer is formed on the carrier plate;

[0041] A dielectric layer is formed on the seed layer;

[0042] After photolithography, the dielectric layer is used to fabricate the bonding pads;

[0043] A seed layer is formed again on the dielectric layer and the solder pad;

[0044] After coating with photoresist, photolithography is used to form the circuit layer, and then the photoresist is removed to obtain the substrate redistribution layer.

[0045] In some alternative embodiments, the spacer is bonded to the first surface by adhesive.

[0046] In some optional implementations, the method further includes:

[0047] The chip is removed and bonded to the redistribution layer of the substrate;

[0048] An underfill is placed between the substrate redistribution layer and the chip.

[0049] In the prior art, the following problems may occur when bonding the FO layer to the substrate:

[0050] (1) Displacement occurs during the bonding process, resulting in a smaller bonding area and reduced electrical performance.

[0051] (2) Significant variation in the height of the solder pads on the substrate: For example, the uniformity of the solder pads on the substrate is typically greater than 20%. This can lead to two possible scenarios when bonding the FO layer to the substrate: First, a weak bonding force results in the conductive pillars of the FO layer being far from the substrate, causing the low-height solder pads on the substrate to fail to contact the FO layer, resulting in cold soldering; Second, a strong bonding force causes the conductive pillars of the FO layer to bend and deform under the pressure of the substrate, resulting in the conductive pillars on the FO layer failing to contact the solder pads on the substrate.

[0052] (3) The substrate warps due to the difference in the coefficient of thermal expansion (CTE) between the FO layer and the substrate, which in turn causes the lines or conductive holes on the FO layer to be unable to connect to the pads on the substrate.

[0053] In summary, FOSub substrates may currently experience electrical functional issues such as open circuits, over-resistance, lack of functionality, and signal errors, leading to a low overall product yield.

[0054] To address the aforementioned issues that may arise in fan-out packaging, the semiconductor packaging apparatus and manufacturing method disclosed herein improve the connectivity between the FO layer and the substrate by providing a spacer between the substrate and the FO layer. This improves connectivity even when there are significant variations in the height of the solder pads on the substrate surface (e.g., uniformity greater than 20%) and when warping may occur. Furthermore, by using conductive vias to connect the FO layer and the substrate instead of conductive pillars, the conductive vias offer greater process control precision compared to conductive pillars, avoiding problems such as cold soldering, damage or deformation of conductive pillars, and reduced bonding area that may occur with conductive pillars in the prior art. In other words, overall product yield can be improved. Attached Figure Description

[0055] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0056] Figure 1A , 1B 1C, 1D, 1E, 1F, 1G, and 1H are schematic diagrams of the longitudinal cross-sectional structure of semiconductor packaging devices 1a, 1b, 1c, 1d, 1e, 1f, 1g, and 1h according to the present disclosure.

[0057] Figure 1I and 1J These are enlarged views of rectangular dashed frames r1 and r2 in one embodiment 1a of the semiconductor packaging device according to this invention.

[0058] Figure 2A-1 , 2A-2 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I, and 2J are schematic diagrams of longitudinal cross-sectional structures manufactured at various stages according to an embodiment of the semiconductor packaging apparatus of the present disclosure.

[0059] Figure 3A-3G This is a longitudinal cross-sectional schematic diagram at various manufacturing stages of an embodiment of the substrate redistribution layer according to the present disclosure;

[0060] Figures 4A-4CThis is a longitudinal cross-sectional schematic diagram of a substrate according to an embodiment of the present disclosure at various manufacturing stages;

[0061] Symbol explanation:

[0062] 11 Substrate; 13 Adhesive layer;

[0063] 11a First surface; 14 Substrate redistribution layer;

[0064] 11b Second surface; 14a Top surface of substrate redistribution layer;

[0065] 11c Electrical connection on substrate; 141 First bonding pad;

[0066] 11d Under-substrate electrical interconnects; 142 Circuit pattern;

[0067] 12 Spacers; 143 Substrate redistribution layer lines;

[0068] 121 Spacer core; 1431 Substrate redistribution layer line barrier layer;

[0069] 122 Spacer coating; 1432 Substrate redistribution layer conductive traces;

[0070] h: Height of spacer; 15: Conductive via;

[0071] w represents the horizontal cross-sectional diameter of the cylindrical spacer; 16 chips;

[0072] d1 Horizontal distance between the spacer and the electrical connection on the substrate; 161 Chip redistribution layer;

[0073] d2 Spacer and redistribution layer on substrate; 17 Passive component;

[0074] Horizontal distance;

[0075] 18. Wire bonding; 19. Carrier board;

[0076] 20 Seed layer; 21 Dielectric layer;

[0077] 22 Photoresist; 23 Adhesive;

[0078] 24. Bottom filler. Detailed Implementation

[0079] The specific embodiments of the present invention will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by the present invention and the resulting technical effects from the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the relevant invention and not intended to limit the invention. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0080] It should be noted that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and to facilitate understanding and reading of the invention. They are not intended to limit the scope of the invention and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effectiveness and objectives of the invention, should still fall within the scope of the technical content disclosed herein. Furthermore, terms such as "above," "first," "second," and "a" used in this specification are merely for clarity and not intended to limit the scope of the invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the invention's implementation.

[0081] It should also be noted that the longitudinal section corresponding to the embodiments of this disclosure can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0082] Furthermore, the embodiments and features described herein can be combined with each other, unless otherwise specified. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0083] refer to Figure 1A , Figure 1A A longitudinal cross-sectional structural schematic diagram of an embodiment 1a of a semiconductor packaging device according to the present disclosure is shown.

[0084] like Figure 1A As shown, the semiconductor packaging device 1a includes: a substrate 11, at least two spacers 12, an adhesive layer 13, a substrate redistribution layer 14, and a conductive via 15, wherein:

[0085] The substrate 11 has a first surface 11a and a second surface 11b opposite to the first surface 11a. An electrical connector 11c disposed on the first surface 11a is electrically connected to an electrical connector 11d disposed on the second surface 11b. For example, the electrical connector 11c and the electrical connector 11d can be solder balls, solder bumps, conductive pillars, solder pads, etc.

[0086] The substrate 11 can be of various types, and this disclosure does not specifically limit it. The substrate 11 may include organic and / or inorganic materials, wherein the organic materials may be, for example, polyamide fiber (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, prepreg, also known as semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc., while the inorganic materials may be, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc.

[0087] The substrate 11 can also be, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass fiber-based copper foil laminate.

[0088] The substrate 11 may also include interconnect structures, such as conductive traces.

[0089] Spacers 12 are disposed on the first surface 11a. Here, the spacers 12 can be various elastic materials. The number of spacers 12 is at least two, and the height of each spacer 12 (e.g., ...) Figure 1A As shown in h), the heights can be the same and greater than or equal to the heights of the electrical connectors 11c on each substrate. Therefore, when bonding the substrate redistribution layer to the substrate, the heights of the electrical connectors 11c on each substrate do not need to be considered; only the height of the spacer 12 needs to be considered, which reduces the difficulty of the bonding process.

[0090] An adhesive layer 13 surrounds the first surface 11a, the electrical connector 11c on the substrate, and each spacer 12. The adhesive layer 13 is used to securely bond each spacer 12 to the first surface 11a of the substrate 11.

[0091] A substrate redistribution layer 14 is disposed on the adhesive layer 13 and the spacer 12. The substrate redistribution layer 14 may be a redistribution layer (RDL) composed of conductive traces and dielectric material.

[0092] A conductive via 15 extends from the upper surface of the substrate redistribution layer 14 toward the substrate 11 and contacts the electrical connector 11c on the substrate. Here, the conductive via 15 can be filled with a conductive material such as a metal or metal alloy; the metal may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or an alloy thereof. There may be at least one conductive via 15. The conductive via 15 is used to electrically connect the substrate redistribution layer 14 to the substrate 11.

[0093] The semiconductor packaging device 1a provided in the above embodiments of this disclosure can achieve the following technical effects, including but not limited to: First, by designing at least two supports with a height greater than the electrical connection height on each substrate, and the supports being made of elastic material, the supports can support the gap between the substrate redistribution layer and the substrate regardless of whether the substrate is warped or the height of the electrical connections on each substrate varies significantly, thereby avoiding electrical connection problems such as open circuits and cold solder joints; Second, by using conductive vias instead of conductive pillars to connect the substrate redistribution layer and the substrate, problems such as unconnected conductive pillars, damage to conductive pillars, or deformation that may occur with conductive pillar connections can be avoided. In summary, the semiconductor packaging device 1a can improve product yield.

[0094] In some alternative embodiments, the material strength of each spacer 12 can be between 10 and 100 megapascals. Consequently, the spacers 12 can better resist the bonding forces generated during the bonding process of the substrate redistribution layer 14 to the substrate.

[0095] In some alternative embodiments, the spacer 12 may be bonded to the first surface 11a by a non-conductive paste or a non-conductive film.

[0096] In some alternative implementations, the spacer 12 may be a cylindrical spacer or a cuboid spacer.

[0097] In some alternative implementations, the height of the cylindrical spacer (e.g.) Figure 1A The diameter h shown can be greater than twice the horizontal cross-sectional diameter of the cylindrical spacer (e.g., h). Figure 1A(as shown in w). The height of the cuboid spacer can be greater than twice the side length of any horizontal cross-section of the rectangular spacer, such as the long side length of a horizontally rectangular cross-section. Based on this optional implementation, the horizontal area occupied by the spacer in the semiconductor packaging device and its supporting performance can be balanced. If the height of the spacer is too small relative to its horizontal cross-sectional area, the spacer may tip over due to instability or occupy a large area, affecting the overall package size.

[0098] In some alternative implementations, the horizontal cross-sectional diameter of the cylindrical spacer or the side length of any horizontal cross-section of the cuboid spacer may be greater than twice the sum of the linewidth and spacing of the traces in the substrate redistribution layer, or greater than twice the sum of the linewidth and spacing of the electrical connectors on the substrate. This is to ensure that the horizontal cross-section of the support can span at least two traces in the substrate redistribution layer, or at least two electrical connectors on the substrate, thereby preventing the spacer from tilting and falling over, thus losing its supporting function.

[0099] In some alternative embodiments, the linewidth / space of the substrate redistribution layer 14 can be less than 2 / 2 micrometers, and the uniformity of the substrate redistribution layer 14 can be less than 5%. That is, this semiconductor packaging device bonds a high-level fine redistribution layer to the substrate surface, suitable for high-end product requirements.

[0100] In some alternative embodiments, the linewidth / spacing of the electrical connector 11c on the substrate is greater than 10 / 10 micrometers, and the uniformity of the height of the first surface 11a is greater than 20%. That is, when the linewidth / spacing of the electrical connector 11c on the substrate is greater than 10 / 10 micrometers, even if the height of the first surface 11a varies greatly, the semiconductor package device can still achieve good electrical connection due to the design of the spacer 12 and the conductive via 15.

[0101] In some alternative embodiments, the semiconductor packaging device 1a may further include a first bonding pad 141 disposed on the upper surface of the substrate redistribution layer 14 away from the substrate 11 and electrically connected to the substrate redistribution layer 14. Subsequently, the upper surface of the substrate redistribution layer 14 may also bond other electronic components through the first bonding pad 141, so that the other electronic components bonded thereon can be electrically connected to the substrate 11 through the substrate redistribution layer 14.

[0102] In some optional embodiments, the distance between the lower surface of the substrate redistribution layer 14 and the first surface 11a is less than 20 micrometers. That is, the gap between them is an ultra-small gap. Based on this optional embodiment, the adhesive layer 13 may optionally be a B-stage dielectric material. In this way, the adhesive layer 13 can not only serve as an adhesive but also as a reinforcing layer between the substrate redistribution layer 14 and the substrate 11 to enhance and fix the electrical connector 13 on the substrate.

[0103] In some alternative embodiments, the minimum horizontal distance between the spacer 12 and the electrical connection 11c on the substrate (e.g., Figure 1A The minimum horizontal distance between the spacer 12 and the circuit pattern 142 in the redistribution layer 14 on the substrate (as shown in the figure) is greater than or equal to 5 micrometers. Figure 1A The d2 shown is greater than or equal to 2 micrometers. This is a comprehensive setting that takes into account the bonding accuracy of the substrate redistribution layer 14 to the substrate 11 and the length tolerance of the circuit pattern 142 of the redistribution layer 14 on the substrate.

[0104] In some alternative embodiments, the number of spacers 12 in the semiconductor packaging device 1a, the yield strength and material strength of the spacers 12, the horizontal cross-sectional area of ​​the spacers 12, and the bonding force for bonding the substrate redistribution layer 14 to the substrate 11 satisfy the following formula:

[0105] Sy≤Fm / A(Formula 1)

[0106] Fm / (nA)≤Sp(Formula 2)

[0107] Where Sy and Sp are the yield strength and material strength of spacer 12, respectively, Fm is the bonding force for bonding the substrate redistribution layer 14 to the substrate 11, n is the number of spacers 12 in the semiconductor packaging device 1a, and A is the horizontal cross-sectional area of ​​the spacers. From Equation 1, it can be seen that the yield strength Sy of spacer 12 is less than or equal to the pressure exerted on the horizontal cross-section of a single spacer 12 by the bonding force for bonding the substrate redistribution layer 14 to the substrate 11, indicating that even if only one spacer 12 is in contact with the substrate redistribution layer 14, that single spacer 12 will not be damaged. From Equation 2, it can be seen that the material strength Sp of spacer 12 is greater than or equal to the pressure exerted on the horizontal cross-section of each of the n spacers 12 by the bonding force for bonding the substrate redistribution layer 14 to the substrate 11, indicating that when all spacers 12 are in contact with the substrate redistribution layer 14, each spacer 12 will not be damaged.

[0108] In some alternative embodiments, the bonding force for bonding the substrate redistribution layer 14 to the substrate 11 is 5 to 50 Newtons. This is set with respect to the capabilities of existing bonding processes.

[0109] In some alternative embodiments, the height of the spacer 12 may be greater than or equal to 20 micrometers. This is because the maximum thickness of the electrical connector 11c on the upper surface of the substrate is typically 15 micrometers, while the maximum thickness of the bottom conductive trace of the redistribution layer 14 on the substrate is typically 3 micrometers. In order to cover the gap between the two, the height of the spacer 12 may be designed to be greater than or equal to 20 micrometers.

[0110] Continue to refer to Figure 1B , Figure 1BThe semiconductor packaging device 1b shown is similar to Figure 1A The semiconductor packaging device 1a shown differs in that the semiconductor packaging device 1b may further include a chip 16, which is disposed on the upper surface of the substrate redistribution layer 14 and electrically connected to the first bonding pad 141. Furthermore, the chip 16 can be electrically connected to the substrate redistribution layer 14 via the first bonding pad 141, and then electrically connected to the substrate 11 via the conductive via 15.

[0111] In some alternative embodiments, a chip redistribution layer 161 may be provided on the chip 16 in the direction close to the substrate redistribution layer 14, through which the chip 16 is electrically connected to the first bonding pad. Furthermore, the chip redistribution layer 161 can be used to fan out the chip 16, thereby increasing the number of I / O (Input / Output) ports on the chip 16.

[0112] Continue to refer to Figure 1C , Figure 1C The semiconductor packaging device 1c shown is similar to Figure 1A The semiconductor packaging device 1c shown is different in that the substrate redistribution layer 14 in the semiconductor packaging device 1c includes at least one layer of lines 143.

[0113] Continue to refer to Figure 1D , Figure 1D The semiconductor packaging device 1d shown is similar to Figure 1A The semiconductor packaging device 1a shown is different in that the semiconductor packaging device 1d may also include a circuit pattern 142 disposed on the upper surface 14a of the substrate redistribution layer 14 and electrically connected to the substrate redistribution layer 14.

[0114] Continue to refer to Figure 1E and 1F , Figure 1E and 1F The semiconductor packaging devices 1e and 1f shown are similar to Figure 1A The semiconductor packaging device 1a shown is different in that: the semiconductor packaging devices 1e and 1f also include passive components 17 disposed on the adhesive layer 13.

[0115] Continue to refer to Figure 1G , Figure 1G The semiconductor packaging device 1g shown is similar to Figure 1A The semiconductor packaging device 1a shown is different in that the semiconductor packaging device 1g also includes wire bonding 18 disposed on the adhesive layer 13.

[0116] Continue to refer to Figure 1H , Figure 1H The semiconductor packaging device 1h shown is similar to Figure 1AThe semiconductor packaging device 1a shown is different in that the spacer 12 of the semiconductor packaging device 1h includes a spacer core 121 and a spacer coating 122 surrounding the spacer core 121, wherein the spacer coating 122 is a metal coating or a non-metal coating.

[0117] Please refer to Figure 1I and Figure 1J , Figure 1I and Figure 1J This is a partially enlarged schematic diagram of the rectangular dashed frames r1 and r2 in the semiconductor packaging device 1a according to this invention. (See attached diagram.) Figure 1I and Figure 1J As shown, the substrate redistribution layer 143 may include a barrier layer 1431 and a conductive trace 1432. The barrier layer 1431 prevents the conductive trace 1432 from penetrating the dielectric material of the substrate redistribution layer 14, and the barrier layer 1431 can improve the bonding strength between the conductive trace 1432 and the dielectric material of the substrate redistribution layer 14. The barrier layer 1431 may be, for example, titanium (Ti), tungsten (W), nickel (Ni), etc., while the conductive trace 1432 may be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0118] Figure 2A-1 , 2A-2 Figures 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I, and 2J are longitudinal cross-sectional structural schematic diagrams of semiconductor packaging devices 4a, 4b, 4c, 4d, 4e, 4f, 4g, 4h, 4i, and 4j manufactured at various stages according to an embodiment of the semiconductor packaging device of the present disclosure. The figures have been simplified for better understanding of various aspects of the present disclosure.

[0119] refer to Figure 2A-1 and Figure 2A-2 The substrate redistribution layer 14 is bonded to the substrate 11 via the adhesive layer 13, so that the substrate redistribution layer 14 is electrically connected to the electrical connector 11c on the substrate.

[0120] The substrate 11 has a first surface 11a and a second surface 11b opposite to the first surface 11a. An electrical connector 11c disposed on the first surface 11a is electrically connected to a lower electrical connector 11d disposed on the second surface 11b. At least two spacers 12 are disposed on the first surface 11a, and the height of the spacers 12 is greater than or equal to the height of each electrical connector 11c. The spacers 12 can be bonded to the substrate 11 using adhesive.

[0121] The upper surface of the substrate redistribution layer 14 is provided with a seed layer 20 and a carrier 19. Optionally, the substrate redistribution layer may also be provided with a dielectric layer 21 and substrate redistribution layer lines 143, and the substrate redistribution layer lines 143 may include a barrier layer 1431 and a conductive trace 1432.

[0122] like Figure 2A-2 As shown, multiple smaller substrate redistribution layers 14, each containing a seed layer 20 and a carrier plate 19, can be simultaneously bonded to a larger substrate 11 via an adhesive layer 13. The substrate 11 has multiple corresponding spacers 12, allowing each substrate redistribution layer 14 to electrically connect to different electrical connectors 11c on the substrate. Here, the area of ​​the substrate redistribution layer 14 can be, for example, 300 square millimeters, while the area of ​​the substrate 11 can be, for example, 600 square millimeters. This method can improve production capacity and reduce costs.

[0123] refer to Figure 2B Remove the carrier plate 19 on the substrate redistribution layer 14.

[0124] In terms of the manufacturing process, laser or similar technologies can be used to remove the carrier plate 19.

[0125] refer to Figure 2C The seed layer 20 on the substrate redistribution layer 14 is etched away.

[0126] The etching process can be carried out using either dry or wet etching methods to remove the seed layer 20.

[0127] refer to Figure 2D A hole is drilled from the upper surface 14a of the substrate redistribution layer 14 toward the substrate 11 to form a through hole that penetrates the substrate redistribution layer 14 and the adhesive layer 13 and contacts the electrical connector 11c on the substrate.

[0128] For example, laser drilling or similar techniques can be used to drill holes.

[0129] refer to Figure 2E Seed layer 20 is fabricated on the upper surface of substrate redistribution layer 14 and via 15.

[0130] refer to Figure 2F , Coat with photoresist 22.

[0131] refer to Figure 2G Photolithography is used to expose the via 15, a metal layer is formed in the via 15, the photoresist 22 is removed, and the seed layer 20 is etched away to obtain the semiconductor package device 2g.

[0132] Forming a metal layer within a through-hole can be achieved using techniques such as sputtering, electroplating, electroless plating, or similar methods. The metal layer can be, for example, gold (Au), silver (Ag), aluminum (Al), nickel (Ni), palladium (Pd), copper (Cu), or alloys thereof.

[0133] For further reference, please also refer to Figure 2H Take chip 16.

[0134] Continue to refer to Figure 2I The chip 16 is bonded to the substrate redistribution layer 14.

[0135] Here, chip 16 may also include a chip redistribution layer 161. During bonding, the chip redistribution layer 161 can be oriented toward the substrate redistribution layer 14, and the substrate redistribution layer 14 has a first bonding pad 141 disposed on its upper surface 14a away from the substrate 11. After bonding, chip 16 can be electrically connected to the first bonding pad 141 through the chip redistribution layer 161.

[0136] In the bonding process, techniques such as flip chip bonding (FCB), thermal compression bonding (FCB), or similar technologies can be used.

[0137] refer to Figure 2J An underfill 24 is filled between the substrate redistribution layer 14 and the chip 16.

[0138] Filling with underfill 24 can improve the bottom of the protective chip 16 and improve the bonding strength between the substrate redistribution layer 14 and the chip 16.

[0139] The following is for reference. Figure 3A-3G , Figure 3A-3G This is a longitudinal cross-sectional schematic diagram of an embodiment of the substrate redistribution layer according to the present disclosure at various manufacturing stages.

[0140] refer to Figure 3A Seed layer 20 is formed on carrier plate 19.

[0141] Specific processes can employ techniques such as sputtering, plating, electroless plating, or similar methods.

[0142] refer to Figure 3B A dielectric layer 21 is formed on the seed layer 20.

[0143] Specific processes may employ techniques such as printing, lamination, potting, coating, or similar methods.

[0144] refer to Figure 3C After photolithography is performed on dielectric layer 21, bonding pad 141 is fabricated.

[0145] refer to Figure 3D Seed layer 20 is formed again on dielectric layer 21 and pad 141.

[0146] refer to Figure 3E , Coat with photoresist 22.

[0147] refer to Figure 3F After photolithography to form the circuit layer 143, the photoresist 22 is removed to obtain the substrate redistribution layer 14.

[0148] refer to Figure 3G , inject glue to form adhesive layer 13.

[0149] The following is for reference. Figures 4A-4C , Figures 4A-4C This is a longitudinal cross-sectional schematic diagram of an embodiment of the substrate according to the present disclosure at various manufacturing stages.

[0150] refer to Figure 4A Substrate 11 is provided.

[0151] The substrate 11 has a first surface 11a and a second surface 11b opposite to the first surface 11a. An electrical connector 11c disposed on the first surface 11a is electrically connected to a lower electrical connector 11d disposed on the second surface 11b. The heights of the electrical connectors 11c on the substrate can be the same or different.

[0152] refer to Figure 4B , pour glue 23.

[0153] refer to Figure 4C At least two spacers 12 are bonded to the first surface 11a with glue 23.

[0154] Although this disclosure has been described and illustrated with reference to specific embodiments thereof, such descriptions and illustrations are not limiting of this disclosure. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within embodiments without departing from the true spirit and scope of this disclosure as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation in this disclosure and actual implementation due to variables in the manufacturing process, etc. Other embodiments of this disclosure may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, composition, methods, or processes to the objectives, spirit, and scope of this disclosure. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of this disclosure. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit this disclosure.

Claims

1. A semiconductor packaging device, comprising: A substrate having a first surface and a second surface opposite to the first surface, wherein an electrical connector disposed on the first surface is electrically connected to a lower electrical connector disposed on the second surface; At least two spacers are disposed on the first surface, and the height of the spacers is greater than or equal to the height of the electrical connectors on each of the substrates; An adhesive layer surrounds the first surface, the electrical connectors on the substrate, and each of the spacers; A substrate redistribution layer is disposed on the adhesive layer and the spacer; A conductive via is exposed on the upper surface of the redistribution layer of the substrate, extends toward the substrate, and contacts an electrical connector on the substrate. The spacer is an elastic material and is bonded to the first surface by a non-conductive adhesive or a non-conductive film.

2. The semiconductor packaging apparatus according to claim 1, wherein, The spacer has a material strength of 10 to 100 megapascals.

3. The semiconductor packaging apparatus according to claim 1, wherein, The semiconductor packaging device further includes a first bonding pad disposed on the upper surface of the substrate redistribution layer away from the substrate and electrically connected to the substrate redistribution layer.

4. The semiconductor packaging apparatus according to claim 3, wherein, The semiconductor packaging device further includes a chip disposed on the upper surface of the substrate redistribution layer and electrically connected to the first bonding pad.

5. The semiconductor packaging apparatus according to claim 4, wherein, The chip has a chip redistribution layer in the direction close to the substrate redistribution layer, and the chip is electrically connected to the first pad through the chip redistribution layer.

6. The semiconductor packaging apparatus according to claim 1, wherein, The adhesive layer is a B-stage dielectric material.

7. The semiconductor packaging apparatus according to claim 1, wherein, The minimum horizontal distance between the spacer and the electrical connector on the substrate is greater than or equal to 5 micrometers, and the minimum horizontal distance between the spacer and the circuit pattern in the redistribution layer on the substrate is greater than or equal to 2 micrometers.

8. The semiconductor packaging apparatus according to claim 1, wherein, The following formula applies to the number of spacers in the semiconductor packaging apparatus, the yield strength and material strength of the spacers, the horizontal cross-sectional area of ​​the spacers, and the bonding force for bonding the substrate redistribution layer to the substrate: Sy≤Fm / A Fm / (nA)≤Sp Wherein, Sy and Sp are the yield strength and material strength of the spacer, respectively, Fm is the bonding force for bonding the substrate redistribution layer to the substrate, n is the number of spacers in the semiconductor packaging device, and A is the horizontal cross-sectional area of ​​the spacer.

9. The semiconductor packaging apparatus according to claim 1, wherein, The semiconductor packaging device further includes at least one of the following disposed on the adhesive layer: passive components, wire bonding.

Images