Camera

Abstract

A camera device according to one technical solution of the present invention comprises: a photoelectric conversion portion that converts incident light into electric charge; a first impurity region located in a semiconductor substrate, electrically connected to the photoelectric conversion portion, and containing impurities of a first conductivity type; a second impurity region different from the first impurity region, located in the semiconductor substrate, and containing impurities of the first conductivity type; a third impurity region located in the semiconductor substrate, located between the first impurity region and the second impurity region in a planar view, and containing impurities of a second conductivity type different from the first conductivity type; and a first contact portion located on the semiconductor substrate, electrically connected to the third impurity region, and including a semiconductor containing impurities of the second conductivity type.

Description

Technical Field

[0001] The present invention relates to a camera device. Background Art

[0002] CCD (Charge Coupled Device) image sensors and CMOS (Complementary Metal Oxide Semiconductor) image sensors are widely used in digital cameras, etc. As is well known, these image sensors have photodiodes formed on a semiconductor substrate.

[0003] On the other hand, for example, Patent Documents 1 and 2 propose structures in which a photoelectric conversion unit having a photoelectric conversion layer is disposed above a semiconductor substrate. An imaging device having such a structure is sometimes referred to as a stacked-type imaging device. In a stacked-type imaging device, the charge generated by photoelectric conversion is accumulated in a charge accumulation region (referred to as a "floating diffusion"). A signal corresponding to the amount of charge accumulated in the charge accumulation region is read out via a CCD circuit or CMOS circuit formed on the semiconductor substrate.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: International Publication No. 2014 / 002330

[0007] Patent Document 2: International Publication No. 2012 / 147302 Summary of the Invention

[0008] Problems to be solved by the invention

[0009] If charges different from the signal charge representing the image flow into the diffusion region that temporarily holds the signal charge, this can cause noise. This noise degrades the resulting image. Suppressing this unwanted charge movement is beneficial. Below, there are cases where this unwanted charge movement manifests as leakage current.

[0010] Means used to solve problems

[0011] According to the non-limiting exemplary technical solution of the present invention, the following technology is provided.

[0012] A camera device according to one technical solution of the present invention comprises: a semiconductor substrate; a photoelectric conversion portion that converts incident light into electric charges; a first impurity region located in the semiconductor substrate, electrically connected to the photoelectric conversion portion, and containing impurities of a first conductivity type; a second impurity region different from the first impurity region, located in the semiconductor substrate, and containing impurities of the first conductivity type; a third impurity region located in the semiconductor substrate, between the first impurity region and the second impurity region in a planar view, and containing impurities of a second conductivity type different from the first conductivity type; and a first contact portion located on the semiconductor substrate, electrically connected to the third impurity region, and including a semiconductor containing impurities of the second conductivity type.

[0013] In addition, another technical solution of the present invention provides an imaging device comprising: a semiconductor substrate; a photoelectric conversion portion that converts incident light into electric charges; a first impurity region located in the semiconductor substrate, electrically connected to the photoelectric conversion portion, and containing impurities of a first conductivity type; a second impurity region different from the first impurity region, located in the semiconductor substrate, and containing impurities of the first conductivity type; a sixth impurity region located in the semiconductor substrate, between the first impurity region and the second impurity region in plan view, and containing impurities of the first conductivity type; a third contact portion located on the semiconductor substrate, electrically connected to the sixth impurity region, and including a semiconductor containing impurities of the first conductivity type; and a seventh impurity region located in the semiconductor substrate, between the first impurity region and the sixth impurity region and between the second impurity region and the sixth impurity region in plan view, and containing impurities of a second conductivity type different from the first conductivity type.

[0014] The general or specific aspects may also be implemented by components, devices, modules, systems, or methods. In addition, the general or specific aspects may also be implemented by any combination of components, devices, modules, systems, and methods.

[0015] Additional effects and advantages of the disclosed embodiments will become apparent from the specification and drawings. Effects and / or advantages are independently provided by the various embodiments or features disclosed in the specification and drawings, and it is not necessary to obtain all of them in order to obtain one or more of them.

[0016] Effects of the Invention

[0017] According to the present invention, it is possible to provide an imaging device in which leakage current is suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a diagram showing an exemplary configuration of an imaging device according to the first embodiment of the present invention.

[0019] Figure 2This is a diagram showing an exemplary circuit configuration of an imaging device according to the first embodiment of the present invention.

[0020] Figure 3A It is a plan view showing an example of the layout of each element in the pixel according to the first embodiment of the present invention.

[0021] Figure 3B This is a schematic cross-sectional view showing an exemplary structure of a pixel according to the first embodiment of the present invention.

[0022] Figure 4A Is the distance Figure 3B The diagram shows a distribution diagram of impurity concentration obtained by simulation in a region close to the truncated structure.

[0023] Figure 4B Is the distance Figure 3B The diagram shows a distribution diagram of impurity concentration obtained by simulation in a region close to the truncated structure.

[0024] Figure 5 This is a diagram showing the magnitude of leakage current to the charge storage region, comparing the first embodiment and a reference example.

[0025] Figure 6 This figure shows the electron current distribution in the cross section of the semiconductor substrate close to the cutoff structure, comparing the first embodiment and the reference example.

[0026] Figure 7 It is a plan view showing an example of the layout of each element in a pixel according to a first modification of the first embodiment of the present invention.

[0027] Figure 8A It is a plan view showing an example of the layout of each element in a pixel according to the second modification example of the first embodiment of the present invention.

[0028] Figure 8B This is a schematic cross-sectional view showing an exemplary structure of a pixel according to a second modification of the first embodiment of the present invention.

[0029] Figure 9 It is a plan view showing an example of the layout of each element in a pixel according to the third modification example of the first embodiment of the present invention.

[0030] Figure 10A This is a schematic cross-sectional view showing an exemplary structure of a pixel according to a fourth modification of the first embodiment of the present invention.

[0031] Figure 10B This is a schematic cross-sectional view showing an exemplary structure of a pixel according to a fourth modification of the first embodiment of the present invention.

[0032] Figure 11 This is a diagram showing an exemplary circuit configuration of an imaging device according to a second embodiment of the present invention.

[0033] Figure 12 It is a plan view showing an example of the layout of each element in a pixel according to the second embodiment of the present invention.

[0034] Figure 13 This is a diagram showing an exemplary circuit configuration of an imaging device according to a third embodiment of the present invention.

[0035] Figure 14 It is a plan view showing an example of the layout of each element in a pixel according to the third embodiment of the present invention. DETAILED DESCRIPTION

[0036] (Summary of the Invention)

[0037] An outline of one aspect of the present invention is as follows.

[0038] A camera device according to one technical solution of the present invention comprises: a semiconductor substrate; a photoelectric conversion portion that converts incident light into electric charges; a first impurity region located in the semiconductor substrate, electrically connected to the photoelectric conversion portion, and containing impurities of a first conductivity type; a second impurity region different from the first impurity region, located in the semiconductor substrate, and containing impurities of the first conductivity type; a third impurity region located in the semiconductor substrate, between the first impurity region and the second impurity region in a planar view, and containing impurities of a second conductivity type different from the first conductivity type; and a first contact portion located on the semiconductor substrate, electrically connected to the third impurity region, and including a semiconductor containing impurities of the second conductivity type.

[0039] Thus, even if minority carriers attempt to migrate from the second impurity region toward the first impurity region by diffusion, their migration is hindered by the potential barrier created by the third impurity region formed immediately below the first contact. Furthermore, the minority carriers disappear by recombination with charges of opposite polarity. In other words, the movement of minority carriers toward the first impurity region is blocked by the third impurity region, thereby suppressing leakage current caused by the influx of minority carriers into the first impurity region.

[0040] Here, the second conductivity type impurity concentration in the first contact portion may be higher than the second conductivity type impurity concentration in a portion of the third impurity region located below the surface of the semiconductor substrate.

[0041] This makes it possible to further increase the impurity concentration of the third impurity region on the surface of the semiconductor substrate, thereby making it possible to more reliably suppress leakage current by the third impurity region.

[0042] In addition, the above-mentioned camera device may further include: a voltage supply circuit that supplies voltage to the above-mentioned first contact portion; and a well region located in the above-mentioned semiconductor substrate and containing impurities of the above-mentioned second conductivity type; the above-mentioned first impurity region, the above-mentioned second impurity region and the above-mentioned third impurity region are located in the above-mentioned well region.

[0043] Thus, the voltage supplied to the first contact portion is applied to the well region via the third impurity region. Thus, the first contact portion can be used as a substrate contact portion.

[0044] Furthermore, the imaging device may further include a first pixel; and the first pixel may include the first impurity region, the second impurity region, the third impurity region, and the first contact portion.

[0045] Furthermore, the imaging device may further include a first pixel and a second pixel different from the first pixel; the first pixel includes the first impurity region; and the second pixel includes the second impurity region.

[0046] Thus, the third impurity region is located between pixels, thereby suppressing leakage current caused by the mixing of minority carriers between pixels.

[0047] In addition, it may be that the above-mentioned camera device further includes a first pixel and a second pixel different from the above-mentioned first pixel; the above-mentioned first pixel includes the above-mentioned first impurity region, the above-mentioned second impurity region, the above-mentioned third impurity region and the above-mentioned first contact portion; the above-mentioned second pixel includes: a fourth impurity region, located in the above-mentioned semiconductor substrate, containing impurities of the above-mentioned first conductivity type; a fifth impurity region, located in the above-mentioned semiconductor substrate, located between the above-mentioned first impurity region and the above-mentioned fourth impurity region when viewed in a planar manner, containing impurities of the above-mentioned second conductivity type; and a second contact portion, located on the above-mentioned semiconductor substrate, electrically connected to the above-mentioned fifth impurity region, and including a semiconductor containing impurities of the above-mentioned second conductivity type.

[0048] Thus, a second contact portion and a fifth impurity region similar to the first contact portion and the third impurity region are formed at the boundary between two adjacent pixels, thereby suppressing leakage current not only within a pixel but also between pixels.

[0049] In addition, another technical solution of the present invention provides an imaging device comprising: a semiconductor substrate; a photoelectric conversion portion that converts incident light into electric charges; a first impurity region located in the semiconductor substrate, electrically connected to the photoelectric conversion portion, and containing impurities of a first conductivity type; a second impurity region different from the first impurity region, located in the semiconductor substrate, and containing impurities of the first conductivity type; a sixth impurity region located in the semiconductor substrate, between the first impurity region and the second impurity region in plan view, and containing impurities of the first conductivity type; a third contact portion located on the semiconductor substrate, electrically connected to the sixth impurity region, and including a semiconductor containing impurities of the first conductivity type; and a seventh impurity region located in the semiconductor substrate, between the first impurity region and the sixth impurity region and between the second impurity region and the sixth impurity region in plan view, and containing impurities of a second conductivity type different from the first conductivity type.

[0050] Thus, even if minority carriers attempt to migrate from the second impurity region toward the first impurity region by diffusion, their migration is hindered by the potential barrier created by the sixth impurity region formed immediately below the third contact. Furthermore, the presence of the seventh impurity region, which serves as an element isolation region, eliminates minority carriers by recombination with charges of opposite polarity. In other words, the movement of minority carriers toward the first impurity region is blocked by the third and seventh impurity regions, thereby suppressing leakage current caused by the influx of minority carriers into the first impurity region.

[0051] Here, the concentration of the first conductivity type impurity in the third contact portion may be higher than the concentration of the first conductivity type impurity in a portion of the sixth impurity region located below the surface of the semiconductor substrate.

[0052] This makes it possible to further increase the impurity concentration of the sixth impurity region on the surface of the semiconductor substrate, thereby making it possible to more reliably suppress leakage current by the sixth impurity region.

[0053] In addition, it may be possible to further include: a voltage supply circuit that supplies voltage to the above-mentioned third contact portion; and a well region located in the above-mentioned semiconductor substrate and containing the above-mentioned second conductivity type impurities; the above-mentioned first impurity region, the above-mentioned second impurity region, the above-mentioned sixth impurity region and the above-mentioned seventh impurity region are located in the above-mentioned well region.

[0054] Thus, the voltage supplied to the third contact portion is applied to the well region via the sixth impurity region. Thus, the third contact portion can be used as a substrate contact portion.

[0055] Furthermore, the imaging device may further include a first pixel and a second pixel different from the first pixel; the first pixel includes the first impurity region; and the second pixel includes the second impurity region.

[0056] Thus, the sixth impurity region is located between pixels, thereby suppressing leakage current caused by the mixing of minority carriers between pixels.

[0057] In addition, it may be that the above-mentioned camera device further includes a first pixel and a second pixel different from the above-mentioned first pixel; the above-mentioned first pixel includes the above-mentioned first impurity region, the above-mentioned second impurity region, the above-mentioned sixth impurity region, the above-mentioned seventh impurity region and the above-mentioned third contact portion; the above-mentioned second pixel includes: a fourth impurity region, located in the above-mentioned semiconductor substrate, containing impurities of the above-mentioned first conductivity type; an eighth impurity region, located in the above-mentioned semiconductor substrate, between the above-mentioned first impurity region and the above-mentioned fourth impurity region when viewed in a planar manner, containing impurities of the above-mentioned first conductivity type; a fourth contact portion, located on the above-mentioned semiconductor substrate, electrically connected to the above-mentioned eighth impurity region, including a semiconductor containing impurities of the above-mentioned first conductivity type; and a ninth impurity region, located in the above-mentioned semiconductor substrate, between the above-mentioned first impurity region and the above-mentioned eighth impurity region and between the above-mentioned fourth impurity region and the above-mentioned eighth impurity region when viewed in a planar manner, containing impurities of the above-mentioned second conductivity type.

[0058] Thus, a fourth contact portion and an eighth impurity region similar to the third contact portion and the sixth impurity region are formed at the boundary between two adjacent pixels, thereby suppressing leakage current not only within a pixel but also between pixels.

[0059] In addition, the above-mentioned camera device may further include: a first region located in the above-mentioned semiconductor substrate, containing the above-mentioned second conductive type impurities; and a second region covering the entire surface of the above-mentioned first region, containing the above-mentioned first conductive type impurities; the above-mentioned well region is located on the above-mentioned second region.

[0060] Thus, the second region containing the first conductivity type impurities is provided to cover the entire surface of the first region containing the second conductivity type impurities. This suppresses the inflow of minority carriers from the first region or the peripheral circuit.

[0061] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, the embodiments described below all represent general or specific examples. The numerical values, shapes, materials, constituent elements, configuration positions of constituent elements and connection forms, steps, order of steps, etc. shown in the following embodiments are examples and are not intended to limit the present invention. The various forms described in this specification can be combined with each other as long as no contradiction occurs. In addition, among the constituent elements of the following embodiments, constituent elements that are not recorded in the independent claims representing the highest concepts are described as arbitrary constituent elements. In the following description, there are cases where constituent elements having substantially the same function are represented by common reference numerals and the description is omitted. In addition, in order to avoid the drawings being too complicated, the illustrations of some elements may be omitted.

[0062] Furthermore, the various elements shown in the drawings are merely schematic representations for purposes of understanding the present invention, and their dimensional ratios and appearance may differ from those of the actual objects. In other words, the drawings are schematic and not necessarily illustrative. Therefore, for example, scales and other factors may not necessarily be consistent across the drawings.

[0063] In addition, in this specification, terms such as parallel or consistent that indicate the relationship between elements, terms such as circular or rectangular that indicate the shape of elements, and numerical ranges do not express only strict meanings, but also mean essentially equivalent ranges, for example, also including differences of several percentage points.

[0064] In addition, in this specification, the terms "above" and "below" do not refer to the above (vertically above) and below (vertically below) in absolute spatial identification, but are used as terms specified by relative positional relationships based on the stacking order in the stacking structure. Specifically, the light-receiving side of the camera device is set to "above", and the side opposite to the light-receiving side is set to "below". The same applies to the "upper surface" and "lower surface" of each component. The surface of the camera device opposite to the light-receiving side is set to "upper surface", and the surface opposite to the light-receiving side is set to "lower surface". In addition, the terms "above", "below", "upper surface" and "lower surface" are only used to specify the mutual configuration between components and are not intended to limit the posture of the camera device when in use. In addition, the terms "above" and "below" are not only applicable to the case where two components are spaced apart and there are other components between the two components, but also to the case where two components are closely arranged and the two components are in contact. In addition, in this specification, the so-called "planar view" refers to the situation when observed from a direction perpendicular to the semiconductor substrate.

[0065] (First embodiment)

[0066] Figure 1An exemplary configuration of the imaging device 100 according to the first embodiment of the present invention is shown. Figure 1 The illustrated imaging device 100 includes a plurality of pixels 10 and peripheral circuits formed on a semiconductor substrate 60 .

[0067] exist Figure 1 In the example shown, the pixels 10 are arranged in a plurality of rows and columns of m rows and n columns. Here, m and n independently represent integers greater than 1. The pixels 10 are arranged, for example, two-dimensionally on the semiconductor substrate 60 to form an imaging region R1.

[0068] The number and arrangement of pixels 10 are not limited to the illustrated example. For example, the number of pixels 10 included in the imaging device 100 may be one. In this example, the center of each pixel 10 is located at a point on a square lattice. However, multiple pixels 10 may be arranged such that the center of each pixel 10 is located at a point on a triangular lattice, a hexagonal lattice, or the like. For example, by arranging the pixels 10 in a one-dimensional manner, the imaging device 100 can be used as a line sensor.

[0069] exist Figure 1 In the illustrated structure, the peripheral circuit includes a vertical scanning circuit 42 and a horizontal signal reading circuit 44. Figure 1 As shown in FIG, the peripheral circuit may additionally include a control circuit 46 and a voltage supply circuit 48. The peripheral circuit may also include a signal processing circuit, an output circuit, etc. Figure 1 In the example shown, each circuit included in the peripheral circuit is provided on the semiconductor substrate 60. However, a part of the peripheral circuit may be arranged on a substrate different from the semiconductor substrate 60 on which the pixels 10 are formed.

[0070] The vertical scanning circuit 42, also referred to as a row scanning circuit, is connected to the address signal lines 34 provided for each row of the plurality of pixels 10. As will be described later, the signal lines provided for each row of the plurality of pixels 10 are not limited to the address signal lines 34, and the vertical scanning circuit 42 may be connected to a plurality of types of signal lines for each row of the plurality of pixels 10. The horizontal signal readout circuit 44, also referred to as a column scanning circuit, is connected to the vertical signal lines 35 provided for each column of the plurality of pixels 10.

[0071] The control circuit 46 receives command data, clocks, etc. provided from the outside of the imaging device 100, and controls the entire imaging device 100. Typically, the control circuit 46 includes a timing generator, and supplies drive signals to the vertical scanning circuit 42, the horizontal signal reading circuit 44, the voltage supply circuit 48, etc. Figure 1In FIG, arrows extending from control circuit 46 schematically represent the flow of output signals from control circuit 46. Control circuit 46 can be implemented, for example, by a microcontroller including one or more processors. The functions of control circuit 46 can be implemented by a combination of general-purpose processing circuits and software, or by hardware customized for such processing.

[0072] The voltage supply circuit 48 supplies a predetermined voltage to each pixel 10 via the voltage line 38. The voltage supply circuit 48 is not limited to a specific power supply circuit, and may be a circuit that converts a voltage supplied from a power source such as a battery into a predetermined voltage, or may be a circuit that generates a predetermined voltage. The voltage supply circuit 48 may also be a part of the vertical scanning circuit 42 described above. Figure 1 As schematically shown in FIG, these circuits constituting the peripheral circuit are arranged in the peripheral region R2 outside the imaging region R1.

[0073] Figure 2 FIG. 1 schematically shows an exemplary circuit configuration of the imaging device 100 according to the first embodiment of the present invention. Figure 2 In order to avoid the complexity of the drawing, four pixels 10A arranged in two rows and two columns are representatively shown. These pixels 10A are Figure 1 The example of pixel 10 shown here includes a photoelectric conversion structure 12 as a photoelectric conversion portion, and includes a signal detection circuit 14A electrically connected to the photoelectric conversion structure 12. As will be described in detail later with reference to the accompanying drawings, the photoelectric conversion structure 12 includes a photoelectric conversion layer disposed above a semiconductor substrate 60. Specifically, a stacked-type imaging device is exemplified herein as imaging device 100.

[0074] The photoelectric conversion structure 12 receives incident light and generates positive and negative charges, typically hole-electron pairs. The photoelectric conversion structure 12 may be a photoelectric conversion structure including a photoelectric conversion layer disposed above the semiconductor substrate 60, or a photodiode formed on the semiconductor substrate 60. Figure 2 In the figure, the photoelectric conversion structures 12 of each pixel 10A are shown as being spatially separated from each other, but this is merely for the convenience of explanation. In some cases, the photoelectric conversion structures 12 of a plurality of pixels 10A may be continuously arranged on the semiconductor substrate 60 without being spaced apart from each other. In the case where each pixel 10A has a photoelectric conversion structure 12, for example, above the semiconductor substrate 60, Figure 1 The imaging region R1 can be defined as a region of the semiconductor substrate 60 covered by the photoelectric conversion structure.

[0075] The photoelectric conversion structure 12 of each pixel 10A is connected to a storage control line 31. During operation of the imaging device 100, a predetermined voltage is applied to the storage control line 31. For example, if positive charges are used as signal charges among the positive and negative charges generated by photoelectric conversion, a positive voltage of approximately 10V can be applied to the storage control line 31 during operation of the imaging device 100. The following example illustrates the use of holes as signal charges.

[0076] exist Figure 2 In the illustrated structure, the signal detection circuit 14A includes a signal detection transistor 22, an address transistor 24, and a reset transistor 26. As described in detail later with reference to the accompanying drawings, the signal detection transistor 22, the address transistor 24, and the reset transistor 26 are typically field effect transistors (FETs) formed on the semiconductor substrate 60 that supports the photoelectric conversion structure 12. Unless otherwise specified, the following examples use N-channel MOSFETs (Metal Oxide Semiconductor FETs) as transistors. Furthermore, which of the two diffusion layers of an FET corresponds to the source and drain is determined by the polarity of the FET and the potential level at that point in time. Therefore, which corresponds to the source and drain may vary depending on the operating state of the FET.

[0077] As in Figure 2 As schematically shown in FIG, the gate of the signal detection transistor 22 is electrically connected to the photoelectric conversion structure 12. By applying a predetermined voltage to the accumulation control line 31 during operation, holes, for example, can be accumulated as signal charges in the charge accumulation node FD. Here, the charge accumulation node FD is a node connecting the gate of the signal detection transistor 22 to the photoelectric conversion structure 12. As will be described later with reference to the accompanying drawings, a portion of the node includes an impurity region formed in the semiconductor substrate 60. In the illustrated example, the charge accumulation node FD has the function of temporarily storing the charge generated by the photoelectric conversion structure 12.

[0078] The drain of the signal detection transistor 22 is connected to a power supply wiring 32 that supplies a power supply voltage VDD of, for example, approximately 3.3 V to each pixel 10A during operation of the imaging device 100, and the source is connected to a vertical signal line 35 via the address transistor 24. The signal detection transistor 22 receives the power supply voltage VDD at its drain and outputs a signal voltage corresponding to the amount of signal charge accumulated in the charge accumulation node FD.

[0079] The gate of the address transistor 24 connected between the signal detection transistor 22 and the vertical signal line 35 is connected to the address signal line 34. Therefore, the vertical scanning circuit 42 applies a row selection signal to the address signal line 34 to control the on / off state of the address transistor 24, thereby reading the output of the signal detection transistor 22 of the selected pixel 10A to the corresponding vertical signal line 35. The arrangement of the address transistor 24 is not limited to Figure 2 In the example shown, the connection may be between the drain of the signal detection transistor 22 and the power supply wiring 32 .

[0080] Each vertical signal line 35 is connected to a load circuit 45 and a column signal processing circuit 47. The load circuit 45, together with the signal detection transistor 22, forms a source-follower circuit. The column signal processing circuit 47, also known as a row signal accumulation circuit, performs noise suppression signal processing typified by correlated double sampling, analog-to-digital conversion, and other functions. The horizontal signal readout circuit 44 sequentially reads signals from the multiple column signal processing circuits 47 to a horizontal common signal line 49. The load circuit 45 and the column signal processing circuit 47 may be part of the aforementioned peripheral circuits.

[0081] The gate of the reset transistor 26 is connected to a reset signal line 36 connected to the vertical scanning circuit 42. Similar to the address signal lines 34, the reset signal line 36 is provided for each row of the plurality of pixels 10A. The vertical scanning circuit 42 applies a row selection signal to the address signal line 34 to select the pixels 10A to be reset on a row-by-row basis. Applying a reset signal to the gate of the reset transistor 26 via the reset signal line 36 turns on the reset transistor 26 in the selected row. Turning on the reset transistor 26 resets the potential of the charge storage node FD.

[0082] In this example, one of the drain and source of the reset transistor 26 is connected to the charge storage node FD, and the other of the drain and source is connected to a corresponding one of the feedback lines 53 provided for each column of the plurality of pixels 10A. That is, in this example, the voltage of the feedback line 53 is supplied to the charge storage node FD as a reset voltage for initializing the charge in the photoelectric conversion structure 12.

[0083] exist Figure 2 In the illustrated configuration, the imaging device 100 includes a feedback circuit 16A including an inverting amplifier 50 in a portion of a feedback path. Figure 2 As shown, the inverting amplifier 50 is provided for each column of the plurality of pixels 10A, and the feedback line 53 is connected to the output terminal of a corresponding one of the plurality of inverting amplifiers 50. The inverting amplifier 50 may be part of the aforementioned peripheral circuit.

[0084] As shown in the figure, the inverting input terminal of the inverting amplifier 50 is connected to the vertical signal line 35 of the corresponding column. During operation of the imaging device 100, a positive reference voltage Vref, for example, at or near 1V, is supplied to the non-inverting input terminal of the inverting amplifier 50. By turning on the address transistor 24 and the reset transistor 26, a feedback path is formed that provides negative feedback to the output of the pixel 10A. This feedback path causes the voltage of the vertical signal line 35 to converge to the input voltage Vref to the non-inverting input terminal of the inverting amplifier 50. In other words, the feedback path resets the voltage of the charge storage node FD to a voltage such that the voltage of the vertical signal line 35 reaches Vref. Any voltage within the range of the power supply voltage and ground can be used as the voltage Vref. Forming the feedback path reduces reset noise generated when the reset transistor 26 is turned off. International Publication No. 2012 / 147302 describes in detail how reset noise is suppressed using feedback. The entire disclosure of International Publication No. 2012 / 147302 is incorporated herein by reference.

[0085] (Device Structure of Pixel 10A)

[0086] Figure 3A An example of the layout of each element in the pixel 10A is shown. Figure 3B An example of the device structure of the pixel 10A is schematically shown. Figure 3A Schematically showing the semiconductor substrate 60 viewed along the normal direction Figure 3B The arrangement of the elements formed on the semiconductor substrate 60 in the case of the pixel 10A shown in FIG. Figure 3A Cut pixel 10A by the dotted line 3B-3B in the figure and expand it, and we can get Figure 3B Cross section shown.

[0087] Reference Figure 3B . The pixel 10A generally includes a semiconductor substrate 60, a photoelectric conversion structure 12 arranged above the semiconductor substrate 60, and a conductive structure 89. As shown in the figure, the photoelectric conversion structure 12 is supported by an interlayer insulating layer 90 covering the semiconductor substrate 60, and the conductive structure 89 is arranged inside the interlayer insulating layer 90. In the example shown in the figure, the interlayer insulating layer 90 includes a plurality of insulating layers, and the conductive structure 89 includes portions of the plurality of wiring layers arranged inside the interlayer insulating layer 90. The plurality of wiring layers arranged in the interlayer insulating layer 90 may include a wiring layer having an address signal line 34 and a reset signal line 36 in a portion, a wiring layer having a vertical signal line 35, a power supply wiring 32 and a feedback line 53 in a portion, and the like. Of course, the number of insulating layers and the number of wiring layers in the interlayer insulating layer 90 are not limited to this example and can be set arbitrarily.

[0088] The photoelectric conversion structure 12 is an example of a photoelectric conversion unit that converts incident light into electric charge. It includes a pixel electrode 12a formed on the interlayer insulating layer 90, an opposing electrode 12c arranged on the light-incident side, and a photoelectric conversion layer 12b arranged between these electrodes. The photoelectric conversion layer 12b of the photoelectric conversion structure 12 is formed from an organic material or an inorganic material such as amorphous silicon. It receives light incident via the opposing electrode 12c and generates positive and negative charges through photoelectric conversion. Typically, the photoelectric conversion layer 12b is formed continuously in multiple pixels 10A. The photoelectric conversion layer 12b may include a layer composed of an organic material and a layer composed of an inorganic material.

[0089] The counter electrode 12c is a light-transmitting electrode formed of a transparent conductive material such as ITO. The term "light-transmitting" in this specification means that it allows at least a portion of light of a wavelength that can be absorbed by the photoelectric conversion layer 12b to pass through, and does not necessarily allow light to pass through the entire wavelength range of visible light. Typically, the counter electrode 12c is formed in multiple pixels 10A in the same manner as the photoelectric conversion layer 12b. Figure 3B Although not shown in the figure, the opposing electrode 12c is connected to the aforementioned accumulation control line 31. During operation of the imaging device 100, by controlling the potential of the accumulation control line 31 so that the potential of the opposing electrode 12c is, for example, higher than the potential of the pixel electrode 12a, the positive charges generated by photoelectric conversion can be selectively collected by the pixel electrode 12a. By forming the opposing electrode 12c as a continuous single layer across the plurality of pixels 10A, a predetermined potential can be uniformly applied to the opposing electrodes 12c of the plurality of pixels 10A.

[0090] The pixel electrode 12a is formed of polysilicon or the like that has been made conductive by doping with a metal such as aluminum or copper, a metal nitride, or impurities. The pixel electrode 12a is spatially separated from the pixel electrodes 12a of adjacent pixels 10A, thereby being electrically isolated from the pixel electrodes 12a of other pixels 10A.

[0091] The conductive structure 89 includes multiple wirings, plugs PA1, and contact plugs CP1, one end of which is connected to the pixel electrode 12a. The multiple wirings and plugs PA1 are typically formed of a metal such as copper or tungsten, or a metal compound such as a metal nitride or metal oxide. The contact plugs CP1 are formed, for example, of polysilicon doped with p-type impurities. The same applies to the other contact plugs described later. As described later, by connecting the other end of the conductive structure 89 to a circuit element formed on the semiconductor substrate 60, the pixel electrode 12a of the photoelectric conversion structure 12 and the circuit on the semiconductor substrate 60 are electrically connected to each other.

[0092] Here, we focus on the semiconductor substrate 60. Figure 3BAs schematically shown in FIG, the semiconductor substrate 60 includes a support substrate 61 and one or more semiconductor layers formed on the support substrate 61. Here, a p-type silicon substrate is exemplified as the support substrate 61.

[0093] exist Figure 3B In the illustrated structure, the semiconductor substrate 60 has a p-type semiconductor layer 61p on a supporting substrate 61, an n-type semiconductor layer 62n on the p-type semiconductor layer 61p, a p-type semiconductor layer 63p on the n-type semiconductor layer 62n, and a p-type semiconductor layer 65p as a first semiconductor layer located on the p-type semiconductor layer 63p.

[0094] In this embodiment, the n-type is referred to as the first conductivity type, and the p-type is referred to as the second conductivity type. The p-type semiconductor layer 61p is located in the semiconductor substrate 60 and is an example of a first region containing impurities of the second conductivity type. Furthermore, the n-type semiconductor layer 62n covers the first region and is an example of a second region containing impurities of the first conductivity type. Furthermore, the p-type semiconductor layer 65p and the p-type impurity region 66p (described later) form a well region located above the second region.

[0095] Typically, the p-type semiconductor layer 63p is formed over the entire surface of the support substrate 61. Typically, the p-type semiconductor layer 61p, the n-type semiconductor layer 62n, the p-type semiconductor layer 63p, and the p-type semiconductor layer 65p are each formed by ion implanting impurities into a semiconductor layer formed by epitaxial growth. The impurity concentration of the p-type semiconductor layer 65p is higher than that of the p-type semiconductor layer 61p.

[0096] The n-type semiconductor layer 62n as the second semiconductor layer is located between the p-type semiconductor layer 61p and the p-type semiconductor layer 63p. Figure 3A Although not shown in the figure, the n-type semiconductor layer 62n is connected to a well contact (not shown). The well contact is provided outside the imaging region R1. During operation of the imaging device 100, the potential of the n-type semiconductor layer 62n is controlled via the well contact. The provision of the n-type semiconductor layer 62n suppresses the influx of minority carriers from the support substrate 61 or peripheral circuits into the charge accumulation region, which stores signal charges.

[0097] In addition, the semiconductor substrate 60 has a p-type region 64 provided between the p-type semiconductor layer 63p and the support substrate 61 so as to penetrate the p-type semiconductor layer 61p and the n-type semiconductor layer 62n. The p-type region 64 has a higher impurity concentration than the p-type semiconductor layer 63p and the p-type semiconductor layer 65p, and electrically connects the p-type semiconductor layer 63p and the support substrate 61. Figure 3BThe substrate 61 and the p-type semiconductor layer 63p are connected to a substrate contact portion (not shown) provided outside the imaging region R1. During operation of the imaging device 100, the potential of the support substrate 61 and the p-type semiconductor layer 63p is controlled via the substrate contact portion. Furthermore, by arranging the p-type semiconductor layer 65p in contact with the p-type semiconductor layer 63p, the potential of the p-type semiconductor layer 65p can be controlled via the p-type semiconductor layer 63p during operation of the imaging device 100.

[0098] exist Figure 3B In the illustrated structure, the p-type semiconductor layer 65p has a p-type impurity region 66p with a lower impurity concentration, and an n-type impurity region 67n is formed in the p-type impurity region 66p. The n-type impurity region 67n is located in the semiconductor substrate 60 and is electrically connected to the photoelectric conversion structure 12. It is an example of a first impurity region containing impurities of the first conductivity type. Figure 3B As schematically shown in FIG, the n-type impurity region 67n is formed near the surface of the semiconductor substrate 60, and at least a portion thereof is located on the surface of the semiconductor substrate 60. Here, the n-type impurity region 67n includes a first region 67a and a second region 67b located within the first region 67a and having a relatively higher impurity concentration than the first region 67a.

[0099] An insulating layer is disposed on the main surface of the semiconductor substrate 60 facing the photoelectric conversion structure 12. In this example, the main surface of the semiconductor substrate 60 facing the photoelectric conversion structure 12 is covered by a first insulating layer 70 and a second insulating layer 71. The first insulating layer 70 is, for example, a thermally oxidized silicon film. The second insulating layer 71 is, for example, a silicon dioxide layer. The second insulating layer 71 may have a stacked structure including multiple insulating layers.

[0100] The first insulating layer 70 has a contact hole h1 on the second region 67b of the n-type impurity region 67n. Figure 3B In the example shown, the contact plug cp1 as part of the conductive structure 89 penetrates the contact hole h1 and is connected to the second region 67 b . Thus, the n-type impurity region 67 n is electrically connected to the pixel electrode 12 a of the photoelectric conversion structure 12 via the conductive structure 89 .

[0101] The junction capacitance formed by the pn junction between p-type impurity region 66p, which serves as a p-well, and n-type impurity region 67n functions as a capacitor that accumulates at least a portion of the signal charge, and n-type impurity region 67n functions as a charge accumulation region that temporarily stores the signal charge. Conductive structure 89 and n-type impurity region 67n can be said to constitute at least a portion of the charge accumulation node FD.

[0102] As described above, by arranging the p-type semiconductor layer 65p adjacent to the p-type semiconductor layer 63p, the potential of the p-type semiconductor layer 65p can be controlled via the p-type semiconductor layer 63p during operation of the imaging device 100. This structure allows for the placement of a region with a relatively low impurity concentration around the portion of the contact plug cp1 electrically connected to the photoelectric conversion structure 12 that contacts the semiconductor substrate 60. In this example, the first region 67a and the p-type impurity region 66p are arranged around the second region 67b of the n-type impurity region 67n. By arranging the first region 67a, which has a relatively low impurity concentration, around the second region 67b, the electric field strength generated by the pn junction between the n-type impurity region 67n and the p-type semiconductor layer 65p or the p-type impurity region 66p can be mitigated. By mitigating the electric field strength generated by the pn junction, leakage current caused by the electric field generated by the pn junction can be suppressed.

[0103] The formation of the second region 67b within the n-type impurity region 67n is not essential. However, by having a relatively high impurity concentration in the second region 67b, which serves as the connection between the contact plug cp1 and the semiconductor substrate 60, the expansion of the depletion layer around the contact portion of the contact plug cp1 and the semiconductor substrate 60 can be suppressed. This can suppress the inflow and / or outflow of undesired charges into and from the n-type impurity region 67n, which serves as a charge accumulation region, caused by crystal defects in the semiconductor substrate 60, or in other words, interface states, at the interface between the contact plug cp1 and the semiconductor substrate 60. Furthermore, by connecting the contact plug cp1 to the second region 67b, which has a relatively high impurity concentration, the contact resistance can be reduced.

[0104] The aforementioned signal detection circuit 14A is formed on the semiconductor substrate 60. The signal detection circuit 14A in the pixel 10A is electrically isolated from the signal detection circuits 14A in other adjacent pixels 10A by providing an element isolation region 69 between adjacent pixels 10A. The element isolation region 69 is, for example, a p-type impurity region.

[0105] In signal detection circuit 14A, reset transistor 26 includes an n-type impurity region 67n as one of its drain and source regions, and an n-type impurity region 68an as the other of its drain and source regions. Reset transistor 26 also includes a gate electrode 26e on a first insulating layer 70. The portion of first insulating layer 70 located between gate electrode 26e and semiconductor substrate 60 functions as a gate insulating film for reset transistor 26. N-type impurity region 68an is formed in p-type semiconductor layer 65p and is connected to feedback line 53 via contact plug cp2.

[0106] N-type impurity regions 68bn, 68cn, and 68dn are also provided in p-type semiconductor layer 65p. N-type impurity regions 68bn, 68cn, and 68dn are located in semiconductor substrate 60 and contain impurities of the first conductivity type. They are examples of second impurity regions different from the first impurity regions. Furthermore, the impurity concentrations of n-type impurity regions 68an, 68bn, 68cn, and 68dn are higher than the impurity concentration of first region 67a of n-type impurity region 67n.

[0107] The signal detection transistor 22 includes an n-type impurity region 68bn, an n-type impurity region 68cn, and a gate electrode 22e on the first insulating layer 70. In this example, the gate electrode 22e is connected to a portion of the conductive structure 89 that connects the pixel electrode 12a and the contact plug cp1 to each other, in a layer where the address signal line 34 and the reset signal line 36 are located. In other words, the conductive structure 89 is also electrically connected to the gate electrode 22e.

[0108] The contact hole h3 penetrates the n-type impurity region 68bn serving as the drain region and is connected to a contact plug cp3. The contact plug cp3 is connected to the power supply wiring 32 serving as a source follower power supply.

[0109] As in Figure 3B As schematically shown in FIG, n-type impurity region 68bn is arranged in p-type semiconductor layer 65p away from n-type impurity region 67n, which serves as a charge storage region. In this example, n-type impurity region 68bn is electrically isolated from n-type impurity region 67n by interposing impurity regions 69pa and 69pb between n-type impurity region 68bn and n-type impurity region 67n. Impurity regions 69pa and 69pb are each part of the aforementioned element isolation region 69 and are typically p-type impurity regions. The impurity concentration in impurity regions 69pa and 69pb is higher than that in p-type semiconductor layer 65p, for example, 5×10 17 cm －3 Above 1×10 19 cm －3 As shown in the figure, when observing a cross section perpendicular to the main surface of semiconductor substrate 60, impurity regions 69pa and 69pb are provided in p-type semiconductor layer 65p, separated from each other, between n-type impurity region 67n and n-type impurity region 68bn.

[0110] Furthermore, a truncation structure 28 is provided in the region between the impurity region 69pa and the impurity region 69pb on the first insulating layer 70. The truncation structure 28 comprises a semiconductor layer cp5 and a p-type impurity region 28a. As shown, the semiconductor layer cp5 is covered by a stacked structure of a second insulating layer 71 and a third insulating layer 72. Furthermore, in this example, the stacked structure of the second insulating layer 71 and the third insulating layer 72 also covers the gate electrode 26e of the reset transistor 26 and gate electrodes 22e and 24e (described later). The semiconductor layer cp5 penetrates the contact hole h5 provided in the first insulating layer 70 and is connected to the p-type impurity region 28a in the semiconductor substrate 60.

[0111] exist Figure 3A In the illustrated structure, the partitioning structure 28 has a rectangular shape extending in parallel in the column direction of the plurality of pixels 10A. Figure 3A In the example shown, the signal detection transistor 22 and the address transistor 24 are arranged in a straight line along the vertical direction of the paper. Their drain regions and source regions are electrically isolated from the drain region and source region of the reset transistor 26 by the element isolation region 69, which partially includes the impurity region 69pa and the impurity region 69pb.

[0112] (Details of truncation structure)

[0113] Here, refer again Figure 3B , describing the detailed structure of the truncation structure 28.

[0114] As described above, the truncation structure 28 includes a p-type impurity region 28a, which serves as an example of a third impurity region. The p-type impurity region 28a is formed within the p-type semiconductor layer 65p by diffusing p-type impurities from the semiconductor layer cp5, which is polycrystalline silicon and doped with p-type impurities. The p-type impurity region 28a is a high-concentration p-type impurity region near the surface of the semiconductor substrate. Furthermore, the semiconductor layer cp5, located on the semiconductor substrate 60 and electrically connected to the third impurity region, serves as an example of a first contact portion comprising a semiconductor containing an impurity of the second conductivity type.

[0115] As described above, n-type impurity region 68bn, which functions as the drain region of signal detection transistor 22, is applied with a relatively high voltage of approximately 3.3V during operation of imaging device 100. According to the present inventors' research, when electrons are generated by the pn junction formed between the high-voltage drain region and its surroundings, some of these electrons may flow into the charge accumulation region through diffusion utilizing interface states in the device isolation region and on the silicon substrate surface. Leakage current caused by this excess charge inflow can degrade the resulting image.

[0116] In contrast, here, a blocking structure 28 is provided between n-type impurity region 68an, which serves as the drain region of signal detection transistor 22, and n-type impurity region 67n, which serves as a charge storage region for holding signal charge. Therefore, even if electrons migrate from n-type impurity region 68bn toward n-type impurity region 67n due to diffusion, these electrons are prevented from reaching the other n-type impurity region due to the potential barrier created by p-type impurity region 28a formed immediately below semiconductor layer cp5 in semiconductor substrate 60, or may be eliminated by recombination with holes. In other words, the movement of minority carriers toward n-type impurity region 67n is blocked by p-type impurity region 28a formed immediately below semiconductor layer cp5. As a result, leakage current caused by the influx of minority carriers into n-type impurity region 67n is suppressed.

[0117] Figure 4A and Figure 4B Is the distance Figure 3B FIG. 2 is a diagram showing a distribution of impurity concentration in a region near the truncated structure 28 obtained by simulation. Figure 4A Indicates distance Figure 3B The distribution diagram of the impurity concentration in the cross section of the region near the truncated structure 28 in FIG. Figure 4A In FIG. 1 , the positional relationship between the n-type impurity region 68bn and the n-type impurity region 67n and the cutoff structure 28 is relative to Figure 3B Reversed. Figure 4B express Figure 4A The distribution diagram of the impurity concentration in the depth direction of the semiconductor substrate 60 at the dotted line. Figure 4B The distribution graph of this embodiment and the distribution graph of the reference example are shown in . Here, the reference example is an imaging device in which, instead of the truncated structure 28 of this embodiment, only a p-type impurity region formed near the surface of the semiconductor substrate 60 is used as the truncated structure.

[0118] like Figure 4BAs shown, in this embodiment, due to the presence of the p-type impurity region 28a formed immediately below the semiconductor layer cp5, the impurity concentration is highest at the surface of the semiconductor substrate 60 and decreases with increasing depth. Furthermore, the second conductivity-type impurity concentration within the semiconductor layer cp5, which serves as the first contact, is higher than the second conductivity-type impurity concentration in the portion of the semiconductor substrate 60 below the surface of the p-type impurity region 28a, which serves as the third impurity region. In contrast, in the reference example, the impurity concentration is highest slightly deeper than the surface of the semiconductor substrate 60 and decreases with increasing depth. The reason for this difference is explained below. This is because, in this embodiment, the stop structure 28 comprises the semiconductor layer cp5, which is polycrystalline silicon doped with a high concentration of p-type impurities. The p-type impurities diffuse from the semiconductor layer cp5 into the semiconductor substrate 60, forming the p-type impurity region 28a. In the reference example, however, the semiconductor layer cp5 is not provided, and the p-type impurity region is formed by ion implantation into the semiconductor substrate 60.

[0119] Thus, in this embodiment, the second conductivity type impurity concentration within semiconductor layer cp5, which serves as the first contact portion, is greater than the second conductivity type impurity concentration in the portion below the surface of semiconductor substrate 60, which is p-type impurity region 28a, which serves as the third impurity region. Consequently, compared to the reference example, leakage current caused by electron diffusion from n-type impurity region 68bn to n-type impurity region 67n at the interface level on the surface of semiconductor substrate 60 is suppressed.

[0120] Figure 5 This is a diagram showing the magnitude of the leakage current flowing from the n-type impurity region 68bn to the n-type impurity region 67n obtained by simulation, comparing the first embodiment and the reference example. More specifically, Figure 5 Indicates the magnitude of the leakage current in the present embodiment and the reference example when the n-type impurity region 68bn is relatively small. The vertical axis indicates the ratio of the current flowing in the n-type impurity region 67n. Specifically, it indicates INQ / (INL+IGW+INQ). INQ, INL, and IGW are the current flowing in the n-type impurity region 67n, the current flowing in the n-type impurity region 68bn, and the current flowing in the n-type semiconductor layer 62n, respectively. In the simulation, it was assumed that 0.5V was applied to the n-type impurity region 67n, 3.3V was applied to the n-type impurity region 68bn, 0.5V was applied to the n-type semiconductor layer 62n, and 0V was applied to the p-type semiconductor layer 61p. In addition, the reference example in this figure is different from the reference example in Figure 4B The same as the reference example described in .

[0121] according to Figure 5It can be seen that in this embodiment where the blocking structure 28 includes the semiconductor layer cp5, leakage current caused by electron diffusion into the n-type impurity region 67n is suppressed compared to the reference example. The same trend is observed when the n-type impurity region 68bn is relatively small or large.

[0122] Figure 6 2 is a diagram showing the electron current distribution in the cross section of the semiconductor substrate 60 close to the cutoff structure 28 obtained by simulation. More specifically, Figure 6 Part (a) shows the electron current distribution in the reference example, Figure 6 Part (b) shows the electron current distribution in this embodiment. Figure 4B The same as the reference example described in . Figure 6 In parts (a) and (b), arrows indicate electron diffusion paths from the n-type impurity region 68bn.

[0123] Focus on the electron current distribution from the n-type impurity region 68bn to the n-type impurity region 67n. Figure 6 In the reference example shown in part (a) of FIG. 1 , a higher value distribution can be seen in a region closer to the n-type impurity region 67n. In contrast, in Figure 6 In this embodiment, as shown in part (b), a distribution with extremely low values ​​is observed in a region close to n-type impurity region 67n. This indicates that, in this embodiment, p-type impurity region 28a formed immediately below semiconductor layer cp5 suppresses electron current flowing from n-type impurity region 68bn to n-type impurity region 67n.

[0124] (First Modification of the First Embodiment)

[0125] Figure 7 This is a plan view showing an example of the layout of each element in the pixel 10B of the first variant of the first embodiment of the present invention. In this variant, unlike the first embodiment, in addition to the truncation structure 28, a semiconductor layer cp6 is also provided. The semiconductor layer cp6 penetrates the contact hole h6 and is electrically connected to the p-type semiconductor layer 65p serving as a p-type well. In addition, the semiconductor layer cp6 is connected to the voltage supply circuit 48 via the voltage line 38. By supplying a voltage from the voltage supply circuit 48 to the semiconductor layer cp6, the potential of the p-type semiconductor layer 65p can be controlled to a desired value. In other words, the semiconductor layer cp6 can be used as a substrate contact portion. As a result, there is no need to provide a substrate contact portion outside the imaging area for fixing the potential of the support substrate 61, so the overall size of the imaging device can be reduced.

[0126] (Second Modification of the First Embodiment)

[0127] Figure 8A 1 is a plan view showing an example of the layout of each element in the pixel 10C according to the second modification of the first embodiment of the present invention. Figure 3A The difference from the first embodiment shown is that the semiconductor layer cp5 is connected to a voltage supply circuit 48 via a voltage line 38. By supplying a voltage from the voltage supply circuit 48 to the semiconductor layer cp5, the potential of the p-type semiconductor layer 65p can be controlled to a desired value via the p-type impurity region 28a. In other words, the interrupting structure 28 can also serve as a substrate contact portion.

[0128] Figure 8B is a schematic cross-sectional view showing an exemplary structure of a pixel 10C. Figure 8B It is along Figure 8A A cross-sectional view showing the pixel 10C being cut and unfolded by the dotted line 8B-8B in FIG. As shown in the figure, the semiconductor layer cp5 constituting the truncation structure 28 is connected to the voltage line 38 via the plug pa8. In addition, in this modification, the p-type semiconductor layer 61p is located in the semiconductor substrate 60 and is an example of the first region containing impurities of the second conductive type. The n-type semiconductor layer 62n covers the entire surface of the first region and is an example of the second region containing impurities of the first conductive type. Furthermore, the p-type semiconductor layer 65p and the p-type impurity region 66p are examples of well regions located on the second region. That is, in this modification, no Figure 3B A p-type region 64 is shown.

[0129] With such a structure, the cutoff structure 28 can be used not only to suppress leakage current to the n-type impurity region 67n, but also to be used as a substrate contact portion. Figure 3B As can be seen from the p-type region 64 shown, there is no need to provide a separate substrate contact portion for fixing the potential of the support substrate 61, so the size of the entire imaging device can be reduced.

[0130] (Third Modification of the First Embodiment)

[0131] Figure 9 This is a plan view showing an example of the layout of various elements in a pixel according to the third variation of the first embodiment of the present invention. In this variation, in plan view, truncation structures 28 and 281 are formed on the left and right sides of the n-type impurity region 67n, which serves as a charge accumulation region. Specifically, while in the above-described embodiment, truncation structure 28 is provided only between the n-type impurity region 67n and the n-type impurity region 68bn in each pixel, in this variation, truncation structure 281 is also provided between the n-type impurity region 67n in the first pixel and the n-type impurity region 68bn in the second pixel adjacent to the first pixel. Truncation structure 281 is provided, for example, at the boundary between the first and second pixels.

[0132] The truncation structure 281 also has the same structure as the truncation structure 28. Specifically, the truncation structure 281 is a structure including a semiconductor layer cp5 and a p-type impurity region 28a. The semiconductor layer cp5 constituting the truncation structure 281 is covered by a stacked structure of a second insulating layer 71 and a third insulating layer 72. The semiconductor layer cp5 penetrates the contact hole h5 provided in the first insulating layer 70 and is connected to the semiconductor substrate 60. Furthermore, a high-concentration p-type impurity region 28a is formed in the p-type semiconductor layer 65p immediately below the semiconductor layer cp5 constituting the truncation structure 281.

[0133] Furthermore, n-type impurity region 68bn in the second pixel is located in semiconductor substrate 60 in the second pixel and is an example of a fourth impurity region containing impurities of the first conductivity type. P-type impurity region 28a, located immediately below semiconductor layer cp5 constituting truncation structure 281, is located in semiconductor substrate 60 and, in plan view, is located between the first and fourth impurity regions. It is an example of a fifth impurity region containing impurities of the second conductivity type. Semiconductor layer cp5 constituting truncation structure 281 is located on semiconductor substrate 60 and is electrically connected to the fifth impurity region. It is an example of a second contact portion comprising a semiconductor containing impurities of the second conductivity type.

[0134] According to this modification, not only leakage current that may occur in a pixel is suppressed, but also leakage current caused by mixing of minority carriers from adjacent pixels is suppressed.

[0135] (Fourth Modification of the First Embodiment)

[0136] Figure 10A is a schematic cross-sectional view showing an exemplary structure of a pixel 10D according to a fourth modification of the first embodiment of the present invention. Figure 10B 1 is a schematic cross-sectional view showing an exemplary structure of a pixel 10E according to a fourth modification of the first embodiment of the present invention. Figure 10A and Figure 10B In FIG. 1 , the hatched area with a rightward ascending slant line indicates that p-type impurities are contained, and the hatched area with a rightward descending slant line indicates that n-type impurities are contained.

[0137] Figure 10AThe illustrated pixel 10D differs from the first embodiment in that it lacks an element isolation region 69 between the n-type impurity region 67n and the n-type impurity region 68bn. The p-type impurity region 28a contains p-type impurities of opposite conductivity to the n-type impurity regions 67n and 68bn. This not only suppresses leakage current into the charge storage region but also allows the p-type impurity region 28pa to double as an element isolation region. This eliminates the need for a separate element isolation region, reducing the number and amount of impurity injections into the semiconductor substrate. Consequently, damage to the semiconductor substrate caused by impurity injection can be mitigated.

[0138] exist Figure 10B In the illustrated pixel 10E, unlike the first embodiment, semiconductor layer cp5a constituting the truncation structure 28 comprises a semiconductor containing n-type impurities of the same conductivity type as the n-type impurity regions 67n and 68bn. Furthermore, n-type impurity region 28b contains n-type impurities. In this example, as in the first embodiment, p-type impurity regions 69pa and 69pb are formed as element isolation regions.

[0139] Specifically, in pixel 10E, n-type impurity region 67n is located in semiconductor substrate 60, electrically connected to photoelectric conversion structure 12, and is an example of a first impurity region containing impurities of the first conductivity type. n-type impurity region 68bn is located in semiconductor substrate 60, contains impurities of the first conductivity type, and is an example of a second impurity region different from the first impurity region. n-type impurity region 28b is located in semiconductor substrate 60, positioned between the first and second impurity regions in plan view, and is an example of a sixth impurity region containing impurities of the first conductivity type. Semiconductor layer cp5a is located on semiconductor substrate 60, electrically connected to the sixth impurity region, and is an example of a third contact portion comprising a semiconductor containing impurities of the first conductivity type. P-type impurity regions 69pa and 69pb, which constitute element isolation regions, are located in semiconductor substrate 60, positioned between the first and sixth impurity regions, and between the second and sixth impurity regions, in plan view, and are an example of a seventh impurity region containing impurities of the second conductivity type, different from the first conductivity type. Due to the presence of p-type impurity regions 69pa and 69pb constituting the element isolation region, n-type impurity region 28b, formed immediately below semiconductor layer cp5a, is electrically isolated from n-type impurity region 67n and n-type impurity region 68bn. Furthermore, n-type impurity region 28b absorbs unwanted charge that would otherwise migrate toward n-type impurity region 67n. Therefore, even with this type of cutoff structure, leakage current into n-type impurity region 67n can be suppressed.

[0140] (Second embodiment)

[0141] Figure 11This is a diagram showing an exemplary circuit structure of an imaging device according to a second embodiment of the present invention. The main difference from the first embodiment is that, in the second embodiment, each pixel 10F is provided with an OF transistor 27. The OF transistor 27 performs an overflow operation to discharge the charge in order to prevent an excessive potential rise in the charge accumulation region. One of the drain and source of the OF transistor 27 is connected to the gate of the OF transistor 27 and to the charge accumulation node FD. The other of the drain and source of the OF transistor 27 is connected to the power supply wiring 33. Thus, when excessive charge is accumulated at the charge accumulation node FD, the excess charge is discharged to the power supply wiring 33 via the OF transistor 27. Thus, an excessive potential rise in the charge accumulation node FD is prevented. As a result, blooming, a phenomenon in which charge generated by strong incident light above the saturation level overflows into adjacent pixels, is suppressed.

[0142] Figure 12 10F is a plan view showing an example of the layout of each element in the pixel 10F according to the second embodiment of the present invention. Figure 3A The difference from the first embodiment shown is that an OF transistor 27 and a power supply line 33 are added in the second embodiment. The OF transistor 27 includes a gate electrode 27e and an n-type impurity region 68en serving as a source region. Furthermore, the OF transistor 27 and the reset transistor 26 share an n-type impurity region 67n. The n-type impurity region 68en is connected to the power supply line 33 via the semiconductor layer cp6.

[0143] (Third embodiment)

[0144] Figure 13 This figure shows an exemplary configuration of an imaging device according to the third embodiment of the present invention. The main difference from the first embodiment is that, in the third embodiment, each pixel 10G includes a photodiode formed in a semiconductor substrate as a photoelectric conversion structure 12A. Furthermore, the signal detection circuit 14B also differs from the first embodiment in that it includes a transfer transistor 29 for transferring charge generated by the photodiode to a charge storage node FD.

[0145] Figure 14This is a plan view showing an example of the layout of the various components in pixel 10G. In the third embodiment, the charge generated by the photoelectric conversion structure 12A is transferred to the n-type impurity region 67n by a transfer transistor 29 having a gate electrode 29e. As in the first embodiment, a cutoff structure 282, similar to that in the first embodiment, is provided between the n-type impurity region 67n and the n-type impurity region 68bn. The cutoff structure 282 includes a semiconductor layer cp7 electrically connected to the p-type semiconductor layer 65p, which serves as a p-type well. Furthermore, as in the second variation of the first embodiment, the semiconductor layer cp7 is connected to the voltage supply circuit 48 via a voltage line 38.

[0146] The same effects as those of the first embodiment can be obtained in an imaging device including a photodiode in a semiconductor substrate by the dividing structure 282. Furthermore, as in the second modification of the first embodiment, the dividing structure 282 can also be used as a substrate contact portion.

[0147] As described above, according to the embodiment and the modified example of the present invention, the influence of the leakage current can be suppressed, and thus an imaging device capable of capturing images with high image quality can be provided.

[0148] In addition, the imaging device of the present invention has been described based on the embodiments and variations thereof, but the present invention is not limited to these embodiments and variations. Forms obtained by applying various modifications conceived by those skilled in the art to the embodiments and variations thereof, as well as other forms constructed by combining some of the constituent elements of the embodiments and variations thereof, are also included within the scope of the present invention, without departing from the gist of the present invention. Furthermore, various changes, substitutions, additions, and omissions may be made to the above-described embodiments and variations within the scope of the claims or their equivalents.

[0149] For example, the signal detection transistor 22, address transistor 24, and reset transistor 26 can each be an N-channel MOSFET or a P-channel MOSFET. It is not necessary for all of these transistors to be either N-channel or P-channel MOSFETs. If each transistor in a pixel is an N-channel MOSFET and electrons are used as signal charge, the source and drain configurations of these transistors can be interchanged.

[0150] Furthermore, in the above-described embodiment and modified examples, the blocking structure is provided between n-type impurity region 68bn and n-type impurity region 67n in plan view, but this is not limited to this location. Alternatively, it may be provided between n-type impurity region 67n and any other impurity region that may serve as a carrier generation region. Thus, by providing blocking structures in the numerous paths that may flow into the charge accumulation region, leakage current into the charge accumulation region can be further suppressed.

[0151] Furthermore, in the above-described embodiments and variations, the semiconductor layer in the truncated structure is a linear rectangular region in plan view, but this is not limited to such a shape. It can also be an L-shaped shape, or a shape that extends longer than in the above-described embodiments and variations. Thus, by providing a truncated structure in a path where there is a high probability of current flowing into the charge accumulation region, leakage current into the charge accumulation region can be further suppressed.

[0152] Industrial applicability

[0153] According to an embodiment of the present invention, an imaging device is provided that can suppress the effects of leakage current and capture images with high image quality. The imaging device of the present invention is useful, for example, in image sensors and digital cameras. The imaging device of the present invention can be used in medical cameras, robotic cameras, surveillance cameras, and cameras mounted on vehicles.

[0154] Label Description

[0155] 10, 10A, 10B, 10C, 10D, 10E, 10F, 10G pixels

[0156] 12 Photoelectric conversion structure

[0157] 14A, 14B signal detection circuit

[0158] 16A feedback circuit

[0159] 22 Signal detection transistor

[0160] 22e Gate electrode of the signal detection transistor

[0161] 24 address transistors

[0162] 24e Gate electrode of address transistor

[0163] 26 Reset transistor

[0164] 26e Gate electrode of reset transistor

[0165] 27 OF transistor

[0166] 27e gate electrode of OF transistor

[0167] 28, 281, 282 truncation structures

[0168] 28a p-type impurity region

[0169] 28b n-type impurity region

[0170] 29 Transfer transistor

[0171] 29e Gate electrode of transfer transistor

[0172] 60 semiconductor substrate

[0173] 61 Support base plate

[0174] 61p, 63p, 65p p-type semiconductor layer

[0175] 62n n-type semiconductor layer

[0176] 64 p-type region

[0177] 66p p-type impurity region

[0178] 67a, 67b, 67n, 68an, 68bn, 68cn, 68dn, 68en n-type impurity regions

[0179] 69 Component separation area

[0180] 69pa, 69pb impurity region

[0181] 70, 71, 72 insulation layer

[0182] 90 interlayer insulation layer

[0183] 100 Camera

[0184] R1 Camera Area

[0185] R2 surrounding area

[0186] cp1, cp2, cp3 contact plugs

[0187] cp5, cp6, cp7, cp5a semiconductor layer

[0188] h1, h2, h3, h4, h5, h6 contact holes

[0189] pa1, pa2, pa3, pa4, pa4, pa6, pa7, pa8 plugs

Claims

1. A camera device, characterized in that: have: semiconductor substrates; A photoelectric conversion unit converts incident light into electric charge; a first impurity region located in the semiconductor substrate, storing the charge, and containing impurities of the first conductivity type; a second impurity region different from the first impurity region, located in the semiconductor substrate and containing impurities of the first conductivity type; a third impurity region located in the semiconductor substrate, between the first impurity region and the second impurity region in plan view, and containing impurities of a second conductivity type different from the first conductivity type; and The first contact portion is located on the semiconductor substrate, is electrically connected to the third impurity region, and includes a semiconductor containing an impurity of the second conductivity type.

2. The imaging device according to claim 1, wherein The second conductivity type impurity concentration in the first contact portion is higher than the second conductivity type impurity concentration in a portion of the third impurity region located below a surface of the semiconductor substrate.

3. The imaging device according to claim 1 or 2, wherein: Also features: a voltage supply circuit for supplying voltage to the first contact portion; and a well region located in the semiconductor substrate and containing the second conductivity type impurities; The first impurity region, the second impurity region, and the third impurity region are located in the well region.

4. The imaging device according to claim 1 or 2, wherein: Also has the first pixel; The first pixel includes the first impurity region, the second impurity region, the third impurity region, and the first contact portion.

5. The imaging device according to claim 1 or 2, wherein: further comprising a first pixel and a second pixel different from the first pixel; The first pixel includes the first impurity region; The second pixel includes the second impurity region.

6. The imaging device according to claim 1 or 2, wherein: further comprising a first pixel and a second pixel different from the first pixel; The first pixel includes the first impurity region, the second impurity region, the third impurity region, and the first contact portion; The second pixel includes: a fourth impurity region located in the semiconductor substrate and containing the first conductivity type impurities; a fifth impurity region located in the semiconductor substrate, between the first impurity region and the fourth impurity region in plan view, and containing an impurity of the second conductivity type; and The second contact portion is located on the semiconductor substrate, is electrically connected to the fifth impurity region, and includes a semiconductor containing an impurity of the second conductivity type.

7. The imaging device according to claim 1 or 2, wherein: The first impurity region and the second impurity region are not electrically connected.

8. The imaging device according to claim 1 or 2, wherein: A transistor is further provided, the transistor including the second impurity region as one of a source and a drain, and detecting a signal corresponding to the potential of the first impurity region.

9. The imaging device according to claim 8, wherein The transistor includes a gate electrode electrically connected to the first impurity region.

10. The imaging device according to claim 1 or 2, wherein: The third impurity region is in contact with the surface of the semiconductor substrate.

11. A camera device, characterized in that: have: semiconductor substrates; A photoelectric conversion unit converts incident light into electric charge; a first impurity region located in the semiconductor substrate, storing the charge, and containing impurities of the first conductivity type; a second impurity region different from the first impurity region, located in the semiconductor substrate and containing impurities of the first conductivity type; a sixth impurity region located in the semiconductor substrate, between the first impurity region and the second impurity region in plan view, and containing an impurity of the first conductivity type; a third contact portion, located on the semiconductor substrate, electrically connected to the sixth impurity region, and comprising a semiconductor containing an impurity of the first conductivity type; and The seventh impurity region is located in the semiconductor substrate, between the first impurity region and the sixth impurity region and between the second impurity region and the sixth impurity region in a planar view, and contains impurities of a second conductivity type different from the first conductivity type.

12. The imaging device according to claim 11, wherein The first conductivity type impurity concentration in the third contact portion is higher than the first conductivity type impurity concentration in a portion of the sixth impurity region located below the surface of the semiconductor substrate.

13. The imaging device according to claim 11 or 12, wherein: Also features: a voltage supply circuit for supplying voltage to the third contact portion; and a well region located in the semiconductor substrate and containing the second conductivity type impurities; The first impurity region, the second impurity region, the sixth impurity region, and the seventh impurity region are located in the well region.

14. The imaging device according to claim 11 or 12, wherein: further comprising a first pixel and a second pixel different from the first pixel; The first pixel includes the first impurity region; The second pixel includes the second impurity region.

15. The imaging device according to claim 11 or 12, wherein: further comprising a first pixel and a second pixel different from the first pixel; The first pixel includes the first impurity region, the second impurity region, the sixth impurity region, the seventh impurity region, and the third contact portion; The second pixel includes: a fourth impurity region located in the semiconductor substrate and containing the first conductivity type impurities; an eighth impurity region located in the semiconductor substrate, between the first impurity region and the fourth impurity region in plan view, and containing an impurity of the first conductivity type; a fourth contact portion, located on the semiconductor substrate and electrically connected to the eighth impurity region, comprising a semiconductor containing an impurity of the first conductivity type; and The ninth impurity region is located in the semiconductor substrate between the first impurity region and the eighth impurity region and between the fourth impurity region and the eighth impurity region in plan view, and contains impurities of the second conductivity type.

16. The imaging device according to claim 13, wherein Also features: a first region located in the semiconductor substrate and containing the second conductivity type impurities; and a second region covering the entire surface of the first region and containing the first conductivity type impurities; The well region is located on the second region.

17. The imaging device according to claim 11 or 12, wherein: The first impurity region and the second impurity region are not electrically connected.

18. The imaging device according to claim 11 or 12, wherein: A transistor is further provided, the transistor including the second impurity region as one of a source and a drain, and detecting a signal corresponding to the potential of the first impurity region.

19. The imaging device according to claim 18, wherein The transistor includes a gate electrode electrically connected to the first impurity region.

20. The imaging device according to claim 11 or 12, wherein: The sixth impurity region is in contact with the surface of the semiconductor substrate.

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