DRAM testing methods, apparatus, readable storage media and electronic devices
By conducting two rounds of testing on DRAM, using different preset directions and data comparison methods, the problem of low fault coverage in DRAM testing was solved, achieving higher testing reliability and accuracy, and detecting chip defects that are difficult to detect.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-03-05
- Publication Date
- 2026-03-10
AI Technical Summary
Existing technologies for DRAM testing suffer from low fault coverage and difficulty in detecting chip defects that are easily triggered under discontinuous access.
A two-round testing method was adopted, in which the DRAM storage array was traversed in units of preset test units. The first and second rounds used different preset directions and performed data read and write operations on each preset operation unit. The difference between the read data and the written data was compared and the second round of testing was performed by inverse data.
It improves fault coverage, enhances the reliability and accuracy of test results, covers chip defects that are difficult to detect in existing technologies, and improves product quality.
Smart Images
Figure CN113035259B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of DRAM chip testing, and more particularly to a DRAM testing method, apparatus, readable storage medium, and electronic device. Background Technology
[0002] Dynamic Random Access Memory (DRAM) is an indispensable component of modern computer systems. Platforms may include Double Data Rate (DDR) modules for personal computers or servers, as well as Low Power Double Data Rate (LPDDR) chips for embedded ARM architectures.
[0003] The basic storage unit of LPDDR is a cell. Computers and embedded systems store and read data by writing high or low voltage levels into the cells. Cells are arranged in rows and columns, and the array formed by them is called a bank. Each LPDDR chip has multiple banks. The current LPDDR4 has 8 banks. For the sake of illustration, the diagram in this article uses 4 banks as an example.
[0004] Furthermore, current DRAM uses burst read / write for high access speeds. This means read / write operations within a memory array are performed in units of burst length (BL), handling multiple bits (e.g., 8-bit, 16-bit, or 32-bit) of column addresses at a time, accessing data consisting of 0s and 1s within each burst length. For example, if the target address is row 0 and the burst length is 8 bits, then 1 bit of data is written to each bit in the space from row 0, column 0 to row 0, column 7, for a total of 8 bits. The second burst length is from row 0, column 8 to column 15, and so on. When all memory locations in a row are written, the memory controller (MC) locates the address of the next row and continues the same operation.
[0005] Different access methods can affect the state of memory cells. Generally, integrated circuits (ICs) are accessed sequentially, meaning they are accessed consecutively within a bank. However, in memory failure models, some faults are more likely to be triggered by non-contiguous access, such as coupling faults (CF). Therefore, some fault types cannot be covered under sequential access conditions. Summary of the Invention
[0006] The technical problem to be solved by the present invention is to provide a DRAM testing method, apparatus, readable storage medium and electronic device that can improve the fault coverage when testing DRAM.
[0007] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:
[0008] A DRAM testing method, comprising the following steps:
[0009] The DRAM to be tested was subjected to two rounds of testing, and the first comparison result and the second comparison result were obtained respectively.
[0010] The test includes:
[0011] Preset test data is written to the memory array of the DRAM under test until all memory cells of the DRAM under test have been written with data;
[0012] The storage array is traversed in units of preset test units until all storage units of the storage array have been traversed. The preset test unit includes a preset operation unit corresponding to the same position on each storage cell of the storage array.
[0013] For each target test unit traversed, based on the preset test data, data read and write operations are performed on each preset operation unit of the target test unit in a preset order, and the read data is compared with the corresponding written data.
[0014] The preset test data for the first round of testing is the inverse of the preset test data for the second round of testing;
[0015] The test results of the DRAM to be tested are obtained based on the first comparison result and the second comparison result.
[0016] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is as follows:
[0017] A DRAM testing apparatus, comprising:
[0018] The data read / write module is used to perform two rounds of testing on the DRAM under test, and obtain the first comparison result and the second comparison result respectively.
[0019] The test includes:
[0020] Preset test data is written to the memory array of the DRAM under test until all memory cells of the DRAM under test have been written with data;
[0021] The storage array is traversed in units of preset test units until all storage units of the storage array have been traversed. The preset test unit includes a preset operation unit corresponding to the same position on each storage cell of the storage array.
[0022] For each target test unit traversed, based on the preset test data, data read and write operations are performed on each preset operation unit of the target test unit in a preset order, and the read data is compared with the corresponding written data.
[0023] The preset test data for the first round of testing is the inverse of the preset test data for the second round of testing;
[0024] The testing module is used to obtain the test results of the DRAM to be tested based on the first comparison result and the second comparison result.
[0025] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is as follows:
[0026] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the DRAM testing method described above.
[0027] To solve the above-mentioned technical problems, another technical solution adopted by the present invention is as follows:
[0028] An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the DRAM testing method described above.
[0029] The beneficial effects of this invention are as follows:
[0030] By performing two rounds of testing on the DRAM under test, the memory array is traversed in units of preset test units until all memory cells in the memory array have been traversed. The preset test units include preset operation units corresponding to the same position on each memory bank of the memory array. For the target test unit traversed, data read and write operations are performed on each preset operation unit of the target test unit according to a preset order based on preset test data. The read data is compared with the corresponding written data. The final test result is obtained by comparing the results of the two rounds of testing. Since some faults are more easily triggered by non-continuous access, the memory array is traversed in units of preset test units until all memory cells in the memory array have been traversed. The preset test units include preset operation units corresponding to the same position on each memory bank of the memory array. Then, data read and write operations are performed on each preset operation unit of the target test unit according to a preset order. This achieves matrix jump access, which is no longer a sequential access in a memory bank as in the existing technology. It simulates the situation of non-continuous access, covers the previous test blind spots, and detects chip defects that are difficult to detect in the existing technology. This improves the fault coverage, enhances the reliability of the test results, and thus improves the product yield. Attached Figure Description
[0031] Figure 1 This is a flowchart illustrating the steps of a DRAM testing method according to an embodiment of the present invention;
[0032] Figure 2 This is a schematic diagram of the structure of a DRAM testing device according to an embodiment of the present invention;
[0033] Figure 3 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention;
[0034] Figure 4 This is a schematic diagram of preset test data and the inverse of preset test data in the DRAM testing method of this embodiment of the invention;
[0035] Figure 5 This is a flowchart of the DRAM testing method according to an embodiment of the present invention;
[0036] Figure 6 This is a schematic diagram of the first round of testing in the DRAM testing method of this invention.
[0037] Figure 7 This is a schematic diagram of the first round of testing in the DRAM testing method of this invention.
[0038] Figure 8 This is a schematic diagram of the second round of testing in the DRAM testing method of this invention.
[0039] Figure 9This is a schematic diagram of the second round of testing in the DRAM testing method of this invention.
[0040] Figure 10 This is a schematic diagram of the second round of testing in the DRAM testing method of this invention. Detailed Implementation
[0041] To explain in detail the technical content, objectives, and effects of the present invention, the following description is provided in conjunction with the embodiments and accompanying drawings.
[0042] Please refer to Figure 1 This invention provides a DRAM testing method, including the following steps:
[0043] The DRAM to be tested was subjected to two rounds of testing, and the first comparison result and the second comparison result were obtained respectively.
[0044] The test includes:
[0045] Preset test data is written to the memory array of the DRAM under test until all memory cells of the DRAM under test have been written with data;
[0046] The storage array is traversed in units of preset test units until all storage units of the storage array have been traversed. The preset test unit includes a preset operation unit corresponding to the same position on each storage cell of the storage array.
[0047] For each target test unit traversed, based on the preset test data, data read and write operations are performed on each preset operation unit of the target test unit in a preset order, and the read data is compared with the corresponding written data.
[0048] The preset test data for the first round of testing is the inverse of the preset test data for the second round of testing;
[0049] The test results of the DRAM to be tested are obtained based on the first comparison result and the second comparison result.
[0050] As can be seen from the above description, the beneficial effects of the present invention are as follows: By performing two rounds of testing on the DRAM to be tested, the memory array is traversed in units of preset test units until all memory cells of the memory array have been traversed. The preset test units include preset operation units corresponding to the same position on each memory cell of the memory array. For the target test unit that has been traversed, data read and write operations are performed on each preset operation unit of the target test unit according to a preset order based on preset test data. The read data is compared with the corresponding written data. The final test result is obtained through the comparison results of the two rounds of testing. Since some faults are more easily triggered by non-continuous access, the memory array is traversed in units of preset test units until all memory cells of the memory array have been traversed. The preset test units include preset operation units corresponding to the same position on each memory cell of the memory array. Then, data read and write operations are performed on each preset operation unit of the target test unit according to a preset order. Matrix jump access is realized, unlike the continuous access in a memory cell in the prior art. This simulates the situation of non-continuous access, covers the previous test blind spots, and detects chip defects that are difficult to detect in the existing technology, improves the fault coverage, enhances the reliability of the test results, and thus improves the product quality.
[0051] Further, the step of writing preset test data to the memory array of the DRAM under test until all memory cells of the DRAM under test have been written with data includes:
[0052] The preset test data is written from the low address of each preset read / write cell of the DRAM under test in units of a preset burst length until all cells of the DRAM under test have been written with data.
[0053] The preset read / write unit includes rows or columns.
[0054] As described above, writing preset test data to the DRAM to be tested in burst length units can improve the data writing speed and has low time complexity, making it suitable for mass production testing.
[0055] Furthermore, the step of traversing the storage array in units of preset test units until all storage units of the storage array have been traversed includes:
[0056] The storage array is traversed in a preset direction, with each preset test unit as a unit, until all storage units of the storage array have been traversed.
[0057] Furthermore, the preset direction includes either the row direction or the column direction;
[0058] The preset directions for the first round of testing and the second round of testing are different.
[0059] As described above, the storage array is traversed in a preset direction until all storage cells of the storage array have been traversed. Testers can set the preset direction to row or column as needed, which is highly flexible. Furthermore, the preset directions for the two rounds of testing are different, which can better stimulate the failure of multiple storage cells.
[0060] Furthermore, the step of performing data read / write operations on each preset operation unit of the target test unit according to a preset order based on the preset test data includes:
[0061] Based on the preset test data, data read and write operations are performed on each preset operation unit of the target test unit in the order of the serial numbers of each memory bank in the target test unit.
[0062] As described above, writing a value with a different voltage level to a memory cell than to the surrounding cells will cause a potential difference. For the target test cell that is traversed, data read and write operations are performed on each preset operation cell of the target test cell according to the sequence number of each memory cell in the target test cell based on the preset test data. This can effectively simulate this potential difference and simulate matrix jump access, cover the previous test blind spots, and detect chip defects that are difficult to detect in the existing technology, thus ensuring the reliability and accuracy of the test.
[0063] Furthermore, for each preset operation unit, after performing the comparison, the inverse of the preset test data is written to the preset operation unit;
[0064] The second round of testing also includes the following steps:
[0065] Read the data from all preset test units of the DRAM to be tested, and compare the read data with the corresponding written data;
[0066] The preset read / write unit includes rows or columns.
[0067] As described above, for each preset operation unit, first reading the data to be written, then writing the inverse of the preset test data, can trigger a single memory cell fault, thus improving fault coverage. Finally, reading the data of all preset test units of the DRAM to be tested can once again check whether the data in the memory cell after testing meets expectations, improving the accuracy of the test and enhancing the reliability of the test results.
[0068] Further, obtaining the test result of the DRAM to be tested based on the first comparison result and the second comparison result includes:
[0069] If both the first comparison result and the second comparison result are consistent, the test result is successful; otherwise, the test result is unsuccessful.
[0070] As can be seen from the above description, by obtaining the first comparison result and the second comparison result through two rounds of testing, it is possible to detect chip defects that are difficult to find, improve the fault coverage during testing, and ensure the reliability of testing.
[0071] Please refer to Figure 2 Another embodiment of the present invention provides a DRAM testing apparatus, comprising:
[0072] The data read / write module is used to perform two rounds of testing on the DRAM under test, and obtain the first comparison result and the second comparison result respectively.
[0073] The test includes:
[0074] Preset test data is written to the memory array of the DRAM under test until all memory cells of the DRAM under test have been written with data;
[0075] The storage array is traversed in units of preset test units until all storage units of the storage array have been traversed. The preset test unit includes a preset operation unit corresponding to the same position on each storage cell of the storage array.
[0076] For each target test unit traversed, based on the preset test data, data read and write operations are performed on each preset operation unit of the target test unit in a preset order, and the read data is compared with the corresponding written data.
[0077] The preset test data for the first round of testing is the inverse of the preset test data for the second round of testing;
[0078] The testing module is used to obtain the test results of the DRAM to be tested based on the first comparison result and the second comparison result.
[0079] Another embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the various steps in the above-described DRAM testing method.
[0080] Please refer to Figure 3 Another embodiment of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the various steps in the above-described DRAM testing method.
[0081] The DRAM testing method, apparatus, computer-readable storage medium, and electronic device described above are applicable to the testing of any type of DRAM, such as DDR and LPDDR generations of products. Specific embodiments are described below:
[0082] Example 1
[0083] Please refer to Figure 1 This embodiment of a DRAM testing method includes the following steps:
[0084] S1. Perform two rounds of testing on the DRAM to be tested, and obtain the first comparison result and the second comparison result respectively;
[0085] The test includes:
[0086] S11. Write preset test data into the storage array of the DRAM to be tested until all storage cells of the DRAM to be tested have been written with data;
[0087] Specifically, the preset test data is written starting from the low address of each preset read / write cell of the DRAM under test in units of a preset burst length until all memory cells of the DRAM under test have been written with data.
[0088] The preset read / write unit can be flexibly configured according to actual needs, such as being set as a column or a row;
[0089] The burst length (BL) is defined by the JEDEC standard, but it can also be set arbitrarily. This means that multiple bits (e.g., 8 bits or 16 bits) are used for the corresponding read and write operations in one operation. For example, when writing data based on rows, if the address is row 0 and the burst length is 8 bits, the first 8 bits of the data to be written are written simultaneously starting at the position of row 0, column 0. Then, the second burst length is used to write bits 9-16 of the data to be written, and so on, until the storage location of row 0 is completely written. Then, the address of the next row is repositioned and the operation of the previous row is continued until the data is written to the entire disk. Reading data is a similar operation.
[0090] In this embodiment, the preset read / write unit is a row;
[0091] For example, start writing preset test data from the first column of the first row. After writing the first row, start writing preset test data from the first column of the second row, and so on, until data is written to every memory cell of the DRAM to be tested.
[0092] S12. Traverse the storage array in units of preset test units until all storage units of the storage array have been traversed. The preset test unit includes a preset operation unit corresponding to the same position on each storage cell of the storage array.
[0093] Specifically, the storage array is traversed in a preset direction, unit by unit, until all storage units of the storage array have been traversed;
[0094] The preset direction includes either the row direction or the column direction;
[0095] The first round of testing and the second round of testing have different preset directions;
[0096] In this embodiment, the preset direction for the first round of testing is the column direction, and the preset direction for the second round of testing is the row direction;
[0097] For example, if a storage array has 4 memory banks, and each memory bank has 4 rows and 4 columns, then there are 16 preset test units. Each preset test unit includes 4 preset operation units. The first preset test unit includes the preset operation unit in row 0, column 0 of the 0th memory bank, the preset operation unit in row 0, column 0 of the 1st memory bank, the preset operation unit in row 0, column 0 of the 2nd memory bank, and the preset operation unit in row 0, column 0 of the 3rd memory bank. The second preset test unit includes the preset operation unit in row 0, column 1 of the 0th memory bank, the preset operation unit in row 0, column 1 of the 1st memory bank, the preset operation unit in row 0, column 1 of the 2nd memory bank, and the preset operation unit in row 0, column 1 of the 3rd memory bank, and so on.
[0098] Assuming the preset direction is column direction, then start traversing a preset test cell from the 0th row and 0th column of the 0th memory cell of the storage array, then start traversing a preset test cell from the 0th row and 1st column of the 0th memory cell of the storage array, and so on, until all memory cells of the storage array have been traversed.
[0099] Assuming the preset direction is row direction, then start traversing a preset test cell from the 0th row and 0th column of the 0th memory cell of the storage array, then start traversing a preset test cell from the 1st row and 0th column of the 0th memory cell of the storage array, and so on, until all memory cells of the storage array have been traversed.
[0100] S13. For the target test unit that has been traversed, based on the preset test data, perform data read and write operations on each preset operation unit of the target test unit in a preset order, and compare the read data with the corresponding written data.
[0101] Specifically, based on the preset test data, data read and write operations are performed on each preset operation unit of the target test unit in the order of the sequence number of each storage bank in the target test unit;
[0102] Specifically, for each preset operation unit, after performing the comparison, the inverse of the preset test data is written to the preset operation unit;
[0103] For example, if the target test unit includes 4 preset operation units, then first read the data of the preset operation unit in the 0th memory bank of the target test unit, compare the read data with the corresponding written data, and write the inverse of the preset test data to it. Then read the data of the preset operation unit in the 1st memory bank of the target test unit, compare the read data with the corresponding written data, and write the inverse of the preset test data to it. Next, read the data of the preset operation unit in the 2nd memory bank of the target test unit, compare the read data with the corresponding written data, and write the inverse of the preset test data to it. Finally, read the data of the preset operation unit in the 3rd memory bank of the target test unit, compare the read data with the corresponding written data, and write the inverse of the preset test data to it.
[0104] After the first round of testing is completed, the second round of testing is conducted. The preset test data of the first round of testing is the inverse of the preset test data of the second round of testing, and the preset directions of the first round of testing and the second round of testing are different.
[0105] The second round of testing also includes the following steps:
[0106] Read the data from all preset test units of the DRAM to be tested, and compare the read data with the corresponding written data;
[0107] For example, if a storage array has 4 storage blocks, each storage block has 4 rows and 4 columns, and a preset test unit includes 4 preset operation units, then the storage array includes 16 preset test units. Read the data from these 16 preset test units and compare the read data with the corresponding written data.
[0108] S2. Obtain the test results of the DRAM to be tested based on the first comparison result and the second comparison result;
[0109] If both the first comparison result and the second comparison result are consistent, the test result is successful; otherwise, the test result is unsuccessful.
[0110] Example 2
[0111] Please refer to Figure 4-10 This embodiment further specifies how to test the DRAM under test, based on Embodiment 1, specifically as follows:
[0112] In this embodiment, specific references are made. Figure 4-10First, the first round of testing was performed on the DRAM to be tested:
[0113] like Figure 4 As shown, the test data to be written is defined as / D = 10101010……1010, and its inverse is D = 01010101……0101. Assuming the preset burst length is BL = 8 bits, then / D = 10101010, D = 01010101, and the preset direction is column direction.
[0114] S1. The address is the 0th row and 0th column of the 0th bank (memory cell). Starting from the memory cell corresponding to the 0th row and 0th column, write test data / D according to BL. After writing the 0th row, start writing test data / D from the 1st row and 0th column, and so on, until the entire memory array is written with data. Figure 6 As shown in (a);
[0115] After the data is written, the data in the DRAM to be tested is as follows: Figure 6 As shown in (a);
[0116] like Figure 6 As shown in (b), starting from the 0th row and 0th column of the 0th bank of the storage array, a preset test unit is traversed, the preset operation unit on (R0, C0) of the 0th bank in the preset test unit is read, the read data is compared with / D, and then written to D;
[0117] like Figure 6 As shown in (c), the preset operation unit on (R0, C0) of the first bank in the preset test unit is read, the read data is compared with / D, and then written to D;
[0118] like Figure 7 As shown in (a), the preset operation unit on (R0, C0) of the second bank in the preset test unit is read, the read data is compared with / D, and then written to D;
[0119] like Figure 7 As shown in (b), the preset operation unit on (R0, C0) of the third bank in the preset test unit is read, the read data is compared with / D, and then written to D;
[0120] Next, as Figure 7 As shown in (c), starting from the 0th row and 1st column of the 0th bank of the storage array, a preset test unit is traversed, the preset operation unit on (R0, C1) of the 0th bank in the preset test unit is read, the read data is compared with / D, and then written to D;
[0121] Read the preset operation unit on (R0, C1) of the first bank in the preset test unit, compare the read data with / D, and then write it to D;
[0122] Read the preset operation unit on (R0, C1) of the second bank in the preset test unit, compare the read data with / D, and then write it to D;
[0123] Read the preset operation unit on (R0, C1) of the 3rd bank in the preset test unit, compare the read data with / D, and then write it to D;
[0124] This process continues until all memory cells of the DRAM to be tested have been traversed.
[0125] After the traversal is complete, the data of the DRAM to be tested is as follows: Figure 8 As shown in (a);
[0126] Obtain the first comparison result;
[0127] In the second round of testing, the test data to be written is defined as D = 10101010, and its inverse / D = 01010101. The default direction is row direction.
[0128] like Figure 8 As shown in (b), starting from the 0th row and 0th column of the 0th bank of the storage array, a preset test unit is traversed, the preset operation unit on (R0, C0) of the 0th bank in the preset test unit is read, the read data is compared with / D, and then written to D;
[0129] like Figure 9 As shown in (a), the preset operation unit on (R0, C0) of the first bank in the preset test unit is read, the read data is compared with / D, and then written to D;
[0130] like Figure 9 As shown in (b), the preset operation unit on (R0, C0) of the second bank in the preset test unit is read, the read data is compared with / D, and then written to D;
[0131] like Figure 10 As shown in (a), the preset operation unit on (R0, C0) of the third bank in the preset test unit is read, the read data is compared with / D, and then written to D;
[0132] Next, as Figure 10As shown in (b), starting from the first row and the 0th column of the 0th bank of the storage array, a preset test unit is traversed, the preset operation unit on (R1, C0) of the 0th bank in the preset test unit is read, the read data is compared with / D, and then written to D;
[0133] Read the preset operation unit on (R1, C0) of the first bank in the preset test unit, compare the read data with / D, and then write it to D;
[0134] Read the preset operation unit on (R1, C0) of the second bank in the preset test unit, compare the read data with / D, and then write it to D;
[0135] Read the preset operation unit on (R1, C0) of the 3rd bank in the preset test unit, compare the read data with / D, and then write it to D;
[0136] This process continues until all memory cells of the DRAM to be tested have been traversed.
[0137] Read data from all preset test units, and compare the read data with / D, such as... Figure 10 As shown in (c);
[0138] A second comparison result was obtained;
[0139] If both the first and second comparison results are consistent, the test is successful; otherwise, the test fails.
[0140] Example 3
[0141] The difference between this embodiment and Embodiment 1 or Embodiment 2 is that the preset read / write unit is a column, the preset direction of the first round of testing is the row direction, and the preset direction of the second round of testing is the column direction. Specifically:
[0142] The address is the 0th column and 0th row of the 0th bank. Start writing test data / D from the storage cell corresponding to the 0th column and 0th row according to BL. That is, write test data / D from the 0th column and 0th row to the 0th column and 3rd row. After writing, start writing test data / D from the 1st row of the 0th column. After writing all rows from the 0th column to the 3rd column, the entire storage array is now written with data.
[0143] Starting from row 0, column 0 of the 0th bank of the storage array, traverse a preset test unit, read the preset operation unit on (R0, C0) of the 0th bank in the preset test unit, compare the read data with / D, and then write it to D;
[0144] Read the preset operation unit on (R0, C0) of the first bank in the preset test unit, compare the read data with / D, and then write it to D;
[0145] Read the preset operation unit on (R0, C0) of the second bank in the preset test unit, compare the read data with / D, and then write it to D;
[0146] Read the preset operation unit on (R0, C0) of the 3rd bank in the preset test unit, compare the read data with / D, and then write it to D;
[0147] Next, starting from the first row and the first column of the 0th bank of the storage array, a preset test unit is traversed, and the preset operation unit on (R1, C0) of the 0th bank in the preset test unit is read. The read data is compared with / D and then written to D.
[0148] Read the preset operation unit on (R1, C0) of the first bank in the preset test unit, compare the read data with / D, and then write it to D;
[0149] Read the preset operation unit on (R1, C0) of the second bank in the preset test unit, compare the read data with / D, and then write it to D;
[0150] Read the preset operation unit on (R1, C0) of the 3rd bank in the preset test unit, compare the read data with / D, and then write it to D;
[0151] This process continues until all memory cells of the DRAM to be tested have been traversed.
[0152] Obtain the first comparison result;
[0153] In the second round of testing, the test data to be written is defined as D = 10101010, and its inverse / D = 01010101:
[0154] Starting from row 0, column 0 of the 0th bank of the storage array, traverse a preset test unit, read the preset operation unit on (R0, C0) of the 0th bank in the preset test unit, compare the read data with / D, and then write it to D;
[0155] Read the preset operation unit on (R0, C0) of the first bank in the preset test unit, compare the read data with / D, and then write it to D;
[0156] Read the preset operation unit on (R0, C0) of the second bank in the preset test unit, compare the read data with / D, and then write it to D;
[0157] Read the preset operation unit on (R0, C0) of the 3rd bank in the preset test unit, compare the read data with / D, and then write it to D;
[0158] Next, starting from the 0th row and 1st column of the 0th bank of the storage array, a preset test unit is traversed, the preset operation unit on (R0, C1) of the 0th bank in the preset test unit is read, the read data is compared with / D, and then written to D;
[0159] Read the preset operation unit on (R0, C1) of the first bank in the preset test unit, compare the read data with / D, and then write it to D;
[0160] Read the preset operation unit on (R0, C1) of the second bank in the preset test unit, compare the read data with / D, and then write it to D;
[0161] Read the preset operation unit on (R0, C1) of the 3rd bank in the preset test unit, compare the read data with / D, and then write it to D;
[0162] This process continues until all memory cells of the DRAM to be tested have been traversed.
[0163] Read data from all preset test units and compare the read data with / D;
[0164] A second comparison result was obtained;
[0165] If both the first and second comparison results are consistent, the test is successful; otherwise, the test fails.
[0166] Example 4
[0167] Please refer to Figure 2 A DRAM testing apparatus, comprising:
[0168] The data read / write module is used to perform two rounds of testing on the DRAM under test, and obtain the first comparison result and the second comparison result respectively.
[0169] The test includes:
[0170] Preset test data is written to the memory array of the DRAM under test until all memory cells of the DRAM under test have been written with data;
[0171] The storage array is traversed in units of preset test units until all storage units of the storage array have been traversed. The preset test unit includes a preset operation unit corresponding to the same position on each storage cell of the storage array.
[0172] For each target test unit traversed, based on the preset test data, data read and write operations are performed on each preset operation unit of the target test unit in a preset order, and the read data is compared with the corresponding written data.
[0173] The preset test data for the first round of testing is the inverse of the preset test data for the second round of testing;
[0174] The testing module is used to obtain the test results of the DRAM to be tested based on the first comparison result and the second comparison result.
[0175] Example 5
[0176] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, can implement the various steps of the DRAM testing method in Embodiment 1, Embodiment 2, or Embodiment 3.
[0177] Example 6
[0178] Please refer to Figure 3 An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the various steps of the DRAM testing method in Embodiment 1, Embodiment 2, or Embodiment 3.
[0179] In summary, the DRAM testing method, apparatus, readable storage medium, and electronic device provided by this invention perform two rounds of testing on the DRAM to be tested. During the process of writing preset test data to the DRAM to be tested, writing is performed in units of preset burst length, which can improve the data writing speed and reduce the time complexity, facilitating mass production testing. The preset test unit includes preset operation units corresponding to the same position on each memory cell of the memory array. The memory array is traversed in a preset direction, including row or column directions, in units of preset test units until all memory cells of the memory array have been traversed. Based on the preset test data, data read and write operations are performed on each preset operation unit of the target test unit according to the sequence number of each memory cell in the target test unit, realizing matrix jump access and simulating non-contiguous access. In the case of access, a potential difference is created when a different voltage level is written to a memory cell than to its surrounding cells. Based on preset test data, data read and write operations are performed on each preset operation cell of the target test cell according to the sequence number of each memory cell in the target test cell. This can effectively simulate this potential difference. In the second round of testing, data from all preset test cells of the DRAM under test is also read. The read data is compared with the corresponding written data, which can once again check whether the data in the memory cell after testing meets expectations, thus improving the reliability and accuracy of the test. By implementing matrix jump access to the DRAM under test, previous test blind spots are covered and chip defects that are difficult to detect in the present technology are detected, thereby improving fault coverage, enhancing the reliability of test results, and thus improving product quality.
[0180] In the embodiments provided in this application, it should be understood that the disclosed methods, apparatuses, computer-readable storage media, and electronic devices can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple components or modules may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices, components, or modules may be electrical, mechanical, or other forms.
[0181] The components described as separate parts may or may not be physically separate. The components shown as components may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the components can be selected to achieve the purpose of this embodiment according to actual needs.
[0182] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing module, or each component can exist physically separately, or two or more modules can be integrated into one module. The integrated modules described above can be implemented in hardware or as software functional modules.
[0183] If the integrated module is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0184] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the present invention is not limited to the described order of actions, because according to the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.
[0185] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.
[0186] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent modifications made based on the content of the present invention specification and drawings, or direct or indirect applications in related technical fields, are similarly included within the patent protection scope of the present invention.
Claims
1. A DRAM testing method, characterized by, The method comprises the steps of: performing two rounds of testing on the DRAM to be tested to obtain a first comparison result and a second comparison result respectively; the testing comprises: writing preset test data to a memory array of the DRAM to be tested until all memory cells of the DRAM to be tested are written with data; traversing the memory array in units of preset test units until all memory cells of the memory array are traversed, the preset test units including preset operation units corresponding to the same position on each memory bank of the memory array; for a target test unit traversed, performing data read-write operations on each preset operation unit of the target test unit in a preset order based on the preset test data, and comparing the read data with the corresponding written data; the preset test data of the first round of testing is the inverse of the preset test data of the second round of testing; obtaining a test result of the DRAM to be tested according to the first comparison result and the second comparison result; the traversing the memory array in units of preset test units until all memory cells of the memory array are traversed comprises traversing the memory array in a preset direction in units of preset test units until all memory cells of the memory array are traversed; the preset direction includes a row direction or a column direction; the preset direction of the first round of testing is different from that of the second round of testing.
2. The DRAM testing method of claim 1, wherein, the writing preset test data to a memory array of the DRAM to be tested until all memory cells of the DRAM to be tested are written with data comprises: writing the preset test data from a low address of each preset read-write unit of the memory array of the DRAM to be tested in units of preset burst lengths until all memory cells of the DRAM to be tested are written with data; the preset read-write unit includes a row or a column.
3. The method of claim 1, wherein, the performing data read-write operations on each preset operation unit of the target test unit in a preset order based on the preset test data comprises: performing data read-write operations on each preset operation unit of the target test unit in a sequence order of the sequence numbers of the memory banks in the target test unit based on the preset test data.
4. The DRAM testing method of any one of claims 1 to 3, wherein, for each preset operation unit, after the comparison, writing the inverse of the preset test data to the preset operation unit; the second round of testing further comprises the steps of: reading data of all preset test units of the DRAM to be tested, and comparing the read data with the corresponding written data.
5. The DRAM testing method of any one of claims 1 to 3, wherein, the obtaining a test result of the DRAM to be tested according to the first comparison result and the second comparison result comprises: if the first comparison result and the second comparison result are both consistent, the test result is success; otherwise, the test result is failure.
6. A DRAM testing apparatus, characterized by comprising: The method comprises: a data read-write module, configured to perform two rounds of testing on the DRAM to be tested to obtain a first comparison result and a second comparison result respectively; the testing comprises: writing preset test data to a memory array of the DRAM to be tested until all memory cells of the DRAM to be tested are written with data; traversing the memory array by preset test units until all memory cells of the memory array are traversed, the preset test unit including preset operation units corresponding to the same position on each memory bank of the memory array; for a target test unit that is traversed, performing data read-write operations on each preset operation unit of the target test unit according to the preset test data and in a preset order, and comparing the read data with the corresponding written data; the preset test data of the first round of tests is the inverse of the preset test data of the second round of tests; a test module configured to obtain a test result of the DRAM to be tested according to the first comparison result and the second comparison result; the traversing the memory array by preset test units until all memory cells of the memory array are traversed includes traversing the memory array by preset test units in a preset direction until all memory cells of the memory array are traversed; the preset direction includes a row direction or a column direction; the preset direction of the first round of tests is different from the preset direction of the second round of tests.
7. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program, when executed by a processor, implements each step of the DRAM test method of any one of claims 1 to 5.
8. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor, when executing the computer program, implements each step of the DRAM test method of any one of claims 1 to 5.
Citation Information
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