Semiconductor device

Abstract

This invention discloses a semiconductor device comprising: a substrate having a first region and a second region; a gate electrode stacked in the first region to form a pad region having a stepped shape, extending to different lengths in the second region; an interlayer insulating layer stacked alternately with the gate electrode; a channel structure passing through the gate electrode in the first region and including a channel layer; a partition region passing through the gate electrode in the first and second regions; an etch stop layer disposed on the uppermost gate electrode among the gate electrodes forming the pad region in the second region, not overlapping with the first region and the partition region; a cell region insulating layer covering the gate electrode and the etch stop layer; and a contact plug passing through the cell region insulating layer and the etch stop layer in the second region and connected to the gate electrode in the pad region.

Description

Technical Field

[0001] The present invention relates to semiconductor devices. Background Technology

[0002] Semiconductor devices are electronic components whose functionality depends on the electronic properties of semiconductor materials. Semiconductor devices are becoming increasingly smaller and require high-capacity data processing. Therefore, it is essential to increase the integration density of the semiconductor elements that constitute such devices. Semiconductor devices with vertical transistor structures have a significantly higher integration density than those with conventional planar transistor structures. Summary of the Invention

[0003] At least one exemplary embodiment of the present invention provides a semiconductor device with improved reliability.

[0004] According to an exemplary embodiment of the present invention, a semiconductor device includes: a substrate having a first region and a second region; gate electrodes stacked on the substrate in a first direction and spaced apart from each other in the first region, the gate electrodes extending along a second direction to different lengths in the second region to form a pad region having a stepped shape; an interlayer insulating layer stacked alternately with the gate electrodes; a channel structure passing through the gate electrodes in the first region, extending in the first direction and including a channel layer; a separator region passing through the gate electrodes in the first and second regions and extending in the second direction; an etch stop layer disposed on the uppermost gate electrode among the gate electrodes forming the pad region in the second region, not overlapping with the first region and the separator region; a cell region insulating layer covering the gate electrodes and the etch stop layer; and a contact plug passing through the cell region insulating layer and the etch stop layer from the upper portion of the second region and connected to the gate electrode in the pad region.

[0005] According to an exemplary embodiment of the present invention, a semiconductor device includes: gate electrodes stacked on a substrate and spaced apart from each other in a first direction, the gate electrodes extending at different lengths along a second direction to form a pad region having a stepped shape; a partition region extending through the gate electrodes and in the second direction; an etch stop layer disposed on the uppermost gate electrode among the gate electrodes forming the pad region; and a contact plug extending through the etch stop layer and connected to the gate electrode in the pad region, wherein the etch stop layer is spaced apart from the side surface of the partition region.

[0006] According to an exemplary embodiment of the present invention, a semiconductor device includes: a substrate having a first region and a second region; gate electrodes stacked on the substrate in a first direction and spaced apart from each other in the first region, the gate electrodes extending along a second direction to different lengths in the second region to form a pad region having a stepped shape; a channel structure passing through the gate electrodes in the first region, extending in the first direction and including a channel layer; a separation region passing through the gate electrodes in the first and second regions and extending in the second direction; an etch stop layer disposed on the uppermost gate electrode among the gate electrodes forming the pad region in the second region; and a contact plug passing through the etch stop layer and connected to the gate electrode in the pad region, wherein a first end of the etch stop layer in the second direction is located at the boundary between the first and second regions, and the etch stop layer contacts or is spaced apart from the side surfaces of the separation regions on opposite sides in a third direction perpendicular to the first and second directions. Attached Figure Description

[0007] The inventive concept will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 This is a schematic plan view illustrating a semiconductor device according to an example embodiment of the inventive concept.

[0009] Figures 2A to 2C This is a schematic cross-sectional view showing an example embodiment of a semiconductor device according to the inventive concept.

[0010] Figure 3A and Figure 3B These are schematic plan and cross-sectional views illustrating an exemplary embodiment of a semiconductor device according to the inventive concept.

[0011] Figure 4 This is a schematic cross-sectional view showing an example embodiment of a semiconductor device according to the inventive concept.

[0012] Figure 5A and Figure 5B This is a schematic cross-sectional view showing an example embodiment of a semiconductor device according to the inventive concept.

[0013] Figure 6A and Figure 6B These are schematic plan and cross-sectional views illustrating an exemplary embodiment of a semiconductor device according to the inventive concept.

[0014] Figure 7 This is a schematic cross-sectional view showing a semiconductor device according to an example embodiment.

[0015] Figure 8 This is a schematic plan view illustrating a semiconductor device according to an exemplary embodiment of the inventive concept.

[0016] Figure 9 This is a schematic cross-sectional view showing an example embodiment of a semiconductor device according to the inventive concept.

[0017] Figures 10A to 15B These are schematic plan and cross-sectional views illustrating a method for manufacturing a semiconductor device according to an example embodiment of the inventive concept. Detailed Implementation

[0018] In the following description, exemplary embodiments of the inventive concept will be described with reference to the accompanying drawings.

[0019] Figure 1 This is a schematic plan view illustrating a semiconductor device according to an example embodiment of the inventive concept.

[0020] Figures 2A to 2C This is a schematic cross-sectional view showing an example embodiment of a semiconductor device according to the inventive concept. Figures 2A to 2C Show respectively Figure 1 Cross-sectional views of a semiconductor device taken along lines I-I', II-II', and III-III'.

[0021] Reference Figures 1 to 2C The semiconductor device 100 includes a substrate 101 having a first region A and a second region B, a gate electrode 130 stacked on the substrate 101, a channel structure CH disposed in the first region A to pass through the gate electrode 130, a separating region MS passing through the gate electrode 130 and extending in the first region A and the second region B, an etch stop layer 160 disposed on the uppermost gate electrode 130 in each portion of the second region B, and a contact plug 180 passing through the etch stop layer 160 and connected to the gate electrode 130. In one example embodiment, the portion of the uppermost gate electrode 130 disposed in the first region A is not covered by the etch stop layer 160. In one example embodiment, each channel structure CH includes an epitaxial layer 105, a channel layer 140, a gate dielectric layer 145, a channel insulating layer 150, and a channel pad 155. The semiconductor device 100 may further include an interlayer insulating layer 120 alternately stacked with the gate electrode 130 on the substrate 101, an upper partition region SS passing through a portion of the gate electrode 130, and a cell region insulating layer 190. For example, the upper partition region SS may pass through some of the uppermost gate electrodes 130.

[0022] In one example embodiment, a first region A of substrate 101 is a region in which gate electrodes 130 are vertically stacked and a channel structure CH is disposed therein, and may be a region in which memory cells are disposed. In one example embodiment, a second region B is a region in which gate electrodes 130 extend to different lengths, and may correspond to a region of circuit elements for electrically connecting memory cells to peripheral circuit regions that drive memory cells. The second region B may be disposed adjacent to at least one end of the first region A in at least one direction (e.g., in the X direction).

[0023] Substrate 101 may have an upper surface extending in both the X and Y directions. Substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may include silicon, germanium, or silicon-germanium. Substrate 101 may be provided as a bulk wafer or an epitaxial layer.

[0024] The gate electrode 130 may be stacked alternately with the interlayer insulating layer 120 to form a stacked structure GS. The gate electrode 130 may sequentially include, starting from the substrate 101, a lower gate electrode 130L forming a portion of a ground select transistor, a memory cell gate electrode 130M forming a portion of a memory cell, and an upper gate electrode 130U forming a portion of a string select transistor. The number of memory cell gate electrodes 130M may be determined according to the capacity of the semiconductor device 100. In some embodiments, the lower gate electrode 130L and the upper gate electrode 130U may each be one or two or more, and may have the same or different structures as the memory cell gate electrode 130M. In an example embodiment, the upper gate electrode 130U further includes an upper gate electrode 130U disposed in the upper portion of the string select transistor and forming a portion of an erase transistor for erase operations utilizing the gate-induced drain leakage current (GIDL) phenomenon. In one example implementation, a portion of the gate electrode 130, such as the portion of the memory cell gate electrode 130M adjacent to the lower gate electrode 130L and the upper gate electrode 130U, is a dummy gate electrode.

[0025] Gate electrodes 130 may be vertically stacked at intervals in a first region A and may extend to different lengths in a second region B to form a pad region PAD having a stepped differential structure with a stepped shape. In this specification, the term pad region PAD may be used to refer to the entire region having a stepped shape, wherein the gate electrode 130 below extends longer than the gate electrode 130 above, thereby exposing the ends of the gate electrode 130 below. Figure 2AAs shown, in at least a portion of the gate electrode 130 excluding the lower gate electrode 130L and the upper gate electrode 130U, a predetermined number of gate electrodes 130, such as one, two, four, or six gate electrodes 130, form a gate group to form a stepped differential structure between the gate groups in the X direction. Figure 1 and Figure 2C As shown, the gate electrodes 130 forming a gate group can be arranged to have a stepped difference structure relative to each other in the Y direction.

[0026] like Figure 1 As shown, the gate electrode 130 can be separated from the adjacent gate electrode 130 in the Y direction by a pair of separating regions MS extending in the X direction. The gate electrode 130 between the pair of separating regions MS can form a single memory block, but the scope of the single memory block is not limited thereto. A portion of the gate electrode 130, for example, each memory cell gate electrode 130M, can form a single layer in the single memory block. The gate electrode 130 can include a semiconductor material, such as polycrystalline silicon (Si).

[0027] Interlayer insulating layers 120 may be disposed between gate electrodes 130. Like gate electrodes 130, interlayer insulating layers 120 may be spaced apart from each other in a direction perpendicular to the upper surface of substrate 101 and may extend in the X direction. Interlayer insulating layers 120 may comprise insulating materials such as silicon oxide or silicon nitride.

[0028] The separating regions MS can be configured to pass through the gate electrode 130 in the first region A and the second region B and extend in the X direction. In an example embodiment of the inventive concept, the separating regions MS are arranged parallel to each other. The separating regions MS can be connected to the substrate 101 through all the gate electrodes 130 stacked on the substrate 101. In the embodiments, the arrangement position, number, etc., of the separating regions MS are not limited to... Figure 1 Those shown in the image.

[0029] like Figure 2B and Figure 2C As shown, conductive layer 110 and insulating layer 107 are disposed in the partition region MS. Conductive layer 110 can be spaced apart from gate electrode 130 by insulating layer 107. Conductive layer 110 can be used as a common source line of semiconductor device 100 or as a contact plug connected to common source line.

[0030] The upper separating region SS can extend in the X direction between the separating regions MS. The upper separating region SS can be located in a portion of the second region B and the first region A, extending through a portion of the gate electrode 130 (including the uppermost gate electrode 130 among the gate electrodes 130). Figure 2BAs shown, the upper separating region SS can, for example, separate the three gate electrodes 130 from each other in the Y direction. In various embodiments, the number of gate electrodes 130 separated by the upper separating region SS can vary. The upper separating region SS may include an upper insulating layer 103.

[0031] The channel structure CH can form a string of memory cells and can be spaced apart from each other in rows and columns in the first region A. The channel structure CH can be arranged to form a grid or to have a zigzag shape in one direction. For example, the channel structure CH can be arranged in columns aligned with each other or arranged offset from each other to form zigzag columns. The channel structure CH can have a column shape and can have sidewalls such that, depending on the aspect ratio, the width of the channel structure CH becomes narrower as it gets closer to the substrate 101. In an example embodiment, the channel structure CH disposed in the end (or edge portion) of the first region A adjacent to the second region B is a dummy channel. Additionally, the channel structure CH overlapping the upper separating region SS can also be a dummy channel. In an example embodiment, the dummy channel has the same or similar structure as the channel structure CH, but does not perform any substantial function in the semiconductor device 100. In an example embodiment, applying current or voltage to the dummy channel does not affect the state of the memory cells of the semiconductor device 100. In an example embodiment, the dummy channel is not connected to any active bit line.

[0032] Reference Figure 2B The enlarged view shows that the channel layer 140 can be disposed in the channel structure CH. In the channel structure CH, the channel layer 140 can be formed in an annular shape having a channel insulating layer 150 surrounding it, but can have a pillar shape, such as a cylindrical shape or a cornered pillar shape, without the channel insulating layer 150. The lower portion of the channel layer 140 can be connected to the epitaxial layer 105. The channel layer 140 can include a semiconductor material such as polycrystalline silicon or monocrystalline silicon, and the semiconductor material can be an undoped material or a material including p-type or n-type impurities.

[0033] A gate dielectric layer 145 may be disposed between the gate electrode 130 and the channel layer 140. In an example embodiment of the inventive concept, the gate dielectric layer 145 extends along the channel layer 140 perpendicular to the upper surface of the substrate 101. Although not specifically shown, the gate dielectric layer 145 may include a tunneling layer, a charge storage layer, and a barrier layer sequentially stacked from the channel layer 140. The tunneling layer allows charge to tunnel into the charge storage layer and may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxide nitride (SiON), or combinations thereof. The charge storage layer may be a charge trapping layer or a floating gate conductive layer. The barrier layer may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxide nitride (SiON), a high-k dielectric material, or combinations thereof.

[0034] The epitaxial layer 105 may be disposed on the substrate 101 at the lower end of the channel structure CH, and may be disposed on the side surface of at least one gate electrode 130. The epitaxial layer 105 may be disposed in a recessed region of the substrate 101. In one example embodiment, the upper surface of the epitaxial layer 105 is higher than the upper surface of the lowermost gate electrode 130 and lower than the lower surface of the gate electrode 130 directly disposed on the lowermost gate electrode 130, but is not limited thereto. In one example embodiment, the epitaxial layer 105 is omitted, in which case the channel layer 140 is directly connected to the substrate 101.

[0035] Channel pads 155 can be disposed on the channel layer 140 within the channel structure CH. Channel pads 155 can be configured to cover the upper surface of the channel insulating layer 150 and be electrically connected to the channel layer 140. Channel pads 155 can include, for example, doped polysilicon. The channel structure CH, disposed along a straight line in the Y direction between the separator region MS and the upper separator region SS, can be connected to different bit lines depending on the arrangement of the upper wiring structure connected to the channel pads 155.

[0036] In one example embodiment, an etch stop layer 160 is disposed on the upper surface of the uppermost gate electrode 130 among the gate electrodes 130 forming the pad region PAD. When forming the contact plug 180, the etch stop layer 160 can be a layer used to control the etch depth. For example, the etch stop layer 160 can prevent the contact plug 180 from passing through more than a single uppermost gate electrode. The etch stop layer 160 can extend from an upper portion to a lower portion to have a stepped shape along the pad region PAD. Specifically, the etch stop layer 160 can cover the exposed upper and side surfaces of the uppermost gate electrode 130 and can extend to cover the side surfaces of the interlayer insulating layer 120.

[0037] The etch stop layer 160 can be disposed in the portion of the second region B in which the separator region MS is not disposed. Therefore, the etch stop layer 160 does not overlap with the first region A and the separator region MS in the plan view, as... Figure 1 As shown. The etch stop layer 160 can be configured as a single layer between a pair of separator regions MS. In one example embodiment, the etch stop layer 160 is spaced apart from the channel structure CH closest to the second region B by a first distance D1. The etch stop layer 160 can be configured to contact the side surface of the separator region MS, such as... Figure 2C As shown. Therefore, the entire etch stop layer 160 can be configured to overlap with a portion of the gate electrode 130 forming the pad region PAD and the substrate 101 outside the gate electrode 130.

[0038] The first end of the etch stop layer 160 in the X direction may be located at or near the boundary between the first region A and the second region B. The second end of the etch stop layer 160 in the X direction may be positioned to contact the substrate 101 on its upper surface. For example, the second end of the etch stop layer 160 may contact the upper surface of the substrate 101 in the second region B. In an example embodiment, the second end of the etch stop layer 160 does not extend to the upper surface of the substrate 101, but is located on the lowermost gate electrode 130. The two ends of the etch stop layer 160 in the Y direction may be positioned to contact the side surfaces of the separation region MS. Through these ends, the etch stop layer 160 can... Figure 1 The plan view has a rectangular shape.

[0039] In one exemplary embodiment of the inventive concept, the etch stop layer 160 comprises a material different from that of the gate electrode 130 and the cell region insulating layer 190. The etch stop layer 160 may comprise a metal oxide. In one exemplary embodiment, the etch stop layer 160 is made entirely of a metal oxide. For example, the etch stop layer 160 may comprise aluminum oxide (Al₂O₃). x O y ), Hafnium oxide (Hf) x O y ), tantalum oxide (Ta x O y ), titanium oxide (Ti x O y ), yttrium oxide (Y x O y ), zirconium oxide (Zr x O y ), lanthanum oxide (La) x O y ), lanthanum aluminum oxide (LaAl) x O y ), lanthanum hafnium oxide (LaHf) xO y ), Hafnium aluminum oxide (HfAl) x O y Any of ) and praseodymium oxide (Pr2O3).

[0040] Because the etch stop layer 160 can be disposed only in the pad area PAD of the gate electrode 130 on which the contact plug 180 is disposed, the etching process can be easily performed when forming the channel structure CH and the separator region MS. In addition, the separator region MS can be formed such that the lower end of the separator region MS is maintained at the same or substantially the same height level along the X direction.

[0041] The cell region insulating layer 190 may be configured to cover the substrate 101, the gate electrode 130, and the etch stop layer 160. In one example embodiment, the cell region insulating layer 190 includes multiple insulating layers. The cell region insulating layer 190 may include an insulating material such as silicon oxide, silicon nitride, etc.

[0042] Contact plugs 180 can extend from the top through a portion of the cell region insulating layer 190 and the etch stop layer 160, and can be connected to the uppermost gate electrode 130 of the gate electrodes 130 forming the pad region PAD. Contact plugs 180 can partially recess the gate electrode 130 and can be connected to the gate electrode 130. For example, contact plugs 180 can extend into the recess of the uppermost gate electrode. Contact plugs 180 can be connected to wiring 170 thereon. Contact plugs 180 can electrically connect the gate electrode 130 to circuit elements in the peripheral circuit region. In example embodiments, the arrangement, number, and shape of contact plugs 180 can be varied. For example, one of the contact plugs 180 can be connected to only one of the gate electrodes 130. Contact plugs 180 and wiring 170 can include conductive materials, such as tungsten (W), copper (Cu), aluminum (Al), etc.

[0043] Figure 3A and Figure 3B These are schematic plan views and cross-sectional views illustrating a semiconductor device according to an example embodiment. Figure 3B Show along Figure 3A The cross-sectional view taken from line III-III'.

[0044] Reference Figure 3A and Figure 3BIn semiconductor device 100a, etch stop layer 160a is spaced apart from channel structure CH by a first distance D1 in the X direction and from separator region MS by a second distance D2 in the Y direction. In an example embodiment, the second distance D2 is smaller than a third distance D3 between separator region MS and adjacent contact plug 180. Specifically, etch stop layer 160a may be spaced apart from two side surfaces of separator region MS in the Y direction. In the spaced regions, the uppermost gate electrode 130 may be exposed in an upward direction from etch stop layer 160a to contact cell region insulating layer 190. For example, the uppermost gate electrode 130 in the spaced regions will be exposed before being covered by cell region insulating layer 190.

[0045] In one example implementation, prior to forming the separator region MS, an initial etch stop layer 160P (see [reference needed]) is formed in a region relatively wider than the separator region MS (including the region in which the separator region MS will be formed). Figure 11A and Figure 11B The etch stop layer 160a is removed to form an etch stop layer 160a. As a result, the separation region MS can be stably formed in the region where the etch stop layer 160a is not formed.

[0046] Figure 4 This is a schematic cross-sectional view showing a semiconductor device according to an example embodiment of the inventive concept. Figure 4 Showing the corresponding Figure 2A The area.

[0047] Reference Figure 4 In semiconductor device 100b, gate electrode 130 has a thickened end region RR in pad region PAD for stable connection to contact plug 180. Contact plug 180 can be connected to gate electrode 130 in end region RR. In this case, even if the depth to which contact plug 180 recesses gate electrode 130 is relatively deep, contact plug 180 can be stably connected to gate electrode 130. For example, contact plug 180 can extend through the thickened portion (i.e., end region RR) of the uppermost gate electrode into the recess of the uppermost gate electrode.

[0048] Figure 5A and Figure 5B This is a schematic cross-sectional view showing a semiconductor device according to an example embodiment of the inventive concept. Figure 5A Showing the corresponding Figure 2A The area Figure 5B Showing the corresponding Figure 2B The area.

[0049] Reference Figure 5A and Figure 5BThe semiconductor device 100c further includes a first horizontal conductive layer 102 and a second horizontal conductive layer 104 disposed on the upper surface of the substrate 101 between the substrate 101 and the lowest interlayer insulating layer 120. Additionally, in the semiconductor device 100c, the structure of the channel structure CHc can be similar to... Figures 1 to 2C The channel structure differs from that of the embodiments described above, and the separation region MSc can be formed by the separation insulating layer 107. For example, with Figure 2C The separation region MS is different; the separation region MSc does not include the conductive layer 110.

[0050] At least a portion of the first horizontal conductive layer 102 and the second horizontal conductive layer 104 can be used as part of the common source line of the semiconductor device 100c, and can also be used together with the substrate 101 as the common source line. Figure 5B As shown in the enlarged view, a first horizontal conductive layer 102 is disposed around and directly connected to the channel layer 140. The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may comprise a semiconductor material, such as polysilicon. In this case, at least the first horizontal conductive layer 102 may be a doped layer, and the second horizontal conductive layer 104 may be a doped layer or a layer including impurities diffused from the first horizontal conductive layer 102.

[0051] and Figure 2A The channel structure is different; the channel structure CHc does not include the epitaxial layer 105 (refer to...). Figure 2A Instead, it can have a structure in which the channel layer 140 extends to its lower end to connect to the first horizontal conductive layer 102.

[0052] Figure 6A and Figure 6B These are schematic plan and cross-sectional views illustrating a semiconductor device according to an example embodiment of the inventive concept. Figure 6B Show along Figure 6A The cross-sectional view taken from line I-I'.

[0053] Reference Figure 6A and Figure 6B In semiconductor device 100d, the material of gate electrode 130d and the structure of gate dielectric layer 145d are similar to those of... Figures 1 to 2C The materials of the gate electrode and the structure of the gate dielectric layer differ in the embodiments described. Additionally, the semiconductor device 100d includes a first separation region MS1 ​​and a second separation region MS2 extending through the gate electrode 130d in the X direction, and may further include a dummy channel structure DCH in a second region B of the substrate 101.

[0054] In one example embodiment, the gate electrode 130d comprises a metallic material such as tungsten (W). In another example embodiment, the gate electrode 130d is made entirely of a metallic material. In the example embodiment, the gate electrode 130d may further include a diffusion barrier layer. For example, the diffusion barrier layer may include tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), or a combination thereof.

[0055] The gate dielectric layer 145d may include a first dielectric layer 145A and a second dielectric layer 145B. The first dielectric layer 145A may extend horizontally along the gate electrode 130d to surround the gate electrode 130d. The second dielectric layer 145B may extend perpendicularly to the upper surface of the substrate 101 along the channel structure CH.

[0056] In one example embodiment, the first separating region MS1 ​​and the second separating region MS2 are arranged parallel to each other. The first separating region MS1 ​​and the second separating region MS2 can extend through all the gate electrodes 130 stacked on the substrate 101 to connect to the substrate 101. The first separating region MS1 ​​can extend along the first region A and the second region B in a single form, and the second separating region MS2 can be arranged intermittently in the first region A and the second region B. For example, the first separating region MS1 ​​can include a single monolithic layer extending along the first region A and the second region B. In the example embodiment, the arrangement order, number, etc., of the first separating region MS1 ​​and the second separating region MS2 can be varied. Each of the first separating region MS1 ​​and the second separating region MS2 can include a conductive layer 110 and a separating insulating layer 107, similar to... Figures 1 to 2C The dividing region MS.

[0057] The dummy channel structures (DCHs) can be regularly arranged in the second region B of the substrate 101. For example, the dummy channel structures (DCHs) can be equidistant from each other. The dummy channel structures (DCHs) can have the same internal structure as the channel structure (CH), and can have the same or different dimensions and shapes as the channel structure (CH).

[0058] In the semiconductor device 100d, the etch stop layer 160 may be configured not to overlap with the first separation region MS1 ​​and the second separation region MS2. The etch stop layer 160 may contact or be spaced from the side surfaces of the first separation region MS1 ​​and the second separation region MS2. In an example embodiment, when the dummy channel structure DCH is formed before the etch stop layer 160, the etch stop layer 160 may be formed on the upper surface of the dummy channel structure DCH. Alternatively, in an example embodiment, when the etch stop layer 160 is formed before the dummy channel structure DCH, the dummy channel structure DCH may be configured to pass through the etch stop layer 160.

[0059] Semiconductor device 100d can be referenced in the following way Figures 10A to 15B Description Figures 1 to 2C The semiconductor device 100 is manufactured using a different manufacturing method. Specifically, firstly, a gate sacrificial layer can be stacked alternately with the interlayer insulating layer 120. The gate sacrificial layer can be removed by openings formed in the regions where the first separation region MS1 ​​and the second separation region MS2 are arranged. Then, a first dielectric layer 145A and a gate electrode 130d can be formed. During the removal of the gate sacrificial layer, in order to facilitate the removal of the gate sacrificial layer, a second separation region MS2 can be further formed in addition to the first separation region MS1. During the removal of the gate sacrificial layer, a dummy channel structure DCH can be formed to stably support the stacked structure of the interlayer insulating layer 120.

[0060] Figure 7 This is a schematic cross-sectional view showing a semiconductor device according to an example embodiment of the inventive concept. Figure 7 Showing the corresponding Figure 2A The area.

[0061] Reference Figure 7 In the semiconductor device 100e, the stacked structure of the gate electrode 130 may include a lower stacked structure ST1 and an upper stacked structure ST2 stacked in the vertical direction, and the channel structure CHe may include a first channel structure CH1 and a second channel structure CH2 stacked in the vertical direction. When the number of stacked gate electrodes 130 is relatively large, the structure of the channel structure CHe can be introduced to stably form the channel structure CHe.

[0062] The channel structure CHe can have the following form: a first channel structure CH1 in the lower portion and a second channel structure CH2 in the upper portion are connected to each other and have a curved portion due to the difference in width in the region where they are connected. For example, the first channel structure CH1 can be connected to the second channel structure CH2 via this curved portion. The channel layer 140, gate dielectric layer 145, and channel insulating layer 150 in the first channel structure CH1 and the channel layer 140, gate dielectric layer 145, and channel insulating layer 150 in the second channel structure CH2 can be connected to each other between the first channel structure CH1 and the second channel structure CH2. In one example embodiment, the channel pad 155 is provided only on the upper end of the second channel structure CH2 in the upper portion. In another example embodiment, each of the first channel structure CH1 and the second channel structure CH2 includes a channel pad 155, in which case the channel pad 155 of the first channel structure CH1 can be connected to the channel layer 140 of the second channel structure CH2.

[0063] The gate electrode 130 can form a pad region PAD with a stepped shape, and a stepped structure can be formed in the lower stack structure ST1 and the upper stack structure ST2 respectively. The cell region insulating layer 190e can include a first insulating layer 192 covering the lower stack structure ST1 and a second insulating layer 194 covering the upper stack structure ST2.

[0064] The etch stop layer 160e may include a first etch stop layer 160A disposed on the gate electrode 130 of the lower stacked structure ST1 and a second etch stop layer 160B disposed on the gate electrode 130 of the upper stacked structure ST2. In an example embodiment, the first etch stop layer 160A and the second etch stop layer 160B are spaced apart from each other in the vertical direction. For example, since the first insulating layer 192 is disposed between the first etch stop layer 160A and the second etch stop layer 160B, the first etch stop layer 160A and the second etch stop layer 160B can be spaced apart.

[0065] Figure 8 This is a schematic plan view illustrating a semiconductor device according to an example embodiment of the inventive concept.

[0066] Reference Figure 8 In the semiconductor device 100f, in addition to the first region A and the second region B, the substrate 101 may further include a third region C. The third region C may be located outside the second region B and not facing the first region A. The third region C may be a peripheral circuit region in which circuit elements 220 electrically connected to the gate electrode 130 are arranged. Each circuit element 220 may include an active region 205 and a circuit gate electrode 225. A circuit gate insulating layer may be interposed between the circuit gate electrode 225 and the active region 205. In the example embodiment, the circuit elements 220 may have various sizes and arrangements.

[0067] In one exemplary embodiment of the inventive concept, the etch stop layer 160 is not disposed in the first region A and not disposed in the third region C. Therefore, in the etch stop layer 160, the first end in the X direction may be located at or near the boundary between the first region A and the second region B, and the second end on the other side may be located at or near the boundary between the second region B and the third region C. For example, the etch stop layer 160 may extend from the boundary between the first region A and the second region B to the boundary between the second region B and the third region C. In the etch stop layer 160, the two ends in the Y direction may contact or be spaced apart from the side surface of the separating region MS. In one exemplary embodiment of the inventive concept, the separating region MS is not disposed in the third region C.

[0068] Figure 9This is a schematic cross-sectional view showing a semiconductor device according to an example embodiment of the inventive concept. Figure 9 Showing the corresponding Figure 2A The area.

[0069] Reference Figure 9 The semiconductor device 100g includes a memory cell region (CELL) and a peripheral circuit region (PERI). The memory cell region (CELL) may be disposed on the peripheral circuit region (PERI). In one example embodiment, the memory cell region (CELL) is disposed below the peripheral circuit region (PERI).

[0070] As referenced above Figures 1 to 2C As described, the memory cell region (CELL) may include a substrate 101, a gate electrode 130, a channel structure (CH), a separation region (MS), an etch stop layer 160, and contact plugs 180. The memory cell region (CELL) may have the features described above. Figures 3A to 7 The structures of the various implementation methods described.

[0071] The peripheral circuit region PERI may include a base substrate 201 and circuit elements 220g, circuit contact plugs 270 and circuit wiring 280 disposed on the base substrate 201.

[0072] The base substrate 201 may have an upper surface extending in both the X and Y directions. Within the base substrate 201, a device separation layer may be formed separately to define an active region. Source / drain regions 205, including impurities, may be disposed within a portion of the active region. The base substrate 201 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor.

[0073] Circuit element 220g may include a planar transistor. Each circuit element 220g may include a gate insulating layer 222, a spacer layer 224, and a gate electrode 225. Source / drain regions 205 may be disposed in the base substrate 201 on both sides of the gate electrode 225. For example, a source / drain region disposed on one side of the gate electrode 225 in the source / drain region 205 may be used as the source electrode of the transistor, and another source / drain region disposed on the other side of the gate electrode 225 in the source / drain region 205 may be used as the drain electrode of the transistor.

[0074] A peripheral region insulating layer 290 can be disposed on circuit elements 220g on a base substrate 201. Circuit contact plugs 270 can pass through the peripheral region insulating layer 290 to connect to the source / drain region 205. Electrical signals can be applied to the circuit elements 220g through the circuit contact plugs 270. In an area not shown, the circuit contact plugs 270 can also be connected to the circuit gate electrode 225. Circuit wiring 280 can be connected to the circuit contact plugs 270 and can be configured in multiple layers. In an area not shown, the gate electrode 130 of the memory cell region CELL can be connected to the circuit elements 220g of the peripheral circuit region PERI through a through-path in the through-region of the peripheral circuit region PERI.

[0075] The semiconductor device 100g can be manufactured by fabricating the memory cell region CELL on a substrate 101 on which the peripheral circuit region PERI is formed. The substrate 101 may have the same size as the base substrate 201, or it may be formed smaller than the base substrate 201.

[0076] Figures 10A to 15B These are schematic plan and cross-sectional views illustrating a method for manufacturing a semiconductor device according to an example embodiment of the inventive concept.

[0077] Reference Figure 10A and Figure 10B Gate electrodes 130 and interlayer insulating layers 120 are alternately stacked on substrate 101, and a portion of gate electrodes 130 and a portion of interlayer insulating layers 120 are removed, so that gate electrodes 130 have different lengths while extending in the X direction, and an upper separation region SS is formed.

[0078] The gate electrode 130 and the interlayer insulating layer 120 can be deposited alternately using a deposition process to form a stacked structure GS. In one example embodiment, the thickness of the interlayer insulating layers 120 of the stacked structure GS is the same. In an alternative example embodiment, the thickness of the interlayer insulating layers 120 of the stacked structure GS is different. For example, among the interlayer insulating layers 120, the bottommost interlayer insulating layer 120 can be formed relatively thin, and the topmost interlayer insulating layer 120 can be formed relatively thick. The thickness of the interlayer insulating layers 120 and the gate electrode 130, as well as the number of films forming them, can be varied in ways different from those shown.

[0079] In the second region B of the substrate 101, photolithography and etching processes can be repeatedly performed on the gate electrode 130, such that the upper gate electrode 130 extends less than the lower gate electrode 130. For example, the width of the upper gate electrode 130 can be smaller than the width of the lower gate electrode 130. As a result, the gate electrode 130 can form a pad region PAD with a stepped shape. In an example embodiment, the gate electrode 130 may have a stepped shape only in the X direction, or it may have a stepped shape in both the X and Y directions. Figure 4 In the implementation of this method, the gate electrode 130 can be formed in the end region RR with a relatively thick thickness by further depositing the material forming the gate electrode 130 in the exposed region by means of extending the gate electrode 130 longer than the gate electrode 130 thereon.

[0080] The upper partition region SS can be formed by using a mask layer to expose the area in which the upper partition region SS will be formed and removing a predetermined number of gate electrodes 130 and interlayer insulating layers 120 from the uppermost portion. For example... Figure 2B As shown, the upper separating region SS can extend below the upper gate electrode 130U. The upper insulating layer 103 can be formed by depositing an insulating material in the region where the gate electrode 130 and the interlayer insulating layer 120 are removed. The upper insulating layer 103 can be made of, for example, the same material as the interlayer insulating layer 120.

[0081] Reference Figure 11A and Figure 11B An initial etch stop layer 160P is formed to cover the stacked structure GS.

[0082] An initial etch stop layer 160P can be formed on the entire substrate 101. The initial etch stop layer 160P can be formed to cover the upper surface of the topmost gate electrode 130 of the stacked structure GS. In the pad region PAD, the initial etch stop layer 160P can cover the side surfaces of the gate electrode 130 and the interlayer insulating layer 120 along the contour of the gate electrode 130, forming a stepped shape. In addition to the upper surface of the gate electrode 130, the initial etch stop layer 160P can also be formed to cover the upper separation region SS in the first region A of the substrate 101.

[0083] In one exemplary embodiment of the inventive concept, the initial etch stop layer 160P includes an insulating layer 190 with respect to the gate electrode 130 and the cell region to be formed later (see [link]). Figure 2ADifferent materials can be used. The initial etch stop layer 160P can be formed of a material that has etch selectivity relative to the gate electrode 130 and the cell region insulating layer 190. For example, the gate electrode 130 may include polysilicon, the cell region insulating layer 190 may include silicon oxide or silicon nitride, and the initial etch stop layer 160P may include metal oxide. When the initial etch stop layer 160P includes metal oxide, the initial etch stop layer 160P can be more easily removed by a wet etching process under certain etch conditions, and is less easily removed by a dry etching process under certain etch conditions.

[0084] Reference Figure 12A and Figure 12B Pattern the initial etch stop layer 160P to form the etch stop layer 160.

[0085] The initial etch stop layer 160P can be patterned using a photomask layer formed by a photolithography process. Separating regions MS (see [reference]) will be formed in the first region A and the second region B. Figure 1 The initial etch stop layer 160P in the region can be removed. The removal operation can be performed, for example, by a wet etching process. Therefore, the etch stop layer 160 can remain only in the portion of the second region B, excluding the area where the separating region MS will be formed. Figure 3A and Figure 3B In this implementation, the initial etch stop layer 160P can be removed from the region that includes the area in which the separator region MS will be formed and is wider than the area in which the separator region MS will be formed. As a result, the etch stop layer 160a can be formed.

[0086] In the example implementation, a heat treatment process for the etch stop layer 160 may be additionally performed. Through the heat treatment process, the etch stop layer 160 can be hardened to have relatively hard film properties.

[0087] Reference Figure 13A and Figure 13B The channel structure CH is formed through the stacked structure GS.

[0088] First, a cell region insulating layer 190 is formed to cover the upper portion of the stacked structure GS. The channel structure CH can be formed by anisotropically etching the gate electrode 130 and the interlayer insulating layer 120 to form a channel hole with a hole shape, and then filling the channel hole. Due to the height of the stacked structure GS, the sidewalls of the channel structure CH may not be perpendicular to the upper surface of the substrate 101. The channel structure CH can be formed such that a portion of the substrate 101 is recessed. For example, the channel structure CH can extend into a recess in the substrate 101. Since the channel hole can be formed in a region where the etch stop layer 160 is not disposed, the formation operation can be easily performed.

[0089] Next, an epitaxial layer 105, a gate dielectric layer 145, a channel layer 140, a channel insulating layer 150, and a channel pad 155 are sequentially formed in the channel via.

[0090] The epitaxial layer 105 can be formed using a selective epitaxial growth (SEG) process. The epitaxial layer 105 can be formed as a single layer or multiple layers. The epitaxial layer 105 can include polycrystalline silicon, monocrystalline silicon, polycrystalline germanium, or monocrystalline germanium, with or without doped impurities.

[0091] The gate dielectric layer 145 can be formed to have a uniform thickness using atomic layer deposition (ALD) or chemical vapor deposition (CVD) processes. The channel layer 140 can be formed on the gate dielectric layer 145 within the channel structure CH. The channel insulating layer 150 can be formed to fill the channel structure CH and can be an insulating material. In an example embodiment of the inventive concept, the interior of the channel layer 140 is also filled with a conductive material, instead of the channel insulating layer 150. The channel pads 155 can be made of a conductive material, such as polysilicon.

[0092] Reference Figure 14A and Figure 14B This can form a partition region MS that passes through the stacked structure GS.

[0093] In one example implementation, firstly, an opening (or through-hole) is formed in the region where the partition region MS will be formed by forming a mask layer and etching (e.g., anisotropic etching) the stacked structure GS using a photolithography process. Before forming the opening, a cell region insulating layer 190 may be further formed on the channel structure CH to protect the underlying channel structure CH. Next, a conductive layer 110 and a partition insulating layer 107 are formed in the opening to form the partition region MS.

[0094] Since the etch stop layer 160 is not provided in the region where the partition region MS will be formed, the process of forming the opening can be easily performed. Specifically, since the gate electrode 130 can form a pad region PAD in the second region B, the uppermost gate electrode 130 can be located at different height levels. Therefore, the opening can be formed by etching a stacked structure GS including gate electrodes 130 located at different height levels. Even in this case, since the etch stop layer 160, which acts as a barrier to the etching operation, is not provided in the region where the partition region MS will be formed, the lower end of the opening can be formed with a substantially constant position along the X direction.

[0095] Reference Figure 15A and Figure 15BA contact hole PH is formed through the insulating layer 190 of the cell region to expose the gate electrode 130 that forms the pad region PAD.

[0096] The formation of the contact hole PH can be performed using a two-step etching operation. In the first etching operation, the contact hole PH can penetrate the cell region insulating layer 190 from the upper portion to expose the etch stop layer 160. The contact hole PH can partially recess the etch stop layer 160. The first etching operation can be performed, for example, by a dry etching process. In the second etching operation, the etch stop layer 160 exposed by the contact hole PH can be removed to expose the uppermost gate electrode 130 in the lower portion. The contact hole PH can partially recess the gate electrode 130. For example, the second etching operation can be performed to remove a portion of the uppermost gate electrode 130 to form a recess in the gate electrode. The second etching operation can be performed, for example, by a wet etching process, and the etch stop layer 160 can be selectively removed.

[0097] In this operation, since the etch stop layer 160 can be placed on the uppermost gate electrode 130, contact holes PH of different depths can be formed simultaneously on the pad area PAD by a minimum number of photolithography processes (e.g., by a single photolithography process).

[0098] Next, refer to again Figures 1 to 2C This can form a contact plug 180 and wiring 170.

[0099] First, the contact plug 180 can be formed by filling the contact hole PH with a conductive material. Then, wiring 170 connected to the contact plug 180 can be formed.

[0100] Semiconductor devices with improved reliability can be achieved by selectively setting etch stop layers in certain areas.

[0101] Although exemplary embodiments of the inventive concept have been shown and described above, it will be apparent to those skilled in the art that modifications and variations can be made without departing from the scope of the inventive concept.

[0102] This patent application claims priority to Korean Patent Application No. 10-2019-0173879, filed with the Korean Intellectual Property Office on December 24, 2019, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: A substrate having a first region and a second region; Multiple gate electrodes are stacked on the substrate in a first direction and spaced apart from each other in the first region, and the gate electrodes extend along a second direction to different lengths in the second region to form a pad region with a stepped shape; Multiple interlayer insulating layers are stacked alternately with the gate electrode; Multiple channel structures extend through the gate electrode in the first region, extend in the first direction, and include a channel layer; Multiple partitioned regions pass through the gate electrode in the first region and the second region and extend in the second direction; An etch stop layer is disposed in the second region on the uppermost gate electrode at each step of the gate electrode forming the pad region, and does not overlap with the first region and the separating region; An insulating layer for the unit region covers the gate electrode and the etch stop layer; as well as Multiple contact plugs pass through the cell region insulating layer and the etch stop layer in the second region and connect to the gate electrode in the pad region. The etch stop layer is spaced apart from the side surface of the partition region in a third direction perpendicular to the first and second directions.

2. The semiconductor device according to claim 1, wherein, The etch stop layer is spaced apart from the side surface of the channel structure.

3. The semiconductor device according to claim 1, wherein, The etch stop layer extends continuously along the pad region to have a stepped shape.

4. The semiconductor device according to claim 1, wherein, The etch stop layer comprises a metal oxide.

5. The semiconductor device according to claim 1, wherein, The gate electrode comprises a semiconductor material.

6. The semiconductor device according to claim 1, wherein, The gate electrode comprises metal.

7. The semiconductor device according to claim 6, further comprising: Multiple dummy channel structures pass through the gate electrode in the second region, extend in the first direction, and include the channel layer.

8. The semiconductor device according to claim 1, wherein, The separation region includes a conductive layer and a separating insulating layer disposed between the conductive layer and the gate electrode.

9. The semiconductor device of claim 1, further comprising at least one horizontal conductive layer, the at least one horizontal conductive layer being disposed horizontally on the substrate and below the gate electrode and the interlayer insulating layer, and configured to be in direct contact with the channel layer.

10. The semiconductor device according to claim 1, wherein, The end of the etch stop layer is in contact with the upper surface of the substrate.

11. The semiconductor device according to claim 1, wherein, The gate electrode and the interlayer insulating layer form a first stacked structure and a second stacked structure stacked in the first direction. The etch stop layer includes a first etch stop layer and a second etch stop layer located on the first stacked structure and the second stacked structure, respectively, in the pad region.

12. The semiconductor device according to claim 1, wherein, The substrate further has a third region located outside the second region and in which circuit elements are disposed. The etch stop layer extends from the boundary between the first region and the second region to the boundary between the second region and the third region.

13. A semiconductor device, comprising: Multiple gate electrodes are stacked on a substrate in a first direction and spaced apart from each other, and the gate electrodes extend at different lengths along a second direction to form a pad region with a stepped shape; Multiple partitioned regions extend through the gate electrode and in the second direction; An etch stop layer is disposed on the uppermost gate electrode among the gate electrodes forming the pad region; and Multiple contact plugs pass through the etch stop layer and connect to the gate electrode in the pad region. The etch stop layer is spaced apart from the side surface of the partition region.

14. The semiconductor device of claim 13, further comprising a channel structure extending through the gate electrode in the first direction and including a channel layer.

15. The semiconductor device according to claim 14, wherein, The substrate has a first region and a second region located on at least one side of the first region. The channel structure is disposed in the first region, and the etch stop layer is disposed in a portion of the second region.

16. The semiconductor device of claim 13, further comprising a base substrate spaced apart from the substrate in the first direction and on which circuit elements are disposed.

17. A semiconductor device, comprising: A substrate having a first region and a second region; Multiple gate electrodes are stacked on the substrate in a first direction and spaced apart from each other in the first region, and the gate electrodes extend along a second direction to different lengths in the second region to form a pad region with a stepped shape; Multiple channel structures extend through the gate electrode in the first region, extend in the first direction, and include a channel layer; Multiple partitioned regions pass through the gate electrode in the first region and the second region and extend in the second direction; An etch stop layer is disposed in the second region on the uppermost gate electrode at each step among the gate electrodes forming the pad region; and Multiple contact plugs pass through the etch stop layer and connect to the gate electrode in the pad region. The first end of the etch stop layer in the second direction is located at the boundary between the first region and the second region, and the etch stop layer is spaced apart from the separating region on opposite sides in a third direction perpendicular to the first direction and the second direction.

18. The semiconductor device according to claim 17, wherein, The second end of the etch stop layer, opposite to the first end of the etch stop layer in the second direction, is located on the upper surface of the substrate.

19. The semiconductor device according to claim 17, wherein, The etch stop layer has a rectangular shape in the plan view.

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