Memory element and method for manufacturing the same

Abstract

The present invention discloses a memory element and a preparation method thereof, wherein the memory element comprises a substrate, a stacked structure, a plurality of channel structures, a storage layer and a plurality of isolation structures. The substrate has an upper surface. The stacked structure is located on the upper surface of the substrate, wherein the stacked structure comprises a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer and a third insulating layer sequentially stacked on the substrate. The channel structure passes through the stacked structure and is electrically connected to the substrate, wherein each channel structure comprises an upper portion and a lower portion, wherein the upper portion corresponds to the second conductive layer, and the lower portion corresponds to the first conductive layer. The storage layer is located between the second conductive layer and the upper portion. The isolation structure passes through the stacked structure to separate the stacked structure into a plurality of sub-stacks.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure and a method for preparing the same, and more particularly to a memory element and a method for preparing the same. Background Art

[0002] Recently, the demand for the use of flash memory has been increasing. Flash memory devices can be divided into NOR or NAND flash memory devices. Among them, the NOR memory device typically provides faster programming and reading speeds by connecting one end of each memory cell to ground and the other end to a bit line. Generally speaking, NOR flash memory is a two-dimensional type, and the memory cells exist in a two-dimensional array on a substrate. However, with the increasing number of applications nowadays, the size limitation of the two-dimensional structure is no longer sufficient. Therefore, in order to provide a memory device with a higher storage capacity, it is still urgent to develop a three-dimensional NOR memory element with better electrical characteristics (for example, having good data retention reliability and operating speed). Summary of the invention

[0003] In the present invention, a memory element and a method for manufacturing the same are provided to solve at least a part of the above problems.

[0004] According to one embodiment of the present invention, a memory element includes a substrate, a stacked structure, a plurality of channel structures, a storage layer and a plurality of isolation structures. The substrate has an upper surface. The stacked structure is located on the upper surface of the substrate, wherein the stacked structure includes a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer and a third insulating layer sequentially stacked on the substrate. The channel structure passes through the stacked structure and is electrically connected to the substrate, wherein each channel structure includes an upper portion and a lower portion, the upper portion corresponds to the second conductive layer, and the lower portion corresponds to the first conductive layer. The storage layer is located between the second conductive layer and the upper portion. The isolation structure passes through the stacked structure to separate the stacked structure into a plurality of sub-stacks.

[0005] According to an embodiment of the present invention, a method for preparing a memory element includes the following steps. First, a substrate is provided, the substrate having an upper surface; then, a stacked body is formed on the upper surface of the substrate, wherein the stacked body includes a first insulating layer, a first conductive layer, a second insulating layer, an upper sacrificial layer and a third insulating layer sequentially stacked on the upper surface of the substrate; a plurality of first openings are formed through the stacked body; a plurality of channel structures are formed in the first openings, and the channel structures are electrically connected to the substrate, wherein each channel structure includes an upper portion and a lower portion, the lower portion corresponds to the first conductive layer, and the upper portion is located above the lower portion; a storage layer corresponding to the upper portion is formed; a plurality of second openings are formed through the stacked body; the upper sacrificial layer is removed and an upper opening is formed at the position where the upper sacrificial layer is removed; a conductive material is filled in the upper opening to form a second conductive layer, thereby forming a stacked structure including the first insulating layer, the first conductive layer, the second insulating layer, the second conductive layer and the third insulating layer; thereafter, a plurality of isolation structures are formed in the second openings, and the isolation structures separate the stacked structure into a plurality of sub-stacks.

[0006] According to an embodiment of the present invention, a method for manufacturing a memory device includes the following steps. First, a substrate is provided, the substrate having an upper surface; then, a stacked body is formed on the upper surface of the substrate, wherein the stacked body includes a first insulating layer, a lower sacrificial layer, a second insulating layer, an upper sacrificial layer and a third insulating layer stacked in sequence on the upper surface of the substrate; a plurality of first openings are formed through the stacked body; a plurality of lower parts of a plurality of channel structures are formed in the first openings; a storage layer corresponding to the upper sacrificial layer is formed in each of the first openings; a plurality of upper parts of the channel structure are formed in the first openings, the upper parts are located above the lower parts; a plurality of second openings are formed through the stacked body; the upper sacrificial layer and the lower sacrificial layer are removed, and an upper opening and a lower opening are formed respectively at the positions where the upper sacrificial layer and the lower sacrificial layer are removed; a conductive material is filled in the upper opening and the lower opening to form a second conductive layer and a first conductive layer respectively, thereby forming a stacked structure including the first insulating layer, the first conductive layer, the second insulating layer, the second conductive layer and the third insulating layer; thereafter, a plurality of isolation structures are formed in the second openings, the isolation structures separating the stacked structure into a plurality of sub-layers.

[0007] In order to better understand the above and other aspects of the present invention, the following embodiments are specifically described in detail with reference to the accompanying drawings. However, the scope of protection of the present invention shall be subject to the definition of the above claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A A top view of a memory device according to an embodiment of the present invention is shown.

[0009] Figure 1B A cross-sectional view of a memory device according to an embodiment of the present invention is shown along line AA' of FIG. 1 .

[0010] Figure 1C FIG. 4 is a cross-sectional view of a memory device according to another embodiment of the present invention.

[0011] Figure 1D FIG. 4 is a cross-sectional view of a memory device according to another embodiment of the present invention.

[0012] Figure 1E FIG. 4 is a cross-sectional view of a memory device according to another embodiment of the present invention.

[0013] Figure 1F FIG. 4 is a cross-sectional view of a memory device according to another embodiment of the present invention.

[0014] Figure 1G FIG. 4 is a cross-sectional view of a memory device according to another embodiment of the present invention.

[0015] Figure 1H FIG. 4 is a cross-sectional view of a memory device according to another embodiment of the present invention.

[0016] FIG. 2A to FIG. 2N A cross-sectional view is shown of a method for forming a memory device according to an embodiment of the present invention.

[0017] FIG. 3A to FIG. 3M FIG. 4 is a cross-sectional view showing a method for forming a memory device according to another embodiment of the present invention.

[0018] FIG. 4A to FIG. 4L FIG. 5 is a cross-sectional view showing a method for forming a memory device according to another embodiment of the present invention.

[0019] Figure 5 FIG. 4 is an equivalent circuit diagram of a memory device according to an embodiment of the present invention.

[0020] Fig. 6A FIG. 4 is an equivalent circuit diagram of a memory device that performs a programming operation by Fowler-Nordheim injection according to an embodiment of the present invention.

[0021] Figure 6B FIG. 4 is an equivalent circuit diagram of a memory device that performs programming operation by channel-hot-electron injection according to an embodiment of the present invention.

[0022] Fig. 7A FIG. 4 is an equivalent circuit diagram of a memory device that performs an erase operation by Fowler-Nordheim injection according to an embodiment of the present invention.

[0023] Figure 7B FIG. 4 is an equivalent circuit diagram of a memory device that performs an erase operation by band-to-band tunneling induced hot hole injection according to an embodiment of the present invention.

[0024] Figure 8 FIG. 4 is an equivalent circuit diagram of a memory element for a read operation according to an embodiment of the present invention.

[0025] FIG. 9A to FIG. 9R FIG. 5 is a cross-sectional view showing a method for forming a memory device according to another embodiment of the present invention.

[0026] FIG. 10A to FIG. 10K FIG. 5 is a cross-sectional view showing a method for forming a memory device according to another embodiment of the present invention.

[0027] FIG. 11A to FIG. 11M FIG. 5 is a cross-sectional view showing a method for forming a memory device according to another embodiment of the present invention.

[0028] FIG. 12A to FIG. 12K FIG. 5 is a cross-sectional view showing a method for forming a memory device according to another embodiment of the present invention.

[0029] Fig.13 FIG. 4 is an equivalent circuit diagram of a memory device that performs a programming operation by Fowler-Nordheim injection according to an embodiment of the present invention.

[0030] Fig.14A FIG. 4 is an equivalent circuit diagram of a memory device that performs an erase operation by Fowler-Nordheim injection according to an embodiment of the present invention.

[0031] Fig. 14B FIG. 4 is an equivalent circuit diagram of a memory device that performs an erase operation by band-to-band tunneling-induced hot holes according to an embodiment of the present invention.

[0032] Fig.15 FIG. 4 is an equivalent circuit diagram of a memory element for a read operation according to an embodiment of the present invention.

[0033]

Explanation of symbols

[0034] 100, 200, 300, 400, 500, 600, 700: memory components

[0035] 110, 210, 310, 410, 510, 610, 710: Substrate

[0036] 110a, 210a, 310a, 410a, 510a, 610a, 710a: upper surface

[0037] 112, 212, 312, 412, 512, 612, 712: channel structure

[0038] 112a, 212a, 312a: lower part

[0039] 112b, 212b, 312b: upper part

[0040] 112c, 212c, 312c, 412c, 512c, 612c, 712c, 118, 218, 318, 418, 518, 618, 718: doped regions

[0041] 112t: Top surface

[0042] 122, 222, 322, 422, 522, 622, 722: first insulation layer

[0043] 124, 224, 324, 424, 524, 624, 724: Second insulation layer

[0044] 126, 226, 326, 426, 526, 626, 726: The third insulation layer

[0045] 128, 228, 328: Cover layer

[0046] 130, 230, 330, 430, 530, 630, 730: first conductive layer

[0047] 132, 232, 332, 432, 532, 632, GO4, GO5, GO6: thermal oxide layer

[0048] 132', 232', 332', 432', 532', 632', 732': oxide layer

[0049] 140, 240, 340, 440, 540, 640, 740: Upper sacrificial layer

[0050] 152, 252, 352, 452, 552, 652, 752: First opening

[0051] 154, 254, 354, 454, 554, 654, 754: Second opening

[0052] 156, 256, 356, 456, 556, 656, 756: upper opening

[0053] 162, 262, 362, 462, 562, 662, 762: storage layer

[0054] 164, 364, 664: protective layer

[0055] 166, 266, 366, 566, 666, 766: Dielectric materials

[0056] 172, 272, 372, 472, 572, 672, 772: second conductive layer

[0057] 172', 272', 372', 472', 572', 672', 772': conductive materials

[0058] 174, 274, 374, 474, 574, 674, 774: Isolation structures

[0059] 176, 276, 376, 476, 576, 676, 776: Conductive connection structure

[0060] 211: Adulterants

[0061] 342, 442, 642, 742: Lower sacrificial layer

[0062] 259, 459, 559, 759: vertical opening

[0063] 358, 458, 658: bottom opening

[0064] 472': Conductive materials

[0065] BL, BL0, BL1, BL2: bit lines

[0066] CL4, CL5, CL6, CL7: Top conductive layer

[0067] CSL: Common Source Line

[0068] GSL0, GSL1, GSL2: Ground selection lines

[0069] H1: First height

[0070] H2: The second highest

[0071] M, M1, M2, M3, M4, M5, M6, M7: storage unit

[0072] OL4, OL5, OL6, OL7: Top insulation layer

[0073] P1: Top opening

[0074] S1, S2, S3, S4, S5, S6, S7: laminated structure

[0075] S1', S2', S3', S4', S5', S6', S7': laminated body

[0076] SLT1: First channel

[0077] SLT2: Second channel

[0078] SLT3: Third channel

[0079] SS1, SS2: Secondary stacking

[0080] T, T1, T2, T3, T4, T5, T6, T7, TS4, TS5, TS6, TS7: Transistor

[0081] UN, UN1, UN2, UN3, UN4, UN5, UN6, UN7, UN t : Unit storage unit

[0082] WL0, WL1, WL2: word lines DETAILED DESCRIPTION

[0083] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0084] In the detailed description below, various specific details are provided to provide an overall understanding of the embodiments of the present invention for ease of explanation. However, it should be understood that one or more embodiments can be implemented without adopting these specific details. In other cases, in order to simplify the accompanying drawings, known structures and elements are represented by schematic diagrams.

[0085] Figure 1A A top view of a memory device 100 according to an embodiment of the present invention is shown; Figure 1B A cross-sectional view of a memory device 100 according to an embodiment of the present invention is shown along line AA' of FIG. 1 .

[0086] Please refer to Figure 1A , a plurality of bit lines BL and a common source line CSL are located above the stacked structure S1, wherein the plurality of bit lines BL and the common source line CSL are parallel to the upper surface 110a of the substrate 110 (shown in FIG. Figure 1B ), and the plurality of bit lines BL are arranged and separated along a second direction (e.g., the X-axis direction) perpendicular to the first direction. The bit lines BL are electrically connected to the corresponding channel structures 112. The common source line CSL is electrically connected to the corresponding conductive connection structure 176.

[0087] Please also refer to Figure 1A and Figure 1BThe memory device 100 includes a substrate 110, a stacked structure S1, a cap layer 128, a plurality of channel structures 112, a thermal oxide layer 132, a storage layer 162, a dielectric material 166, a plurality of isolation structures 174, and a plurality of conductive connection structures 176. The stacked structure S1 is formed on the upper surface 110a of the substrate 110. The stacked structure S1 includes a first insulating layer 122, a first conductive layer 130, a second insulating layer 124, a second conductive layer 172, and a third insulating layer 126 stacked in sequence (e.g., along the Z axis) on the substrate 110. The cap layer 128 may cover the stacked structure S1, that is, it is located on the third insulating layer 126. In some embodiments, the substrate 110 may be a silicon substrate or other suitable substrates. The first insulating layer 122, the second insulating layer 124, the third insulating layer 126, and the cap layer 128 may be formed of oxide, such as silicon dioxide (SiO2). The first conductive layer 130 and the second conductive layer 172 may be formed of a conductive material, such as tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), doped or undoped polysilicon (poly-silicon) or other suitable materials. In the present embodiment, the first conductive layer 130 and the second conductive layer 172 are formed of different materials, such as n-type doped polysilicon and tungsten, respectively, but the present invention is not limited thereto, and the first conductive layer 130 and the second conductive layer 172 may be formed of the same material. In some embodiments, the thickness of the first conductive layer 130 may be Can be used to adjust the threshold voltage (Vt).

[0088] The channel structure 112 passes through (e.g., along the Z-axis) the stacked structure S1 and is electrically connected to the substrate 110, wherein each channel structure 112 includes a lower portion 112a and an upper portion 112b. The upper portion 112b is located above the lower portion 112a, and the upper portion 112b is directly connected to the lower portion 112a. In other words, the upper portion 112b corresponds to the second conductive layer 172, and the lower portion 112a corresponds to the first conductive layer 130. The top region of the channel structure 112 may have a doped region 112c, such as an n-type semiconductor dopant, so that the channel structure 112 can be electrically connected to the bit line BL. In some embodiments, the channel structure 112 may be an epitaxial growth layer, such as a single crystal or polycrystalline silicon layer formed by an epitaxial growth process or any combination thereof, and may be an undoped or slightly P-type doped epitaxial growth layer. A top surface 112t of the channel structure 112 (i.e., the epitaxial growth layer) has a first height H1 with the upper surface 110a of the substrate 110, and a top surface 172t of the second conductive layer 172 has a second height H2 with the upper surface 110a of the substrate 110, and the first height H1 may be greater than the second height H2. Compared to the comparative example in which the channel structure only partially includes the epitaxial growth layer, since the channel structure 112 of the present invention including the upper portion 112b and the lower portion 112a is formed by the epitaxial growth process, the channel structure 112 may have a lower resistance and better conductivity, and the memory device 100 may have a faster operating speed (e.g., the operating speed of reading and writing).

[0089] The thermal oxide layer 132 is located between the first conductive layer 130 and the channel structure 112. For example, the thermal oxide layer 132 surrounds at least a portion of the lower portion 112a of the channel structure 112. In some embodiments, the thermal oxide layer 132 is an oxide layer formed by directly performing an oxidation process on the first conductive layer 130, such as silicon dioxide (SiO2). Since the thermal oxide layer 132 is an oxide layer formed by directly oxidizing the conductive layer (such as the first conductive layer 130) rather than an oxide layer formed by a deposition process (such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or other deposition processes), the purity of the oxide of the thermal oxide layer 132 is greater than the purity of the oxide of the insulating layer (such as the first insulating layer 122, the second insulating layer 124 or the third insulating layer 126) formed by the deposition method. Compared to the comparative example in which the thermal oxide layer is an oxide layer formed by a deposition process, since the thermal oxide layer of the present invention is an oxide layer formed by directly performing an oxidation process on the conductive layer, the thermal oxide layer has higher oxide purity and quality, and can better control the threshold voltage (Vt). Therefore, it can have a lower threshold voltage in low-power applications, so that the memory element 100 can have better reliability.

[0090] The storage layer 162 is located between the second conductive layer 172 and the upper portion 112b of the channel structure 112. For example, the storage layer 162 extends along the Z-axis direction and surrounds the upper portion 112b of the channel structure 112. The storage layer 162 may be composed of a composite layer (i.e., an ONO layer) including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. For example, the storage layer 162 may include a tunneling layer, a capture layer, and a barrier layer. The tunneling layer may include silicon dioxide (SiO2), a double-layer structure formed by silicon dioxide (SiO2) / silicon oxynitride (SiON), or other suitable materials. The capture layer may include silicon nitride, polysilicon, or other suitable materials. The barrier layer may include silicon dioxide (SiO2) or other suitable materials.

[0091] The dielectric material 166 is located between the storage layer 162 and the second conductive layer 172. Part of the dielectric material 166 may extend along the normal direction on the upper surface 110a of the substrate 110, and part of the dielectric material 166 may extend along the direction parallel to the upper surface 110a of the substrate 110. The dielectric material 166 may cover the second conductive layer 172. In some embodiments, the dielectric material 166 may include a high-k material, such as aluminum oxide (Al2O3) or other suitable materials. The dielectric material 166 may also serve as a blocking layer to prevent lateral diffusion of charges. Compared to the comparative example in which the high-k material is not used as the dielectric material, since the dielectric material 166 of the present case can use a high-k material, the operation of the memory element (such as erasing and writing) can be performed without using too high a voltage, so the performance of the memory element can be improved.

[0092] The isolation structure 174 can pass through the stacked structure S1 and separate the stacked structure S1 into a plurality of sub-stacks SS1 and SS2. This embodiment only illustrates two sub-stacks, but the present invention is not limited thereto, and the number of sub-stacks can be greater than two. The isolation structure 174 can be formed of an insulating material, such as an oxide or other suitable material. The second conductive layers 172 in adjacent sub-stacks SS1 and SS2 can be physically and electrically isolated by the isolation structure 174, so that the second conductive layers 172 in different sub-stacks can be operated independently, for example, by applying different voltages.

[0093] The conductive connection structure 176 may pass through the stacked structure S1 and be electrically connected to the substrate 110 through the doped region 118, for example. The doped region 118 is doped with an n-type semiconductor dopant, for example. The conductive connection structure 176 may be electrically connected to the common source line CSL.

[0094] In some embodiments, each intersection between the first conductive layer 130 and the thermal oxide layer 132 may form a transistor T1, and each intersection between the second conductive layer 172, the dielectric material 166, and the memory layer 162 may form a memory cell M1. The transistor T1 and the memory cell M1 are connected in series through the channel structure 112, and may together form a unit cell UN1. The first conductive layer 130 may serve as a ground select line, and the second conductive layer 172 may serve as a word line.

[0095] Figure 1C A cross-sectional view of a memory device 200 according to another embodiment of the present invention is shown. The memory device 200 has a similar top view to the memory device 100 (eg, Figure 1A ), so Figure 1C The cross-sectional view is similar to that along the AA' line of Figure 1. The memory device 200 has a structure similar to that of the memory device 100, except that the shape of the memory layer 262 is different.

[0096] Please refer to Figure 1C The memory device 200 includes a substrate 210, a stacked structure S2, a cap layer 228, a plurality of channel structures 212, a thermal oxide layer 232, a storage layer 262, a dielectric material 266, a plurality of isolation structures 274, and a plurality of conductive connection structures 276. The stacked structure S2 is formed on the upper surface 210a of the substrate 210. The stacked structure S2 includes a first insulating layer 222, a first conductive layer 230, a second insulating layer 224, a second conductive layer 272, and a third insulating layer 226 stacked on the substrate 210 in sequence (e.g., along the Z axis). The cap layer 228 can cover the stacked structure S2, that is, it is located on the third insulating layer 226. In the present embodiment, the first conductive layer 230 and the second conductive layer 272 are formed of different materials, such as n-type doped polysilicon and tungsten (W), respectively. However, the present invention is not limited thereto, and the first conductive layer 230 and the second conductive layer 272 can be formed of the same material. In some embodiments, the thickness of the first conductive layer 230 can be Can be used to adjust the threshold voltage (Vt).

[0097] The channel structure 212 (for example, along the Z axis) passes through the stacked structure S2 and is electrically connected to the substrate 210, wherein each channel structure 212 includes an upper portion 212b and a lower portion 212a. The upper portion 212b corresponds to the second conductive layer 272, and the lower portion 212a corresponds to the first conductive layer 230. The top region of the channel structure 212 may have a doped region 212c, for example, a dopant of an n-type semiconductor, so that the channel structure 212 can be electrically connected to the bit line BL. In some embodiments, the channel structure 212 may be an epitaxial growth layer, for example, a single crystal or polycrystalline silicon layer formed by an epitaxial growth process or any combination thereof, and may be an undoped or slightly P-type doped epitaxial growth layer. Compared to the comparative example in which the channel structure only partially includes the epitaxial growth layer, since the channel structure 212 of the present invention including the upper part 212b and the lower part 212a is formed by the epitaxial growth process, the channel structure 212 can have lower resistance and better conductivity, and the memory element 200 can have a faster operating speed (for example, the reading and writing operation speed).

[0098] The thermal oxide layer 232 is located between the first conductive layer 230 and the channel structure 212. For example, the thermal oxide layer 232 surrounds at least a portion of the lower portion 212a of the channel structure 212. In some embodiments, the thermal oxide layer 232 is an oxide formed by directly performing an oxidation process on the first conductive layer 230, such as silicon dioxide (SiO2). Since the thermal oxide layer 232 is an oxide layer formed by directly oxidizing the conductive layer (such as the first conductive layer 130) rather than an oxide layer formed by a deposition process (such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or other deposition processes), the purity of the oxide of the thermal oxide layer 232 is greater than the purity of the oxide of the insulating layer (such as the first insulating layer 222, the second insulating layer 224 or the third insulating layer 226) formed by the deposition method. Compared to the comparative example in which the thermal oxide layer is an oxide layer formed by a deposition process, since the thermal oxide layer of the present invention is an oxide layer formed by directly performing an oxidation process on the conductive layer, the thermal oxide layer has higher oxide purity and quality, and can better control the threshold voltage (Vt). Therefore, it can have a lower threshold voltage in low-power applications, so that the memory element 200 can have better reliability.

[0099] The storage layer 262 is located between the second conductive layer 272 and the upper portion 212b of the channel structure 212. For example, part of the storage layer 262 extends along the normal direction of the upper surface 210a of the substrate 210 (for example, the Z-axis direction), and part of the storage layer 262 extends along the direction parallel to the upper surface 210a of the substrate 210. The storage layer 262 may surround the upper portion 212b of the channel structure 212 and cover the second conductive layer 272. The storage layer 262 may be composed of a composite layer (i.e., ONO layer) including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. For example, the storage layer 262 may include a tunneling layer, a capture layer, and a barrier layer. The tunneling layer may include silicon dioxide (SiO2), a double-layer structure formed by silicon dioxide (SiO2) / silicon oxynitride (SiON), or other suitable materials. The capture layer may include silicon nitride, polysilicon, or other suitable materials. The barrier layer may include silicon dioxide (SiO2) or other suitable material.

[0100] The dielectric material 266 is located between the storage layer 262 and the second conductive layer 272. Part of the dielectric material 266 may extend along the normal direction of the upper surface 210a of the substrate 210, and part of the dielectric material 266 may extend along the direction parallel to the upper surface 210a of the substrate 210. The dielectric material 266 may cover the second conductive layer 272. In some embodiments, the dielectric material 266 may include a high-k material, such as aluminum oxide (Al2O3) or other suitable materials. The dielectric material 266 may also serve as a blocking layer to prevent lateral diffusion of charges. Compared to the comparative example in which the high-k material is not used as the dielectric material, since the dielectric material 266 of the present case can use a high-k material, the operation of the memory element (such as erasing and writing) can be performed without using too high a voltage, so the performance of the memory element can be improved.

[0101] The isolation structure 274 may pass through the stacked structure S2 to separate the stacked structure S2 into a plurality of sub-stacks. The isolation structure 274 may be formed of an insulating material, such as an oxide or other suitable material. The second conductive layers 272 in adjacent sub-stacks may be physically and electrically isolated by the isolation structure 274, so that the second conductive layers 272 in different sub-stacks may be operated independently, for example, by applying different voltages.

[0102] The conductive connection structure 276 may pass through the stacked structure S2 and be electrically connected to the substrate 210 through the doped region 218, for example. The doped region 218 is doped with an n-type semiconductor dopant, for example. The conductive connection structure 276 may be electrically connected to a common source line.

[0103] In some embodiments, each intersection between the first conductive layer 230 and the thermal oxide layer 232 may form a transistor T2, and each intersection between the second conductive layer 272, the dielectric material 266, and the memory layer 262 may form a memory cell M2. The transistor T2 and the memory cell M2 are connected in series through the channel structure 212, and may together form a unit memory cell UN2. The first conductive layer 230 may be used as a ground selection line, and the second conductive layer 272 may be used as a word line.

[0104] Compared to the storage element 100, since the storage layer 262 of the storage element 200 partially extends along the normal direction of the upper surface 210a of the substrate 210 and the other part extends along the direction parallel to the upper surface 210a of the substrate 210, it has a U-shaped appearance and can better prevent lateral diffusion of charges and is less likely to affect the critical voltage.

[0105] Figure 1D A cross-sectional view of a memory device 300 according to another embodiment of the present invention is shown. The memory device 300 has a similar top view to the memory device 100 (eg, Figure 1A ), so Figure 1D Draw similar to Figure 1A The memory element 300 has a structure similar to the memory 100, except that the material of the first conductive layer 330 is different, and the distribution position of the dielectric material 366 is different.

[0106] Please refer to Figure 1D The memory device 300 includes a substrate 310, a stacked structure S3, a cap layer 328, a plurality of channel structures 312, a thermal oxide layer 332, a storage layer 362, a dielectric material 366, a plurality of isolation structures 374, and a plurality of conductive connection structures 376. The stacked structure S3 is formed on the upper surface 210a of the substrate 210. The stacked structure S3 includes a first insulating layer 322, a first conductive layer 330, a second insulating layer 324, a second conductive layer 372, and a third insulating layer 326 stacked on the substrate 310 in sequence (e.g., along the Z axis). The cap layer 328 may cover the stacked structure S3, that is, it is located on the third insulating layer 326. In some embodiments, the first conductive layer 330 and the second conductive layer 372 are formed of the same conductive material, such as tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), polysilicon (poly-silicon) or other suitable materials. In this embodiment, the first conductive layer 330 and the second conductive layer 372 are both formed of tungsten. In some embodiments, the thickness of the first conductive layer 330 may be Can be used to adjust the threshold voltage (Vt).

[0107] The channel structure 312 passes through (e.g., along the Z-axis) the stacked structure S3 and is electrically connected to the substrate 310, wherein each channel structure 312 includes an upper portion 312b and a lower portion 312a. The upper portion 312b corresponds to the second conductive layer 372, and the lower portion 312a corresponds to the first conductive layer 330. The top region of the channel structure 312 may have a doped region 312c, such as an n-type semiconductor dopant, so that the channel structure 312 can be electrically connected to the bit line BL. In some embodiments, the channel structure 312 may be an epitaxial growth layer, such as a single crystal or polycrystalline silicon layer formed by an epitaxial growth process or any combination thereof, and may be an undoped or slightly P-type doped epitaxial growth layer. Compared to the comparative example in which the channel structure only partially includes the epitaxial growth layer, since the channel structure 312 of the present invention including the upper part 312b and the lower part 312a is formed by the epitaxial growth process, the channel structure 312 can have a lower resistance and better conductivity, and the memory element 300 can have a faster operating speed (for example, the reading and writing operation speed).

[0108] The thermal oxide layer 332 is located between the first conductive layer 330 and the channel structure 312. For example, the thermal oxide layer 332 surrounds at least a portion of the lower portion 312a of the channel structure 312. In some embodiments, the thermal oxide layer 332 is an oxide formed by directly performing an oxidation process on the channel structure 312, such as silicon dioxide (SiO2). Since the thermal oxide layer 332 is an oxide layer formed by directly oxidizing the conductive layer (such as the channel structure 312) rather than an oxide layer formed by a deposition process (such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or other deposition processes), the purity of the oxide of the thermal oxide layer 332 is greater than the purity of the oxide of the insulating layer (such as the first insulating layer 322, the second insulating layer 324 or the third insulating layer 326) formed by the deposition method. Compared to the comparative example in which the thermal oxide layer is an oxide layer formed by a deposition process, since the thermal oxide layer of the present invention is an oxide layer formed by directly performing an oxidation process on the conductive layer, the thermal oxide layer has higher oxide purity and quality, and can better control the critical voltage (Vt). Therefore, it can have a lower critical voltage in low-power applications, so that the memory element 300 can have better reliability.

[0109] The storage layer 362 is located between the second conductive layer 372 and the upper portion 312b of the channel structure 312. For example, the storage layer 362 extends along the normal direction of the upper surface 210a of the substrate 210 (for example, the Z-axis direction) and may surround the upper portion 312b of the channel structure 312. The storage layer 362 may be composed of a composite layer (i.e., an ONO layer) including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. For example, the storage layer 362 may include a tunneling layer, a capture layer, and a barrier layer. The tunneling layer may include silicon dioxide (SiO2), a double-layer structure formed by silicon dioxide (SiO2) / silicon oxynitride (SiON), or other suitable materials. The capture layer may include silicon nitride, polysilicon, or other suitable materials. The barrier layer may include silicon dioxide (SiO2) or other suitable materials.

[0110] The dielectric material 366 is located between the storage layer 362 and the second conductive layer 372, and between the first conductive layer 330 and the thermal oxide layer 332. Part of the dielectric material 366 may extend along the normal direction of the upper surface 310a of the substrate 310, and part of the dielectric material 366 may extend along the direction parallel to the upper surface 310a of the substrate 310. The dielectric material 366 may cover the first conductive layer 330 and the second conductive layer 372. In some embodiments, the dielectric material 366 may include a high-k material, such as aluminum oxide (Al2O3) or other suitable materials. The dielectric material 366 may also serve as a blocking layer to prevent lateral diffusion of charges. Compared with the comparative example in which the high-k material is not used as the dielectric material, since the dielectric material 366 of the present case can use the high-k material, the operation of the memory element (such as erasing and writing) can be performed without using too high a voltage, so the performance of the memory element 300 can be improved.

[0111] The isolation structure 374 may pass through the stacked structure to separate the stacked structure into a plurality of sub-stacks. The isolation structure 374 may be formed of an insulating material, such as an oxide or other suitable material. The second conductive layers 372 in adjacent sub-stacks may be physically and electrically isolated by the isolation structure 374, so that the second conductive layers 372 in different sub-stacks may be operated independently, for example, by applying different voltages.

[0112] The conductive connection structure 376 may pass through the stacked structure and be electrically connected to the substrate 310 through the doped region 318, for example. The doped region 318 is doped with an n-type semiconductor dopant, for example. The conductive connection structure 376 may be electrically connected to a common source line.

[0113] In some embodiments, the intersection between the first conductive layer 330 and the thermal oxide layer 332 may form a transistor T3, and the intersection between the second conductive layer 372, the dielectric material 366 and the memory layer 362 may form a memory cell M3. The transistor T3 and the memory cell M3 are connected in series through the channel structure 312, and may together form a unit memory cell UN3. The first conductive layer 330 may be used as a ground selection line, and the second conductive layer 372 may be used as a word line.

[0114] The above embodiments of the present invention provide some memory elements 100-300 with two conductive layers, but the present invention is not limited thereto, and the number of conductive layers may be greater than two. Among them, some embodiments of memory elements 400-700 with three conductive layers are listed below. Elements similar to the memory elements 100-300 in the memory elements 400-700 are represented by similar element symbols. The same element names may have the same or similar materials.

[0115] Figure 1E A cross-sectional view of a memory device 400 according to another embodiment of the present invention is shown. The memory device 400 has a similar top view to the memory device 100 (eg, Figure 1A ), so Figure 1E A cross-sectional view similar to that taken along line AA' of FIG. 1 is shown.

[0116] Please refer to Figure 1E The memory element 400 includes a substrate 410, a first insulating layer 422, a first conductive layer 430, a second insulating layer 424, a second conductive layer 472, a plurality of channel structures 412, a thermal oxide layer 432 and GO4, a storage layer 462, a third insulating layer 426, a top conductive layer CL4, a top insulating layer OL4, a plurality of isolation structures 474 and a plurality of conductive connection structures 476.

[0117] In this embodiment, the first conductive layer 430 and the second conductive layer 472 are formed of different materials, such as n-type doped polysilicon and tungsten (W), respectively. However, the present invention is not limited thereto, and the first conductive layer 430 and the second conductive layer 472 can be formed of the same material. In some embodiments, the thickness of the first conductive layer 430 can be Can be used to adjust the threshold voltage (Vt).

[0118] The channel structure 412 (e.g., along the Z axis) passes through the stacked structure S4 and is electrically connected to the substrate 410. The top region of the channel structure 412 may have a doped region 412c, such as an n-type semiconductor dopant, so that the channel structure 412 can be electrically connected to the bit line BL. In some embodiments, the channel structure 412 may be an epitaxial growth layer, such as a single crystal or polycrystalline silicon layer formed by an epitaxial growth process or any combination thereof, and may be an undoped or slightly P-type doped epitaxial growth layer.

[0119] The thermal oxide layer 432 and GO4 are respectively located between the first conductive layer 430 and the channel structure 412, and between the top conductive layer CL4 and the channel structure 412. For example, the thermal oxide layer 432 surrounds at least a portion of the lower portion of the channel structure 412, and the thermal oxide layer GO4 surrounds at least a portion of the upper portion of the channel structure 412. In some embodiments, the thermal oxide layer 432 and GO4 are oxides formed by directly performing an oxidation process on the channel structure 412, such as silicon dioxide (SiO2). Since the thermal oxide layer 432 and GO4 are oxide layers formed by directly oxidizing the channel structure 412, rather than oxide layers formed by a deposition process (such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or other deposition processes), the purity of the oxides of the thermal oxide layer 432 and GO4 is greater than the purity of the oxides of the insulating layers (such as the first insulating layer 422, the second insulating layer 424 or the third insulating layer 426) formed by the deposition method. Compared to the comparative example in which the thermal oxide layer is an oxide layer formed by a deposition process, since the thermal oxide layer of the present invention is an oxide layer formed by directly performing an oxidation process on the conductive layer, the thermal oxide layer has higher oxide purity and quality, and can better control the critical voltage (Vt). Therefore, it can have a lower critical voltage in low-power applications, so that the memory element 400 can have better reliability.

[0120] The storage layer 462 is located between the second conductive layer 472 and the channel structure 412. For example, part of the storage layer 462 extends along the normal direction of the upper surface 410a of the substrate 410 (for example, the Z-axis direction), and part of the storage layer 462 extends along the direction parallel to the upper surface 410a of the substrate 410. The storage layer 462 may surround the channel structure 412 and cover the second conductive layer 472. The storage layer 462 may be composed of a composite layer (i.e., AONO layer) including aluminum oxide (Al2O3, aluminum oxide), a silicon oxide (silicon oxide) layer, a silicon nitride (silicon nitride) layer and a silicon oxide layer. For example, the storage layer 462 may include a tunneling layer, a capture layer and a barrier layer. The tunneling layer may include silicon dioxide (SiO2), a double-layer structure formed by silicon dioxide (SiO2) / silicon oxynitride (SiON) or other suitable materials. The capture layer may include silicon nitride, polysilicon or other suitable materials. The barrier layer may include silicon dioxide (SiO2) or other suitable material.

[0121] The isolation structure 474 may pass through the stacked structure S4 to separate the stacked structure S4 into a plurality of sub-stacks. The isolation structure 474 may be formed of an insulating material, such as an oxide or other suitable material. The second conductive layers 472 in adjacent sub-stacks may be physically and electrically isolated by the isolation structure 474, so that the second conductive layers 472 in different sub-stacks may be operated independently, for example, by applying different voltages.

[0122] The conductive connection structure 476 may pass through the stacked structure S4 and be electrically connected to the substrate 410 through the doped region 418, for example. The doped region 418 is doped with an n-type semiconductor dopant, for example. The conductive connection structure 476 may be electrically connected to a common source line.

[0123] In some embodiments, each overlap position between the first conductive layer 430 and the thermal oxide layer 432 can form a transistor T4, each overlap position between the top conductive layer CL4 and the thermal oxide layer GO4 can form a transistor TS4, and each overlap position between the second conductive layer 472 and the memory layer 462 can form a memory cell M4. The transistor T4, the transistor TS4 and the memory cell M4 are connected in series through the channel structure 412, and can form a unit cell UN4, which can also be called a memory cell series. The first conductive layer 430 can be used as a ground selection line, the second conductive layer 472 can be used as a word line, and the top conductive layer CL4 can be used as a series selection line.

[0124] Figure 1FA cross-sectional view of a memory device 500 according to another embodiment of the present invention is shown. The memory device 500 has a similar top view to the memory device 100 (eg, Figure 1A ), so Figure 1F A cross-sectional view similar to that taken along line AA' of FIG. 1 is shown.

[0125] Please refer to Figure 1F The memory element 500 includes a substrate 510, a first insulating layer 522, a first conductive layer 530, a second insulating layer 524, a second conductive layer 572, a plurality of channel structures 512, a thermal oxide layer 532 and GO5, a storage layer 562, a third insulating layer 526, a top conductive layer CL5, a top insulating layer OL5, a plurality of isolation structures 574 and a plurality of conductive connection structures 576.

[0126] In this embodiment, the first conductive layer 530 and the second conductive layer 572 are formed of different materials, such as n-type doped polysilicon and tungsten (W), respectively. However, the present invention is not limited thereto, and the first conductive layer 530 and the second conductive layer 572 can be formed of the same material. In some embodiments, the thickness of the first conductive layer 530 can be Can be used to adjust the threshold voltage (Vt).

[0127] The channel structure 512 (e.g., along the Z axis) passes through the stacked structure S5 and is electrically connected to the substrate 510. The top region of the channel structure 512 may have a doped region 512c, such as an n-type semiconductor dopant, so that the channel structure 512 can be electrically connected to the bit line BL. In some embodiments, the channel structure 512 may be an epitaxial growth layer, such as a single crystal or polycrystalline silicon layer formed by an epitaxial growth process or any combination thereof, and may be an undoped or slightly P-type doped epitaxial growth layer.

[0128] The thermal oxide layer 532 and GO5 are respectively located between the first conductive layer 530 and the channel structure 512, and between the top conductive layer CL5 and the channel structure 512. For example, the thermal oxide layer 532 surrounds at least a portion of the lower portion of the channel structure 512, and the thermal oxide layer GO5 surrounds at least a portion of the upper portion of the channel structure 512. In some embodiments, the thermal oxide layer 532 and GO5 are oxides formed by directly performing an oxidation process on the channel structure 512, such as silicon dioxide (SiO2). Since the thermal oxide layer 532 and GO5 are oxide layers formed by directly oxidizing the channel structure 512, rather than oxide layers formed by a deposition process (such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or other deposition processes), the purity of the oxides of the thermal oxide layer 532 and GO5 is greater than the purity of the oxides of the insulating layers (such as the first insulating layer 522, the second insulating layer 524 or the third insulating layer 526) formed by the deposition method. Compared to the comparative example in which the thermal oxide layer is an oxide layer formed by a deposition process, since the thermal oxide layer of the present invention is an oxide layer formed by directly performing an oxidation process on the conductive layer, the thermal oxide layer has higher oxide purity and quality, and can better control the critical voltage (Vt). Therefore, it can have a lower critical voltage in low-power applications, so that the memory element 500 can have better reliability.

[0129] The storage layer 562 is located between the second conductive layer 572 and the channel structure 512. For example, part of the storage layer 562 extends along the normal direction of the upper surface 510a of the substrate 510 (for example, the Z-axis direction), and part of the storage layer 562 extends along the direction parallel to the upper surface 510a of the substrate 510. The storage layer 562 may surround the channel structure 512 and cover the second conductive layer 572. The storage layer 562 may be composed of a composite layer (i.e., an ONO layer) including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. For example, the storage layer 562 may include a tunneling layer, a capture layer, and a barrier layer. The tunneling layer may include silicon dioxide (SiO2), a double-layer structure formed by silicon dioxide (SiO2) / silicon oxynitride (SiON), or other suitable materials. The capture layer may include silicon nitride, polysilicon, or other suitable materials. The barrier layer may include silicon dioxide (SiO2) or other suitable materials.

[0130] The isolation structure 574 may pass through the stacked structure S5 to separate the stacked structure S5 into a plurality of sub-stacks. The isolation structure 574 may be formed of an insulating material, such as an oxide or other suitable material. The second conductive layers 572 in adjacent sub-stacks may be physically and electrically isolated by the isolation structure 574, so that the second conductive layers 572 in different sub-stacks may be operated independently, for example, by applying different voltages.

[0131] The conductive connection structure 576 may pass through the stacked structure S5 and be electrically connected to the substrate 410 through the doped region 518, for example. The doped region 418 is doped with an n-type semiconductor dopant, for example. The conductive connection structure 476 may be electrically connected to a common source line.

[0132] In some embodiments, each overlap position between the first conductive layer 530 and the thermal oxide layer 532 can form a transistor T5, each overlap position between the top conductive layer CL5 and the thermal oxide layer GO5 can form a transistor TS5, and each overlap position between the second conductive layer 572 and the memory layer 562 can form a memory cell M5. The transistor T5, the transistor TS5, and the memory cell M5 are connected in series through the channel structure 512, and can form a unit memory cell UN5, which can also be called a memory cell series. The first conductive layer 530 can be used as a ground selection line, the second conductive layer 572 can be used as a word line, and the top conductive layer CL5 can be used as a series selection line.

[0133] Figure 1G A cross-sectional view of a memory device 600 according to another embodiment of the present invention is shown. The memory device 600 has a similar top view to the memory device 100 (eg, Figure 1A ), so Figure 1F A cross-sectional view similar to that taken along line AA' of FIG. 1 is shown.

[0134] Please refer to Figure 1G The memory element 600 includes a substrate 610, a first insulating layer 622, a first conductive layer 630, a second insulating layer 624, a second conductive layer 672, a plurality of channel structures 612, a thermal oxide layer 632 and GO6, a storage layer 662, a third insulating layer 626, a top conductive layer CL6, a top insulating layer OL6, a plurality of isolation structures 674 and a plurality of conductive connection structures 676.

[0135] The channel structure 612 (e.g., along the Z axis) passes through the stacked structure S6 and is electrically connected to the substrate 610. The top region of the channel structure 612 may have a doped region 612c, such as an n-type semiconductor dopant, so that the channel structure 612 can be electrically connected to the bit line BL. In some embodiments, the channel structure 612 may be an epitaxial growth layer, such as a single crystal or polycrystalline silicon layer formed by an epitaxial growth process or any combination thereof, and may be an undoped or slightly P-type doped epitaxial growth layer.

[0136] The thermal oxide layer 632 and GO6 are respectively located between the first conductive layer 630 and the channel structure 612, and between the top conductive layer CL6 and the channel structure 612. For example, the thermal oxide layer 632 surrounds at least a portion of the lower portion of the channel structure 612, and the thermal oxide layer GO6 surrounds at least a portion of the upper portion of the channel structure 612. In some embodiments, the thermal oxide layer 632 and GO6 are oxides formed by directly performing an oxidation process on the channel structure 612, such as silicon dioxide (SiO2). Since the thermal oxide layer 632 and GO6 are oxide layers formed by directly oxidizing the channel structure 612, rather than oxide layers formed by a deposition process (such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or other deposition processes), the purity of the oxides of the thermal oxide layer 632 and GO6 is greater than the purity of the oxides of the insulating layers (such as the first insulating layer 622, the second insulating layer 624 or the third insulating layer 626) formed by the deposition method. Compared to the comparative example in which the thermal oxide layer is an oxide layer formed through a deposition process, since the thermal oxide layer of the present invention is an oxide layer formed by directly performing an oxidation process on the conductive layer, the thermal oxide layer has higher oxide purity and quality, and can better control the critical voltage (Vt). Therefore, it can have a lower critical voltage in low-power applications, so that the memory element 600 can have better reliability.

[0137] The storage layer 662 is located between the second conductive layer 672 and the channel structure 612. For example, the storage layer 662 extends along the normal direction of the upper surface 610a of the substrate 610 (for example, the Z-axis direction). The storage layer 662 can be composed of a composite layer (i.e., an ONO layer) including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. For example, the storage layer 662 may include a tunneling layer, a capture layer, and a barrier layer. The tunneling layer may include silicon dioxide (SiO2), a double-layer structure formed by silicon dioxide (SiO2) / silicon oxynitride (SiON), or other suitable materials. The capture layer may include silicon nitride, polysilicon, or other suitable materials. The barrier layer may include silicon dioxide (SiO2) or other suitable materials.

[0138] The isolation structure 674 may pass through the stacked structure S6 to separate the stacked structure S6 into a plurality of sub-stacks. The isolation structure 674 may be formed of an insulating material, such as an oxide or other suitable material. The second conductive layers 672 in adjacent sub-stacks may be physically and electrically isolated by the isolation structure 674, so that the second conductive layers 672 in different sub-stacks may be operated independently, for example, by applying different voltages.

[0139] The conductive connection structure 676 may pass through the stacked structure S6 and be electrically connected to the substrate 610 through the doped region 618. The doped region 618 is doped with an n-type semiconductor dopant, for example. The conductive connection structure 676 may be electrically connected to a common source line.

[0140] In some embodiments, each intersection between the first conductive layer 630 and the thermal oxide layer 632 can form a transistor T6, each intersection between the top conductive layer CL6 and the thermal oxide layer GO6 can form a transistor TS6, and each intersection between the second conductive layer 672 and the memory layer 662 can form a memory cell M6. The transistor T6, the transistor TS6, and the memory cell M6 are connected in series through the channel structure 612, and can together form a unit memory cell UN6, which can also be called a memory cell series. The first conductive layer 630 can be used as a ground selection line, the second conductive layer 672 can be used as a word line, and the top conductive layer CL6 can be used as a series selection line.

[0141] Figure 1H A cross-sectional view of a memory device 700 according to another embodiment of the present invention is shown. The memory device 700 has a similar top view to the memory device 100 (eg, Figure 1A ), so Figure 1H A cross-sectional view similar to that taken along line AA' of FIG. 1 is shown.

[0142] Please refer to Figure 1H , the memory device 700 includes a substrate 710, a first insulating layer 722, a first conductive layer 730, a second insulating layer 724, a second conductive layer 772, a plurality of channel structures 712, an oxide layer 732', a storage layer 762, a third insulating layer 726, a top conductive layer CL7, a top insulating layer OL7, a plurality of isolation structures 774, and a plurality of conductive connection structures 776. In some embodiments, the first insulating layer 722, the second insulating layer 724, the oxide layer 732', the third insulating layer 726, and the top insulating layer OL7 may be formed of the same material.

[0143] The channel structure 712 (e.g., along the Z axis) passes through the stacked structure S7 and is electrically connected to the substrate 710. The top region of the channel structure 712 may have a doped region 712c, such as an n-type semiconductor dopant, so that the channel structure 712 can be electrically connected to the bit line BL. In some embodiments, the channel structure 712 may be an epitaxial growth layer, such as a single crystal or polycrystalline silicon layer formed by an epitaxial growth process or any combination thereof, and may be an undoped or slightly P-type doped epitaxial growth layer.

[0144] The oxide layer 732 ′ is located between the first conductive layer 730 and the channel structure 712 , and between the top conductive layer CL7 and the channel structure 712 .

[0145] The storage layer 762 is located between the second conductive layer 772 and the channel structure 712. For example, a portion of the storage layer 762 extends along the normal direction of the upper surface 710a of the substrate 710 (for example, the Z-axis direction), and a portion of the storage layer 762 extends along a direction parallel to the upper surface 710a of the substrate 710. The storage layer 762 may be composed of a composite layer including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. For example, the storage layer 762 may include a tunneling layer, a capture layer, and a barrier layer. The tunneling layer may include silicon dioxide (SiO2), a double-layer structure formed by silicon dioxide (SiO2) / silicon oxynitride (SiON), or other suitable materials. The capture layer may include silicon nitride, polysilicon, or other suitable materials. The barrier layer may include silicon dioxide (SiO2) or other suitable materials.

[0146] The isolation structure 774 may pass through the stacked structure S7 to separate the stacked structure S7 into a plurality of sub-stacks. The isolation structure 774 may be formed of an insulating material, such as an oxide or other suitable material. The second conductive layers 772 in adjacent sub-stacks may be physically and electrically isolated by the isolation structure 774, so that the second conductive layers 772 in different sub-stacks may be operated independently, for example, by applying different voltages.

[0147] The conductive connection structure 776 may pass through the stacked structure S7 and be electrically connected to the substrate 710 through the doped region 718. The doped region 718 is doped with an n-type semiconductor dopant, for example. The conductive connection structure 776 may be electrically connected to a common source line.

[0148] In some embodiments, each overlap position between the first conductive layer 730 and the oxide layer 732' can form a transistor T7, each overlap position between the top conductive layer CL7 and the oxide layer 732' can form a transistor TS7, and each overlap position between the second conductive layer 772 and the memory layer 762 can form a memory cell M7. The transistor T7, the transistor TS7 and the memory cell M7 are connected in series through the channel structure 712, and can form a unit cell UN7, which can also be called a memory cell series. The first conductive layer 730 can be used as a ground selection line, the second conductive layer 772 can be used as a word line, and the top conductive layer CL7 can be used as a series selection line.

[0149] FIG. 2A to FIG. 2N FIG. 1 is a cross-sectional view showing a method for forming a memory device 100 according to an embodiment of the present invention.

[0150] Please refer to Figure 2A , providing a substrate 110, and forming a stacked body S1' on the upper surface 110a of the substrate 110, the stacked body S1' includes a first insulating layer 122, a first conductive layer 130, a second insulating layer 124, an upper sacrificial layer 140 and a third insulating layer 126 stacked in sequence (for example, through a deposition process) on the upper surface 110a of the substrate 110.

[0151] In some embodiments, the substrate 110 may be a silicon substrate or other suitable substrate. The first insulating layer 122, the second insulating layer 124 and the third insulating layer 126 may be formed of an oxide, such as silicon dioxide. The first conductive layer 130 may be formed of a conductive material, such as tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), doped or undoped polysilicon (poly-silicon) or other suitable materials. In some embodiments, the first conductive layer 130 may be an n-type doped polysilicon layer. The upper sacrificial layer 140 may be formed of silicon nitride (SiN).

[0152] Please refer to Figure 2B , forming a plurality of first openings 152, each of which passes through the stack body S1' to expose a portion of the substrate 110 to the outside. In some embodiments, the first openings 152 may be formed by an etching method, such as a dry etching method. In some embodiments, the substrate 110 may be overetched so that the bottom of the first opening 152 is lower than the upper surface 110a of the substrate 110.

[0153] Please refer to Figure 2C , through an oxidation process, a portion of an oxide layer 132' is formed on a side surface of the first conductive layer 130 exposed by the first opening 152, and a portion of an oxide layer 132' is formed on a surface of the substrate 110 exposed by the first opening 152. In some embodiments, the first conductive layer 130 is an n-type doped polysilicon layer, and the substrate 110 is a silicon substrate. Through the oxidation process and high temperature, an oxide layer 132' including silicon dioxide is formed on the side surface of the first conductive layer 130 exposed by the first opening 152, and an oxide layer 132' including a silicon dioxide layer is formed on the surface of the substrate 110 exposed by the first opening 152.

[0154] Please refer to Figure 2D, remove the excess oxide layer 132' in the first opening 152, form a thermal oxide layer 132 directly contacting the first conductive layer 130, and expose the substrate 110. In some embodiments, the excess oxide layer 132' in the first opening 152 is removed by immersing in a solvent, such as hydrofluoric acid (HF). Since the thermal oxide layer 132 is an oxide layer formed by directly oxidizing the conductive layer (such as the first conductive layer 130) rather than an oxide layer formed by a deposition process (such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or other deposition processes), the purity of the oxide of the thermal oxide layer 132 is greater than the purity of the oxide of the insulating layer (such as the first insulating layer 122, the second insulating layer 124 or the third insulating layer 126) formed by the deposition method.

[0155] Please refer to Figure 2E The lower portion 112a of the channel structure covering the thermal oxide layer 132 is formed by a first epitaxial growth process, and the thermal oxide layer 132 is located between the first conductive layer 130 and the lower portion 112a of the channel structure. That is, the lower portion 112a of the channel structure is an epitaxial growth layer of silicon. The height of the top surface of the lower portion 112a of the channel structure is greater than the height of the top surface of the first conductive layer 130.

[0156] Thereafter, P-type dopants are implanted into the lower portion 112a of the channel structure by ion implantation. The P-type dopants are helpful in adjusting the threshold voltage.

[0157] Please refer to Figure 2F , forming a storage layer 162 covering a portion of the sidewall of the first opening 152 and the lower portion 112a of the channel structure. The storage layer 162 may be composed of a composite layer (i.e., an ONO layer) including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. For example, the storage layer 162 may include a tunneling layer, a capture layer, and a barrier layer. The tunneling layer may include silicon dioxide (SiO2), a double-layer structure formed by silicon dioxide (SiO2) / silicon oxynitride (SiON), or other suitable materials. The capture layer may include silicon nitride, polysilicon, or other suitable materials. The barrier layer may include silicon dioxide (SiO2) or other suitable materials.

[0158] Next, a protective layer 164 is formed on the memory layer 162 through a deposition process. The protective layer 164 can prevent the memory layer 162 from being damaged in subsequent processes. The protective layer 164 is, for example, silicon nitride, polysilicon or other suitable materials.

[0159] Please refer to Figure 2G, a portion of the storage layer 162 and the protection layer 164 is removed by an etching process to expose the lower portion 112a of the channel structure. The etching process may be a dry etching process or a wet etching process.

[0160] Please refer to Figure 2H The protective layer 164 is removed by soaking in a solvent, so that the storage layer 162 is exposed. The solvent is, for example, hot phosphoric acid (H3PO4), but the present invention is not limited thereto, as long as the solvent can remove the protective layer 164 but will not damage the storage layer 162.

[0161] Please refer to Fig.2I , an upper portion 112b of the channel structure is formed by a second epitaxial growth process, thereby forming a channel structure 112 including a lower portion 112a and an upper portion 112b. In this embodiment, the channel structure 112 is an epitaxial growth layer of silicon.

[0162] Thereafter, an ion implantation is performed to form a doped region 112c on the top of the channel structure 112. The doped region 112c is, for example, a heavily doped region of an n-type semiconductor. The doped region 112c can be used to form a contact structure in a subsequent process to be electrically connected to the bit line.

[0163] Please refer to Figure 2J , a covering layer 128 covering the stacked body S1 ′ is formed by a deposition process, that is, the covering layer 128 covers the third insulating layer 126 and the channel structure 112 .

[0164] Thereafter, a second opening 154 is formed through the stack body S1' by an etching process. The etching process is, for example, a dry etching process. Thereafter, a doped region 118 may be formed on the substrate 110 corresponding to the second opening 154 by ion implantation. The doped region 118 may include, for example, a heavily doped n-type semiconductor. Alternatively, the step of forming the doped region 118 may be performed after removing the upper sacrificial layer 140.

[0165] Please refer to Figure 2K The upper sacrificial layer 140 is removed from the second opening 154 by an etching process to form an upper opening 156 at the position where the upper sacrificial layer 140 is removed. The etching process may be an isotropic etching (e.g., a wet etching method) and may be a highly selective etching, such as selectively etching silicon nitride without etching silicon dioxide and polysilicon.

[0166] Next, a dielectric material 166 is formed by a deposition process to extend along the sidewalls of the second opening 154 and the upper opening 156 and cover the capping layer 128. In some embodiments, the dielectric material 166 may include a high-k material, such as aluminum oxide (Al2O3) or other suitable materials. The dielectric material 166 may also serve as a barrier layer to prevent lateral diffusion of charges.

[0167] Please refer to Figure 2L , a conductive material 172' is filled into the second opening 154 and the upper opening 156 by a deposition process. The conductive material 172' may include tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN) or other suitable materials.

[0168] Please refer to Figure 2M , the conductive material 172' located in the second opening 154 is removed by an etching process to form a second conductive layer 172 located in the upper opening 156. This etching process is, for example, a dry etching process. In some embodiments, the etching process can also remove a portion of the conductive material located in the upper opening 156. The second conductive layer 172 may include tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN) or other suitable conductive materials. In this embodiment, the second conductive layer 172 includes tungsten (W). Thus, a stacked structure S1 including the first insulating layer 122, the first conductive layer 130, the second insulating layer 124, the second conductive layer 172 and the third insulating layer 126 is formed.

[0169] Please refer to Figure 2N , an insulating material is filled into the second opening 154 through a deposition process to form a plurality of isolation structures 174. The isolation structures 174 may include oxide or other suitable insulating materials.

[0170] After this, please refer back to Figure 1B , forming a plurality of vertical openings that pass through the isolation structure 174 and extend along the normal direction of the upper surface 110a of the substrate 110, and then filling a conductive material in these vertical openings through a deposition process to form a plurality of conductive connection structures 176. The conductive connection structure 176 may include tungsten (W), aluminum (Al), titanium nitride (TiN) or other suitable conductive materials. In this way, a plurality of conductive connection structures 176 are formed. Figure 1B A memory element 100 is shown.

[0171] FIG. 3A to FIG. 3M FIG. 2 is a cross-sectional view showing a method for forming a memory device 200 according to an embodiment of the present invention.

[0172] Please refer to Figure 3A, providing a substrate 210, and forming a stacked body S2' on the upper surface 210a of the substrate 210, the stacked body S2' including a first insulating layer 222, a first conductive layer 230, a second insulating layer 224, an upper sacrificial layer 240 and a third insulating layer 226 stacked in sequence (for example, through a deposition process) on the upper surface 210a of the substrate 210.

[0173] In some embodiments, the substrate 202 may be a silicon substrate or other suitable substrate. The first insulating layer 222, the second insulating layer 224 and the third insulating layer 226 may be formed of an oxide, such as silicon dioxide. The first conductive layer 230 may be formed of a conductive material, such as tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), doped or undoped polysilicon (poly-silicon) or other suitable materials. In some embodiments, the first conductive layer 230 may be an n-type doped polysilicon layer. The upper sacrificial layer 240 may be formed of silicon nitride (SiN).

[0174] Please refer to Figure 3B , forming a plurality of first openings 252, each of which passes through the stack body S2' to expose a portion of the substrate 210 to the outside. In some embodiments, the first openings 252 may be formed by an etching method, such as a dry etching method. In some embodiments, the substrate 210 may be overetched so that the bottom of the first opening 252 is lower than the upper surface 210a of the substrate 210.

[0175] Please refer to Figure 3C , a dopant 211 is implanted into the substrate 210 corresponding to the first opening 252 by ion implantation. The dopant 211 is, for example, a P-type dopant. The dopant 211 helps to adjust the threshold voltage.

[0176] Please refer to Figure 3D , through an oxidation process, a portion of the oxide layer 232' is formed on the side surface of the first conductive layer 230 exposed by the first opening 252, and a portion of the surface of the substrate 210 exposed by the first opening 252 is formed into an oxide layer 232'. In some embodiments, the first conductive layer 230 is an n-type doped polysilicon layer, and the substrate 210 is a silicon substrate. Through the oxidation process and high temperature, the side surface of the first conductive layer 230 exposed by the first opening 252 is formed into an oxide layer 232' including silicon dioxide, and the surface of the substrate 210 exposed by the first opening 252 is formed into an oxide layer 232' including silicon dioxide.

[0177] Please refer to Figure 3E, remove the excess oxide layer 232' in the first opening 252, form a thermal oxide layer 232 directly contacting the first conductive layer 230, and expose the substrate 210. In some embodiments, the excess oxide layer 232' in the first opening 252 is removed by immersing in a solvent, such as hydrofluoric acid (HF). Since the thermal oxide layer 232 is an oxide layer formed by directly oxidizing the conductive layer (such as the first conductive layer 230) rather than an oxide layer formed by a deposition process (such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or other deposition processes), the purity of the oxide of the thermal oxide layer 232 is greater than the purity of the oxide of the insulating layer (such as the first insulating layer 222, the second insulating layer 224 or the third insulating layer 226) formed by the deposition method.

[0178] Please refer to Figure 3F , the lower portion 212a and the upper portion 212b of the channel structure 212 are formed by the same first epitaxial growth process. The lower portion 212a of the channel structure 212 corresponds to the first conductive layer 230. The upper portion 212b of the channel structure 212 corresponds to the upper sacrificial layer 240. The lower portion 212a of the channel structure 212 is covered with a thermal oxide layer 232, and the thermal oxide layer 232 is located between the first conductive layer 230 and the lower portion 212a of the channel structure 212. In this embodiment, the entire channel structure 212 is an epitaxial growth layer of silicon.

[0179] Thereafter, an ion implantation is performed to form a doped region 212c on the top surface of the channel structure 212. The doped region 212c is, for example, a heavily doped region of an n-type semiconductor. The doped region 212c can be used to form a contact structure in a subsequent process to be electrically connected to a bit line.

[0180] Please refer to Figure 3G A covering layer 228 covering the stacked body S2' is formed by a deposition process, that is, the covering layer 228 covers the third insulating layer 226 and the channel structure 212. In this embodiment, the dopant 211 can be diffused into the lower portion 212a of the channel layer 212 by a thermal process. The thermal process can activate the dopant 211.

[0181] Please refer to Figure 3H , a second opening 254 is formed through the stack body S2' by an etching process. The etching process is, for example, a dry etching process. Afterwards, a doped region 218 can be formed on the substrate 210 through the second opening 254. The doped region 218 is, for example, a heavily doped n-type semiconductor. Alternatively, the step of forming the doped region 218 can be performed after removing the upper sacrificial layer 240.

[0182] Please refer to Fig. 3IThe upper sacrificial layer 240 is removed from the second opening 254 by an etching process to form an upper opening 256 at the position where the upper sacrificial layer 240 is removed. The etching process may be an isotropic etching (e.g., a wet etching method), and may be a highly selective etching, such as selectively etching silicon nitride (SiN) without etching silicon dioxide (SiO2).

[0183] Next, a storage layer 262 and a dielectric material 266 are sequentially formed by a deposition process, which extend along the sidewalls of the second opening 254, the sidewalls of the upper opening 256, and part of the sidewalls of the channel structure 212 and cover the capping layer 128. The storage layer 262 may be composed of a composite layer (i.e., an ONO layer) including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. For example, the storage layer 162 may include a tunneling layer, a capture layer, and a barrier layer. The tunneling layer may include silicon dioxide (SiO2), a double-layer structure formed by silicon dioxide (SiO2) / silicon oxynitride (SiON), or other suitable materials. The capture layer may include silicon nitride, polysilicon, or other suitable materials. The barrier layer may include silicon dioxide (SiO2) or other suitable materials. In some embodiments, the dielectric material 266 may include a high dielectric constant material (high k material), such as aluminum oxide (Al2O3) or other suitable materials. The dielectric material 166 may also serve as a barrier layer to prevent lateral diffusion of charges.

[0184] Please refer to Figure 3J The conductive material 272' is filled into the second opening 254 and the upper opening 256 by a deposition process. The conductive material 272' may include tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN) or other suitable materials.

[0185] Please refer to Figure 3K , the conductive material 272' located in the second opening 254 is removed by an etching process to form a second conductive layer 272 located in the upper opening 256. This etching process is, for example, a dry etching process. In some embodiments, the etching process can also remove a portion of the conductive material located in the upper opening 256. The second conductive layer 272 may include tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN) or other suitable conductive materials. In this embodiment, the second conductive layer 272 includes tungsten (W). Thus, a stacked structure S2 including the first insulating layer 222, the first conductive layer 230, the second insulating layer 224, the second conductive layer 272 and the third insulating layer 226 is formed.

[0186] Please refer to Figure 3L, an insulating material is filled into the second opening 254 through a deposition process to form a plurality of isolation structures 274. The isolation structures 274 may include oxide or other suitable insulating materials.

[0187] Please refer to Figure 3M , forming a plurality of vertical openings 259 that pass through the isolation structure 274 and extend along a normal direction of the upper surface 210 a of the substrate 210 .

[0188] After this, please refer back to Figure 1C , a conductive material is filled into the vertical openings 259 by a deposition process to form a plurality of conductive connection structures 276. The conductive connection structures 276 may include tungsten (W), aluminum (Al), titanium nitride (TiN) or other suitable conductive materials. In this way, a conductive structure 276 is formed. Figure 1C Memory element 200 is shown.

[0189] FIG. 4A to FIG. 4L FIG. 1 is a cross-sectional view showing a method for forming a memory device 300 according to an embodiment of the present invention.

[0190] Please refer to Figure 4A , providing a substrate 310, and forming a stacked body S3' on the upper surface 310a of the substrate 310, the stacked body S3' includes a first insulating layer 322, a lower sacrificial layer 342, a second insulating layer 324, an upper sacrificial layer 340 and a third insulating layer 326 stacked in sequence (for example, through a deposition process) on the upper surface 310a of the substrate 310.

[0191] In some embodiments, the substrate 310 may be a silicon substrate or other suitable substrate. The first insulating layer 322, the second insulating layer 324 and the third insulating layer 326 may be formed of oxide, such as silicon dioxide. The lower sacrificial layer 342 and the upper sacrificial layer 340 may be formed of silicon nitride (SiN).

[0192] Please refer to Figure 4B , forming a plurality of first openings 352, each of which passes through the stack body S3' to expose a portion of the substrate 310 to the outside. In some embodiments, the first openings 352 may be formed by an etching process, such as a dry etching process. In some embodiments, the substrate 310 may be overetched so that the bottom of the first opening 352 is lower than the upper surface 310a of the substrate 310.

[0193] Please refer to Figure 4C The lower portion 312a of the channel structure is formed by a first epitaxial growth process. That is, the lower portion 312a of the channel structure is an epitaxial growth layer of silicon. The height of the top surface of the lower portion 312a of the channel structure is greater than the height of the top surface of the lower sacrificial layer 342.

[0194] Thereafter, P-type dopants are implanted into the lower portion 312a of the channel structure by an ion implantation process. The P-type dopants are helpful in adjusting the threshold voltage.

[0195] Please refer to Figure 4D , forming a storage layer 362 covering a portion of the sidewall of the first opening 352 and the lower portion 312a of the channel structure. The storage layer 362 may be composed of a composite layer (i.e., an ONO layer) including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. For example, the storage layer 362 may include a tunneling layer, a capture layer, and a barrier layer. The tunneling layer may include silicon dioxide (SiO2), a double-layer structure formed by silicon dioxide (SiO2) / silicon oxynitride (SiON), or other suitable materials. The capture layer may include silicon nitride, polysilicon, or other suitable materials. The barrier layer may include silicon dioxide (SiO2) or other suitable materials.

[0196] Next, a protective layer 364 is formed on the memory layer 362 by deposition. The protective layer 364 can prevent the memory layer 362 from being damaged in subsequent processes. The protective layer 364 is, for example, silicon nitride, polysilicon or other suitable materials.

[0197] Please refer to Figure 4E , a portion of the storage layer 362 and the protection layer 364 is removed by an etching process to expose the lower portion 312a of the channel structure. The etching process may be a dry etching process or a wet etching process.

[0198] Please refer to Figure 4F , the protective layer 364 is removed by soaking in a solvent, so that the storage layer 362 is exposed. The solvent is, for example, hot phosphoric acid (H3PO4), but the present invention is not limited thereto, as long as the solvent can remove the protective layer 364 but will not damage the storage layer 362.

[0199] Please refer to Figure 4G , an upper portion 312b of the channel structure is formed by a second epitaxial growth process, thereby forming a channel structure 312 including a lower portion 312a and an upper portion 312b. In this embodiment, the channel structure 312 is an epitaxial growth layer of silicon.

[0200] Thereafter, an ion implantation is performed to form a doped region 312c on the top of the channel structure 312. The doped region 312c is, for example, a heavily doped region of an n-type semiconductor. The doped region 312c can be used to form a contact structure in a subsequent process to be electrically connected to the bit line.

[0201] Next, a covering layer 328 covering the stacked body S3 ′ is formed by a deposition process. That is, the covering layer 328 covers the third insulating layer 326 and the channel structure 312 .

[0202] Please refer to Figure 4H , a second opening 354 is formed through the stack body S3' by an etching process. The etching process is, for example, a dry etching process. Afterwards, a doped region 318 may be formed on the substrate 310 corresponding to the second opening 354 by ion implantation. The doped region 318 may include, for example, a heavily doped n-type semiconductor. Alternatively, the step of forming the doped region 318 may be performed after removing the upper sacrificial layer 340 and the lower sacrificial layer 342.

[0203] Please refer to Fig. 4I The upper sacrificial layer 340 and the lower sacrificial layer 342 are removed from the second opening 354 by an etching process to form an upper opening 356 and a lower opening 358 at the positions where the upper sacrificial layer 340 and the lower sacrificial layer 342 are removed, respectively. The etching process may be an isotropic etching (e.g., a wet etching method) and may be a highly selective etching, such as selectively etching silicon nitride without etching silicon dioxide.

[0204] Next, a thermal oxide layer 332 is formed on one side surface of the channel structure 312 exposed by the lower opening 358 through an oxidation process. In some embodiments, the channel structure 312 is an epitaxial growth layer of silicon. Through the oxidation process and high temperature, the thermal oxide layer 332 including silicon dioxide is formed on the side surface of the channel structure 312 exposed by the lower opening 358.

[0205] Thereafter, a dielectric material 366 is formed by a deposition process to extend along the sidewalls of the second opening 354, the lower opening 358, and the upper opening 356 and cover the capping layer 328. In some embodiments, the dielectric material 366 may include a high-k material, such as aluminum oxide (Al2O3) or other suitable materials. The dielectric material 366 may also serve as a barrier layer to prevent lateral diffusion of charges.

[0206] Please refer to Figure 4J The conductive material 372' is filled into the second opening 354, the lower opening 358 and the upper opening 356 by a deposition process. The conductive material 372' may include tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN) or other suitable materials.

[0207] Please refer to Figure 4K, the conductive material 372' in the second opening 354 is removed by an etching process to form a first conductive layer 330 in the lower opening 358 and a second conductive layer 372 in the upper opening 356. This etching process is, for example, a dry etching process. In some embodiments, the etching process can remove a portion of the conductive material 372' in the upper opening 356 and the lower opening 358 at the same time. The first conductive layer 330 and the second conductive layer 372 can respectively include tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN) or other suitable conductive materials. In this embodiment, the first conductive layer 330 and the second conductive layer 372 can include the same conductive material, such as tungsten (W). Thereby, a stacked structure S3 including the first insulating layer 322, the first conductive layer 330, the second insulating layer 324, the second conductive layer 372 and the third insulating layer 326 is formed.

[0208] Please refer to Figure 4L , an insulating material is filled into the second opening 354 through a deposition process to form a plurality of isolation structures 374. The isolation structures 374 may include oxide or other suitable insulating materials.

[0209] After this, please refer back to Figure 1D , forming a plurality of vertical openings that pass through the isolation structure 374 and extend along the normal direction of the upper surface 310a of the substrate 310, and then filling a conductive material in these vertical openings through a deposition process to form a plurality of conductive connection structures 376. The conductive connection structures 376 may include tungsten (W), aluminum (Al), titanium nitride (TiN) or other suitable conductive materials. In this way, a plurality of conductive connection structures 376 are formed. Figure 1D Memory element 300 is shown.

[0210] Figure 5 An equivalent circuit diagram of a memory device 100 , 200 or 300 according to an embodiment of the present invention is shown.

[0211] The memory element 100, 200 or 300 may be a three-dimensional NOR type memory element. In the array area of ​​the memory element 100, 200 or 300, three word lines WL0, WL1, WL2, three bit lines BL0, BL1, BL2 and three ground selection lines GSL0, GSL1, GSL2 are exemplarily depicted. However, the present invention is not limited thereto, and the number of word lines, bit lines and ground selection lines may be greater than 3, respectively. The overlapping position of each word line and the channel structure forms a memory cell M, and the overlapping position of each ground selection line and the channel structure forms a transistor T. The memory cell M is located above the transistor T, and the channel structure connects the memory cell M and the transistor T in series. A memory cell M and a transistor T may together form a unit memory cell UN. Each transistor T is electrically connected to a common source line CSL. The word lines (e.g., WL0, WL1, WL2) may be electrically isolated by an isolation structure.

[0212] Fig. 6A FIG. 4 is an equivalent circuit diagram of a memory device that performs a programming operation by Fowler-Nordheim injection according to an embodiment of the present invention.

[0213] Please refer to Fig. 6A , to store the target unit UN t During programming operation, word line WL0 and ground selection line GSL0 are selected, a programming voltage Vpgm1 is applied to word line WL0, and 0V is applied to ground selection line GSL0. Word line WL1 and ground selection line GSL1 are not selected, and 0V is applied. A common source voltage V CSL 0V is applied to the bit line BL0. The inhibit voltage V is applied to the bit line BL1. inhibit The memory cell coupled to the bit line BL1 is inhibited.

[0214] Figure 6B FIG. 4 is an equivalent circuit diagram of a memory device that performs programming operation by channel-hot-electron injection according to an embodiment of the present invention.

[0215] Please refer to Figure 6B , to store the target unit UN tDuring the programming operation, the word line WL0 and the ground selection line GSL0 are selected. The word line WL0 is applied with a programming voltage Vpgm1, and the ground selection line GSL0 is applied with a programming voltage Vpgm2. The word line WL1 and the ground selection line GSL1 are not selected, and 0 volt (V) is applied. The common source line CSL is applied with 0V. The bit line BL0 is applied with a drain programming voltage Vdpgm. The bit line BL1 is applied with 0V. The programming voltage Vpgm2 may be less than the programming voltage Vpgm1. In some embodiments, the programming voltage Vpgm1 may be 5 to 10V. The drain programming voltage Vdpgm may be 4 to 10V.

[0216] Fig. 7A FIG. 4 is an equivalent circuit diagram of a memory device that performs an erase operation by Fowler-Nordheim injection according to an embodiment of the present invention.

[0217] Please refer to Fig. 7A , to store the target unit UN t (For example, including 2 memory cells and 2 transistors) to perform an erase operation, word line WL0 and ground selection line GSL0 are selected. 0V is applied to word line WL0. The ground selection line GSL0 applies an erase voltage Vers2. Word line WL1 and ground selection line GSL1 are not selected, both are floating (i.e., no voltage is applied). A common source voltage V is applied to the common source line. CSL A P-type well voltage V is applied to the P-type well (p well) PWI The peripheral circuit applies an erase voltage Vers1. The bit lines BL0 and BL1 are floating. The common source voltage V CSL It can be the same as the erase voltage Vers1 and the P-type well voltage V PWI .

[0218] Figure 7B FIG. 4 is an equivalent circuit diagram of a memory device that performs an erase operation by band-to-band tunneling induced hot hole injection according to an embodiment of the present invention.

[0219] Please refer to Figure 7B , to store the target unit UN t During the erase operation, the word line WL0 and the ground selection line GSL0 are selected. 0V is applied to the ground selection line GSL0. A ground erase voltage Vgers is applied to the word line WL0. The ground erase voltage Vgers may be less than 0. The word line WL1 and the ground selection line GSL1 are not selected and 0 volt (V) is applied. A drain erase voltage Vders may be applied to the bit line BL0. The drain erase voltage Vders may be greater than 0. 0V may be applied to the bit line BL1. A common source voltage V CSLA Fowler-Nordheim erase is applied using a BL bias (erase / inhibit) (+Vders for erase, 0V for non-inhibit) to perform a bit line replacement erase operation (all GSLs (eg, GSL0, GSL1, ...) = 0V, CSL = +Vcsl).

[0220] Figure 8 FIG. 4 is an equivalent circuit diagram of a memory element for a read operation according to an embodiment of the present invention.

[0221] Please refer to Figure 8 , to store the target unit UN t (For example, including 2 memory cells and 2 transistors) to perform a read operation, the word line WL0 and the ground selection line GSL0 are selected. The word line WL0 can be applied with 0V. The ground selection line GSL0 can be applied with a power supply voltage V CC The word line WL1 and the ground selection line GSL1 are unselected and applied with 0 volt (V). The bit lines BL0 and BL1 can apply a bit line read voltage Vblr. The common source line applies a common source voltage V CSL When performing a read operation in the memory element of the present invention, all voltages applied to the bit line, word line, and ground selection line may be equal to or less than the power supply voltage V CC , so it can reduce power consumption.

[0222] FIG. 9A to FIG. 9R FIG. 4 is a cross-sectional view showing a method for forming a memory device 400 according to an embodiment of the present invention.

[0223] Please refer to Fig.9A , a substrate 410 is provided, and a stacked body S4' is formed on the upper surface 410a of the substrate 410, the stacked body S4' includes a lower sacrificial layer 442, a second insulating layer 424, an upper sacrificial layer 440, a third insulating layer 426, a top sacrificial layer SF4 and a top insulating layer OL4 stacked in sequence (for example, through a deposition process) on the upper surface 410a of the substrate 410.

[0224] In some embodiments, the substrate 410 may be a silicon substrate or other suitable substrate. The second insulating layer 424, the third insulating layer 426 and the top insulating layer OL4 may be formed of oxide, such as silicon dioxide. The lower sacrificial layer 442, the upper sacrificial layer 440 and the top sacrificial layer SF4 may be formed of silicon nitride (SiN).

[0225] Please refer to Fig. 9B, forming a plurality of first openings 452, each of which passes through the stack body S4' to expose a portion of the substrate 410 to the outside. In some embodiments, the first openings 452 may be formed by an etching process, such as a dry etching process. In some embodiments, the substrate 410 may be overetched so that the bottom of the first opening 452 is lower than the upper surface 410a of the substrate 410.

[0226] Please refer to Fig. 9C , the channel structure 412 is formed by the same first epitaxial growth process. That is, in this embodiment, the entire channel structure 412 (including the lower part and the upper part) is an epitaxial growth layer of silicon.

[0227] Please refer to Fig.9D , a plurality of first trenches SLT1 are formed through the top sacrificial layer SF4 and the top insulating layer OL4 by an etching process.

[0228] Please refer to Fig.9E , the top sacrificial layer SF4 is removed through the first channel SLT1. The space where the top sacrificial layer SF4 is removed forms a top opening 460. Then, a thermal oxide layer GO4 is formed on one side surface of the upper portion of the exposed channel structure 412 through an oxidation process. In some embodiments, the channel structure 412 is a P-type doped polysilicon epitaxial growth layer. Through the oxidation process and high temperature, the side surface of the exposed channel structure 412 forms a thermal oxide layer GO4 including silicon dioxide.

[0229] Please refer to Fig.9F A conductive material CL4' is deposited in the top opening 460 and the first trench SLT1 by a deposition process. The conductive material CL4' may include tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), doped or undoped polysilicon (poly-silicon) or other suitable materials.

[0230] Please refer to Figure 9G , a portion of the conductive material CL4 ′ is removed through an etching process to form a top opening P1 , and a top conductive layer CL4 is formed between the third insulating layer 426 and the top insulating layer OL4 .

[0231] Please refer to Figure 9H , an insulating material is filled in the top opening P1 through a deposition process.

[0232] Please refer to Fig.9I, through an etching process, a second channel SLT2 is formed through the top insulating layer OL4 and the third insulating layer 426, and then the upper sacrificial layer 440 is removed to form an upper opening 456. Thereafter, through a deposition process, a storage layer 462 extending along the second channel SLT2 and the upper opening 456 is formed, and the storage layer 462 may be composed of a composite layer (i.e., AONO layer) including aluminum oxide (Al2O3, aluminum oxide), silicon oxide (silicon oxide) layer, silicon nitride (silicon nitride) layer and silicon oxide layer.

[0233] Please refer to Figure 9J , a conductive material 472 ′ is deposited on the memory layer 462 through a deposition process. The conductive material 472 ′ may include tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN) or other suitable conductive materials. That is, the conductive material 472 ′ fills the second trench SLT2 and the upper opening 456 .

[0234] Please refer to Figure 9K , a portion of the conductive material 472 ′ and the storage layer 462 are removed by an etching process to form a third channel SLT3 , and the second conductive layer 472 and the storage layer 462 are retained between the second insulating layer 424 and the third insulating layer 426 .

[0235] Please refer to Figure 9L , an insulating material is filled in the third trench SLT3 through a deposition process.

[0236] Please refer to Figure 9M , a second opening 454 is formed through the lower sacrificial layer 442, the second insulating layer 424, the third insulating layer 426 and the top insulating layer OL4 by an etching process. Thereafter, the lower sacrificial layer 442 is removed from the second opening 454 by an etching process, and a lower opening 458 is formed at the position where the lower sacrificial layer 442 is removed.

[0237] Please refer to Figure 9N A thermal oxide layer 432 is formed on one side of the channel structure 412 exposed by the lower opening 458 through an oxidation process, and a first insulating layer 422 is formed on the upper surface of the substrate 410 exposed. For example, the thermal oxide layer 432 and the first insulating layer 422 may include silicon dioxide, respectively.

[0238] Please refer to Fig.9O , a conductive material 430' is filled into the second opening 454 and the lower opening 458 by a deposition process. The conductive material 430' may include polysilicon or other suitable materials.

[0239] Please refer to Figure 9P, the conductive material 430' in the second opening 454 is removed by an etching process to form a first conductive layer 430 in the lower opening 458. In some embodiments, the etching process may also remove a portion of the conductive material in the lower opening 458. The first conductive layer 2430 may include polysilicon or other suitable conductive materials. Thus, a stacked structure S4 including a first insulating layer 422, a first conductive layer 430, a second insulating layer 424, a second conductive layer 472, a third insulating layer 426, a top conductive layer CL4 and a top insulating layer OL4 is formed. In some embodiments, doped regions 412c and 418 may be formed on the top of the channel structure 412 and the surface of the substrate 410 exposed to the second opening 454 by an ion implantation, and the doped regions 412c and 418 are, for example, heavily doped regions of an n-type semiconductor. Doping 412c and 418 may be used to form contact structures in subsequent processes to be electrically connected to the bit line and the common source line, respectively.

[0240] Please refer to Figure 9Q , an insulating material is filled into the second opening 454 through a deposition process to form a plurality of isolation structures 474. The isolation structures 474 may include oxide or other suitable insulating materials.

[0241] Please refer to Figure 9R , forming a plurality of vertical openings 459 that pass through the isolation structure 474 and extend along a normal direction of the upper surface 410 a of the substrate 410 .

[0242] After this, please refer back to Figure 1E , a conductive material is filled into the vertical openings 459 by a deposition process to form a plurality of conductive connection structures 476. The conductive connection structures 476 may include tungsten (W), aluminum (Al), titanium nitride (TiN) or other suitable conductive materials. In this way, a conductive structure 476 is formed. Figure 1E Memory element 400 is shown.

[0243] FIG. 10A to FIG. 10K FIG. 5 is a cross-sectional view showing a method for forming a memory device 500 according to an embodiment of the present invention.

[0244] Please refer to Fig. 10A , a substrate 510 is provided, and a stacked body S5' is formed on the upper surface 510a of the substrate 510, the stacked body S5' includes a first insulating layer 522, a first conductive layer 530, a second insulating layer 524, an upper sacrificial layer 540, a third insulating layer 526, a top conductive layer CL5 and a top insulating layer OL5 stacked in sequence (for example, through a deposition process) on the upper surface 510a of the substrate 510.

[0245] In some embodiments, the substrate 510 may be a silicon substrate or other suitable substrates. A first insulating layer 522, a second insulating layer 524, a third insulating layer 526 and a top insulating layer OL5 may be formed of oxide, such as silicon dioxide. The upper sacrificial layer 540 may be formed of silicon nitride (SiN).

[0246] Please refer to Fig. 10B , forming a plurality of first openings 552, each of which passes through the stack body S5' to expose a portion of the substrate 510 to the outside. In some embodiments, the first openings 552 may be formed by an etching process, such as a dry etching process. In some embodiments, the substrate 510 may be overetched so that the bottom of the first opening 552 is lower than the upper surface 510a of the substrate 510.

[0247] Please refer to Fig. 10C , through an oxidation process, a portion of an oxide layer 532' is formed on a side surface of the first conductive layer 530 exposed by the first opening 552, and a portion of an oxide layer 532' is formed on a surface of the substrate 510 exposed by the first opening 552, and an oxide layer GO5 is formed on a side surface of the top conductive layer CL5. In some embodiments, the first conductive layer 530 and the top conductive layer CL5 are respectively n-type doped polysilicon layers, and the substrate 510 is a silicon substrate. Through the oxidation process and high temperature, an oxide layer 532' including silicon dioxide is formed on the side surface of the first conductive layer 530 exposed by the first opening 552, and an oxide layer 532' including a silicon dioxide layer is formed on the surface of the substrate 510 exposed by the first opening 552.

[0248] Please refer to Fig. 10D , remove the excess oxide layer 532' in the first opening 552, form a thermal oxide layer 532 directly contacting the first conductive layer 530, and expose the substrate 510. Since the thermal oxide layer 532 is an oxide layer formed by directly oxidizing the conductive layer (e.g., the first conductive layer 530), rather than an oxide layer formed by a deposition process (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD) or other deposition processes), the purity of the oxide of the thermal oxide layer 532 is greater than the purity of the oxide of the insulating layer (e.g., the first insulating layer 522, the second insulating layer 524 or the third insulating layer 526) formed by the deposition method. In some embodiments, a P-type dopant is implanted into the substrate 510 by an ion implantation. The P-type dopant helps to adjust the threshold voltage.

[0249] Please refer to Fig. 10EA channel structure 512 covering the thermal oxide layer 532 and GO5 is formed by a first epitaxial growth process. The thermal oxide layer 532 is located between the first conductive layer 530 and the channel structure 512 , and the thermal oxide layer GO5 is located between the top conductive layer CL5 and the channel structure 512 .

[0250] Please refer to Fig.10F , a second opening 554 is formed through the first insulating layer 522, the first conductive layer 530, the second insulating layer 524, the upper sacrificial layer 540, the third insulating layer 526, the top conductive layer CL5 and the top insulating layer OL5 by an etching process. Then, the upper sacrificial layer 540 is removed to form an upper opening 556 at the position where the upper sacrificial layer 540 is removed. Then, doped regions 512c and 518 are formed on the top of the channel structure 512 and the surface of the substrate 510 exposed to the second opening 554 by an ion implantation, and the doped regions 512c and 518 are, for example, heavily doped regions of an n-type semiconductor. The doping 512c and 518 can be used to form contact structures in subsequent processes to be electrically connected to the bit line and the common source line, respectively.

[0251] Please refer to Figure 10G , a storage layer 562 and a dielectric material 566 extending along the sidewalls of the second opening 554 and the upper opening 556 and covering the top insulating layer OL5 are sequentially formed through a deposition process. The storage layer 562 may be composed of a composite layer (i.e., an ONO layer) including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. For example, the storage layer 562 may include a tunneling layer, a capture layer, and a barrier layer. The tunneling layer may include silicon dioxide (SiO2), a double-layer structure formed by silicon dioxide (SiO2) / silicon oxynitride (SiON), or other suitable materials. The capture layer may include silicon nitride, polysilicon, or other suitable materials. The barrier layer may include silicon dioxide (SiO2) or other suitable materials. In some embodiments, the dielectric material 566 may include a high dielectric constant material (high k material), such as aluminum oxide (Al2O3) or other suitable materials. The dielectric material 566 may also serve as a barrier layer to prevent lateral diffusion of charges.

[0252] Please refer to Fig. 10H , a conductive material 572' is filled into the second opening 554 and the upper opening 556 by a deposition process. The conductive material 572' may include tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN) or other suitable materials.

[0253] Please refer to Fig.10I, the conductive material 572' located in the second opening 554 is removed by an etching process to form a second conductive layer 572 located in the upper opening 556. This etching process is, for example, a dry etching process. In some embodiments, the etching process can also remove a portion of the conductive material located in the upper opening 556. The second conductive layer 572 may include tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN) or other suitable conductive materials. In this embodiment, the second conductive layer 572 includes tungsten (W). Thus, a stacked structure S5 including a first insulating layer 522, a first conductive layer 530, a second insulating layer 524, a second conductive layer 572, a third insulating layer 526, a top conductive layer CL5 and a top insulating layer OL5 is formed.

[0254] Please refer to Fig.10J , an insulating material is filled into the second opening 554 through a deposition process to form a plurality of isolation structures 574. The isolation structures 574 may include oxide or other suitable insulating materials.

[0255] Please refer to Figure 10K , forming a plurality of vertical openings 559 that pass through the isolation structure 574 and extend along a normal direction of the upper surface 510 a of the substrate 510 .

[0256] After this, please refer back to Figure 1F , a conductive material is filled into the vertical openings 559 by a deposition process to form a plurality of conductive connection structures 576. The conductive connection structures 576 may include tungsten (W), aluminum (Al), titanium nitride (TiN) or other suitable conductive materials. In this way, a conductive structure 576 is formed. Figure 1F Memory element 500 is shown.

[0257] FIG. 11A to FIG. 11M FIG. 5 is a cross-sectional view showing a method for forming a memory device 600 according to an embodiment of the present invention.

[0258] Please refer to Fig.11A , a substrate 610 is provided, and a stacked body S6' is formed on the upper surface 610a of the substrate 610, the stacked body S6' includes a lower sacrificial layer 642, a second insulating layer 624, an upper sacrificial layer 640, a third insulating layer 626, a top sacrificial layer SF6 and a top insulating layer OL6 stacked in sequence (for example, through a deposition process) on the upper surface 610a of the substrate 610.

[0259] In some embodiments, the substrate 610 may be a silicon substrate or other suitable substrate. The second insulating layer 624, the third insulating layer 626 and the top insulating layer OL6 may be formed of oxide, such as silicon dioxide. The lower sacrificial layer 642, the upper sacrificial layer 640 and the top sacrificial SF6 may be formed of silicon nitride (SiN).

[0260] Please refer to Fig. 11B , forming a plurality of first openings 652, each of which passes through the stack body S6' to expose a portion of the substrate 610 to the outside. In some embodiments, the first openings 652 may be formed by an etching process, such as a dry etching process. In some embodiments, the substrate 610 may be overetched so that the bottom of the first opening 652 is lower than the upper surface 610a of the substrate 610.

[0261] Please refer to Fig. 11C The lower portion 612a of the channel structure is formed by a first epitaxial growth process. That is, the lower portion 612a of the channel structure is an epitaxial growth layer of silicon. The height of the top surface of the lower portion 612a of the channel structure is greater than the height of the top surface of the lower sacrificial layer 642.

[0262] Thereafter, P-type dopants are implanted into the lower portion 612a of the channel structure by an ion implantation process. The P-type dopants are helpful in adjusting the threshold voltage.

[0263] Please refer to Fig.11D , forming a storage layer 662 covering a portion of the sidewall of the first opening 652 and the lower portion 612a of the channel structure. The storage layer 662 may be composed of a composite layer (i.e., an ONO layer) including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. For example, the storage layer 662 may include a tunneling layer, a capture layer, and a barrier layer. The tunneling layer may include silicon dioxide (SiO2), a double-layer structure formed by silicon dioxide (SiO2) / silicon oxynitride (SiON), or other suitable materials. The capture layer may include silicon nitride, polysilicon, or other suitable materials. The barrier layer may include silicon dioxide (SiO2) or other suitable materials.

[0264] Next, a protective layer 664 is formed on the memory layer 662 by deposition. The protective layer 664 can prevent the memory layer 662 from being damaged in subsequent processes. The protective layer 664 is, for example, silicon nitride, polysilicon or other suitable materials.

[0265] Please refer to Fig.11E , a portion of the storage layer 662 and the protection layer 664 is removed by an etching process to expose the lower portion 612a of the channel structure. The etching process may be a dry etching process or a wet etching process.

[0266] Please refer to Fig.11F , the protective layer 664 is removed by soaking in a solvent, so that the storage layer 662 is exposed. The solvent is, for example, hot phosphoric acid (H3PO4), but the present invention is not limited thereto, as long as the solvent can remove the protective layer 664 but will not damage the storage layer 662.

[0267] Please refer to Fig.11G , an upper portion 612b' of the channel structure is formed by a second epitaxial growth process.

[0268] Please refer to Fig.11H , remove part of the upper portion 612b' and the storage layer 662, and form a vertical opening through the top insulating layer OL6, the top sacrificial layer SF6 and a portion of the third insulating layer 626. The width of this vertical opening can be greater than the width of the lower portion 612a of the channel structure. Then, the upper portion 612b of the channel structure is formed by a third epitaxial growth process.

[0269] Please refer to Fig.11I , a second opening 654 is formed through the stack body S6' by an etching process. This etching process is, for example, a dry etching process. Afterwards, a doped region 618 can be formed on the substrate 610 corresponding to the second opening 654 by ion implantation, and a doped region 612c can be formed on the top of the channel structure 612. The doped regions 612c and 618 include, for example, heavily doped n-type semiconductors. Alternatively, the steps of forming the doped regions 612c and 618 can be performed after removing the upper sacrificial layer 640 and the lower sacrificial layer 642.

[0270] Please refer to Fig.11J , the top sacrificial layer SF6, the upper sacrificial layer 640 and the lower sacrificial layer 642 are removed from the second opening 654 by an etching process, so as to form a top opening 660, an upper opening 656 and a lower opening 658 at the positions where the top sacrificial layer SF6, the upper sacrificial layer 640 and the lower sacrificial layer 642 are removed, respectively. The etching process may be an isotropic etching (e.g., a wet etching method), and may be a highly selective etching, such as selectively etching silicon nitride without etching silicon dioxide.

[0271] Next, a thermal oxide layer 632 is formed on one side surface of the channel structure 612 exposed by the lower opening 658 through an oxidation process, a first insulating layer 622 is formed on the upper surface 610a of the substrate 610 exposed by the lower opening 658, and a thermal oxide layer GO6 is formed on one side surface of the channel structure 612 exposed by the top opening 660. In some embodiments, the channel structure 612 is an epitaxial growth layer of silicon, and through the oxidation process and high temperature, the side surface of the channel structure 612 exposed by the top opening 660 and the side surface of the channel structure 612 exposed by the lower opening 658 form thermal oxide layers GO6 and 632 including silicon dioxide, respectively.

[0272] Thereafter, a dielectric material 666 is formed by a deposition process, extending along the sidewalls of the second opening 654, the lower opening 658, the upper opening 656, and the top opening 660 and covering the top insulating layer OL6. In some embodiments, the dielectric material 666 may include a high-k material, such as aluminum oxide (Al2O3) or other suitable materials. The dielectric material 666 may also serve as a barrier layer to prevent lateral diffusion of charges.

[0273] Please refer to Figure 11K The conductive material 672' is filled into the second opening 654, the top opening 660, the lower opening 658 and the upper opening 656 by a deposition process. The conductive material 672' may include tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN) or other suitable materials.

[0274] Please refer to Fig.11L , the conductive material 672' in the second opening 654 is removed by an etching process to form a first conductive layer 630 in the lower opening 658, a second conductive layer 672 in the upper opening 656, and a top conductive layer CL6 in the top opening 660. The etching process is, for example, a dry etching process. In some embodiments, the etching process may remove a portion of the conductive material 672' in the top opening 660, the upper opening 656, and the lower opening 658 at the same time. The first conductive layer 630, the second conductive layer 672, and the top conductive layer CL6 may respectively include tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN), or other suitable conductive materials. In the present embodiment, the first conductive layer 630, the second conductive layer 672, and the top conductive layer CL6 may include the same conductive material, for example, tungsten (W). Thus, a stacked structure S6 including the first insulating layer 622, the first conductive layer 630, the second insulating layer 624, the second conductive layer 672, the third insulating layer 626, the top conductive layer CL6 and the top insulating layer OL6 is formed.

[0275] Please refer to Fig.11M , an insulating material is filled into the second opening 654 through a deposition process to form a plurality of isolation structures 674. The isolation structures 674 may include oxide or other suitable insulating materials.

[0276] After this, please refer back to Figure 1G, forming a plurality of vertical openings that pass through the isolation structure 674 and extend along the normal direction of the upper surface 610a of the substrate 610, and then filling a conductive material in these vertical openings through a deposition process to form a plurality of conductive connection structures 676. The conductive connection structure 676 may include tungsten (W), aluminum (Al), titanium nitride (TiN) or other suitable conductive materials. In this way, a plurality of vertical openings that extend along the normal direction of the upper surface 610a of the substrate 610 are formed. Figure 1G Memory element 600 is shown.

[0277] FIG. 12A to FIG. 12K FIG. 7 is a cross-sectional view illustrating a method for forming a memory device 700 according to an embodiment of the present invention.

[0278] Please refer to Fig. 12A , a substrate 710 is provided, and a stacked body S7' is formed on the upper surface 710a of the substrate 710, the stacked body S7' includes a first insulating layer 722, a first conductive layer 730, a second insulating layer 724, an upper sacrificial layer 740, a third insulating layer 726, a top conductive layer CL7 and a top insulating layer OL7 stacked in sequence (for example, through a deposition process) on the upper surface 710a of the substrate 710.

[0279] In some embodiments, the substrate 710 may be a silicon substrate or other suitable substrate. A first insulating layer 722, a second insulating layer 724, a third insulating layer 726 and a top insulating layer OL7 may be formed of oxide, such as silicon dioxide. The lower sacrificial layer 742, the upper sacrificial layer 740 and the top insulating layer OL7 may be formed of silicon nitride (SiN).

[0280] Please refer to Fig. 12B , forming a plurality of first openings 752, each of which passes through the stack body S7' to expose a portion of the substrate 710 to the outside. In some embodiments, the first openings 752 may be formed by an etching process, such as a dry etching process. In some embodiments, the substrate 710 may be overetched so that the bottom of the first opening 752 is lower than the upper surface 710a of the substrate 710.

[0281] Please refer to Fig. 12C An oxide layer 732' is formed on the sidewall and bottom of the first opening 752 by a deposition process. In some embodiments, the first insulating layer 722, the second insulating layer 724, the oxide layer 732', the third insulating layer 726 and the top insulating layer OL7 may be formed of the same material.

[0282] Please refer to Fig.12D , remove the excess oxide layer 732' in the first opening 752, and expose the substrate 510. In some embodiments, P-type dopants are implanted into the substrate 710 by ion implantation. The P-type dopants are helpful in adjusting the threshold voltage.

[0283] Please refer to Fig.12E , a channel structure 712 covering an oxide layer 732 ′ is formed by a first epitaxial growth process.

[0284] Please refer to Fig.12F , a second opening 754 is formed through the first insulating layer 722, the first conductive layer 730, the second insulating layer 724, the upper sacrificial layer 740, the third insulating layer 726, the top conductive layer CL7 and the top insulating layer OL7 by an etching process. Then, the upper sacrificial layer 740 is removed to form an upper opening 756 at the position where the upper sacrificial layer 740 is removed. Then, doped regions 712c and 718 are formed on the top of the channel structure 712 and the surface of the substrate 710 exposed to the second opening 754 by an ion implantation, and the doped regions 712c and 718 are, for example, heavily doped regions of an n-type semiconductor. The doping 712c and 718 can be used to form contact structures in subsequent processes to be electrically connected to the bit line and the common source line, respectively.

[0285] Please refer to Figure 12G , remove the oxide layer 732' corresponding to the upper opening 756 (that is, remove the middle part of the oxide layer 732'), and then form a storage layer 762 and a dielectric material 766 extending along the sidewalls of the second opening 754 and the upper opening 756 and covering the top insulating layer OL7 in sequence through a deposition process. The storage layer 762 can be composed of a composite layer (that is, an ONO layer) including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer. For example, the storage layer 762 may include a tunneling layer, a capture layer, and a barrier layer. The tunneling layer may include silicon dioxide (SiO2), a double-layer structure formed by silicon dioxide (SiO2) / silicon oxynitride (SiON), or other suitable materials. The capture layer may include silicon nitride, polysilicon, or other suitable materials. The barrier layer may include silicon dioxide (SiO2) or other suitable materials. In some embodiments, the dielectric material 766 may include a high-k material, such as aluminum oxide (Al2O3) or other suitable materials. The dielectric material 766 may also serve as a barrier layer to prevent lateral diffusion of charges.

[0286] Please refer to Fig.12H , a conductive material 772' is filled into the second opening 754 and the upper opening 756 by a deposition process. The conductive material 772' may include tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN) or other suitable materials.

[0287] Please refer to Fig.12I, the conductive material 772' located in the second opening 754 is removed by an etching process to form a second conductive layer 772 located in the upper opening 756. This etching process is, for example, a dry etching process. In some embodiments, the etching process can also remove a portion of the conductive material located in the upper opening 756. The second conductive layer 772 may include tungsten (W), aluminum (Al), titanium nitride (TiN), tantalum nitride (TaN) or other suitable conductive materials. In this embodiment, the second conductive layer 772 includes tungsten (W). Thus, a stacked structure S7 including a first insulating layer 722, a first conductive layer 730, a second insulating layer 724, a second conductive layer 772, a third insulating layer 726, a top conductive layer CL7 and a top insulating layer OL7 is formed.

[0288] Please refer to Fig.12J , an insulating material is filled into the second opening 754 through a deposition process to form a plurality of isolation structures 774. The isolation structures 774 may include oxide or other suitable insulating materials.

[0289] Please refer to Figure 12K , forming a plurality of vertical openings 759 that pass through the isolation structure 774 and extend along a normal direction of the upper surface 710 a of the substrate 710 .

[0290] After this, please refer back to Figure 1H , a conductive material is filled into these vertical openings 759 by a deposition process to form a plurality of conductive connection structures 776. The conductive connection structures 776 may include tungsten (W), aluminum (Al), titanium nitride (TiN) or other suitable conductive materials. In this way, a conductive structure 776 is formed. Figure 1H Memory element 700 is shown.

[0291] 13 to 15 are equivalent circuit diagrams of operating the memory device 400 , 500 , 600 or 700 according to an embodiment of the present invention.

[0292] The memory element 400, 500, 600 or 700 may be a three-dimensional NOR type memory element. In FIGS. 13 to 15, two serial selection lines SSL0, SSL1, two word lines WL0, WL1, two bit lines BL0, BL1 and two ground selection lines GSL0, GSL1 are exemplarily shown in the array area of ​​the memory element 400, 500, 600 or 700. However, the present invention is not limited thereto, and the number of serial selection lines, word lines, bit lines and ground selection lines may be greater than 2, respectively. The overlapping position of each word line and the channel structure forms a memory cell M, the overlapping position of each ground selection line and the channel structure forms a transistor T, and the overlapping position of each serial selection line and the channel structure forms a transistor TS. The memory cell M is located above the transistor T, the transistor TS is located above the memory cell M, and the channel structure connects the transistor TS, the memory cell M and the transistor T in series. One transistor TS, one memory cell M and one transistor T may together form a unit memory cell UN. Each transistor T is electrically connected to a common source line CSL. Word lines (eg, WL0 and WL1) may be electrically isolated by an isolation structure.

[0293] Fig.13 FIG. 4 is an equivalent circuit diagram of a memory device that performs a programming operation by Fowler-Nordheim injection according to an embodiment of the present invention.

[0294] Please refer to Fig.13 , to store the target unit UN t During programming operation, the serial selection line SSL0, word line WL0 and ground selection line GSL0 are selected, a pass voltage Vpass is applied to the serial selection line SSL0, a programming voltage Vpgm1 is applied to the word line WL0, and 0V is applied to the ground selection line GSL0. The serial selection line SSL1, word line WL1 and ground selection line GSL1 are not selected and 0V is applied. A common source voltage V CSL 0V is applied to the bit line BL0. The inhibit voltage V is applied to the bit line BL1. inhibit The cell memory cell coupled to the bit line BL1 is inhibited. In one embodiment, the pass voltage Vpass is greater than the inhibit voltage V inhibit , to transmit the suppression voltage V inhibit In one embodiment, the pass voltage Vpass is equal to the inhibit voltage V inhibit , which is used for self-boosting and can reduce programming interference.

[0295] Fig.14AFIG. 4 is an equivalent circuit diagram of a memory device that performs an erase operation by Fowler-Nordheim injection according to an embodiment of the present invention.

[0296] Please refer to Fig.14A , to store the target unit UN t (For example, two memory cells and four transistors in different series) are erased, and the serial selection line SSL0, the word line WL0 and the ground selection line GSL0 are selected. The serial selection line SSL0 is applied with an erase voltage Vers3 or is floating. The word line WL0 is applied with 0V. The ground selection line GSL0 is applied with an erase voltage Vers2. The serial selection line SSL1, the word line WL1 and the ground selection line GSL1 are not selected and are all floating. A common source line is applied with a common source voltage V CSL A P-type well voltage V is applied to the P-type well (p well) PWI The peripheral circuit applies an erase voltage Vers1. The bit lines BL0 and BL1 are floating. The common source voltage V CSL It can be the same as the erase voltage Vers1 and the P-type well voltage V PWI .

[0297] Fig. 14B FIG. 4 is an equivalent circuit diagram of a memory device that performs an erase operation by band-to-band tunneling-induced hot holes according to an embodiment of the present invention.

[0298] Please refer to Fig. 14B , to store the target unit UN t During the erase operation, the serial selection line SSL0, the word line WL0 and the ground selection line GSL0 are selected. The serial selection line SSL0 is applied with a pass voltage Vpass. The ground selection line GSL0 is applied with 0V. The word line WL0 is applied with a ground erase voltage Vgers. The ground erase voltage Vgers may be less than 0. The serial selection line SSL1, the word line WL1 and the ground selection line GSL1 are not selected and are applied with 0 volts (V). The bit line BL0 may be applied with a drain erase voltage Vders. The drain erase voltage Vders may be greater than 0. The bit line BL1 may be applied with 0V. The common source line is applied with a common source voltage V CSL .

[0299] Fig.15 FIG. 4 is an equivalent circuit diagram of a memory element for a read operation according to an embodiment of the present invention.

[0300] Please refer to Fig.15 , to store the target unit UN t (For example, two memory cells and four transistors in different memory strings) are read, and the string selection line SSL0, the word line WL0 and the ground selection line GSL0 are selected. The string selection line SSL0 can be applied with a power supply voltage VCC 0V can be applied to the word line WL0. A power supply voltage V can be applied to the ground selection line GSL0. CC The serial selection line SSL1, the word line WL1 and the ground selection line GSL1 are unselected and applied with 0 volt (V). The bit lines BL0 and BL1 can apply a bit line read voltage Vblr. The common source line applies a common source voltage V CSL When performing a read operation in the memory element of the present invention, all voltages applied to the bit line, word line, and ground selection line may be equal to or less than the power supply voltage V CC , so it can reduce power consumption.

[0301] The present invention provides a memory element, a preparation method and an operation method thereof. Since the memory element of the present invention is a three-dimensional structure, it can be applied to a NOR gate memory element, and has a smaller unit storage unit area than a general two-dimensional NOR gate memory element. Furthermore, the memory element of the present invention can use a high dielectric constant material as a dielectric material, and can operate the memory element (for example, erase, write, and program) without too high a voltage. In addition, according to an embodiment of the present invention, the channel structure is an epitaxial growth layer, which has better electrical characteristics than the comparative example in which the channel structure only partially includes an epitaxial growth layer or is mainly formed by a polysilicon layer, so that the ground selection line can obtain better control ability, and the critical voltage can be relatively small and the distribution is more concentrated (tight distribution). In addition, the thermal oxide layer of the present invention is an oxide formed by directly performing an oxidation process on the first conductive layer or the channel structure. Compared with the thermal oxide layer generally formed by a deposition method, it can have a higher oxide purity, so it is beneficial to the regulation of the critical voltage and can have a smaller critical voltage. Therefore, the memory device of the present invention can have lower power consumption, better reliability and improved performance.

[0302] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A memory element, comprising: a substrate having an upper surface; a stacked structure located on the upper surface of the substrate, wherein the stacked structure comprises a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer and a third insulating layer sequentially stacked on the substrate; A plurality of channel structures passing through the stacked structure and electrically connected to the substrate, wherein each of the channel structures comprises an upper portion and a lower portion, the upper portion corresponds to the second conductive layer, and the lower portion corresponds to the first conductive layer; a storage layer located between the second conductive layer and the upper portion; A plurality of isolation structures passing through the stacked structure to separate the stacked structure into a plurality of sub-stacks; as well as A thermal oxide layer is located between the first conductive layer and each of the channel structures, and the thermal oxide layer directly contacts the first conductive layer.

2. The memory element according to claim 1, wherein each of the channel structures is an epitaxial growth layer, wherein a top surface of the channel structure has a first height with respect to the upper surface of the substrate, a top surface of the second conductive layer has a second height with respect to the upper surface of the substrate, and the first height is greater than the second height. 3 . The memory device according to claim 1 , wherein purity of oxide of the thermal oxide layer is higher than purity of oxide of the first insulating layer.

4. A method for preparing a memory element, comprising: Providing a substrate having an upper surface; Forming a stacked body on the upper surface of the substrate, wherein the stacked body includes a first insulating layer, a first conductive layer, a second insulating layer, an upper sacrificial layer and a third insulating layer sequentially stacked on the upper surface of the substrate; forming a plurality of first openings through the laminate body; Forming a plurality of channel structures in the first openings, and the channel structures are electrically connected to the substrate, wherein each of the channel structures includes an upper portion and a lower portion, the lower portion corresponds to the first conductive layer, and the upper portion is located above the lower portion; forming a storage layer corresponding to the upper portion; forming a plurality of second openings through the laminate body; removing the upper sacrificial layer and forming an upper opening at the location where the upper sacrificial layer is removed; Filling a conductive material in the upper opening to form a second conductive layer, thereby forming a stacked structure including the first insulating layer, the first conductive layer, the second insulating layer, the second conductive layer and the third insulating layer; as well as A plurality of isolation structures are formed in the second openings, and the isolation structures separate the stacked structure into a plurality of sub-stacked structures.

5. The method for preparing a memory element according to claim 4, further comprising: Forming a thermal oxidation layer on one side surface of the first conductive layer through an oxidation process; The lower portion of each channel structure covering the thermal oxide layer is formed by a first epitaxial growth process. The thermal oxide layer is located between the first conductive layer and the lower portion of each channel structure, and the purity of the oxide of the thermal oxide layer is higher than the purity of the oxide of the first insulating layer. 6 . The method for fabricating a memory device according to claim 5 , wherein the upper portion and the lower portion of each of the channel structures are grown by the first epitaxial growth process.

7. The method for preparing a memory element according to claim 5, wherein after the step of forming the lower portion, the memory layer is first formed on the sidewalls of each of the first openings before forming the upper portion, and the upper portion is formed by a second epitaxial growth process.

8. A method for preparing a memory element, comprising: Providing a substrate having an upper surface; Forming a stacked body on the upper surface of the substrate, wherein the stacked body includes a first insulating layer, a lower sacrificial layer, a second insulating layer, an upper sacrificial layer and a third insulating layer sequentially stacked on the upper surface of the substrate; forming a plurality of first openings through the laminate body; forming lower portions of the channel structures in the first openings; forming a storage layer corresponding to the upper sacrificial layer in each of the first openings; forming a plurality of upper portions of the channel structures in the first openings, the upper portions being located above the lower portions; forming a plurality of second openings through the laminate body; Removing the upper sacrificial layer and the lower sacrificial layer, and forming an upper opening and a lower opening at the positions where the upper sacrificial layer and the lower sacrificial layer are removed, respectively; Filling a conductive material in the upper opening and the lower opening to form a second conductive layer and a first conductive layer respectively, thereby forming a stacked structure including the first insulating layer, the first conductive layer, the second insulating layer, the second conductive layer and the third insulating layer; as well as A plurality of isolation structures are formed in the second openings, and the isolation structures separate the stacked structure into a plurality of sub-stacked structures.

9. The method for manufacturing a memory device according to claim 8, further comprising: after forming the first openings: forming the lower portions of the channel structures by a first epitaxial growth process; as well as After forming the memory layer on the lower portion, the upper portions of the channel structures are formed by a second epitaxial growth process.

10. The method for preparing a memory element according to claim 8, wherein after the step of forming the second openings, the method further comprises: Performing an oxidation process to form a thermal oxide layer on partial side surfaces of the lower portions, wherein the purity of the oxide of the thermal oxide layer is higher than the purity of the oxide of the first insulating layer; and A dielectric material is deposited on a side wall of the upper opening and a side wall of the lower opening.

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