Memory array and method for forming a memory array

Abstract

The present application relates to a memory array and a method for forming a memory array. The method includes: forming a stack including a first layer and a second layer that alternate vertically, including a memory block area having a channel material string. A conductor material contact directly abuts against the channel material of an individual channel material string in the channel material string. A first insulator material is formed directly above the conductor material contact. The first insulator material includes at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus, and (b): silicon carbide. A second insulator material is formed directly above the first insulator material and the conductor material contact. The second insulator material does not contain each of (a) and (b). A third insulator material is formed directly above the second insulator material, the first insulator material and the conductor material contact. The third insulator material includes at least one of (a) and (b).

Description

Technical Field

[0001] Embodiments disclosed herein relate to memory arrays and to methods for forming memory arrays. Background Art

[0002] A memory is an integrated circuit and is used in computer systems to store data. The memory can be fabricated as one or more arrays of individual memory cells. The memory cells can be written to or read from using digit lines (which may also be referred to as bit lines, data lines, or sense lines) and access lines (which may also be referred to as word lines). The sense lines can conductively interconnect the memory cells along the columns of the array, and the access lines can conductively interconnect the memory cells along the rows of the array. Each memory cell can be uniquely addressed by a combination of the sense lines and the access lines.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for long periods of time without power. Non-volatile memory is conventionally specified as memory with a retention time of at least about 10 years. Volatile memory dissipates and is therefore refreshed / rewritten to maintain data storage. Volatile memory may have a retention time of a few milliseconds or less. In any case, the memory cell is configured to retain or store storage content in at least two different selectable states. In a binary system, the states are considered "0" or "1". In other systems, at least some individual memory cells may be configured to store information at more than two levels or states.

[0004] A field effect transistor is an electronic component that can be used in a memory cell. These transistors include a pair of conductive source / drain regions with a semiconducting channel region therebetween. A conductive gate is adjacent to the channel region and is separated from the channel region by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow from one of the source / drain regions to the other through the channel region. When the voltage is removed from the gate, current is largely prevented from flowing through the channel region. Field effect transistors may also include additional structures, such as a reversibly programmable charge storage region as part of the gate construction between the gate insulator and the conductive gate.

[0005] Flash memory is a type of memory and is used extensively in modern computers and devices. For example, modern personal computers may have the BIOS stored on a flash memory chip. As another example, it is increasingly common for computers and other devices to utilize flash memory in solid-state drives to replace conventional hard disk drives. As yet another example, flash memory is prevalent in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized and to provide the ability to remotely upgrade devices for enhanced features.

[0006] NAND may be the basic architecture for integrated flash memory. A NAND cell device includes at least one selection device coupled in series with a series combination of memory cells (and the series combination is often referred to as a NAND string). The NAND architecture may be configured in a three-dimensional arrangement including vertically stacked memory cells that individually include reversibly programmable vertical transistors. Controls or other circuitry may be formed beneath the vertically stacked memory cells. Other volatile or non-volatile memory array architectures may also include vertically stacked memory cells that individually include transistors.

[0007] The memory array may be arranged in memory pages, memory blocks and partial blocks (e.g., sub-blocks) and memory planes, such as shown and described in any of U.S. Patent Application Publications Nos. 2015 / 0228659, 2016 / 0267984, and 2017 / 0140833. The memory blocks may at least partially define the longitudinal profiles of individual word lines in individual word line layers of vertically stacked memory cells. Connections to these word lines may occur in a so-called "staircase structure" at the ends or edges of the array of vertically stacked memory cells. The staircase structure includes individual "steps" (alternatively referred to as "steps" or "stairs") that define contact areas for individual word lines, on which vertically extending conductive vias contact to provide electrical access to the word lines. Summary of the invention

[0008] In one aspect, the present disclosure relates to a method for forming a memory array including a memory cell string, comprising: forming a stack including a vertically alternating first layer and a second layer, including a memory block region having a channel material string, a conductor material contact directly abutting the channel material of an individual channel material string in the channel material string; forming a first insulator material directly above the conductor material contact, the first insulator material including at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus, and (b): silicon carbide; forming a second insulator material directly above the first insulator material and the conductor material contact, the second insulator material not containing each of (a) and (b); forming a third insulator material directly above the second insulator material, the first insulator material and the conductor material contact, the third insulator material including at least one of (a) and (b); and forming at least one horizontally elongated isolation structure in the first and second insulator materials and in a top portion of the stack in an individual memory block region in the memory block region.

[0009] On the other hand, the present disclosure relates to a method for forming a memory array including a memory cell string, which includes: forming a stack including a vertically alternating first layer and a second layer, wherein there are channel material strings, and conductor material contacts directly abut the channel material of individual channel material strings in the channel material strings; forming a first insulator material directly above the conductor material contacts, the first insulator material including at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus, and (b): silicon carbide; forming a second insulator material directly above the first insulator material and the conductor material contacts, the second insulator material not containing each of (a) and (b); forming a third insulator material directly above the second insulator material, the first insulator material and the conductor material contacts, the third insulator material including at least one of (a) and (b); and forming conductive through-holes through the first and second insulator materials that are individually directly abutting against individual conductor material contacts in the conductor material contacts.

[0010] On the other hand, the present disclosure relates to a method for forming a memory array including a string of memory cells, comprising: forming a stack including a vertically alternating first layer and a second layer, including a memory block area having a string of channel material; and in individual memory block areas in the memory block area, forming at least one horizontally elongated isolation structure in a top portion of the stack, the isolation structure comprising a lower horizontally elongated insulator material and an upper horizontally elongated insulator material thereover, the upper insulator material comprising at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus, and (b): silicon carbide, the lower insulator material not containing each of (a) and (b).

[0011] On the other hand, the present disclosure relates to a method for forming a memory array including a memory cell string, comprising: forming a stack including a vertically alternating first layer and a second layer, including a memory block area having a channel material string, a conductor material contact directly abutting the channel material of an individual channel material string in the channel material string, and at least one horizontally elongated isolation structure being in the top portion of the stack in an individual memory block area in the memory block area; forming an insulator material directly above the conductor material contact and the at least one isolation structure, the insulator material including at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus, and (b): silicon carbide; and forming conductive vias through the insulator material that are individually directly abutting the individual conductor material contacts in the conductor material contacts.

[0012] On the other hand, the present disclosure relates to a memory array including a string of memory cells, comprising: laterally spaced memory blocks, each of which individually comprises a vertical stack, the vertical stack comprising alternating insulating layers and conductive layers, a string of channel materials of the memory cells in the stack, a conductor material contact directly abutting against the channel material of an individual string of channel materials in the string of channel materials; and an insulator material directly abutting against the top of the conductor material contact, the insulator material comprising at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus, and (b): silicon carbide.

[0013] On the other hand, the present disclosure relates to a memory array including a string of memory cells, comprising: laterally spaced memory blocks, each of which individually comprises a vertical stack, the vertical stack comprising alternating insulating layers and conductive layers, and a string of channel materials of the memory cells is in the stack; and at least one horizontally elongated isolation structure in a top portion of the stack in an individual of the memory blocks, the isolation structure comprising a lower horizontally elongated insulator material and an upper horizontally elongated insulator material thereover, the upper insulator material comprising at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus, and (b): silicon carbide, the lower insulator material does not contain each of (a) and (b). BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a diagrammatic cross-sectional view of a portion of a substrate under processing according to an embodiment of the present invention, and passes through Figure 2 Intercepted by line 1-1.

[0015] Figure 2 It passes through Figure 1 A schematic cross-sectional view taken along line 2-2 in FIG.

[0016] Figure 3 and 4 yes Figure 1 and 2 Magnified view of a portion of.

[0017] Figures 5 to 13 is in process according to some embodiments of the present invention Figures 1 to 4 A schematic, sequential cross-sectional, expanded, enlarged and / or partial view of a structure or part thereof.

[0018] Figures 14 to 38 Alternative example methodological and / or structural embodiments of the present invention are presented. DETAILED DESCRIPTION

[0019] Embodiments of the present invention encompass methods for forming a memory array, such as an array of NAND or other memory cells, which may have at least some peripheral control circuitry under the array (e.g., under-array CMOS). Embodiments of the present invention encompass so-called "gate-last" or "replacement-gate" processes, so-called "gate-first" processes, and other processes, whether present or developed in the future, that are independent of when the transistor gates are formed. Embodiments of the present invention also encompass a memory array (e.g., a NAND architecture) that is independent of the method of manufacture. Reference Figures 1 to 13 and 38 describe a first example method embodiment, which may be viewed as a "gate last" or "replacement gate" process, and from Figures 1 to 4 start.

[0020] Figure 1 and 2 A construction 10 is shown having an array or array region 12 in which vertically extending strings of transistors and / or memory cells are to be formed. Construction 10 includes a base substrate 11 having any one or more of conductive / conductive / conductive, semiconductive / semiconductive / semiconductive, or insulating / insulator / insulating (i.e., electrically herein) materials. Various materials are vertically formed on base substrate 11. The materials may be Figures 1 to 4 1. For example, other partially fabricated or entirely fabricated integrated circuit components may be provided somewhere above, around, or within base substrate 11. Control circuitry and / or other peripheral circuitry for operating components within an array of vertically extending strings of memory cells (e.g., array 12) may also be fabricated, and may or may not be completely or partially within an array or sub-array. In addition, multiple sub-arrays may also be fabricated and operated independently, sequentially, or otherwise relative to one another. In this document, a "sub-array" may also be considered an array.

[0021] A conductor layer 16 including a conductor material 17 is formed over substrate 11. Conductor layer 16 may include portions of control circuitry (e.g., peripheral under-array circuitry and / or common source lines or plates) for controlling read and write access to transistors and / or memory cells to be formed within array 12. A stack 18 including vertically alternating insulating layers 20 and conductive layers 22 is formed over conductor layer 16. An example thickness of each layer 20 and 22 is 22 to 60 nanometers. Only a small number of layers 20 and 22 are shown, with stack 18 more likely including tens, a hundred, or more (etc.) layers 20 and 22. Other circuitry that may or may not be part of peripheral and / or control circuitry may be between conductor layer 16 and stack 18. For example, multiple vertically alternating layers of conductive and insulating material of such circuitry may be below the lowest conductive layer 22 and / or above the uppermost conductive layer 22. For example, one or more select gate layers (not shown) may be between conductor layer 16 and the lowest conductive layer 22, and one or more select gate layers may be above the uppermost conductive layer 22. Alternatively or additionally, at least one of the depicted uppermost and lowest conductive layers 22 may be a select gate layer. Regardless, conductive layer 22 (alternatively referred to as the first layer) may not include conductive material, and insulating layer 20 (alternatively referred to as the second layer) may not include insulating material or may be insulating when processed in conjunction with the “gate last” or “replacement gate” example method embodiments initially described herein. Example conductive layer 22 includes a first material 26 (e.g., silicon nitride) that may be fully or partially sacrificial. Example insulating layer 20 includes a second material 24 (e.g., silicon dioxide) that has a composition different from that of first material 26 and that may be fully or partially sacrificial.

[0022] Channel openings 25 and dummy structure openings 62 are formed through insulating layer 20 and conductive layer 22 to conductor layer 16 (e.g., by etching). In this document, a "dummy structure opening" is an opening in which a "dummy structure" has been formed or will be formed. A "dummy structure" is a circuit invalid structure that may be in the finished circuit system construction and thus no current flows through it in all operations of the circuit system, and it may be a circuit invalid dead end, not part of the current flow path of the circuit, even if it extends to or extends from the electronic component. If necessary, the dummy structure opening 62 may be provided to make the process uniform when forming the effective channel opening 25 and the material therein. The openings 25 and 62 may taper radially inward as they move deeper in the stack 18 (not shown). In some embodiments, the openings 25 and 62 may enter the conductor material 17 of the conductor layer 16 as shown, or may stop at the top there (not shown). Alternatively, as an example, the openings 25 and 62 may stop at the top or inside of the lowest insulating layer 20. The reason for extending the channel opening 25 to at least the conductor material 17 of the conductor layer 16 is to ensure that the subsequently formed channel material (not yet shown) is directly electrically coupled to the conductor layer 16 when such connection is desired without using alternative processing and structures to achieve this. Etch stop material (not shown) may be within or on top of the conductor material 17 of the conductor layer 16 to help stop the etching of the channel opening 25 relative to the conductor layer 16 when such a desire is present. Such etch stop material may be sacrificial or non-sacrificial. By way of example and for simplicity only, the openings 25 / 62 are shown as being arranged in groups or columns of staggered rows of four and five openings 25 / 62 per row, and arranged in laterally spaced memory block regions 58, which will include laterally spaced memory blocks 58 in the finished circuit system configuration. In this document, "block" generally includes "sub-blocks". The memory block regions 58 and the resulting memory blocks 58 (not yet shown) may be considered to be longitudinally elongated and, for example, oriented along the direction 55. The memory block regions 58 may be indistinguishable at this processing point. Any alternative existing or future developed arrangements and configurations may be used.

[0023] The transistor channel material may be formed vertically in individual channel openings along the insulating layer and the conductive layer, thus including individual strings of channel material that are directly electrically coupled to the conductive material in the conductor layer. Individual memory cells of the formed example memory array may include a gate region (e.g., a control gate region) and a memory structure laterally between the gate region and the channel material. In one such embodiment, the memory structure is formed to include a charge blocking region, a storage material (e.g., a charge storage material), and an insulating charge transfer material. The storage material (e.g., a floating gate material, such as doped or undoped silicon, or a charge trapping material, such as silicon nitride, metal dots, etc.) of the individual memory cells is vertically along the individual charge blocking region. The insulating charge transfer material (e.g., a bandgap engineered structure having a nitrogen-containing material (e.g., silicon nitride) sandwiched between two insulator oxides (e.g., silicon dioxide) is laterally between the channel material and the storage material.

[0024] Figures 1 to 4 An embodiment is shown in which charge blocking material 30, storage material 32, and charge transfer material 34 are formed vertically along insulating layer 20 and conductive layer 22 in individual openings 25 and 62. Transistor material 30, 32, and 34 (e.g., memory cell material) may be formed, for example, by depositing a respective thin layer of the transistor material over stack 18 and within individual openings 25 and 62, followed by planarizing such thin layer back to at least the top surface of stack 18.

[0025] Channel material 36 is also formed vertically in openings 25 and 62 along insulating layer 20 and conductive layer 22, thus including individual effective channel material strings 53 in channel opening 25 and dummy structures 63 in dummy structure opening 62. In one embodiment, channel material strings 53 have memory cell materials (e.g., 30, 32, and 34) along them, and wherein a second layer of material (e.g., 24) is horizontally located immediately between channel material strings 53. Due to the proportions, materials 30, 32, 34, and 36 are located horizontally between the channels 25 and 62. Figure 1 and 237. Example channel material 36 includes appropriately doped crystalline semiconductor materials such as one or more of silicon, germanium, and so-called III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). An example thickness of each of materials 30, 32, 34, and 36 is 25 to 100 angstroms. As shown, a stamp etch may be performed to remove materials 30, 32, and 34 from the base of channel opening 25 to expose conductor layer 16 so that channel material 36 is directly against conductor material 17 of conductor layer 16. Such a stamp etch may occur individually with respect to each of materials 30, 32, and 34 (as shown), or may occur collectively with respect to all materials after deposition of material 34 (not shown). Alternatively and by way of example only, a stamp etch may not be performed, and channel material 36 may be directly electrically coupled to conductor material 17 of conductor layer 16 by a separate conductive interconnect (not shown). Channel opening 25 is shown including a radially central solid dielectric material 38 (eg, spin-on dielectric, silicon dioxide, and / or silicon nitride). Alternatively and by way of example only, a radially central portion within channel opening 25 may include void space (not shown) and / or be free of solid material (not shown).

[0026] Regardless, the conductive material contact 70 (e.g., including conductive material 71) is directly against the channel material 36 of the individual channel material string 53 (e.g., radially inward of and directly against the radial inner side 79 of the channel material 36). The conductive material contact 70 can be considered to include the top 21. One or more of the materials 30, 32, 34, and 36 may not extend to the top of the conductive material 71 (not shown). In addition and regardless, the conductive material 71 may not extend to the top of the stack 18 (not shown), may extend above the stack 18 (not shown), and / or may extend below the bottom of the uppermost layer 20 (not shown). The dummy structure 63 can have the same configuration as the material in the channel opening 25.

[0027] refer to Figure 5 and 6, at least one horizontally elongated isolation structure 95 (only one is shown) is formed in the top portion of the stack 18 in the individual memory block region 58. An example manner of forming the isolation structure 95 is to form a horizontally elongated isolation trench 68 in the top portion of the stack 18 and fill such isolation trench with an insulating material 69 (e.g., silicon dioxide). In the finished circuit system configuration, the isolation structure 95 may be laterally between two laterally adjacent select gates (not shown) in the individual memory block 58. More than one isolation structure 95 (not shown) may be provided, such as two isolation structures separating a total of three select gates in the individual memory block, three isolation structures separating a total of four select gates in the individual memory block, etc. The at least one isolation structure 95, the string of channel material 53, and / or the dummy structure 63 may have been formed before or after patterning the steps / stairs in the step region (not shown), and this is not particularly relevant to the inventive aspects disclosed herein.

[0028] refer to Figure 7 , an insulator material 31 (referred to as a first insulator material 31 in some embodiments) (e.g., 200 to 300 angstroms) is formed directly over the conductor material contact 70 and at least one isolation structure 95. In some embodiments, the insulator material 31 may be formed directly against the conductor material contact 70 and / or at least one isolation structure 95. The insulator material 31 includes at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. The insulator material 31 may include only one of (a) or (b), or both.

[0029] Conductive vias are formed through the insulator material 31, which are individually directly against the individual conductor material contacts 70. Figures 8 to 13 Describe an example way of doing this.

[0030] Figure 8 Insulating material 64 (referred to in some embodiments as second insulator material 64) is shown formed directly over and in one embodiment directly against insulator material 31. Insulating material 64 is free of each of (a) and (b). Example insulating material 64 is doped or undoped silicon dioxide.

[0031] Conductive via openings are formed through the insulating material 64 and the insulator material 31 to the individual conductor material contacts 70. Fig. 9 and 10And in one such embodiment, such a case shows the formation of such conductive via opening 42 as including using a first etch chemistry to anisotropically etch through insulating material 64 selectively relative to insulator material 31 while stopping on or in insulator material 31. Such example dry first etch chemistry where insulating material 64 is silicon dioxide and insulator material 31 is (a) or (b) is C x F y With some O2. The conductive via opening 42 can be formed by, for example, photolithographic patterning and etching with or without the use of a hard masking material. For example, the example conductive via opening 42 is shown slightly but acceptably offset to the right relative to the conductor material contact 70.

[0032] refer to Fig.11 , the insulator material 31 has been etched by using a second etch chemistry different from the first etch chemistry to expose individual conductor material contacts 70. Where the insulator material 31 is (a) or (b), the example dry second etch chemistry is CF4 with some CH x F y .

[0033] refer to Fig.12 and 13 , conductive material 54 is formed in conductive via opening 42 to directly abut individual conductor material contacts 70, thereby forming conductive via 41. By way of example only, conductive material 54 may be deposited to initially overfill conductive via opening 42 and then polished back to at least the outer surface of insulating material 64.

[0034] For simplicity and clarity in the drawings, the contact 70 and the through hole 41 are shown as being the same shape in horizontal and vertical cross-sections, with the horizontal cross-section of the through hole 41 being larger than the horizontal cross-section of the contact 70. In addition and regardless, the respective sizes and shapes need not be constant in different horizontal and / or vertical cross-sections through the center of the contact 70 and the through hole 41 (although shown as being constant).

[0035] Any other properties or aspects shown and / or described herein with respect to other embodiments may be used with reference to the embodiments shown and described above.

[0036] Next reference Figures 14 to 37 An alternative example method for forming a memory array is described. Like numbering from the embodiments described above has been used where appropriate, with some construction differences indicated with a suffix "a" or with different numbering.

[0037] See also Fig.14 and 15 , these figures show similarities to the above with respect to Figure 7The process described is however related to the process of construction 10a, where Figure 7 At least one isolation structure 95 (not shown) shown in has not yet been formed. Thus, insulator material 31 has been formed. Prior to this point in processing, the steps / stairs in the step region (not shown) may or may not have been patterned, and this is not particularly relevant to the inventive aspects disclosed herein.

[0038] refer to Fig.16 , the second insulator material 64 is formed directly over the first insulator material 31 , and in one embodiment directly against the first insulator material 31 and thus also directly over the conductor material contact 70 .

[0039] See also Fig.17 , the third insulator material 66 is formed directly above the second insulator material 64, and in one embodiment directly against the second insulator material 64 and thus directly above the first insulator material 31 and the conductor material contact 70. The third insulator material includes at least one of (a) and (b). The first insulator material 31 and the third insulator material 66 may have different compositions relative to each other, or alternatively, have the same composition relative to each other. With respect to the third insulator material 66, any of the properties described above with respect to the insulator material 31 apply. In one embodiment, the construction 10a does not contain each of (a) and (b) between the first insulator material 31 and the third insulator material 66 in the vertical direction. The third insulator material 66 can be completely sacrificial if desired.

[0040] At least one horizontally elongated isolation structure is formed in the first and second insulator materials (whether or not formed in the third insulator material) and in the top portion of the stack in the individual memory block areas. Figures 18 to 23 Describe an example way of doing this.

[0041] refer to Fig.18 and 19 , these figures show the formation of horizontally elongated isolation trenches 68 (i.e., at least one) in the first insulator material 31 and the second insulator material 64 (and in the third insulator material 66 when present) and in the top portion of the stack 18 in the individual memory block areas 58. This is followed by the formation of an insulator material 69 [e.g., excluding each of (a) and (b)] in the isolation trenches.

[0042] Fig. 20 An example embodiment is shown in which insulator material 69 has been vertically recessed into isolation trench 68 (eg, by selective anisotropic etching relative to at least third insulator material 66 ). In some embodiments, insulator material 69 may be considered to include a lower horizontally elongated insulator material 69 .

[0043] refer to Fig.21 , an upper horizontally elongated insulator material 73 is formed above the lower insulator material 69 and includes at least one of (a) and (b) (for example, either or both of (a) or (b) are in the third insulator material 66 or the first insulator 31), wherein in one embodiment, the lower insulator material 69 does not contain each of (a) and (b).

[0044] Fig. 22 and 23 Subsequent processing is shown whereby the third insulator material 66 (not shown) and the upper insulator material 73 are removed at least back to the top surface of the second insulator material 64, thereby forming at least one horizontally elongated isolation structure 95a in the first insulator material 31 and the second insulator material 64 and in the top portion of the stack 18 in the individual memory block areas 58. In one embodiment and as shown, at least one isolation structure 95a is formed to have a top 19 that is higher than the top 21 of the conductor material contact 70.

[0045] In some embodiments, conductive vias are formed through the first insulator material 31 and the second insulator material 64 (at least through such materials) that individually directly abut against individual conductor material contacts 70 . Figures 24 to 28 Show similar to the above about Figures 9 to 13 Examples of the processes described include additional processes.

[0046] refer to Fig.24 , a fourth insulator material 67 (e.g., not containing each of (a) and (b) and may have a composition that is the same as or different from that of the second insulator material 64) is formed directly over the second insulator material 64, and in one embodiment, directly against the second insulator material 64.

[0047] refer to Fig.25 , the conductive via opening 42 has been formed through the fourth insulator material 67 and the second insulator material 64, for example by anisotropic etching selectively with respect to the first insulator material 31 using a first etching chemistry (such as described above) and terminating on or in the first insulator material 31. Fig. 9 That way, an acceptable rightward deviation is exhibited.

[0048] Fig.26 An example subsequent etch is shown through the first insulator material 31 using a second etch chemistry different from the first etch chemistry, such as described above, to expose individual conductor material contacts 70 .

[0049] Fig. 27 and 28Example subsequent processing is shown whereby conductive material 54 is formed in conductive via opening 42 directly against individual conductor material contacts 70, thereby forming conductive vias 41. Providing upper insulator material 73 as comprising at least one of (a) and (b) will provide over-etch protection in the event that conductive via opening 42 is offset such that it overlaps isolation structure 95. This situation may inadvertently occur, for example, in the event that conductive via opening 42 is significantly larger in horizontal cross-sectional area than conductor material contact 70 (not shown).

[0050] As mentioned above, method embodiments of the present invention may use processes that are generally referred to as gate-first or gate-last processes. An example gate-last process is described below, and it may occur earlier than any of the processes described above. The example is performed with respect to construction 10a, but may also occur with respect to construction 10 or other constructions.

[0051] refer to Fig.29 and 30 , horizontally elongated trenches 40 have been formed in stack 18 (e.g., by anisotropic etching) to form laterally spaced memory block regions 58. Trenches 40 may have respective bottoms that are directly against (e.g., on top or inside) conductor material 17 of conductor layer 16 (as shown), or may have respective bottoms that are vertically coincident with or below the bottom of conductor material 17 of conductor layer 16 (not shown).

[0052] refer to Figures 31 to 35 , and in one embodiment, material 26 (not shown) of conductive layer 22 has been removed, for example, by isotropically etching away through trench 40, ideally selectively relative to other exposed materials (e.g., using liquid or vapor H3PO4 as the primary etchant, where material 26 is silicon nitride and the other materials include one or more oxides or polysilicon). In an example embodiment, material 26 (not shown) in conductive layer 22 is sacrificial and has been replaced by conductive material 48 and has thereafter been removed from trench 40, thus forming individual conductive lines 29 (e.g., word lines) and vertically extending strings 49 of individual transistors and / or memory cells 56.

[0053] A thin insulating liner (such as Al2O3 and not shown) may be formed prior to forming the conductive material 48. The approximate location of the transistor and / or memory cell 56 is Fig.34 Indicated by brackets in Fig.31 , 32, 33 and 35 are indicated by dashed outlines, where the transistor and / or memory cell 56 is substantially annular or ring-shaped in the depicted example. Alternatively, the transistor and / or memory cell 56 may not completely surround the individual channel openings 25, so that each channel opening 25 may have two or more vertically extending strings 49 (e.g., multiple transistors and / or memory cells surround the individual channel openings in individual conductive layers, where there may be multiple word lines per channel opening in the individual conductive layers and are not shown). The conductive material 48 can be seen as having an end 50 ( Fig.34 ). In the depicted embodiment, control gate region 52 includes individual portions of individual conductive lines 29. Materials 30, 32, and 34 may be viewed as a memory structure 65 laterally disposed between control gate region 52 and channel material 36. In one embodiment and as shown with respect to an example "gate last" process, conductive material 48 of conductive layer 22 is formed after forming channel opening 25 and / or trench 40. Alternatively, such as with respect to a "gate first" process, conductive material of the conductive layer may be formed prior to forming channel opening 25 and / or trench 40 (not shown).

[0054] A charge blocking region (e.g., charge blocking material 30) is between the storage material 32 and the individual control gate region 52. The charge blocking member may have the following functions in a memory cell: in a programming mode, the charge blocking member may prevent charge carriers from passing from the storage material (e.g., floating gate material, charge trapping material, etc.) to the control gate, and in an erase mode, the charge blocking member may prevent charge carriers from flowing from the control gate into the storage material. Thus, the charge blocking member may be used to block charge migration between the control gate region and the storage material of an individual memory cell. The example charge blocking region as shown includes an insulator material 30. As a further example, the charge blocking region may include a lateral (e.g., radially) outer portion of the storage material (e.g., material 32) where such storage material is insulating (e.g., in the absence of any different composition material between the insulating storage material 32 and the conductive material 48). Regardless, as an additional example, the interface of the storage material and the conductive material of the control gate may be sufficient to act as a charge blocking region in the absence of any separate composition insulator material 30. Furthermore, the interface of conductive material 48 and material 30 (if present) in conjunction with insulator material 30 may together act as a charge blocking region and alternatively or additionally may act as a lateral outer region of insulating storage material such as silicon nitride material 32. Example material 30 is one or more of hafnium silicon oxide and silicon dioxide.

[0055] In the depicted example, the example isolation structure 95a is laterally between two laterally adjacent select gates 85 in an individual memory block 58 .

[0056] refer to Fig.36 and 37 And in one embodiment, intervening material 57 is formed in trench 40, the trench being laterally between and longitudinally along the laterally adjacent memory block regions 58. Intervening material 57 can provide lateral electrical isolation (insulation) between laterally adjacent memory block regions 58. This can include one or more of insulating, semiconducting, and conductive materials, and in any case, can help prevent shorting of conductive layers 22 relative to each other in the finished circuit system construction. Example insulating materials are one or more of SiO2, Si3N4, Al2O3, and undoped polysilicon. Intervening material 57 can include TAV (not shown).

[0057] Fig.38 Display corresponds to Fig.37 An example of construction 10a is construction 10.

[0058] Any other properties or aspects shown and / or described herein with respect to other embodiments may be used with reference to the embodiments shown and described above.

[0059] Embodiments of the present invention encompass a method for forming a memory array (e.g., 12) including a string (e.g., 49) of memory cells (e.g., 56). Such a method includes forming a stack (e.g., 18) including a vertically alternating first layer (e.g., 22) and a second layer (e.g., 20) having a string of channel material (e.g., 53). A conductor material contact (e.g., 70) is directly against the channel material (e.g., 36) of the individual channel material strings. A first insulator material (e.g., 31) is formed directly over the conductor material contact and includes at least one of (a) and (b). A second insulator material (e.g., 64) is formed directly over the first insulator material and the conductor material contact and does not include each of (a) and (b). A third insulator material (e.g., 66) is formed directly over the second insulator material, the first insulator material, and the conductor material contact. The third insulator material includes at least one of (a) and (b). Conductive vias (eg 41) are formed through the first and second insulator materials, respectively directly against respective conductor material contacts (regardless of whether and when at least one horizontally elongated isolation structure is formed if so formed).

[0060] In one embodiment, at least one horizontally elongated isolation structure (eg, 95, 95a) is formed through the first, second, and third insulator materials and in the top portion of the stack 18 in an individual memory block area (eg, 58).

[0061] Any other attributes or aspects shown and / or described herein with respect to other embodiments may be used.

[0062] Embodiments of the present invention include a method for forming a memory array (e.g., 12) including strings (e.g., 49) of memory cells (e.g., 56). Such a method includes: forming a stack (e.g., 18) including vertically alternating first layers (e.g., 22) and second layers (e.g., 20), including a memory block region (e.g., 58) having a channel material string (e.g., 49) (whether or not including a conductor material contact). In individual memory block regions, at least one horizontally elongated isolation structure (e.g., 95a) is formed in a top portion of the stack. The isolation structure includes a lower horizontally elongated insulator material (e.g., 69) and an upper horizontally elongated insulator material (e.g., 73) thereover. The upper insulator material includes at least one of (a) and (b). The lower insulator material does not contain each of (a) and (b). Any other attributes or aspects shown and / or described herein with respect to other embodiments may be used.

[0063] Alternative embodiment configurations may result from the method embodiments described above or otherwise. In any event, embodiments of the invention encompass memory arrays that are independent of the method of manufacture. Nevertheless, such memory arrays may have any of the properties described herein in the method embodiments. Likewise, the method embodiments described above may incorporate, form and / or have any of the properties described with respect to the device embodiments.

[0064] In one embodiment, a memory array (e.g., 12) including strings (e.g., 49) of memory cells (e.g., 56) includes laterally spaced memory blocks (e.g., 58), each of which includes a vertical stack (e.g., 18) comprising alternating insulating layers (e.g., 20) and conductive layers (e.g., 22). A string (e.g., 53) of channel material of a memory cell (e.g., 56) is in the stack. A conductor material contact (e.g., 70) is directly against the channel material (e.g., 36) of the individual string of channel material. An insulator material (e.g., 31) is directly against the top (e.g., 21) of the conductor material contact. The insulator material includes at least one of (a) and (b). Any other attributes or aspects shown and / or described herein with respect to other embodiments may be used.

[0065] In one embodiment, a memory array (e.g., 12) including strings (e.g., 49) of memory cells (e.g., 56) includes laterally spaced memory blocks (e.g., 58), each of which includes a vertical stack (e.g., 18) comprising alternating insulating layers (e.g., 20) and conductive layers (e.g., 22). The strings (e.g., 49) of channel materials of memory cells (e.g., 56) are in the stack (whether or not conductive material contacts are present). In an individual memory block, at least one horizontally elongated isolation structure (e.g., 95a) is at the top portion of the stack. The isolation structure includes a lower horizontally elongated insulator material (e.g., 69) and an upper horizontally elongated insulator material (e.g., 73) thereover. The upper insulator material includes at least one of (a) and (b). The lower insulator material does not include each of (a) and (b). In an individual memory block, at least one isolation structure is laterally between two laterally adjacent select gates (e.g., 85). Any other attributes or aspects shown and / or described herein with respect to other embodiments may be used.

[0066] The above-described processing or construction may be considered to be associated with an array of components formed as a single stack or single stack of such components above or as part of the underlying base substrate or within the single stack or single stack (although the single stack / stack may have multiple layers). Control and / or other peripheral circuitry for operating or accessing such components within the array may also be formed at any location as part of the finished construction, and in some embodiments may be below the array (e.g., CMOS under the array). In any case, one or more additional such stacks / stacks may be provided or manufactured above and / or below the stacks / stacks shown in the figures or described above. In addition, the arrays of components may be the same or different in different stacks / stacks relative to each other, and different stacks / stacks may have the same thickness or different thicknesses relative to each other. Intermediate structures may be provided between vertically adjacent stacks / stacks (e.g., additional circuitry and / or dielectric layers). In addition, different stacks / stacks may be electrically coupled relative to each other. Multiple stacks / stacks may be manufactured individually and sequentially (e.g., one on top of another), or two or more stacks / stacks may be manufactured substantially simultaneously.

[0067] The assemblies and structures discussed above can be used in integrated circuits / circuitry systems and can be incorporated into electronic systems. Such electronic systems can be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can include multi-layer, multi-chip modules. The electronic system can be any of a wide range of systems such as cameras, wireless devices, displays, chipsets, set-top boxes, games, lighting, vehicles, clocks, televisions, cellular phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0068] In this document, unless otherwise indicated, "vertical", "higher", "upper", "lower", "top", "on top", "bottom", "above", "below", "under", "under", "upward", and "downward" generally refer to the vertical direction. "Horizontal" refers to the general direction along the surface of the main substrate (i.e., within 10 degrees) and the substrate can be processed during manufacturing, and vertical is a direction generally orthogonal thereto. Reference to "just horizontal" refers to the direction along the surface of the main substrate (i.e., not forming a degree with the surface) and the substrate can be processed during manufacturing. In addition, "vertical" and "horizontal" as used herein are directions that are generally perpendicular to each other and are independent of the orientation of the substrate in three-dimensional space. In addition, "vertically extending" and "vertically extending" refer to a direction that deviates from just horizontal by at least 45°. In addition, "vertically extending", "vertically extending", "horizontally extending", "horizontally extending", and the like relative to a field effect transistor refer to the orientation of the channel length of the transistor, along which the current flows between the source / drain regions in operation. For bipolar junction transistors, "vertically extending," "vertically extending," "horizontally extending," "horizontally extending," and the like refer to the orientation of the substrate length along which current flows between the emitter and the collector in operation. In some embodiments, any component, feature, and / or region extending vertically extends vertically or within 10° of vertical.

[0069] Furthermore, "directly above," "directly below," and "directly beneath" require at least some lateral overlap (i.e., horizontally) of the two stated areas / materials / components relative to each other. Additionally, the use of "above" without being preceded by "directly" requires only that some portion of the stated area / material / component that is above another stated area / material / component is vertically outside of the other stated area / material / component (i.e., regardless of whether there is any lateral overlap of the two stated areas / materials / components). Similarly, the use of "under" and "below" without being preceded by "directly" requires only that some portion of the stated area / material / component that is below another stated area / material / component is vertically inside of the other stated area / material / component (i.e., regardless of whether there is any lateral overlap of the two stated areas / materials / components).

[0070] Any of the materials, regions, and structures described herein may be uniform or non-uniform, and in any case may be continuous or discontinuous over any material it overlies. Where one or more example components are provided for any material, the material may include, consist essentially of, or consist of such one or more components. Furthermore, unless otherwise stated, each material may be formed using any suitable present or future developed technology, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0071] In addition, "thickness" (without directional adjectives in front) used alone is defined as the average straight-line distance perpendicularly passing through a given material or region from the closest surface of the adjacent material or adjacent region with different compositions. In addition, the various materials or regions described herein may have a substantially constant thickness or a variable thickness. If there is a variable thickness, unless otherwise indicated, the thickness refers to the average thickness, and such materials or regions will have a certain minimum thickness and a certain maximum thickness due to variable thickness. As used herein, "different compositions" only require that those parts of the two stated materials or regions that can directly abut against each other are chemically and / or physically different, such as in the case of such materials or regions being uneven. If the two stated materials or regions do not directly abut against each other, in the case of such materials or regions being uneven, "different compositions" only require that those parts of the two stated materials or regions that are closest to each other are chemically and / or physically different. In this document, when materials, regions or structures are in at least some physical contact relative to each other, the stated materials, regions or structures "directly abut" another material, region or structure. In contrast, "above," "on," "adjacent," "along," and "above" without "directly" encompasses "directly against" as well as configurations in which intervening materials, regions, or structures are such that the stated materials, regions, or structures are not in physical contact with each other.

[0072] Herein, region-material-components are "electrically coupled" relative to one another if, in normal operation, electrical current is able to flow continuously from one region-material-component to another region-material-component, and the flow occurs primarily through the movement of subatomic positive and / or negative charges when sufficient subatomic positive and / or negative charges are generated. Another electronic component may be between the region-material-components and electrically coupled to the region-material-components. In contrast, when region-material-components are referred to as "directly electrically coupled," there are no intervening electronic components (e.g., no diodes, transistors, resistors, transformers, switches, fuses, etc.) between the directly electrically coupled region-material-components.

[0073] "Rows" and "columns" are used in this document for the purpose of convenience in distinguishing features of one series or orientation from features of another series or orientation, and components have been or may be formed along such "rows" and "columns". "Rows" and "columns" are used synonymously with respect to any series of regions, components and / or features, regardless of function. Regardless, rows may be straight and / or curved and / or parallel and / or non-parallel relative to each other, as may columns. Furthermore, rows and columns may intersect at 90° relative to each other, or at one or more other angles (i.e., other than straight angles).

[0074] The components of any of the conductivity / conductor / conductive materials herein may be metallic materials and / or conductively doped semiconductive / semiconducting / semiconductive materials. "Metallic material" is any one or combination of elemental metals, any mixture or alloy of two or more elemental metals, and any one or more conductive metal compounds.

[0075] As used herein, any use of "selective" with respect to etching, removing, removal, deposition, forming, and / or formation is such action performed on one stated material relative to another stated material acted upon at a volume ratio of at least 2:1. Additionally, any use of selectively depositing, selectively growing, or selectively forming is deposition, growth, or formation of one material relative to another stated material or materials for at least the first 75 angstroms at a volume ratio of at least 2:1.

[0076] Unless otherwise indicated, the use of "or" herein includes either or both.

[0077] Summarize

[0078] In some embodiments, a method for forming a memory array including a memory cell string includes: forming a stack including a vertically alternating first layer and a second layer, including a memory block region having a channel material string. A conductor material contact is directly against the channel material of an individual channel material string. A first insulator material is formed directly above the conductor material contact. The first insulator material includes at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus, and (b): silicon carbide. A second insulator material is formed directly above the first insulator material and the conductor material contact. The second insulator material does not contain each of (a) and (b). A third insulator material is formed directly above the second insulator material, the first insulator material and the conductor material contact. The third insulator material includes at least one of (a) and (b). In the individual memory block region, at least one horizontally elongated isolation structure is formed in the first and second insulator materials and in the top portion of the stack.

[0079] In some embodiments, a method for forming a memory array including a memory cell string includes: forming a stack including a vertically alternating first layer and a second layer, wherein there is a channel material string. A conductor material contact directly abuts against the channel material of an individual channel material string. A first insulator material is formed directly above the conductor material contact. The first insulator material includes at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus, and (b): silicon carbide. A second insulator material is formed directly above the first insulator material and the conductor material contact. The second insulator material does not contain each of (a) and (b). A third insulator material is formed directly above the second insulator material, the first insulator material and the conductor material contact. The third insulator material includes at least one of (a) and (b). Conductive vias are formed through the first and second insulator materials that are individually directly abutted against individual conductor material contacts.

[0080] In some embodiments, a method for forming a memory array including a string of memory cells includes: forming a stack including a vertically alternating first layer and a second layer, including a memory block region having a string of channel material. In an individual memory block region, at least one horizontally elongated isolation structure is formed in a top portion of the stack. The isolation structure includes a lower horizontally elongated insulator material and an upper horizontally elongated insulator material thereover. The upper insulator material includes at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide. The lower insulator material does not contain each of (a) and (b).

[0081] In some embodiments, a method for forming a memory array including a memory cell string includes: forming a stack including a vertically alternating first layer and a second layer, including a memory block region having a channel material string. A conductor material contact directly abuts against the channel material of an individual channel material string. In the individual memory block region, at least one horizontally elongated isolation structure is in the top portion of the stack. An insulator material is formed directly above the conductor material contact and the at least one isolation structure. The insulator material includes at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus, and (b): silicon carbide. Conductive vias are formed through the insulator material that are individually directly abutted against the individual conductor material contacts.

[0082] In some embodiments, a memory array including a string of memory cells includes laterally spaced memory blocks, each of which includes a vertical stack including alternating insulating layers and conductive layers. The channel material of the memory cell string is in the stack. The conductor material contact is directly against the channel material of the individual channel material string. The insulator material is directly against the top of the conductor material contact. The insulator material includes at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus, and (b): silicon carbide.

[0083] In some embodiments, a memory array including a string of memory cells includes laterally spaced memory blocks, each of which includes a vertical stack including alternating insulating layers and conductive layers. The channel material string of the memory cells is in the stack. In an individual memory block, at least one horizontally elongated isolation structure is at the top portion of the stack. The isolation structure includes a lower horizontally elongated insulator material and an upper horizontally elongated insulator material above it. The upper insulator material includes at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus, and (b): silicon carbide. The lower insulator material does not contain each of (a) and (b).

[0084] As specified, the subject matter disclosed herein has been described in language more or less specific with respect to structural and methodological features. However, it is to be understood that the claims are not limited to the specific features shown and described, since the components disclosed herein include example embodiments. Therefore, the claims have the full scope as literally stated and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. A method for forming a memory array including a string of memory cells, comprising: forming a stack including vertically alternating first and second layers including a memory block region having strings of channel material with conductive material contacts directly abutting channel material of individual ones of the strings of channel material; forming a first insulator material directly over the conductor material contact, the first insulator material comprising at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide; forming a second insulator material directly over the first insulator material and the conductor material contact, the second insulator material being free of each of (a) and (b); forming a third insulator material directly over the second insulator material, the first insulator material, and the conductor material contact, the third insulator material comprising at least one of (a) and (b); as well as At least one horizontally elongated isolation structure is formed in the first and second insulator materials and in a top portion of the stack in individual ones of the memory block areas. 2 . The method of claim 1 , wherein the first insulator material directly abuts the conductor material contact. The method of claim 1 , wherein the second insulator material is directly against the first insulator material. The method of claim 1 , wherein the third insulator material is directly against the second insulator material.

5. The method according to claim 1, wherein: The first insulator material directly abuts against the conductive material contact; the second insulator material directly abuts the first insulator material; and The third insulator material is directly against the second insulator material. The method of claim 1 , wherein the first and third insulator materials have different compositions relative to each other.

7. The method of claim 1, wherein the first and third insulator materials have the same composition relative to each other. 8 . The method of claim 1 , wherein each of (a) and (b) is not included between the first insulator material and the third insulator material in a vertical direction.

9. The method of claim 1, wherein the first insulator material comprises (a).

10. The method of claim 1, wherein the first insulator material comprises (b).

11. The method of claim 1, wherein the third insulator material comprises the (a).

12. The method of claim 1, wherein the third insulator material comprises (b).

13. The method of claim 1, wherein the first layer comprises a sacrificial material, and the method further comprises: forming horizontally elongated trenches in the stack between the memory block regions; isotropically etching away the sacrificial material in the first layer through the trench and replacing it with conductive material of the respective conductive lines; as well as An intervening material is formed in the trench laterally between the laterally adjacent memory block regions and longitudinally along the memory block regions.

14. The method of claim 1, comprising forming conductive vias through the first and second insulator materials individually directly abutting individual ones of the conductor material contacts.

15. The method of claim 14, wherein forming the conductive via comprises: forming conductive via openings through the second and first insulator materials to individual ones of the conductor material contacts after forming the isolation structure; as well as Conductive material is formed in the conductive via opening directly against the individual conductor material contacts to form a conductive via.

16. The method of claim 15, wherein forming the conductive via opening comprises: anisotropically etching through the second insulator material selectively relative to the first insulator material using a first etch chemistry and stopping on or in the first insulator material; as well as The first insulator material is etched through using a second etch chemistry different from the first etch chemistry to expose the individual conductor material contacts.

17. The method of claim 1, comprising forming the at least one isolation structure to have a top portion that is higher than a top portion of the conductive material contact.

18. A method according to claim 1, wherein the isolation structure includes a lower horizontally elongated insulator material and an upper horizontally elongated insulator material thereover, the upper horizontally elongated insulator material including at least one of (a) and (b), and the lower horizontally elongated insulator material does not contain either of (a) and (b).

19. A method for forming a memory array comprising strings of memory cells, comprising: forming a stack comprising vertically alternating first and second layers having strings of channel material therein, with conductor material contacts directly abutting the channel material of individual ones of the strings of channel material; forming a first insulator material directly over the conductor material contact, the first insulator material comprising at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide; forming a second insulator material directly over the first insulator material and the conductor material contact, the second insulator material being free of each of (a) and (b); forming a third insulator material directly over the second insulator material, the first insulator material, and the conductor material contact, the third insulator material comprising at least one of (a) and (b); as well as Conductive vias are formed through the first and second insulator materials, individually and directly abutting individual ones of the conductor material contacts.

20. The method of claim 19, wherein forming the conductive via comprises: forming conductive via openings through the second and first insulator materials to individual ones of the conductor material contacts; as well as Conductive material is formed in the conductive via opening directly against the individual conductor material contacts.

21. The method of claim 20, comprising removing the third insulator material prior to forming the conductive via opening, whereby the conductive via opening is not formed through the third insulator material.

22. The method of claim 20, wherein forming the conductive via opening comprises: anisotropically etching through the second insulator material selectively relative to the first insulator material using a first etch chemistry and stopping on or in the first insulator material; as well as The first insulator material is etched through using a second etch chemistry different from the first etch chemistry to expose the individual conductor material contacts.

23. The method of claim 19, wherein the alternating first and second layers include memory block regions, and the method further comprises: At least one horizontally elongated isolation structure is formed in individual ones of the memory block areas through the first and second insulator materials and in a top portion of the stack.

24. The method of claim 23, comprising forming the isolation structure to include a lower horizontally elongated insulator material and an upper horizontally elongated insulator material thereover, the upper horizontally elongated insulator material including at least one of (a) and (b), the lower horizontally elongated insulator material not containing either of (a) and (b).

25. The method of claim 23, comprising forming the at least one isolation structure to have a top portion that is higher than a top portion of the conductive material contact.

26. A method for forming a memory array comprising strings of memory cells, comprising: forming a stack including vertically alternating first and second layers including a memory block region having strings of channel material; as well as In individual ones of the memory block areas, at least one horizontally elongated isolation structure is formed in the top portion of the stack, the isolation structure comprising a lower horizontally elongated insulator material and an upper horizontally elongated insulator material thereover, the upper horizontally elongated insulator material comprising at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus, and (b): silicon carbide, the lower horizontally elongated insulator material not containing any of (a) and (b).

27. The method of claim 26, wherein the upper horizontally elongated insulator material comprises (a).

28. The method of claim 26, wherein the upper horizontally elongated insulator material comprises (b).

29. A method for forming a memory array comprising strings of memory cells, comprising: forming a stack comprising vertically alternating first and second layers, including a memory block region having strings of channel material, a conductor material contact directly abutting the channel material of individual ones of the strings of channel material, at least one horizontally elongated isolation structure in a top portion of the stack in individual ones of the memory block regions; forming an insulator material directly over the conductor material contact and the at least one isolation structure, the insulator material comprising at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron, and phosphorus, and (b): silicon carbide; and Conductive vias are formed through the insulator material that are individually and directly abutting individual ones of the conductor material contacts.

30. The method of claim 29, wherein the insulator material directly abuts the conductor material contact.

31. The method of claim 29, wherein the insulator material is directly against the at least one isolation structure.

32. The method of claim 29, wherein: The insulator material directly abuts the conductor material contact; and The insulator material is directly against the at least one isolation structure.

33. The method of claim 29, wherein the insulator material comprises (a).

34. The method of claim 29, wherein the insulator material comprises (b).

35. The method of claim 29, comprising forming an insulating material directly over the insulator material, The insulating material does not contain any of (a) and (b), and the forming of the conductive via includes: forming conductive via openings through the insulating material and the insulator material to individual ones of the conductive material contacts; as well as forming a conductive material in the conductive via opening directly against the individual conductor material contacts; as well as The forming of the conductive via opening comprises: anisotropically etching through the insulating material selectively relative to the insulator material using a first etch chemistry to stop on or in the insulator material; as well as etching through the insulator material using a second etch chemistry different from the first etch chemistry, To expose the individual conductive material contacts.

36. A memory array comprising a string of memory cells, comprising: laterally spaced memory blocks, each comprising a vertical stack including alternating insulating and conductive layers, strings of channel materials of memory cells in the stack, and conductor material contacts directly against channel material of individual ones of the strings of channel materials; as well as An insulator material directly against the top of the conductor material contact, the insulator material comprising at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus, and (b): silicon carbide.

37. The memory array of claim 36 wherein the insulator material comprises the (a).

38. The memory array of claim 36 wherein the insulator material comprises the (b).

39. A memory array comprising a string of memory cells, comprising: laterally spaced memory blocks, each comprising a vertical stack of alternating insulating and conductive layers, with strings of channel material for memory cells in the stack; as well as At least one horizontally elongated isolation structure in a top portion of the stack in an individual one of the memory blocks, the isolation structure comprising a lower horizontally elongated insulator material and an upper horizontally elongated insulator material thereover, the upper horizontally elongated insulator material comprising at least one of (a) and (b), wherein (a): silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus, and (b): silicon carbide, the lower horizontally elongated insulator material not containing each of (a) and (b).

40. The memory array of claim 39 wherein the upper horizontally elongated insulator material comprises said (a).

41. The memory array of claim 39 wherein said upper horizontally elongated insulator material comprises said (b).

42. The memory array of claim 39 wherein in the individual memory blocks, the at least one isolation structure is laterally between two laterally adjacent select gates.

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