Thin film transistor, manufacturing method thereof, display substrate, and display device

Abstract

A thin-film transistor, a method for manufacturing the same, a display substrate, and a display device. The thin-film transistor comprises an active layer, a gate electrode, a source electrode, a drain electrode, and a carrier injector disposed on a substrate. The active layer comprises a source region, a drain region, a channel region, and a carrier injection region. The source electrode is electrically connected to the source region, the drain electrode is electrically connected to the drain region, and the carrier injector is electrically connected to the carrier injection region. The carrier injection region has a different polarity from the source and drain regions. The thin-film transistor provided in the disclosed embodiments injects carriers into the channel via the carrier injection region, thereby suppressing device degradation and improving device service life.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to, but are not limited to, display technology, and in particular to a thin film transistor and a manufacturing method thereof, a display substrate, and a display device. Background Art

[0002] Low-temperature polysilicon (LTPS) thin-film transistors (TFTs) have gradually become the mainstream choice for flat-panel displays due to their high electron mobility, low power consumption, fast response, and flexible display capabilities. However, TFT performance directly impacts display quality. In actual use, variations in gate electrode voltage can easily cause hot carrier degradation in TFTs, leading to TFT degradation. Summary of the Invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] The embodiments of the present disclosure provide a thin film transistor and a method for manufacturing the same, a display substrate, and a display device, thereby improving the performance of the thin film transistor.

[0005] On the one hand, an embodiment of the present disclosure provides a thin film transistor, which includes an active layer, a gate electrode, a source electrode, a drain electrode and a carrier injection electrode arranged on a substrate, the active layer includes a source region, a drain region, a channel region and a carrier injection region, the source electrode is electrically connected to the source region, the drain electrode is electrically connected to the drain region, the carrier injection electrode is electrically connected to the carrier injection region, and the carrier injection region has a different polarity from the source region and the drain region.

[0006] In an exemplary embodiment, the side of the channel region close to the gate electrode is a first side, the source region is arranged on a second side of the channel region, the drain region is arranged on a third side of the channel region, and the carrier injection region is arranged on at least one side of the channel region except the first side, the second side, and the third side.

[0007] In an exemplary embodiment, the carrier injection electrode is provided in the same layer as the source electrode and the drain electrode; or, the carrier injection electrode is provided in a different layer from the source electrode and the drain electrode.

[0008] In an exemplary embodiment, the source region is heavily doped with a first polarity, the drain region is heavily doped with a first polarity, and the carrier injection region is heavily doped with a second polarity.

[0009] In an exemplary embodiment, the gate electrode is connected to a first power supply terminal, the carrier injection electrode is connected to a second power supply terminal, the thin film transistor is an N-type thin film transistor, and when the voltage of the first power supply terminal is in a falling edge period, the voltage of the second power supply terminal is a ground voltage or a positive voltage; or, the thin film transistor is a P-type thin film transistor, and when the voltage of the first power supply terminal is in a rising edge period, the voltage of the second power supply terminal is a ground voltage or a negative voltage.

[0010] On the other hand, embodiments of the present disclosure provide a display substrate comprising the above-mentioned thin film transistor.

[0011] On the other hand, an embodiment of the present disclosure provides a display device including the above-mentioned display substrate.

[0012] In another aspect, the present disclosure provides a method for manufacturing a thin film transistor, comprising:

[0013] An active layer and a gate electrode are formed on a substrate, wherein the active layer includes a source region, a drain region, a channel region and a carrier injection region, and the carrier injection region has a different polarity from the source region and the drain region;

[0014] A source electrode, a drain electrode, and a carrier injection electrode are formed, wherein the source electrode is electrically connected to the source region, the drain electrode is electrically connected to the drain region, and the carrier injection electrode is electrically connected to the carrier injection region.

[0015] In one exemplary embodiment, forming an active layer on a substrate includes:

[0016] forming a polysilicon pattern on a substrate;

[0017] performing first polarity doping on the polysilicon pattern to form a source region and a drain region;

[0018] The polysilicon pattern is doped with a second polarity to form a carrier injection region.

[0019] In an exemplary embodiment, forming a source electrode, a drain electrode, and a carrier injection electrode includes:

[0020] A metal film is deposited, and the source electrode, the drain electrode, and the carrier injection electrode are formed through a single patterning process.

[0021] The embodiments of the present application include a thin film transistor and a method for manufacturing the same, a display substrate, and a display device. The thin film transistor includes an active layer, a gate electrode, a source electrode, a drain electrode, and a carrier injection electrode disposed on a substrate. The active layer includes a source region, a drain region, a channel region, and a carrier injection region. The source electrode is electrically connected to the source region, the drain electrode is electrically connected to the drain region, and the carrier injection electrode is electrically connected to the carrier injection region. The carrier injection region has a different polarity from the source region and the drain region. The thin film transistor provided by the embodiments of the present disclosure injects carriers into the channel through the carrier injection region, thereby suppressing device degradation and improving device service life.

[0022] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained through the structures particularly pointed out in the description and the drawings.

[0023] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are used to provide a further understanding of the technical solution of the present invention and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present invention and do not constitute a limitation on the technical solution of the present invention.

[0025] Figure 1 A schematic diagram of a thin film transistor provided in an embodiment of the present disclosure;

[0026] Figure 2 for Figure 1 A front view of the thin film transistor shown;

[0027] Figure 3 for Figure 1 A side view of the thin film transistor shown;

[0028] Figure 4 for Figure 1 A top view of the thin film transistor shown;

[0029] Figure 5 A schematic diagram of a carrier injection region injecting holes into a channel region in a thin film transistor provided in an exemplary embodiment;

[0030] Figure 6 is a cross-sectional view after a polysilicon active layer pattern is formed in an exemplary embodiment;

[0031] Figure 7 is another cross-sectional view after forming a polysilicon active layer pattern in an exemplary embodiment;

[0032] Figure 8is a top view after a polysilicon active layer pattern is formed in an exemplary embodiment;

[0033] Figure 9 is a cross-sectional view after forming a second insulation layer pattern in an exemplary embodiment;

[0034] Figure 10 is another cross-sectional view after forming a second insulating layer in an exemplary embodiment;

[0035] Figure 11 is a top view after a gate electrode pattern is formed in an exemplary embodiment;

[0036] Figure 12 A flow chart of a method for fabricating a thin film transistor according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0037] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. In the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other in any manner.

[0038] The steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions. Also, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be performed in an order different from that shown here.

[0039] Unless otherwise defined, technical or scientific terms used in the present disclosure should have the same meaning as commonly understood by one of ordinary skill in the art to which the invention belongs.

[0040] In the drawings, the sizes of various components, layer thicknesses, or regions are sometimes exaggerated for clarity. Therefore, the embodiments of the present disclosure are not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and the embodiments of the present disclosure are not limited to the shapes or values shown in the drawings.

[0041] In the present disclosure, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.

[0042] In this disclosure, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it should not be understood as a limitation of this disclosure. The positional relationships of constituent elements may be appropriately changed according to the direction in which each constituent element is described. Therefore, the words and phrases described in this disclosure are not limited and may be appropriately replaced according to the circumstances.

[0043] In this disclosure, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure based on the specific circumstances.

[0044] In this disclosure, a transistor refers to an element comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0045] In the present disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or the first electrode may be the source electrode and the second electrode may be the drain electrode. The functions of the "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarities or when the direction of current changes during circuit operation. Therefore, in the present disclosure, the terms "source electrode" and "drain electrode" may be interchanged.

[0046] In this disclosure, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0047] In this disclosure, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0048] In LTPS TFT, the gate voltage is usually an alternating voltage. During long-term use, N-type TFT is prone to TFT deterioration due to the hot carrier effect. In current actual circuit design, appropriate circuit compensation technology is usually used to eliminate the characteristic drift during the period, such as 4T1C, 6T1C, 7T1C, etc. Increasing the number of TFTs in the compensation circuit can achieve more accurate compensation, but at the same time it will increase the complexity of the driving circuit and the power consumption will also increase. As display technology develops towards high definition, high image quality, and high refresh rate, the operating frequency of the corresponding pixel driving circuit will be higher, and the degradation of the device will be more serious. The compensation circuit can only alleviate the deterioration of the device to a certain extent. In the embodiment of the present disclosure, suppressing TFT deterioration at the device level can increase the service life of the device and reduce the complexity of the compensation circuit.

[0049] The disclosed embodiments provide a thin-film transistor that incorporates a carrier injector in addition to the gate, source, and drain electrodes. The carrier injection region corresponding to the carrier injector can inject carriers into the channel region when the gate electrode voltage changes. The carriers diffuse toward the source and drain regions, eliminating channel imbalances and suppressing dynamic hot carrier degradation in the device, thereby suppressing device degradation and increasing device lifespan.

[0050] Figure 1 A schematic diagram of the three-dimensional structure of a thin film transistor provided in an embodiment of the present disclosure. Figure 2 for Figure 1 A front view of the thin film transistor shown; Figure 3 for Figure 1 A side view of a thin film transistor is shown, Figure 4 for Figure 1 A top view of a thin film transistor is shown. Figure 1 This is just a schematic diagram, showing only part of the film layers of the thin film transistor, and some film layers are omitted. Figure 1 、 2As shown in Figures 3 and 4, the thin film transistor provided by the embodiment of the present disclosure includes: a substrate 1, a light shielding layer 2 arranged on the substrate 1, a buffer layer 3 arranged on the side of the light shielding layer 2 away from the substrate 1, an active layer arranged on the side of the buffer layer 3 away from the substrate 1, a first insulating layer 7 arranged on the side of the active layer away from the substrate 1, a gate electrode 8 arranged on the side of the first insulating layer 7 away from the substrate 1, a second insulating layer 9 arranged on the side of the gate electrode 8 away from the substrate 1, and a gate electrode 8 arranged on the side of the second insulating layer 9 away from the substrate. The drain electrode 10, source electrode 11, and carrier injector 12 on one side of the bottom 1 are provided. The active layer may include a source-drain region 4, a channel region 5, and a carrier injector 6. The source-drain region 4 may include a source region 42 and a drain region 41. The channel region 5 is disposed between the source region 42 and the drain region 41. The drain electrode 10 is connected to the drain region 41 via a first via 13. The source electrode 11 is connected to the source region 42 via another first via 13. The carrier injector 12 is connected to the carrier injector 6 via a second via 14. The active layer may be a polycrystalline silicon active layer, but is not limited thereto. The carrier injector 6 has a different polarity from the source region 42 and the drain region 41. The source region 42 and the drain region 41 have the same polarity.

[0051] The first insulating layer 7 is also called a gate insulating layer, and the second insulating layer 9 is also called an interlayer dielectric layer.

[0052] The polarity refers to P-type or N-type. The source region 42 and the drain region 41 can be of the first polarity, and the carrier injection region can be of the second polarity. For example, in an N-type thin film transistor, the source region 42 and the drain region 41 can be N-type doped, and the carrier injection region 6 can be P-type doped. In a P-type thin film transistor, the source region 42 and the drain region 41 can be P-type doped, and the carrier injection region 6 can be N-type doped.

[0053] The embodiments of the present disclosure are described using an N-type TFT device as an example, referred to as a four-terminal N-type TFT device. In a four-terminal N-type TFT device, the introduction of a carrier injector does not affect the normal operation of the device. When the gate electrode voltage is at the falling edge, the P+N junction formed by the P-type carrier injector and the intrinsic conductive channel is forward biased, allowing the carrier injector to inject holes into the channel region. The injected holes diffuse toward the source and drain, thereby suppressing device degradation and extending the device's service life.

[0054] In an exemplary embodiment, the source region 42 and the drain region 41 may include heavily doped regions, and the carrier injection region may include heavily doped regions. For example, in an N-type thin film transistor, the source region 42 and the drain region 41 may be N+ doped regions, and the carrier injection region may be P+ doped regions; in a P-type thin film transistor, the source region 42 and the drain region 41 may be P+ doped regions, and the carrier injection region may be N+ doped regions.

[0055] In another exemplary embodiment, the source region 42 and the drain region 41 may include a heavily doped region and a lightly doped region (a region with an impurity concentration one order of magnitude lower than that of the heavily doped region). For example, in an N-type thin film transistor, the source region 42 may include an N+ doped region and an N- doped region, and the N- doped region is located between the N+ doped region and the channel region; the drain region 41 may include an N+ doped region and an N- doped region, and the N- doped region is located between the N+ doped region and the channel region. Providing a lightly doped region is equivalent to connecting a large resistor in series between the source, drain, and channel, reducing the horizontal electric field of the channel, reducing the hot carriers generated by impact ionization caused by electric field acceleration, and effectively suppressing leakage current. When the source region 42 and the drain region 41 are not provided with lightly doped regions, the process can be reduced and the cost can be reduced.

[0056] In an exemplary embodiment, the side of the channel region 5 close to the gate electrode 8 is referred to as the first side, the source region 42 is disposed on the second side of the channel region 5, the drain region 41 is disposed on the third side of the channel region 5, and the carrier injection region 6 may be disposed on at least one side of the channel region 5 except the first side, the second side, and the third side. For example, Figure 1 As shown, the thin film transistor can be a top-gate thin film transistor, with the gate electrode 8 disposed on the upper side (first side) of the channel region 5. The source region 42 and the drain region 41 are respectively located on the left and right sides (second side and third side) of the channel region, and the carrier injection region 6 can be disposed on the front side of the channel region 5. In another embodiment, the carrier injection region 6 can be disposed on the rear side or lower side of the channel region 5, or the carrier injection region 6 can be disposed on one or more of the front side, rear side, and lower side of the channel region 5. The front side and the rear side are opposite to each other.

[0057] In an exemplary embodiment, the thin film transistor can be a bottom-gate thin film transistor, and the gate electrode 8 is located on the side of the channel region 5 close to the substrate, that is, when the gate electrode 8 is located on the lower side of the channel region 5, the carrier injection region 6 can be arranged on one or more sides of the front side, rear side, and upper side of the channel region 5.

[0058] In an exemplary embodiment, the substrate 1 may be a rigid substrate, or a flexible substrate or a substrate of other properties. The material of the rigid substrate may be, for example, glass or quartz. The material of the flexible substrate may be, for example, polyimide (PI), polyethylene terephthalate (PET), triacetyl cellulose (TAC), cycloolefin polymer (COP), or colorless polyimide (CPI), or other suitable materials, which are not limited in the present embodiment.

[0059] In an exemplary embodiment, the material of the first insulating layer 7 and the second insulating layer 9 may be, for example, silicon nitride (SiNx), silicon oxide (SiOx), aluminum oxide (Al2O3), aluminum nitride (AlN), etc. The material of the gate electrode may be, for example, aluminum (Al), copper (Cu), etc.

[0060] In one exemplary embodiment, the orthographic projection of the active layer lies within the orthographic projection of the light-shielding layer 2 on a plane parallel to the substrate 1. Because the channel region 5 of the thin-film transistor is made of a semiconductor material, the performance of semiconductor materials can become unstable when exposed to light (e.g., ambient light), causing the thin-film transistor to experience negative drift. This means that the threshold voltage of the thin-film transistor changes, thereby affecting its performance. The light-shielding layer 2 shields the active layer from the effects of light, thereby improving the performance of the thin-film transistor.

[0061] In an exemplary embodiment, the light shielding layer 2 may not be provided in the display substrate. For example, an organic light emitting diode (OLED) display device may not be provided with the light shielding layer 2 .

[0062] In an exemplary embodiment, the material of the light-shielding layer 2 may be, for example, a metal material, and the metal material may be, for example, an opaque metal or alloy such as aluminum (Al), copper (Cu), titanium (Ti), molybdenum (Mu); or it may be other opaque materials, which is not limited in the embodiment of the present disclosure.

[0063] In one exemplary embodiment, the material of the buffer layer 3 may be, for example, silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (Si(ON)x), etc. The buffer layer 3 may planarize the light shielding layer 2 and prevent the light shielding layer 2 from contacting the active layer.

[0064] In an exemplary embodiment, the active layer may be a polysilicon active layer, but is not limited thereto and may be other types of active layers, such as an active layer composed of amorphous silicon, zinc oxynitride ZnON, indium zinc tin oxide IZTO, etc.

[0065] In an exemplary embodiment, the active layer can be formed by doping the active layer thin film. Taking the N-type thin film transistor as an example, after forming the polysilicon pattern, pentavalent elements can be doped to form the N-type source region 42 and drain region 41, and then trivalent elements can be doped to form the P-type carrier injection region 6. For example, B can be doped. 3+ Alternatively, a trivalent element may be doped first to form the P-type carrier injection region 6 , and then a pentavalent element may be doped to form the N-type source region 42 and drain region 41 .

[0066] In an exemplary embodiment, the carrier injection electrode 12 may be provided in the same layer as the source electrode 11 and the drain electrode 10 , or may be provided in a different layer.

[0067] In an exemplary embodiment, the source electrode 11, the drain electrode 10, and the carrier injection electrode 12 can be made of metal materials, such as silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), etc., or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd), molybdenum-niobium alloy (MoNb), etc., and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0068] In an exemplary embodiment, the carrier injection electrode 12 can be in a suspended, grounded, negatively biased, or weakly positively biased state. The gate electrode 8 is connected to a first power supply terminal, the carrier injection electrode 12 is connected to a second power supply terminal, the thin film transistor is an N-type thin film transistor, and when the voltage of the first power supply terminal is in a falling edge period, the voltage of the second power supply terminal is at or above the ground voltage; in this case, the carrier injection electrode can more effectively suppress degradation. Alternatively, the thin film transistor is a P-type thin film transistor, and when the voltage of the first power supply terminal is in a rising edge period, the voltage of the second power supply terminal is at or below the ground voltage. In this case, the carrier injection electrode can more effectively suppress degradation.

[0069] For LTPS TFTs, the gate electrode voltage is an alternating voltage, and N-type TFTs are prone to deterioration due to the hot carrier effect. When the gate electrode voltage drops, the conductive channel should be in a hole accumulation state, but the intrinsic polysilicon channel can only generate holes through thermal excitation, and the hole thermal excitation time is long, much longer than the time of the gate falling edge, resulting in the channel being in an unbalanced depletion state. During the time of the gate electrode falling edge, the potential of the channel region is at a negative potential, causing the PN+ junction at the drain end to be in a reverse biased state. The depletion region expands to the channel region through ionization emission of defect states. The carriers emitted by ionization of deep energy level defect states are exposed to the strong electric field in the depletion region and are accelerated by the electric field to form hot carriers, which leads to dynamic hot carrier deterioration during the TFT period.

[0070] In a four-terminal TFT device, the P+ doped carrier injection region forms a P+N junction with the intrinsic channel. During the time when the gate electrode voltage falls, the potential of the channel region is at a negative potential. When the carrier injection electrode is grounded or weakly forward biased, the P+N junction is in a forward biased state. The carrier injection region can inject holes into the channel region, and the injected holes diffuse toward the source region 42 and the drain region 41, thereby eliminating the non-equilibrium state of the channel region and suppressing the dynamic hot carrier deterioration of the device. Figure 5 As shown, Figure 5 In the figure, S(N+) is the N+ source region 42, and D(N+) is the N+ drain region 41. Holes and electrons exist in the carrier injection region 6. When the carrier injection electrode is left floating, the P+N junction cannot inject holes, so hot carrier degradation cannot be suppressed. When the carrier injection electrode is at a negative voltage, holes can only be injected instantaneously when the potential of the channel region is more negative than the voltage of the carrier injection electrode. Therefore, a weak positive bias at the carrier injection electrode is more effective in suppressing degradation than a negative bias.

[0071] The structure of the thin film transistor of this embodiment is described below through the preparation process of the thin film transistor. Among them, the "composition process" mentioned in the embodiment of the present disclosure includes processes such as depositing a film layer, coating a photoresist, mask exposure, development, etching and stripping the photoresist. Deposition can be carried out by any one or more selected from sputtering, evaporation and chemical vapor deposition, coating can be carried out by any one or more selected from spray coating and spin coating, and etching can be carried out by any one or more selected from dry etching and wet etching. "Thin film" refers to a layer of thin film made by a deposition or coating process on a substrate of a certain material. If the "thin film" does not require a composition process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" still requires a composition process during the entire production process, it is called a "thin film" before the composition process and a "layer" after the composition process. The "layer" after the composition process contains at least one "pattern". "A and B are arranged in the same layer" in the embodiment of the present disclosure means that A and B are formed simultaneously through the same composition process.

[0072] The thin film transistor preparation process includes:

[0073] Depositing a first metal film on the substrate and patterning it to form a light shielding layer 2; depositing a buffer layer film and patterning it to form a buffer layer 3;

[0074] Depositing an amorphous silicon thin film, laser annealing the amorphous silicon thin film to generate a polycrystalline silicon thin film, and patterning the polycrystalline silicon thin film to form a polycrystalline silicon pattern. The laser can be a XeCl laser, ArF laser, KrF laser, or XeF laser. These excimer lasers generate a laser beam in the ultraviolet band. When a short pulse laser beam in the ultraviolet band is irradiated on the amorphous silicon thin film, the amorphous silicon thin film will quickly absorb the laser energy and melt and recrystallize. In another embodiment, the amorphous silicon pattern can be formed first by patterning, and then laser annealing can be performed to generate a polycrystalline silicon pattern.

[0075] Doping the polysilicon pattern includes: coating a photoresist on the substrate formed with the polysilicon pattern, performing exposure and development, forming an unexposed area in the channel region and the carrier injection region, performing a first ion implantation process, and implanting N-type ions for N-type thin film transistors. The N-type ions can be phosphorus ions to form an N+ doped source region 42 and a drain region 41, and stripping the photoresist; the channel region 5 is formed between the source region 42 and the drain region 41;

[0076] A photoresist is coated on the above structure, and exposure and development are performed to form unexposed areas in the channel region, the source region 42, and the drain region 41. A second ion implantation process is performed. For N-type thin film transistors, P-type ion implantation is performed. P-type ions can be implanted using B 3+ , forming a P+ doped carrier injection region 6, stripping the photoresist, forming a polysilicon pattern including a source region 42, a drain region 41 and a carrier injection region 6; Figure 6 、 Figure 7 and Figure 8 shown.

[0077] A first insulating film and a gate metal film are sequentially deposited on the aforementioned structure, and a first insulating layer 7 and a gate electrode 8 are formed by patterning. A second insulating film is deposited and patterned to form a second insulating layer 9. The second insulating layer 9 is provided with a first via hole 13 and a second via hole 14. The second insulating layer 9 and the first insulating layer 7 in the first via hole 13 are etched away to expose the source region 42 and the drain region 41. The second insulating layer 9 and the first insulating layer 7 in the second via hole 14 are etched away to expose the carrier injection region 6. Figure 9 、 Figure 10 and Figure 11 shown.

[0078] A second metal film is deposited and patterned to form a source electrode 11, a drain electrode 10, and a carrier injection electrode 12. The source electrode 11 is electrically connected to the source region 42 through a first via 13, the drain electrode 10 is electrically connected to the drain region 41 through another first via 13, and the carrier injection electrode 12 is electrically connected to the carrier injection region 6 through a second via 14, thereby forming an LTPS thin film transistor. Figure 2 、 Figure 3 and Figure 4 shown.

[0079] The display substrate provided in this embodiment adds a carrier injection region and a carrier injection electrode. The carrier injection region corresponding to the carrier injection electrode can inject carriers into the channel region when the gate electrode voltage changes. The carriers diffuse toward the source region 42 and the drain region 41, eliminating the non-equilibrium state of the channel and suppressing the dynamic hot carrier deterioration of the device, thereby achieving the effect of suppressing device degradation and improving the service life of the device.

[0080] The preparation process of the embodiment of the present disclosure can be realized by using existing mature preparation equipment, with minor improvements to the existing process, and is well compatible with the LTPS preparation process. The process is simple to realize, easy to implement, with high production efficiency, low production cost and high yield rate.

[0081] The embodiment of the present disclosure provides a display substrate including the above-mentioned thin film transistor. The display substrate provided by this embodiment uses the above-mentioned thin film transistor. Due to the improved performance of the thin film transistor, the number of thin film transistors used for compensation can be reduced, thereby reducing the complexity of the compensation circuit.

[0082] The present disclosure also provides a display device comprising the display substrate of the aforementioned embodiment. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system. The display device can be a liquid crystal display, an organic light-emitting diode display, or the like.

[0083] Figure 12 Flowchart of a method for preparing a thin film transistor provided by an embodiment of the present disclosure. Figure 12 As shown, the method for manufacturing a thin film transistor provided by the embodiment of the present disclosure may include:

[0084] Step 1201: forming an active layer and a gate electrode on a substrate, wherein the active layer includes a source region, a drain region, a channel region, and a carrier injection region, wherein the carrier injection region has a different polarity from the source region and the drain region;

[0085] In an exemplary embodiment, the active layer may be formed first and then the gate electrode; or the gate electrode may be formed first and then the active layer.

[0086] Step 1202 , forming a source electrode, a drain electrode and a carrier injection electrode, wherein the source electrode is electrically connected to the source region, the drain electrode is electrically connected to the drain region, and the carrier injection electrode is electrically connected to the carrier injection region.

[0087] In one exemplary embodiment, forming an active layer on a substrate may include:

[0088] patterning a polysilicon pattern on a substrate;

[0089] performing first polarity doping on the polysilicon pattern to form a source region and a drain region;

[0090] The polysilicon pattern is doped with a second polarity to form a carrier injection region.

[0091] In an exemplary embodiment, the source region and the drain region may be formed first, and then the carrier injection region may be formed; or, the carrier injection region may be formed first, and then the source region and the drain region may be formed.

[0092] In an exemplary embodiment, forming a source electrode, a drain electrode, and a carrier injection electrode may include:

[0093] A metal film is deposited, and the source electrode, the drain electrode, and the carrier injection electrode are formed through a single patterning process.

[0094] Although the embodiments disclosed herein are as described above, the contents described herein are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. Any person skilled in the art may make any modifications and variations in the form and details of the embodiments without departing from the spirit and scope of the present invention. However, the scope of patent protection of the present invention shall remain subject to the scope defined by the appended claims.

Claims

1. A thin film transistor, characterized in that: The thin film transistor includes an active layer, a gate electrode, a source electrode, a drain electrode and a carrier injection electrode provided on a substrate, the active layer includes a source region, a drain region, a channel region and a carrier injection region, the source electrode is electrically connected to the source region, the drain electrode is electrically connected to the drain region, the carrier injection electrode is electrically connected to the carrier injection region, the carrier injection region has a different polarity from the source region and the drain region, and a P+N junction is formed between the channel region and the carrier injection region; The side of the channel region close to the gate electrode is a first side, which is the upper side; the source region is arranged on a second side of the channel region, which is the left side; the drain region is arranged on a third side of the channel region, which is the right side; and the carrier injection region is arranged on at least one of the front side and the back side of the channel region except the first side, the second side, and the third side; The gate electrode is connected to a first power supply terminal, the carrier injection electrode is connected to a second power supply terminal, the thin film transistor is an N-type thin film transistor, when the voltage of the first power supply terminal is in a falling edge period, the voltage of the second power supply terminal is a ground voltage or a positive voltage, and when the gate electrode voltage is in a falling edge, the P+N junction formed by the P-type carrier injection electrode and the intrinsic conductive channel region is forward biased.

2. The thin film transistor according to claim 1, wherein The carrier injection electrode is provided in the same layer as the source electrode and the drain electrode; or, the carrier injection electrode is provided in a different layer from the source electrode and the drain electrode.

3. The thin film transistor according to claim 1, wherein The source region is heavily doped with a first polarity, the drain region is heavily doped with a first polarity, and the carrier injection region is heavily doped with a second polarity.

4. A display substrate, characterized in that: The thin film transistor comprises the thin film transistor according to any one of claims 1 to 3.

5. A display device, characterized in that: The display substrate comprises the display substrate as claimed in claim 4.

6. A method for preparing a thin film transistor, characterized in that: include: An active layer and a gate electrode are formed on a substrate, wherein the active layer includes a source region, a drain region, a channel region, and a carrier injection region, wherein the carrier injection region has a different polarity from the source region and the drain region, and a P+N junction is formed between the channel region and the carrier injection region; forming a source electrode, a drain electrode, and a carrier injection electrode, wherein the source electrode is electrically connected to the source region, the drain electrode is electrically connected to the drain region, and the carrier injection electrode is electrically connected to the carrier injection region; The side of the channel region close to the gate electrode is a first side, which is the upper side; the source region is arranged on a second side of the channel region, which is the left side; the drain region is arranged on a third side of the channel region, which is the right side; and the carrier injection region is arranged on at least one of the front side and the back side of the channel region except the first side, the second side, and the third side; The gate electrode is connected to a first power supply terminal, the carrier injection electrode is connected to a second power supply terminal, the thin film transistor is an N-type thin film transistor, when the voltage of the first power supply terminal is in a falling edge period, the voltage of the second power supply terminal is a ground voltage or a positive voltage, and when the gate electrode voltage is in a falling edge, the P+N junction formed by the P-type carrier injection electrode and the intrinsic conductive channel region is forward biased.

7. The method for preparing a thin film transistor according to claim 6, wherein: The forming of an active layer on the substrate comprises: forming a polysilicon pattern on a substrate; performing first polarity doping on the polysilicon pattern to form the source region and the drain region; The polysilicon pattern is doped with a second polarity to form the carrier injection region.

8. The method for preparing a thin film transistor according to claim 6 or 7, wherein: The forming of the source electrode, the drain electrode and the carrier injection electrode comprises: A metal film is deposited, and the source electrode, the drain electrode, and the carrier injection electrode are formed through a single patterning process.

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