Decoding method and apparatus, network device, and storage medium

Abstract

The application provides a decoding method and device, a network device and a storage medium. The method comprises the following steps: receiving pre-deinterleaving data and soft bit coding positions; dividing the pre-deinterleaving data to obtain a first data unit; obtaining punctured data, and obtaining a second data unit according to the punctured data, wherein the pre-deinterleaving data and the punctured data are determined in coded data according to the soft bit coding positions; and decoding according to the soft bit coding positions, the first data unit and the second data unit to obtain decoded data. The application can improve the rate matching and decoding efficiency.

Description

Technical Field

[0001] This application relates to the field of communications, specifically to a decoding method, apparatus, network device, and storage medium. Background Technology

[0002] In communication systems, rate matching adjusts the bit rate output by the channel encoder to ensure that the number of bits output by the rate matching module matches the number of bits that the system's allocated physical resources can support. Rate matching is typically accompanied by interleaving, which scrambles the coded data to discretize errors when they occur, reducing the difficulty of error correction and thus protecting the coded data to improve the stability of coding performance.

[0003] The 3GPP NR protocol uses Low Density Parity Check (LDPC) coding in uplink and downlink traffic channels. After coding, rate matching is performed first, followed by interleaving. These processes are all performed on a code block (CB) basis. Rate matching uses a circular buffer-based rate matching mechanism, and interleaving uses the commonly used R-row C-column grouped interleaving. Deinterleaving and de-rate matching are the inverse processes of rate matching and interleaving. To meet throughput requirements, LDPC decoding typically reads Zc soft bits per cycle for processing. This means that the de-rate matching or decoder needs to combine Zc soft bits together, indirectly requiring the de-rate matching process to have x / Z... c Or x%Z c Equal addressing operation, where x is the position of the soft bit in the decoder, and Z... c The lifting factor used for LDPC encoding has eight possible values, all of which are prime numbers, making this addressing operation complex to implement. Summary of the Invention

[0004] This application provides decoding methods, apparatus, network devices, and storage media.

[0005] This application provides a decoding method, including:

[0006] Receive the data before deinterleaving and the soft bit encoding position;

[0007] The data before deinterleaving is divided to obtain the first data unit;

[0008] Obtain the punched data and obtain the second data unit based on the punched data. The data before deinterleaving and the punched data are determined in the encoded data according to the soft bit encoding position.

[0009] Decoding is performed based on the soft bit encoding position, the first data unit, and the second data unit to obtain decoded data.

[0010] This application provides a decoding device, including:

[0011] The pre-deinterleaving data receiving module is used to receive the pre-deinterleaving data and the soft bit encoding position;

[0012] The first data unit generation module is used to divide the uninterrupted data to obtain the first data unit;

[0013] The second data unit generation module is used to acquire the punched data and obtain the second data unit based on the punched data. The data before deinterleaving and the punched data are determined in the encoded data according to the soft bit encoding position.

[0014] The decoding data determination module is used to decode according to the soft bit encoding position, the first data unit and the second data unit to obtain decoded data.

[0015] This application provides a network device, including at least one processor and a memory; the processor is used to execute a program stored in the memory to implement any of the methods in this application.

[0016] This application provides a storage medium storing a computer program, which, when executed by a processor, implements any of the methods described in the embodiments of this application.

[0017] The decoding method, apparatus, network device, and storage medium provided in this application divide the soft bits in the data before deinterleaving to form multiple first data units. At the same time, the punched data is acquired and divided into multiple second data units. Data to be decoded is formed according to the soft bit encoding position, the first data units, and the second data units, and then decoded. This achieves the processing of multiple soft bit forming units, which solves the problem of low efficiency in the de-rate matching process in the prior art due to the need to process each soft bit individually. It can reduce the need for addressing each soft bit individually in the de-rate matching and decoding process, and improve the efficiency of de-rate matching and decoding.

[0018] Further details regarding the above embodiments and other aspects of this application, as well as their implementations, are provided in the accompanying drawings, detailed description, and claims. Attached Figure Description

[0019] Figure 1 This is a flowchart illustrating the interaction between the sending end and the receiving end in an embodiment of this application;

[0020] Figure 2 This is a flowchart of the decoding method in the embodiments of this application;

[0021] Figure 3 This is a schematic diagram of the encoded data structure in the embodiments of this application;

[0022] Figure 4 This is a schematic diagram illustrating the application scenario to which the embodiments of this application apply;

[0023] Figure 5 This is a schematic diagram of the soft bit storage format in the embodiments of this application;

[0024] Figure 6 This is a timing diagram of the unit processing in the embodiments of this application;

[0025] Figure 7 This is a schematic diagram of the rate-matched data in an embodiment of this application;

[0026] Figure 8 This is a schematic diagram of an interleaving matrix in an embodiment of this application;

[0027] Figure 9 This is a schematic diagram of another interlacing matrix in an embodiment of this application;

[0028] Figure 10 This is a schematic diagram of the decoding device in the embodiments of this application. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0030] Before introducing the technical solutions provided in the embodiments of this application, for ease of understanding, the data processing involved in the communication process between the sending end and the receiving end will be introduced first, specifically as follows: Figure 1 As shown,

[0031] The transmitting end generates a Cyclic Redundancy Check (CRC) code based on the transport block to be transmitted, and divides the transport block into blocks (CBs) as transmission units, calculating the CRC of each CB. Low-Density Parity Check (LDPC) encoding is performed on each code block to obtain the encoded data corresponding to the CB. The encoded data is then sequentially rate-matched and interleaved, and the outputs are concatenated, followed by scrambling, modulation, and inverse Fast Fourier Transform (IFFT) before being transmitted at a set frequency to the receiving end via the wireless interface.

[0032] The receiving end performs Fast Fourier Transform, channel estimation and demodulation, descrambling, and decoded block concatenation sequentially on the received data. Then, the data corresponding to each code block is deinterleaved, and the resulting uninterleaved data undergoes rate matching and soft combining to obtain the data to be decoded. Next, LDPC decoding is performed on the data to be decoded to obtain the decoded data, which is identical to the encoded data. Finally, the obtained code blocks are CRC verified, and multiple code blocks that pass CRC verification are segmented into decoded blocks to obtain the transport blocks. Simultaneously, CRC verification is performed on the transport blocks. The transport blocks that pass verification are the data actually transmitted by the sending end, and the receiving end can perform further processing on this data.

[0033] in,

[0034] Suppose a CB has a total of K′ bits, including all system bits and CRC check bits, of which L are CRC check bits (L>0), and the corresponding sequence is as follows:

[0035] c0, c1, c2, ..., cK′-1

[0036] The current protocol specifies two types of LDPC parity-check matrices: base... Figure 1 (BG1) or base Figure 2 (BG2).

[0037] Once the base map is determined, the LDPC boosting factor Zc used for CB encoding can be uniquely determined based on K′ and the base map.

[0038] The enhancement factor Zc can be based on the formula Zc = a × 2 j The condition is determined, where j = 0, 1, ..., 7, and Zc ≤ 384, while a is a prime number, which is any one of the set {2, 3, 5, 7, 9, 11, 13, 15}. Zc is determined by the sum of the number of information bits and CRC check bits contained in a code block, and the LDPC base map (which takes the value 1 or 2).

[0039] After LDPC encoding, that is, before rate matching, the N-bit sequence is:

[0040] d0, d1, d2, ... d N-1

[0041] Where the system bits are

[0042]

[0043] It can be seen that the system bits are:

[0044]

[0045] The hole is fixed and will not be sent to the receiving end.

[0046] The positions of the filler bits are as follows (including KK′ filler bits):

[0047] d s = <null>s=K′-2Z c ,…,K-1

[0048] Among them, when the base Figure 1 When K = 22Z c When the base Figure 2 When K = 10Z c .

[0049] The remaining bits are parity bits generated based on the LDPC parity check matrix.

[0050] Secondly, rate matching is performed.

[0051] Let E be the number of bits output after rate matching, then the rate matching process is as follows:

[0052]

[0053]

[0054] Where N cb ≤N, N cb The actual size of the circular cache in rate matching based on finite cache;

[0055] k0 is the starting position for rate matching of different redundancy versions. The size corresponding to k0 is (i.e., the value of the K'-2Zth digit). c The number of soft bits between each soft bit is an integer multiple of Zc.

[0056] The number of bits output after rate matching of this code block, i.e., the actual number of bits transmitted by the transmitter, must be Q. m Integer multiples of.

[0057] Next, weave together.

[0058]

[0059] Q m Here, E is the modulation order, and E is the number of bits output after rate matching, which can be converted to Q. m Divisible by.

[0060] This interleaving is a row-column interleaving, where the number of rows R = Q. m ; Number of columns C = E / Q m .

[0061] Finally, the code blocks undergo concatenation, scrambling, modulation, layer mapping, and inverse fast Fourier transform processing before being transmitted via an antenna. During modulation, one Q-column... m Each soft bit is modulated to the same constellation point.

[0062] Example

[0063] Figure 2 The flowchart illustrates a decoding method provided in this application embodiment. This embodiment is applicable to situations where communication data is deinterleaved and rate-matched at the receiving end of the communication data. This method can be executed by the decoding device provided in this application embodiment. This device can be implemented in software and / or hardware and is generally integrated into network devices. Figure 2 As shown, it specifically includes:

[0064] S110 receives the data before deinterleaving and the soft bit encoding position.

[0065] The data before deinterleaving can be soft bits. The data before deinterleaving is actually the bit data written row-by-row into the interleaving matrix and read column-by-column by the transmitting end; one bit from the transmitting end corresponds to one soft bit from the receiving end. The data before deinterleaving should be the same as the interleaved data obtained by the transmitting end through interleaving the CB (Cross-Block Array). However, due to over-the-air transmission, the data received by the receiving end may not be correct; that is, the data before deinterleaving may not be the same as the interleaved data.

[0066] The soft bit encoding position includes at least the position of each soft bit in the data before deinterleaving within the encoded data (i.e., the decoded data). The soft bit encoding position can be determined based on the received interleaving matrix or directly transmitted from the transmitter to the receiver. The encoded data is the data encoded by the transmitter but before rate matching and interleaving.

[0067] The decoding process in this embodiment involves de-rate matching and soft combining of the received data before deinterleaving to obtain the data to be decoded, and then decoding the data to be decoded. The data to be decoded is used to decode the decoded data, and the encoded data is the same as the data to be decoded. In fact, before decoding, it is necessary to restore the encoded data to its original state without any processing, thereby achieving accurate decoding.

[0068] Soft bits refer to bits that, after receiving a signal, are directly output as analog quantities for quantization without making a decision.

[0069] S120, divide the data before deinterleaving to obtain the first data unit.

[0070] The first data unit includes at least two soft bits, which are used to combine the soft bits and process them as a derate matching and soft combining processing unit.

[0071] Dividing the data before deinterleaving actually involves grouping all the soft bits included in the data before deinterleaving.

[0072] S130, acquire the punched data, and generate a second data unit based on the punched data, wherein the data before deinterleaving and the punched data are determined in the encoded data according to the soft bit encoding position.

[0073] The order of S120 can be adjusted from that of S130. It can be performed after S130 or simultaneously with S130. This application embodiment does not impose specific restrictions on this.

[0074] In practice, rate matching in this application embodiment involves the transmitter using either repeated or punctured bits to match the carrying capacity of the physical channel. Punching removes bits that the physical channel cannot carry as redundant data, while simultaneously shifting subsequent soft bits one position forward. Repetition is achieved by cyclically fetching data from a buffer, with repeated bits not being adjacent. De-rate matching is the opposite: restoring the punctured bits and merging the repeated bits. Both puncturing and repetition are optional. In this application embodiment, rate matching is a rate matching mechanism based on a circular buffer.

[0075] The punctured data consists of soft bits that are removed during rate matching. The punctured data is used to combine with the pre-interleaved data to generate the same decoded data as the encoded data.

[0076] The second data unit includes at least two soft bits, used to combine the soft bits as a processing unit that is knocked out in the encoded data, and used to combine with the first data unit to form data to be decoded.

[0077] In fact, the encoded data can be considered as a soft bit sequence. After rate matching, the data before deinterleaving is obtained. The data deleted from the encoded data is called punctured data. For example... Figure 3 As shown, the encoded data includes system bits, padding bits (3), and parity bits. In the communication standard, the first 2Zc bits of the system bits are fixed as punctured data. Furthermore, the system bits may also include other punctured data, and the parity bits may also contain other punctured data. It should be noted that the other punctured data included in the system bits, and the punctured data and padding bits included in the parity bits, may or may not exist. The first 2Zc bits are fixed as punctured data, but the recovery operation of this punctured data does not belong to rate matching de-matching. The recovery operation of the remaining punctured data belongs to rate matching de-matching.

[0078] The soft bit encoding position includes the position of each soft bit in the pre-deinterleaving data within the encoded data and the position of each soft bit in the punctured data within the encoded data. The encoded data completes the rate matching process before interleaving and other operations. Therefore, the punctured data can be determined based on the position of the soft bits in the punctured data within the encoded data, targeting the soft bit encoding position. The pre-deinterleaving data can include various forms of data, such as data formed by repeatedly acquiring and repeating repetitive soft bits; data formed by acquiring retransmitted soft bits; and data formed by acquiring non-repetitive soft bits. The repetitive, retransmitted, and non-repetitive soft bits are located in the pre-deinterleaving data. Thus, the position of each soft bit in the pre-deinterleaving data within the encoded data can be determined based on the positions of these repetitive, retransmitted, and non-repetitive soft bits within the encoded data. The repetitive soft bits actually appear repeatedly; that is, multiple soft bits in the pre-deinterleaving data have the same position in the encoded data.

[0079] In one exemplary embodiment, the unit lengths of both the first data unit and the second data unit are target lengths, which are determined based on a boosting factor and satisfy an integer division condition associated with the boosting factor.

[0080] The target length is used to determine the maximum number of soft bits included in the first and second data units. The boost factor can refer to the boost factor used in encoding at the transmitting end, representing the multiple by which the number of bits is increased.

[0081] By configuring the length of each unit to be the target length and determined according to the boosting factor, the length of the units can be configured reasonably. At the same time, the length of each unit is the same, which facilitates the addressing of soft bits in the unit.

[0082] In practice, the receiver processes a single CB. When the CB is decoded correctly, the process of deinterleaving and rate matching for that CB ends.

[0083] During the first transmission of a code block (CB), the historical merged data stored in the HARQ for that CB is typically cleared. The associated data of a code block can be deleted after the processing of the associated code block data before deinterleaving is complete, or a code block identifier can be added to the associated data of a code block to distinguish it from the associated data of the next code block. The code block identifier is used to mark the valid range of each code block.

[0084] After receiving all the transmitted data, the receiving end stores it in a circular buffer format in the HARQ and then stores it in the LDPC decoder in its original encoded order. Since decoding is performed on 1Zc bits of data at a time, each address needs to store Zc soft bits. When storing to the last address, if the total number of soft bits received for that address is less than Zc, it can be padded with 0s to make the number of soft bits at the last address equal to Zc.

[0085] Optionally, the target length needs to satisfy the divisibility condition associated with the boosting factor, indicating that the boosting factor can be divided by the target length. This ensures that the data of a data unit does not belong to different Zc, thus guaranteeing that the data of a data unit will not span two Zc. This can be combined with the storage format in the LDPC decoder, where the data of n data units is exactly equal to Zc soft bits that can be stored at one address, ensuring that it will not exceed one address, thereby reducing the processing complexity.

[0086] In one exemplary embodiment, the target length is the ratio of the boost factor to a power of 2, and the first quantity is less than or equal to a set quantity threshold, which is determined based on the operating frequency and available resources.

[0087] For example, CB uses LDPC encoding, and the boost factor is the boost factor of the LDPC encoding.

[0088] The enhancement factor Zc can be based on the formula Zc = a × 2 j The condition is determined, where j = 0, 1, ..., 7, and Zc ≤ 384, while a is a prime number, which is any one of the set {2, 3, 5, 7, 9, 11, 13, 15}. Zc is determined by the sum of the number of information bits and CRC check bits contained in a code block, and the LDPC base map (which takes the value 1 or 2).

[0089] By configuring the length of each unit to be the target length and determined according to the boosting factor, the length of the units can be configured reasonably. At the same time, the length of each unit is the same, which facilitates the addressing of soft bits in the unit.

[0090] In one exemplary embodiment, the target length is the ratio of the boost factor to a power of 2, and the first quantity is less than or equal to a set quantity threshold, which is determined based on the operating frequency and available resources.

[0091] Specifically, the target length is Zs. A threshold is set to A, where Zs ≤ A, and A is determined based on the operating frequency and available resources, with a set value of m. Specifically, Zs is determined according to the following process:

[0092] Zs = Zc;

[0093] m = 0;

[0094] If Zs is greater than A, then set Zs = Zs / 2 and m = m+1, and repeat this process until Zs satisfies Zs≤A.

[0095] By determining the target length based on the boost factor, the length of the unit can be configured reasonably, avoiding too many or too few soft bits processed at one time, thereby improving the rate matching efficiency of soft bits.

[0096] S140, Decode the data according to the soft bit encoding position, the first data unit, and the second data unit to obtain decoded data.

[0097] The soft bit encoding position, the first data unit, and the second data unit are used to determine the data to be decoded. Specifically, the first data unit and the second data unit can be combined to form the data to be decoded, which is then decoded to obtain the decoded data. It is understandable that the combination method requires knowledge of the positional relationship between the first and second data units. The position of the soft bits in the first and second data units within the encoded data (i.e., the data to be decoded) can be determined based on the soft bit encoding position. Therefore, the first and second data units can be arranged according to their positional relationship to obtain the data to be decoded.

[0098] In one exemplary embodiment, the decoding based on the soft bit encoding position, the first data unit, and the second data unit includes: determining the unit encoding position of each first data unit based on the soft bit encoding position and the first soft bit in each first data unit; determining the unit encoding position of each second data unit based on the soft bit encoding position and the first soft bit in each second data unit; and storing the first data unit and the second data unit at matching memory addresses in the decoder according to each unit encoding position, thereby arranging the first data unit and the second data unit to form data to be decoded, so that the decoder can decode the data to be decoded.

[0099] The first and second data units can be considered as soft bit sequences. The position of the first soft bit in the soft bit sequence within the encoded data can be used as the position of the soft bit sequence in the encoded data, i.e., the unit encoding position. The positions of all other data units, except for the first soft bit, can be determined based on the order of the soft bits, i.e., their relative positions, and the unit encoding position.

[0100] Accordingly, when storing each unit, the first soft bit is written at the storage address corresponding to the unit's encoding position, and the next soft bit is written at an offset of 1 bit from that storage address. Then, the subsequent soft bits are written sequentially after the subsequent offset addresses, and so on, so that the soft bits in the unit are written into the decoder one by one in order.

[0101] The matching storage address in the decoder corresponds to the unit encoding position. Each first data unit and each second data unit is stored at the matching position according to its unit encoding position. This allows the first and second data units to be arranged according to their unit encoding positions during storage, thus enabling them to be concatenated and combined to form the data to be decoded.

[0102] By determining the unit encoding position of each first data unit and each second data unit according to the soft bit encoding position, and storing each first data unit and each second data unit in the corresponding storage address that matches the unit encoding position, the first data units and each second data units are arranged and combined in the decoder to ensure accurate decoding rate matching, thereby accurately splicing together the data to be decoded.

[0103] The decoding method, apparatus, network device, and storage medium provided in this application divide the soft bits in the data before deinterleaving to form multiple first data units. At the same time, the punched data is acquired and divided into multiple second data units. Data to be decoded is formed according to the soft bit encoding position, the first data units, and the second data units, and then decoded. This achieves the processing of multiple soft bit forming units, which solves the problem of low efficiency in the de-rate matching process in the prior art due to the need to process each soft bit individually. It can reduce the need for addressing each soft bit individually in the de-rate matching and decoding process, and improve the efficiency of de-rate matching and decoding.

[0104] In one exemplary embodiment, receiving data before deinterleaving and dividing the data before deinterleaving to obtain a first data unit includes: receiving soft bits output by column of a multi-channel parallel deinterleaving matrix; sequentially storing the soft bits received from each channel to generate a plurality of third data units; and sequentially performing soft merging on each of the third data units according to a set number of clock cycles to form a plurality of first data units.

[0105] In practice, the data before deinterleaving is obtained from the deinterleaving matrix. The deinterleaving matrix is ​​output column-wise, with a total of Qm rows and Qm soft bits output in each column. Multiple channels receive the column-wise soft bits before deinterleaving in parallel, with each channel receiving at most one soft bit within a set number of clock cycles. Each channel stores the received soft bits in the order they were received; that is, each channel stores the soft bits from one row of the deinterleaving matrix.

[0106] Qm serial-to-parallel conversion modules can be configured, each operating in parallel. Each module processes one row of the deinterleaving matrix to achieve parallel reception of soft bits from multiple sources, which are then stored sequentially. This allows for the independent collection of soft bits for the third data unit, forming a single third data unit. Simultaneously, based on the soft bit positions, the position of the first received soft bit in the encoded data within the third data unit is determined and used as the unit encoding position. This position, along with the resulting third data unit, is then sent to the next processing module for further processing.

[0107] Qm serial-to-parallel conversion modules can generate third data units that are integer multiples of Qm. During the processing of these third data units, a serial processing method is used, processing each third data unit sequentially.

[0108] Soft combining refers to combining data based on Hybrid Automatic Repeat Request (HARQ). In practice, after sending a data packet, the sender waits for feedback from the receiver confirming receipt of the correct message. If no feedback is received, the sender retransmits the data packet or a portion of it to ensure the receiver receives the correct data. The receiver, after acquiring the third data unit, combines it with the cached data matched in the HARQ memory. The combined unit becomes the first data unit, and this first data unit is the valid data unit that has been transmitted correctly.

[0109] The order of serial processing can be determined by selecting one data unit from multiple channels sequentially according to a set rule (such as polling) to form a third data unit, which is then processed.

[0110] The set number of clock cycles is used as the processing frequency for the third data unit, which is also the selection frequency for selecting one channel from multiple channels to form the third data unit. The set number of clock cycles can be set as needed. Usually, one clock cycle is not long enough to complete the processing task of one third data unit, so multiple clock cycles can be selected as one processing cycle to complete the processing task of one third data unit.

[0111] The soft bits are received in parallel from the deinterleaving matrix output and stored sequentially to form a third data unit. The soft bits are converted into units, and each third data unit is processed serially to achieve processing in unit form, thereby improving the processing efficiency of soft bits.

[0112] In one exemplary embodiment, the sequential storage of each received soft bit to generate multiple third data units includes: if the received target soft bit satisfies the padding bit start-adjacent condition, then the current third data unit is generated with the target soft bit as the last received soft bit, and the next soft bit is received to generate the next third data unit.

[0113] In practice, the encoded data may include padding bits, which are not present in the data before deinterleaving. Therefore, when storing the data before deinterleaving, a space for padding bits can be reserved in the current third data unit, and the next third data unit is generated based on the received next soft bit. If the target soft bit is exactly the last soft bit in the current third data unit, there is no need to reserve a space for padding bits in the current third data unit; the current third data unit is generated directly. A new third data unit is formed based on the received next soft bit, which is also the first soft bit of the third data unit.

[0114] In practice, a third data unit can be pre-constructed and filled with the received soft bits, while the positions where soft bits are filled are not filled, leaving the positions reserved.

[0115] The padding bit start-adjacency condition is used to determine whether the position of the received soft bit in the encoded data, offset from the target length, is the position of the padding bit. The target soft bit refers to the soft bit in the encoded data whose position offset from the target length is the position of the padding bit. The target soft bit is used to determine whether to end the acquisition of soft bits in the current third data unit. The current third data unit refers to the third data unit to be generated. The current third data unit can use the target soft bit as the last soft bit received from the data before deinterleaving. If the target soft bit is the last soft bit in the current third data unit, the current third data unit is generated directly; otherwise, the position of the padding bit is reserved, and the current third data unit is generated. In this case, the number of soft bits belonging to the data before deinterleaving included in the current third data unit is less than the target length.

[0116] In fact, the soft bits in the encoded data can be numbered according to their order, and the sequence number can be used as the position of the soft bit.

[0117] Specifically, the starting adjacency condition for padding bits includes whether the position of the soft bit in the encoded data is K′-2Z. c -1. If the position of the soft bit is K′-2Z c -1 indicates that the soft bit satisfies the initial adjacent condition of the padding bit.

[0118] Continue receiving the next soft bit and use it as the first soft bit of the new third data unit to generate the new third data unit.

[0119] By reserving space for padding bits in the third data unit, it can be ensured that the soft bits in the third data unit are in continuous positions in the encoded data. This allows for accurate arrangement of the third data units in subsequent operations, avoiding the situation where a third data unit contains multiple non-contiguous soft bits, which would require the corresponding first data unit to be segmented before it can be arranged and combined. Instead, it allows for direct arrangement and combination based on the first data unit, thereby improving the processing efficiency of the first data unit.

[0120] In one exemplary embodiment, the soft merging of the third data unit to form a first data unit includes: querying a matching unit to be merged in a set to be merged based on the unit encoding position corresponding to the third data unit, and merging them to obtain the first data unit; updating the matching unit to be merged in the set to be merged based on the first data unit, wherein the unit length of the unit to be merged is the target length, the unit to be merged is used to store historical merged data, and the historical merged data is used to merge with the soft bits in the third data unit to update the soft bits in the third data unit.

[0121] The merge set stores historical merged data, which is stored in the form of merged units. The initial value of the historical merged data is 0. Data from the first transmission can be stored in the merge set as historical merged data. If the receiving end can decode correctly, the decoded data is used for subsequent processing. The data in the merge set can be reset, or a new merge set can be configured for the next CB. If the receiving end finds that it cannot decode correctly, it requests the sending end to retransmit the data. This retransmitted data can be all the data in the CB or a portion of the data in the CB. The receiving end merges the second retransmitted data with the stored data from the first transmission (i.e., the historical merged data), updates the historical merged data based on the merged data, and performs decoding. If decoding is correct, the decoded data is used for subsequent processing; if decoding is incorrect, it continues to request retransmission and repeats the above steps.

[0122] Historical merged data is actually data obtained by merging historically transmitted data. Errors may exist in the data before deinterleaving, resulting in errors in the corresponding third data unit. In this case, corrections can be made based on the historical merged data to ensure the formation of a correct first data unit.

[0123] The set to be merged is located in the HARQ memory, and the storage location of the cells to be merged in the HARQ memory corresponds to the cell encoding location of the third data unit. Therefore, a matching cell to be merged can be queried in the HARQ memory based on the cell encoding location of the third data unit.

[0124] In practice, the soft merging in this embodiment involves reading the cell to be merged that matches the third data cell from the HARQ memory. The soft bits in the cell to be merged and the soft bits in the third data cell are matched one-to-one, and the merging is performed in parallel. The soft bits in the third data cell are replaced with the merged soft bits, resulting in a first data cell which is sent to the decoder for storage. Simultaneously, a copy is written back to the HARQ memory to update the original cell to be merged, in preparation for the next soft merging operation.

[0125] By configuring the storage address of the unit to be merged in the soft merge set to correspond with the unit code position of the third data unit, the matching unit to be merged in the third data unit can be accurately queried and merged. This enables soft merge operations to be performed on a unit basis of the third data unit, thereby improving the efficiency of soft merge operations and enhancing data reliability.

[0126] In one exemplary embodiment, the set number of cycles is the same as or determined based on half of the target number of cycles. The target number of cycles includes the number of clock cycles required from the start of soft merging of the third data unit to the generation of the first data unit.

[0127] Specifically, assuming the number of clock cycles required for a third data unit to complete a read from the HARQ memory, soft-merge, and finally write back to the same address is Q, P can be either Q or Q / 2. If Q is odd, then P is the integer part of Q / 2. Q is the target number of cycles, and P is the set number of cycles.

[0128] By configuring and setting the number of cycles, the processing frequency of the third data unit can be flexibly adjusted.

[0129] In one exemplary embodiment, the set number of cycles is determined based on half of the target number of cycles, and the set number of cycles is an integer; the soft merging of the third data unit to form the first data unit includes: if, based on the unit encoding position corresponding to the currently processed third data unit and the unit encoding position corresponding to the previous third data unit, it is determined that the first data unit obtained from the currently processed third data unit satisfies the repetition rate matching condition, then, based on the unit to be merged corresponding to the previous third data unit, the unit to be merged that matches the currently processed third data unit is determined.

[0130] The repetition rate matching condition is used to determine whether the soft bits in two consecutive third data units processed in a serial manner are the same. Specifically, this can be determined based on whether the unit codes corresponding to these two third data units are the same. If the unit code position corresponding to the currently processed third data unit is the same as the unit code position corresponding to the previous third data unit, it indicates that the soft bits in these two third data units are the same, and the currently processed third data unit is determined to satisfy the repetition rate matching condition.

[0131] In practice, the time it takes for a third data unit to initiate a read from the HARQ memory, complete soft merging, and ultimately write back to the same address is the target number of cycles. Setting the number of cycles to half of the target number of cycles, or the integer part of half, indicates that while one third data unit is not yet writing back to the same address, another third data unit begins processing, i.e., it initiates reading the corresponding unit to be merged from the HARQ memory. At this point, the two third data units that meet the repetition rate matching condition correspond to the same unit to be merged. The unit to be merged read from the HARQ memory by the second processed third data unit is actually not updated. Therefore, the first data unit obtained from the first processed third data unit can be directly used as the unit to be merged obtained by the second processed third data unit, reducing the processing time and number of reads required to wait for updated units to be merged from the set to be merged.

[0132] Furthermore, if the number of cycles is set to the target number of cycles, then in any two consecutive third data units, after one third data unit forms the first data unit and is written back, the other third data unit will begin processing. Thus, repetition rate matching has no effect on the processing of these two third data units.

[0133] In an exemplary embodiment, the step of acquiring the punched data and generating a second data unit based on the punched data includes: generating multiple zeroing units, each of which includes soft bits of 0, the unit length of which is a target length, the total number of soft bits in each zeroing unit being the product of a boosting factor and 2, and the unit encoding position corresponding to each zeroing unit preceding the unit encoding position corresponding to each of the first data units; if padding bits exist in the encoded data, the padding bits are acquired and a padding unit is generated, the unit length of which is the target length; if a first data unit satisfies the repetition rate matching condition or the... If there are redundant version punctured bits in the encoded data, then the redundant version punctured bits are obtained, and a redundant version punctured unit is generated. The unit length of the redundant version punctured unit is the target length, and the unit encoding position corresponding to each redundant version punctured unit is before the unit encoding position corresponding to each first data unit. If there is a first data unit that meets the repetition rate matching condition or if there are redundant version punctured bits in the encoded data, then the redundant version punctured bits are obtained, and a redundant version punctured unit is generated. The unit length of the redundant version punctured unit is the target length, and the unit encoding position corresponding to each redundant version punctured unit is after the unit encoding position corresponding to each first data unit.

[0134] Specifically, such as Figure 3 As shown, the encoded data may include a zero-down soft bit (1), a pre-redundant punctured bit (2), a padding bit (3), and a post-redundant punctured bit (5). The zero-down soft bit (1) is a mandatory soft bit in the encoded data. The encoded data may include at least one of the pre-redundant punctured bit (2), the padding bit (3), and the post-redundant punctured bit (5), or none of them. The actual data sent from the transmitter to the receiver is the pre-deinterleaving data (4), which does not include the padding bit (3). Furthermore, the subsequent data (6) is the data transmitted after this CB.

[0135] Typically, the position of soft bits in encoded data starts from... Figure 3 The statistics begin with 0. Because the first 2Z bytes of the encoded data are fixed... c One soft bit is punched and will not be sent to the receiver, thus allowing direct access from the first 2Z bits. c The counting begins with the first soft bit after the first soft bit. k0 is the starting position for rate matching of different redundancy versions, k1 is the ending position for the redundancy version in this transmission, and Nr is the maximum position of all soft bits received in the circular buffer among the multiple redundancy versions already received by this CB, where Nr ≤ Ncb. When using LDPC encoding, when the base... Figure 1 When K = 22Z c When the base Figure 2 When K = 10Z c K′ is the sum of the information bits and CRC check bits contained in a CB. Ncb is the end position of the circular buffer.

[0136] Correspondingly, a zeroing unit is a unit formed by dividing the zeroing soft bits (1), and all soft bits in a zeroing unit are 0. Furthermore, the unit encoding position of all zeroing units is before the circular buffer in the encoded data, that is, before the position of each soft bit in the encoded data before deinterleaving, that is, before the unit encoding position of the first data unit formed by the data (4) before deinterleaving. Specifically, if the target length is Zs, then the number of zeroing units is 2Zc. A zeroing unit is a data unit formed by the first 2Zc soft bits fixed in the system bits.

[0137] The padding unit is a unit formed by dividing the padding bit (3). The padding bit (3) can be obtained from local storage or read from the HARQ memory. The padding bit (3) is usually a soft bit predefined by the transmitting and receiving ends. At the same time, the padding bit (3) is located between the punctured bit (2) before the redundancy version and the punctured bit (5) after the redundancy version, and in the middle of the data (4) before deinterleaving. The unit encoding position of the padding unit formed therefrom is located between the unit encoding positions of the first data unit. Specifically, the starting position of the padding bit (3) in the encoded data is K′-2Zc, and the ending position is K-2Zc. The corresponding unit encoding position of the padding unit is located between K′-2Zc and K-2Zc.

[0138] There exists a first data cell that satisfies the repetition rate matching condition, indicating that E≥N cb -(KK′). The presence of a redundant version pre-punctured bit (2) in the encoded data indicates that the unit encoding position of the first data unit is 0. The redundant version pre-punctured bit (2) can be read from the HARQ memory. The redundant version pre-unit is a unit formed by dividing the redundant version pre-punctured bit (2). The starting position of the redundant version pre-punctured bit (2) in the encoded data is 0, and the ending position is k0. The corresponding unit encoding position of the redundant version pre-unit is between 0 and k0. At the same time, the redundant version pre-punctured bit (2) is before the position of each soft bit in the data (4) before the position in the encoded data. The corresponding unit encoding position of the redundant version pre-unit is before the unit encoding position of the first data unit formed by the data (4) before the position of the first data unit formed by the data (4) before the deinterleaving.

[0139] The presence of redundant punctured bits in the encoded data indicates that E+k0≥N. cb The redundant version of the punctured bit (5) can be read from the HARQ memory. The redundant version of the punctured bit (5) is a unit formed by dividing the redundant version of the punctured bit (5). The starting position of the redundant version of the punctured bit (5) in the encoded data is k1, and the ending position is N. r The corresponding redundant version of the cell has its cell encoding position located at k1 and N. r Meanwhile, the redundant version of the punched bit (5) is located after each soft bit of the data (4) before deinterleaving, and the corresponding unit encoding position of the redundant version of the unit is located after the unit encoding position of the first data unit formed by the data (4) before deinterleaving.

[0140] By configuring multiple second data units and recovering them according to different puncturing methods, the accuracy of the recovered punctured data is ensured. At the same time, the recovered punctured data is recovered by replacing each soft bit in unit form, which improves the speed of solution rate matching.

[0141] Furthermore, the HARQ memory can directly store the punctuation bits before the redundant version according to the preceding cell, thus allowing direct reading of the preceding cell from the HARQ memory. Similarly, the HARQ memory can directly store the punctuation bits after the redundant version according to the following cell, thus allowing direct reading of the following cell from the HARQ memory.

[0142] In one example, it can be done as follows: Figure 4 The modules shown implement the processing procedures of each unit.

[0143] The decoder block concatenation module completes the decoder block segmentation, outputting Qm soft bits from the same column of the deinterleaving matrix each clock cycle. The decoder block concatenation module then outputs the deinterleaving matrix column-by-column in parallel to the Qm-way serial-to-parallel conversion module.

[0144] Each serial-to-parallel conversion module receives the data segmented from the decoded block, implements Qm-way parallel processing, and each path independently collects Zs soft bits to form a third data unit, which is then sent to the deinterleaving arbitration module for processing.

[0145] The deinterleaving arbitration module is used to select one data unit from the third data unit after the Qm-way serial-to-parallel conversion is completed, and send it serially to the de-rate matching module for processing.

[0146] The rate matching module is used to perform HARQ merging processing on the first data unit (including Zs soft bits) sent in by the deinterleaving arbitration module, and to complete rate matching (puncturing rate matching).

[0147] The HARQ memory provides the merging cells for the rate matching module, and the decoder is used for decoding; specifically, the decoder is an LDPC decoder. The storage format of each soft bit in the LDPC decoder and HARQ memory is as follows: Figure 5 As shown. If Zc = 208 and Zs = 13, that is, each cell (Bank) stores 13 soft bits sequentially, and the high 11 soft bits of each Bank are reserved.

[0148] In fact, for each row of the interleaving matrix, a certain number (i.e., Zs) of data are collected before processing begins. Data collected from different rows are processed serially, which avoids read-write rereading.

[0149] Zs is not set arbitrarily. The decoder processes data in blocks of Zc data. If Zc is not divisible by Zs, the Zs data points will belong to different processing blocks, significantly increasing processing complexity. Therefore, Zs can be configured to be divisible by Zc, ensuring that the Zs data points do not span two processing blocks and reducing processing complexity.

[0150] Specifically, a cell identifier can be configured for each cell, and a bit identifier can be configured for the soft bits within the cell. Each soft bit is identified by the cell identifier and the bit identifier. In other words, each soft bit in a cell can be determined by querying which cell it belongs to, and then querying within that cell to identify which soft bit it is.

[0151] It can be configured that each Zc-length unit includes (2 m Given 2 Zs-length cells, based on the cell number Zs_i, directly obtain the address Zs_i >> m of the corresponding Zc-length cell, and which Zs-length cell within the Zc-length cells belongs to: Zs_i % (2 m Thus, addressing each cell of length Zs becomes very simple. For example, if Zs is 16, then Zc / Zs = 24, and it is necessary to calculate Zs_i / 24 and Zs_i%24, which are relatively simple calculations, thereby simplifying the addressing operation.

[0152] First, calculate the target length Zs = a × 2 m If Zs≤A is preferred, then A is 24.

[0153] Secondly, calculate the starting position parameters of the data before deinterleaving, that is, which cell the soft bit in the first column of each row of the deinterleaving matrix is ​​located in, and which soft bit in that cell.

[0154] Specifically, let ks[i] be the position of each row of soft bits in the deinterleaving matrix in the circular buffer, then:

[0155] ks_nZs[i] = floor(ks[i] / Zs)

[0156] ks_oZs[i]=ks[i]%Zs

[0157] Where i = 0, 1, ... Qm-1.

[0158] Accordingly, the cell to which the end position k0 of this redundant version of transmission belongs is:

[0159] k1 nZs[i] =floor(k1 / Zs)

[0160] Next, calculate the relative positions K′ and K of the padding bits and the finite circular cache rate matching N. cb The cell to which the soft bit at a given location belongs, and which soft bit within that cell:

[0161] Kp_nZs[i]=floor((K′-2Zc) / Zs)

[0162] Kp_oZs[i]=K′%Zs

[0163] K_nZs[i] = floor((K-2Zc) / Zs)

[0164] K_oZs[i] = K%Zs

[0165] Ncb_nZs[i] = floor(Ncb / Zs)

[0166] Ncb_oZs[i] = Ncb%Zs

[0167] Finally, calculate which unit the actual circular cache size Nr belongs to:

[0168] Nr_nZs[i] = floor(Nr / Zs)

[0169] (1) Uninterruption process:

[0170] The pre-amplifier demodulation module, because the demodulation of one constellation point in each layer corresponds to Q... m There are _q_ soft bits, where the i-th soft bit corresponds to the i-th row of the deinterleaving matrix, and i takes values ​​of 0, 1, ..., Q_. m -1. The demodulation module in each cycle may output nL layers of soft bits simultaneously, where nL takes the value 1, 2, 3, or 4. The descrambling module processes the nL layers serially, outputting one layer of soft bits sequentially each clock cycle.

[0171] Qm serial-to-parallel conversion modules operate in parallel. Each module processes the i-th soft bit. Each channel receives at most one soft bit per clock cycle, where i takes values ​​of 0, 1, ..., Q. m -1;

[0172] The purpose of serial-to-parallel conversion is to collect Zs soft bits based on address a and offset address to form a unit, which serves as the processing unit for subsequent solution rate matching and HARQ processing. The soft bits in the i-th unit of length Zs are:

[0173] Zs×a+m, m=0,1,...Zs-1.

[0174] The Qm serial-to-parallel conversion modules work independently, and the specific processing is as follows:

[0175] Complete Q before CB data arrives. m Initialization processing of each serial-to-parallel conversion module;

[0176] Each cell includes an address 'a' and an offset 'o' counter, where address 'a' is the cell's encoded position.

[0177] Initialization is specifically

[0178] a = ks_nZs[i]

[0179] o = ks_oZs[i]

[0180] Clear the storage associated with the serial-to-parallel conversion module;

[0181] After initialization, the loop waits for soft bits until each serial-to-parallel conversion module has collected and processed E / Qm soft bits, at which point the deinterleaving process for that CB ends.

[0182] Each time a soft bit is sent from the front-end module, it is stored in the 0th position of the cell, and the cell address 'a' and offset 'o' are updated. The initial value of 'o' is 0. The processing is performed as follows:

[0183] ar = a;

[0184] o = o + 1;

[0185] flag=1.

[0186] If o equals Zs, it indicates that a unit collection is complete. The collected Zs soft bits are then sent to the deinterleaving arbitration module as a third data unit and the address ar as the unit encoding position. After that, the relevant storage of the serial-to-parallel conversion module is cleared, and flag is set to 0. At the same time, o is set to 0, and a = a + 1.

[0187] If o equals Kp_oZs[0] and a equals Kp_nZs[0], it indicates that the next soft bit in the encoded data is at the beginning of the padding bit position and needs to be skipped. That is, the next soft bit received is a soft bit after the end of the padding bit position. If flag equals 1, the soft bit stored in the serial-to-parallel conversion module is sent as a third data unit and the address ar is sent as the unit encoding position to the deinterleaving arbitration module. Then, the relevant storage of the serial-to-parallel conversion module is cleared and flag is set to 0. At the same time, o is set to K_oZs and a = K_nZs.

[0188] If o equals Kp_oZs[0] and a equals Kp_nZs[0], it indicates that the next soft bit in the encoded data is at the beginning of the padding bit position, i.e. Figure 3 At the position corresponding to K′-2Zc, it needs to be skipped, meaning the next soft bit received is the soft bit after the end of the padding bit position. If flag equals 1, the soft bit stored in the serial-to-parallel conversion module is sent as a third data unit and the address ar as the unit encoding position to the deinterleaving arbitration module. Then, the relevant storage of the serial-to-parallel conversion module is cleared, and flag is set to 0; at the same time, o is set to K_oZs, and a = K_nZs, that is... Figure 3 The position corresponding to K-2Zc in the diagram.

[0189] If o equals Ncb_oZs and a equals Ncb_nZs, it indicates that the current soft bit is at the end of the circular buffer, i.e. Figure 3 At the position corresponding to Ncb in the code, it needs to be looped to position 0. If flag equals 1, the soft bit stored in the serial-to-parallel conversion module is sent as a third data unit and the address ar is sent as the unit encoding position to the deinterleaving arbitration module. Then, the relevant storage of the serial-to-parallel conversion module is cleared, and flag is set to 0; at the same time, o is set to 0, and a is also set to 0.

[0190] (2) Disentanglement Arbitration:

[0191] The deinterleaving arbitration module is based on Q m The serial-to-parallel conversion module records the write status of one or more channels that need to be processed. Then, every P clock cycles (P>0), one third data unit and its unit encoding position ar are selected from the multiple data channels in turn according to the polling mechanism and sent to the de-rate matching module for processing. The selected channel number is then cleared from the pending tasks.

[0192] A better approach is to set Q to 4 and P to 2; see details for timing information. Figure 6 The process involves determining whether the third data units of two consecutive sequentially processed data units share the same address (ar). If the addresses are the same, it indicates a repetition rate match. In this case, the subsequent third data unit does not need to read the unit to be merged from the HARQ memory; instead, it directly uses the result of merging the previous third data unit, forming the first data unit, and continues merging. If the addresses are different, the subsequent third data unit simply reads data from the HARQ. This simplifies the repetition rate matching process by requiring only a check to determine if the third data units of two consecutive processes are duplicates.

[0193] In one example, K′=8384, Zc=384, N cb =11904, correspondingly, the LDPC encoded data includes 8448*3+2*384 soft bits. The first 2Zc = 768 soft bits are punctured, and the middle soft bits (8384-8447) are padding soft bits, also punctured. The punctured soft bits are renumbered. The first 0-767 soft bits are punctured, and the soft bit encoding position is reset to 0 starting from the 768th soft bit. At this point, the data after puncturing is 0-9567, where the padding bits are 7616-7679, and the remaining soft bits are 0-7615 and 7680-9567. After rate matching, the padding bits are removed, and the remaining soft bits are repeated four times to form the rate-matched data, as shown below. Figure 7 As shown, the rate-matched data totals 4 * 11840 bits, meaning the actual number of bits transmitted is 4 * 11840. The rate-matched data is then interleaved, meaning it is written row-by-row and read column-by-column. For example... Figure 8 As shown, the interleaving matrix has 4 rows (the same number as the number of cycles) and a total of 11840 columns. Figure 9 As shown, the interleaving matrix has 4 rows (the same as the number of cycles) and a total of 11,839 columns.

[0194] for Figure 8 In the interleaving matrix, each row contains 0-7615 (the area filled with vertical lines) and 7680-11903 (the area filled with diagonal lines), meaning that soft bits in the same column but in different rows of the interleaving matrix are stored in the same location. Figure 9 In this context, the rows of the interleaving matrix are as follows: 0-7615 (regions filled with vertical lines), 7680-11902 (regions filled with diagonal lines); 11903 (regions filled with diagonal lines), 0-7615 (regions filled with vertical lines), 7680-11901 (regions filled with diagonal lines); 11902-11903 (regions filled with diagonal lines), 0-7615 (regions filled with vertical lines), 7680-11900 (regions filled with diagonal lines); 11901-11903 (regions filled with diagonal lines), 0-7615 (regions filled with vertical lines), 7680-11899 (regions filled with diagonal lines). This means that the soft bits in different rows and columns of the interleaving matrix are stored in the same location. In existing technologies, when performing repeated solution rate matching, it is necessary to judge row by row, but when encountering… Figure 9 In such cases, it is also necessary to query the soft bits stored in the same position row by row according to the column offset.

[0195] In this embodiment, each row of soft bits is received in parallel within one clock cycle and processed serially. That is, after the data units obtained from different rows are processed serially, it is only necessary to determine whether the unit encoding positions of two adjacent Zs-length units are the same during the processing. If they are the same, the next Zs-length unit can be directly merged into the merging result corresponding to the previous Zs-length unit. There is no need to query and read the corresponding unit to be merged from the set to be merged again, which saves the time and amount of data to be processed from querying and reading from the set to be merged.

[0196] like Figure 8 The interleaving matrix shown outputs soft bits of 0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2… In this case, during serial processing, four consecutive processing steps correspond to data units with a unit encoding position of 0. Therefore, there is no need to consider row-by-row judgment; only adjacent data units during processing are needed, greatly reducing the complexity of rate matching.

[0197] For other situations, such as Figure 9 The interleaving matrix shown outputs soft bits of 0, 11903, 11902, 11901, 1, 0, 11903, 11902… Data units are repeated every 5 bits. Because the data from the previous data unit has already been written into the HARQ when the next data unit is being processed, the next data unit can directly read the corresponding data from the HARQ, naturally completing the repetition rate matching and merging process. There is no need to perform repetition rate matching checks, improving the efficiency of rate matching resolution.

[0198] (3) De-rate matching and HARQ merging

[0199] When each new CB is transmitted, during the initialization process, all the units to be merged stored in the HARQ memory corresponding to the CB need to be cleared to zero. This can be done by directly writing 0 to the relevant addresses, using flag bits, or any other equivalent method to cache the units to be merged corresponding to the CB.

[0200] De-rate matching actually involves reading the Zs soft bits corresponding to address ar from the HARQ memory, i.e., the unit to be merged, based on the address ar of the deinterleaving arbitration module. The two groups of Zs soft bits formed in the third data unit and the unit to be merged are then merged in parallel, requiring Zs HARQ merging modules to process in parallel. After merging, the Zs merged results, i.e., the first data unit, are written to the LDPC decoder at address 2 + (ar / 2). m At the cell location ) and sequentially write the soft bits of the first data cell into the cell location at address ar%2. m At the specified location. In fact, during decoder storage, it is stored cell by cell; that is, the first data cell is written to the matching cell location. The addressing of this cell location is implemented using a shift selector, which is simple to implement. Simultaneously, the first data cell is written back to the corresponding HARQ memory, overwriting the corresponding cell to be merged.

[0201] In addition, while performing rate matching processing on the third data unit, the following hole punching process is also performed sequentially, unit by unit:

[0202] 3.1) The first 2Zc bits of the system bit set are fixed with puncturing, regardless of whether rate matching is repeated. The LDPC address is 0 to 2. m +1 All cells with a value of -1 need to be written with 0 to form a zeroed cell.

[0203] 3.2) If K′==K, skip this step; otherwise, proceed as follows:

[0204] The padding bits are obtained to generate padding units. The cell encoding position ap corresponding to the padding unit is actually taken from the address range Kp_nZs~Kp_nZs-1 in the encoded data, and then written sequentially to the LDPC decoder at address 2+(ap / 2). m At the cell location ), the soft bits of the fill cell are written sequentially into the cell location at address ap%2. m At the specified position. The written value for each soft bit is the maximum positive value that can be represented.

[0205] 3.3) If a repetition rate match exists, i.e., E ≥ N cb If -(KK′), or both ks_nZs[0] and ks_oZs[0] are equal to 0, then this step is skipped; otherwise, the following processing is performed:

[0206] The redundant version of the pre-punch bit, which matches the cell encoding position ap, is obtained from the HARQ memory to generate the redundant version of the pre-cell. The cell encoding position ap of the redundant version of the pre-cell is actually taken from the address range 0 to k_nZs[0]-1 in the encoded data, and written sequentially to the LDPC decoder at address 2+(ap / 2). m At the cell location ), the soft bits in the cell are written sequentially into the cell location at address ap%2. m At the location.

[0207] 3.4) If a repetition rate match exists, i.e., E ≥ N cb -(KK′), or E+k0≥N cb If the condition is met, skip this step; otherwise, proceed as follows:

[0208] The redundant version of the cell is generated by retrieving the redundant version from the HARQ memory, which matches the cell encoding position ap, and then punching the bits to create the redundant version cell. The cell encoding position ap of the redundant version cell is actually taken from the address range k1_nZs to Nr_nZs in the encoded data, and then sequentially written into the LDPC decoder at address 2 + (ap / 2). m At the cell location ), the soft bits in the cell are written sequentially into the cell location at address ap%2. m At the location.

[0209] This allows the first and second data units to be stored and arranged according to their positional relationship in the encoded data, forming data to be decoded, so that the decoder can decode the data and obtain the decoded data.

[0210] For specific timing details, please refer to [reference needed]. Figure 6 One rectangle represents one clock cycle. In this case, Q is 4 clock cycles and P is 2 clock cycles. Every two clock cycles, the deinterleaving arbitration module selects a third data unit as input to the derate matching module for processing. Figure 6 During the displayed duration, the deinterleaving arbitration module serially inputs seven third data units to the derate matching module for sequential processing. Specifically, within the first P cycles, a mergeable unit query is initiated in the HARQ memory based on the 0th third data unit; within the second P cycles, the mergeable unit matching the 0th third data unit is acquired; within the third P cycles, the 0th third data unit is soft-merged, and a mergeable unit query is initiated based on the 1st third data unit; within the fourth P cycles, the first data unit formed by the soft-merging of the 0th third data unit is written back to the HARQ memory and / or written to the decoder, while the mergeable unit matching the 1st third data unit is acquired. This process continues. Furthermore, the second data unit can be generated and stored in the decoder within any P cycles.

[0211] Figure 10 This is a schematic diagram of a decoding apparatus provided in an embodiment of this application. This embodiment is a corresponding apparatus for implementing the decoding method provided in any of the above embodiments of this application, and the apparatus can be installed in a network device.

[0212] The pre-deinterleaving data receiving module 310 is used to receive pre-deinterleaving data and soft bit encoding positions;

[0213] The first data unit generation module 320 is used to divide the data before deinterleaving to obtain the first data unit;

[0214] The second data unit generation module 330 is used to acquire the punched data and obtain the second data unit based on the punched data. The data before deinterleaving and the punched data are determined in the encoded data according to the soft bit encoding position.

[0215] The decoding data determination module 340 is used to decode according to the soft bit encoding position, the first data unit and the second data unit to obtain decoded data.

[0216] The decoding method, apparatus, network device, and storage medium provided in this application divide the soft bits in the data before deinterleaving to form multiple first data units. At the same time, the punched data is acquired and divided into multiple second data units. Data to be decoded is formed according to the soft bit encoding position, the first data units, and the second data units, and then decoded. This achieves the processing of multiple soft bit forming units, which solves the problem of low efficiency in the de-rate matching process in the prior art due to the need to process each soft bit individually. It can reduce the need for addressing each soft bit individually in the de-rate matching and decoding process, and improve the efficiency of de-rate matching and decoding.

[0217] In one embodiment, the decoding data determination module 340 is further configured to: determine the unit encoding position of each first data unit based on the soft bit encoding position and the first soft bit in each first data unit; determine the unit encoding position of each second data unit based on the soft bit encoding position and the first soft bit in each second data unit; and store the first data unit and the second data unit at matching storage addresses in the decoder according to each unit encoding position, so as to arrange the first data unit and the second data unit to form data to be decoded, so that the decoder can decode the data to be decoded.

[0218] In one implementation, the unit length of both the first data unit and the second data unit is a target length, which is determined based on a boosting factor.

[0219] In one implementation, the target length is the ratio of the boost factor to a power of 2, and the first quantity is less than or equal to a set quantity threshold, which is determined based on the operating frequency and available resources.

[0220] In one embodiment, the first data unit generation module 320 is further configured to: receive soft bits output column-wise from the deinterleaving matrix in multiple parallel channels; sequentially store the soft bits received from each channel to generate multiple third data units; and sequentially perform soft merging on each of the third data units according to a set number of clock cycles to form multiple first data units.

[0221] In one embodiment, the first data unit generation module 320 is further configured to: if the received target soft bit satisfies the padding bit start adjacent condition, generate the current third data unit with the target soft bit as the last received soft bit, and continue to receive the next soft bit to generate the next third data unit.

[0222] In one embodiment, the first data unit generation module 320 is further configured to: query a matching unit to be merged in the set to be merged according to the unit encoding position corresponding to the third data unit, and merge them to obtain a first data unit; update the matching unit to be merged in the set to be merged according to the first data unit, wherein the unit length of the unit to be merged is the target length, the unit to be merged is used to store historical merged data, and the historical merged data is used to merge with the soft bits in the third data unit to update the soft bits in the third data unit.

[0223] In one implementation, the set number of cycles is the same as the target number of cycles, or is determined based on half of the target number of cycles. The set number of cycles is an integer, and the target number of cycles includes the number of clock cycles corresponding to the time required from the start of soft merging of the third data unit to the generation of the first data unit.

[0224] In one implementation, the set number of cycles is determined based on half of the target number of cycles, and the set number of cycles is an integer; the first data unit generation module 320 is further configured to: if, based on the unit encoding position corresponding to the currently processed third data unit and the unit encoding position corresponding to the previous third data unit, it is determined that the first data unit obtained from the currently processed third data unit satisfies the repetition rate matching condition, then, based on the unit to be merged corresponding to the previous third data unit, determine the unit to be merged that matches the currently processed third data unit.

[0225] In one embodiment, the second data unit generation module 330 is further configured to: generate a plurality of zeroing units, wherein each soft bit in the zeroing unit is 0, the unit length of the zeroing unit is a target length, the total number of soft bits in each zeroing unit is the product of a boosting factor and 2, and the unit encoding position corresponding to each zeroing unit precedes the unit encoding position corresponding to each first data unit; if there are padding bits in the encoded data, then the padding bits are acquired and a padding unit is generated, wherein the unit length of the padding unit is the target length; if there is a first data unit that satisfies the repetition rate matching condition or if there is redundancy in the encoded data. If a punctured bit is found before the version number, a redundant version number is obtained, and a redundant version number unit is generated. The unit length of the redundant version number unit is the target length, and the unit encoding position corresponding to each redundant version number unit is before the unit encoding position corresponding to each first data unit. If there is a first data unit that meets the repetition rate matching condition or if there is a redundant version number punctured bit in the encoded data, a redundant version number punctured bit is obtained, and a redundant version number punctured bit is generated. The unit length of the redundant version number punctured bit is the target length, and the unit encoding position corresponding to each redundant version number punctured bit is after the unit encoding position corresponding to each first data unit.

[0226] The above-described decoding device can execute the decoding method provided in the embodiments of this application, and has the corresponding functional modules and beneficial effects of the executed decoding method.

[0227] This application provides a network device, which includes a processor and a memory; the processor is used to execute a program stored in the memory to implement the method described in the above embodiments. The network device is a power supply device for powering the device.

[0228] As a computer-readable storage medium, a memory can be used to store software programs, computer-executable programs, and modules, such as the program instructions / modules corresponding to the decoding method in the embodiments of this application.

[0229] The memory may primarily comprise a program storage area and a data storage area. The program storage area may store the operating system and at least one application program required for a given function; the data storage area may store data created based on terminal usage. Furthermore, the memory may include high-speed random access memory (RAM) and non-volatile memory, such as at least one disk storage device, flash memory, or other non-volatile solid-state storage device. In some instances, the memory may further include memory remotely located relative to the processor, which can be connected to the device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks (LANs), mobile communication networks, and combinations thereof.

[0230] This application provides a storage medium storing a computer program that, when executed by a processor, implements the methods described in the above embodiments.

[0231] The computer storage medium of this invention can be any combination of one or more computer-readable media. A computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: an electrical connection having one or more wires, a portable computer disk, a hard disk, RAM, read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable CD-ROM, optical storage device, magnetic storage device, or any suitable combination thereof. In this document, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0232] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including—but not limited to—electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media may also be any computer-readable medium other than computer-readable storage media, capable of transmitting, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device.

[0233] Program code contained on a computer-readable medium may be transmitted using any suitable medium, including—but not limited to—wireless, wire, optical fiber, radio frequency (RF), etc., or any suitable combination thereof.

[0234] Computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including LANs or WANs—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0235] The above description is merely an exemplary embodiment of this application and is not intended to limit the scope of protection of this application.

[0236] Those skilled in the art will understand that the term user terminal encompasses any suitable type of wireless user equipment, such as mobile phones, portable data processing devices, portable web browsers, or vehicle-mounted mobile stations.

[0237] Generally, the various embodiments of this application can be implemented in hardware or dedicated circuitry, software, logic, or any combination thereof. For example, some aspects can be implemented in hardware, while others can be implemented in firmware or software that can be executed by a controller, microprocessor, or other computing device, although this application is not limited thereto.

[0238] Embodiments of this application can be implemented by executing computer program instructions through the data processor of a mobile device, for example, in a processor entity, or through hardware, or through a combination of software and hardware. The computer program instructions can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages.

[0239] Any block diagram of logical flow in the accompanying drawings of this application may represent program steps, or may represent interconnected logic circuits, modules, and functions, or may represent a combination of program steps and logic circuits, modules, and functions. The computer program may be stored in memory. The memory may be of any type suitable to the local technical environment and may be implemented using any suitable data storage technology, such as, but not limited to, read-only memory (ROM), random access memory (RAM), optical storage devices and systems (Digital Multifunction Discs, DVDs, or CDs), etc. Computer-readable media may include non-transitory storage media. The data processor may be of any type suitable to the local technical environment, such as, but not limited to, general-purpose computers, special-purpose computers, microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), programmable logic devices (FGPAs), and processors based on multi-core processor architectures.

[0240] A detailed description of exemplary embodiments of this application has been provided above through exemplary and non-limiting examples. However, various modifications and adjustments to the above embodiments will be apparent to those skilled in the art when considered in conjunction with the accompanying drawings and claims, without departing from the scope of the invention. Therefore, the proper scope of the invention will be determined by the claims.< / null>

Claims

1. A decoding method, characterized in that, include: Receive the data before deinterleaving and the soft bit encoding position; The soft bit encoding position includes the position of each soft bit in the encoded data in the data before deinterleaving and the position of each soft bit in the encoded data in the data after puncturing. The data before deinterleaving is divided to obtain the first data unit; Obtain the punctured data and obtain a second data unit based on the punctured data. The determination of the pre-deinterleaving data and the punctured data in the encoded data based on the soft bit encoding position includes: determining the punctured data based on the position of the soft bit located in the punctured data in the encoded data for the soft bit encoding position; and determining the position of each soft bit in the pre-deinterleaving data in the encoded data based on the position of at least one of repeated, retransmitted, and non-repeated soft bits in the encoded data, thereby determining the pre-deinterleaving data. Decoding is performed based on the soft bit encoding position, the first data unit, and the second data unit to obtain decoded data. The decoding process includes: determining the unit encoding position of each first data unit based on the soft bit encoding position and the first soft bit in each first data unit; determining the unit encoding position of each second data unit based on the soft bit encoding position and the first soft bit in each second data unit; and storing the first data unit and the second data unit at matching memory addresses in the decoder according to their respective unit encoding positions to arrange the first data units and the second data units, forming data to be decoded, so that the decoder can decode the data to be decoded.

2. The method according to claim 1, characterized in that, The unit length of both the first data unit and the second data unit is a target length, which is determined based on a boosting factor.

3. The method according to claim 2, characterized in that, The target length is the ratio of the enhancement factor to a power of 2.

4. The method according to claim 1, characterized in that, The process of receiving data before deinterleaving and dividing the data before deinterleaving to obtain a first data unit includes: The soft bits of the interleaved matrix are output column by column in a multi-channel parallel receiving process; The soft bits received from each channel are stored sequentially to generate multiple third data units; According to a set number of clock cycles, each of the third data units is sequentially soft-merged to form multiple first data units.

5. The method according to claim 4, characterized in that, The sequential storage of each received soft bit generates multiple third data units, including: If the received target soft bit satisfies the padding bit start-adjacent condition, then the current third data unit is generated with the target soft bit as the last soft bit received, and the next soft bit is received to generate the next third data unit.

6. The method according to claim 4, characterized in that, The soft merging of the third data unit to form the first data unit includes: Based on the unit code position corresponding to the third data unit, query the set to be merged to find the unit to be merged that matches the third data unit, and merge them to obtain the first data unit; Based on the first data unit, the matching unit to be merged is updated in the set to be merged. The unit length of the unit to be merged is the target length. The unit to be merged is used to store historical merge data. The historical merge data is used to merge with the soft bits in the third data unit to update the soft bits in the third data unit.

7. The method according to claim 4, characterized in that, The set number of cycles is the same as the target number of cycles, or is determined based on half of the target number of cycles. The set number of cycles is an integer. The target number of cycles includes the number of clock cycles corresponding to the time required from the start of soft merging of the third data unit to the generation of the first data unit.

8. The method according to claim 7, characterized in that, The set number of cycles is determined based on half of the target number of cycles, and the set number of cycles is an integer. The soft merging of the third data unit to form the first data unit includes: If, based on the unit encoding position corresponding to the currently processed third data unit and the unit encoding position corresponding to the previous third data unit, it is determined that the first data unit obtained from the currently processed third data unit satisfies the repetition rate matching condition, then, based on the unit to be merged corresponding to the previous third data unit, the unit to be merged that matches the currently processed third data unit is determined.

9. The method according to claim 1, characterized in that, The step of acquiring the punched data and generating a second data unit based on the punched data includes: Multiple zeroing units are generated, each of which includes 0 soft bits. The unit length of the zeroing unit is the target length. The total number of soft bits included in each zeroing unit is the product of the boost factor and 2. The unit encoding position corresponding to each zeroing unit is earlier than the unit encoding position corresponding to each of the first data units. If padding bits exist in the encoded data, the padding bits are obtained and padding units are generated, wherein the length of the padding unit is the target length; If there is a first data unit that meets the repetition rate matching condition or if there is a redundant version before punctured bit in the encoded data, then the redundant version before bit is obtained and a redundant version before unit is generated. The unit length of the redundant version before unit is the target length, and the unit encoding position corresponding to each of the redundant version before units is before the unit encoding position corresponding to each of the first data units. If there is a first data unit that meets the repetition rate matching condition or if there is a redundant version followed by a punctured bit in the encoded data, then the redundant version followed bit is obtained and a redundant version followed unit is generated. The unit length of the redundant version followed unit is the target length, and the unit encoding position corresponding to each redundant version followed unit is after the unit encoding position corresponding to each first data unit.

10. A decoding device, characterized in that, include: The pre-deinterleaving data receiving module is used to receive the pre-deinterleaving data and the soft bit encoding position; The soft bit encoding position includes the position of each soft bit in the encoded data in the data before deinterleaving and the position of each soft bit in the encoded data in the data after puncturing. The first data unit generation module is used to divide the uninterrupted data to obtain the first data unit; The second data unit generation module is used to acquire the punctured data and obtain a second data unit based on the punctured data. The determination of the pre-deinterleaving data and the punctured data in the encoded data based on the soft bit encoding position includes: determining the punctured data based on the position of the soft bit located in the punctured data in the encoded data for the soft bit encoding position; and determining the position of each soft bit in the pre-deinterleaving data in the encoded data based on the position of at least one of repeated, retransmitted, and non-repeated soft bits in the encoded data, thereby determining the pre-deinterleaving data. The decoding data determination module is used to decode according to the soft bit encoding position, the first data unit, and the second data unit to obtain decoded data. The decoding data determination module is used to: determine the unit encoding position of each first data unit based on the soft bit encoding position and the first soft bit in each first data unit; determine the unit encoding position of each second data unit based on the soft bit encoding position and the first soft bit in each second data unit; and store the first data unit and the second data unit at matching storage addresses in the decoder according to each unit encoding position, thereby arranging the first data unit and the second data unit to form data to be decoded, so that the decoder can decode the data to be decoded.

11. A network device, the network device comprising at least one processor and a memory; The processor is used to execute a program stored in the memory to implement the method according to any one of claims 1-9.

12. A storage medium, characterized in that, The storage medium stores a computer program that, when executed by a processor, implements the method described in any one of claims 1-9.

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