Display substrate and display device

Abstract

A display substrate and a display device. The display substrate includes a substrate (1), a sub-pixel (10) on the substrate (1), a data line (420), a planar layer (6), and an interlayer insulating layer (2, 3, 4). The sub-pixel (10) includes a light emitting element (11) and a pixel circuit (12), the light emitting element (11) includes a second electrode (112, 122, 220, 320), and the second electrode (112, 122, 220, 320) includes a main body electrode (1121, 1221, 221, 321). The sub-pixel (10) includes a third color sub-pixel (300) and a second color sub-pixel (200). The data line (420) extends along a first direction, and the main body electrodes (321, 221) of the third color sub-pixel (300) and the second color sub-pixel (200) overlap two data lines (420). The sub-pixel (10) includes a second connecting portion (520), in the third color sub-pixel (300), a connecting electrode (322) is connected with the second connecting portion (520) through a second via (3012) penetrating the planar layer (6), the second connecting portion (520) is electrically connected with the pixel circuit (12) through a second connecting hole (3022) penetrating the interlayer insulating layer (2, 3, 4), the second via (3012) and the second connecting hole (3022) do not overlap the main body electrode (321), and the second via (3012) and the second connecting hole (3022) have an overlap in the orthogonal projection on a first straight line extending along the first direction, so as to ensure the flatness of each second electrode (112, 122, 220, 320) and effectively improve color deviation.

Description

[0001] This application claims priority to PCT application No. PCT / CN2019 / 098708, filed on July 31, 2019, and PCT application No. PCT / CN2019 / 098731, filed on July 31, 2019. For all purposes, the disclosures of the aforementioned PCT applications are incorporated herein by reference in their entirety as part of this application. Technical Field

[0002] At least one embodiment of this disclosure relates to a display substrate and a display device. Background Technology

[0003] With the development of organic light-emitting diode (OLED) display technology, such as active-matrix organic light-emitting diode (AMOLED) display technology, people have increasingly higher requirements for display effects. The design of pixel circuits in display products is crucial to the display characteristics of AMOLED products. Currently, improving the display characteristics of organic light-emitting display devices has become a key focus of OLED display device research and development. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a display substrate and a display device.

[0005] At least one embodiment of this disclosure provides a display substrate, comprising: a substrate; and a plurality of sub-pixels located on the substrate, each sub-pixel including a light-emitting element and a pixel circuit for driving the light-emitting element. The light-emitting element includes a first electrode, a light-emitting layer, and a second electrode sequentially stacked along a direction close to the substrate. Each second electrode includes a main electrode and a connecting electrode. The plurality of sub-pixels includes a plurality of first-color sub-pixels and a plurality of second-color sub-pixels. Each first-color sub-pixel includes a first effective light-emitting area. The shape of the main electrode of the first-color sub-pixel is the same as the shape of the first effective light-emitting area, and the orthographic projection of the first effective light-emitting area onto the substrate is located at the position of the main electrode on the substrate. Within the orthographic projection on the substrate, each second color sub-pixel includes a second effective light-emitting area. The shape of the main electrode of the second color sub-pixel is the same as the shape of the second effective light-emitting area, and the orthographic projection of the second effective light-emitting area on the substrate is located within the orthographic projection of the main electrode on the substrate. Multiple data lines are located on the side of the second electrode facing the substrate, each data line extending along a first direction, and the main electrode of at least one of the first color sub-pixel and the second color sub-pixel overlaps with at least two data lines. A planarization layer is located between the film layer containing the multiple data lines and the film layer containing the second electrode. An interlayer insulating layer is located between the film layer containing the multiple data lines and the substrate. Each of the sub-pixels includes a first connection portion disposed on the same layer as the data line. In the first color sub-pixel, the connection electrode is connected to the first connection portion through a first via penetrating the planarization layer. The first connection portion is electrically connected to the pixel circuit through a first connection hole penetrating the interlayer insulating layer. Along the direction perpendicular to the substrate, neither the first via nor the first connection hole overlaps with the main electrode, and the orthographic projections of the first via and the first connection hole on a first straight line extending along the first direction overlap.

[0006] For example, in an embodiment of this disclosure, at least one of the first effective light-emitting area and the second effective light-emitting area is elongated and extends along a second direction, wherein the angle between the second direction and the first direction is in the range of 80° to 100°.

[0007] For example, in an embodiment of this disclosure, in the second color sub-pixel, the connecting electrode is connected to the first connecting portion through a second via penetrating the planarization layer. The first via is located in the first direction on the side of the first effective light-emitting area close to the second effective light-emitting area, and the second via is located in the first direction on the side of the second effective light-emitting area close to the first effective light-emitting area. The first line connecting the first via and the second via is not parallel to the second direction, and the second electrode of the first color sub-pixel and the second electrode of the second color sub-pixel do not overlap in the second direction.

[0008] For example, in an embodiment of this disclosure, in the second color sub-pixel, the first connecting portion is electrically connected to the pixel circuit through a second connecting hole penetrating the interlayer insulating layer, and the second connecting line connecting the first connecting hole and the second connecting hole is parallel to the second direction.

[0009] For example, in an embodiment of this disclosure, the angle between the first connecting line and the second direction is 5 to 15°.

[0010] For example, in an embodiment of this disclosure, the orthographic projection of the first via on the first straight line does not overlap with the orthographic projection of the second via on the first straight line.

[0011] For example, in an embodiment of this disclosure, the first via is located on the side of the first effective light-emitting area close to a second straight line passing through the second via and extending along the second direction.

[0012] For example, in an embodiment of this disclosure, the second effective light-emitting area includes a first long side and a second long side extending along the second direction. The second long side is located on the side of the first long side away from the second via. Along a third direction perpendicular to the substrate, the extension line of the first long side overlaps with the first via.

[0013] For example, in an embodiment of this disclosure, the first effective light-emitting area includes a third long side and a fourth long side extending along the second direction, the fourth long side being located on the side of the third long side away from the first via, and the extension line of the third long side overlapping the second via along the third direction.

[0014] For example, in an embodiment of this disclosure, the first long side is a straight line side, and the third long side is a straight line side.

[0015] For example, in an embodiment of this disclosure, the shortest distance between the first long side and the orthographic projection of the second via on the substrate is a first distance, and the shortest distance between the third long side and the orthographic projection of the first via on the substrate is a second distance, and the ratio of the first distance to the second distance is 0.8 to 1.2.

[0016] For example, in an embodiment of this disclosure, both the first distance and the second distance are greater than 3 micrometers.

[0017] For example, in an embodiment of this disclosure, the pixel circuit includes a first light-emitting control transistor, the first light-emitting control transistor includes an active semiconductor layer, the interlayer insulating layer is located between the active semiconductor layer and the first connection portion, in the first color sub-pixel, the first connection portion is electrically connected to the first electrode of the first light-emitting control transistor through the first connection hole, and in the second color sub-pixel, the second connection hole of the first connection portion is electrically connected to the first electrode of the first light-emitting control transistor.

[0018] For example, in an embodiment of this disclosure, along a third direction perpendicular to the substrate, the second connecting hole overlaps with the second effective light-emitting area, the second via is further away from the second effective light-emitting area than the second connecting hole, and the orthographic projection of the second via on the first straight line does not overlap with the orthographic projection of the second connecting hole on the first straight line.

[0019] For example, in an embodiment of this disclosure, the plurality of sub-pixels further includes a plurality of third color sub-pixel pairs, each of the third color sub-pixel pairs including a first pixel block and a second pixel block arranged along the second direction, the second electrode of the first pixel block being connected to the first connection portion through a third via penetrating the planarization layer, the second electrode of the second pixel block being connected to the first connection portion through a fourth via penetrating the planarization layer, and the third line connecting the third via and the fourth via being parallel to the second direction.

[0020] For example, in an embodiment of this disclosure, along a third direction perpendicular to the substrate, the line containing the third connecting line passes through the second via but not through the first via.

[0021] For example, in an embodiment of this disclosure, the first effective light-emitting area includes a third long side and a fourth long side extending along the second direction. The fourth long side is located on the side of the third long side away from the first via. Along a third direction perpendicular to the substrate, the line containing the third long side overlaps with both the third via and the fourth via.

[0022] For example, in an embodiment of this disclosure, in the first sub-pixel block, the first connection portion is electrically connected to the first electrode of the first light-emitting control transistor through a third connection hole penetrating the interlayer insulating layer; in the second sub-pixel block, the first connection portion is electrically connected to the first electrode of the first light-emitting control transistor through a fourth connection hole penetrating the interlayer insulating layer, and the fourth connecting line connecting the third connection hole and the fourth connection hole substantially coincides with the second connecting line.

[0023] For example, in an embodiment of this disclosure, a third or fourth via is provided between the first and second vias along the second direction.

[0024] For example, in an embodiment of this disclosure, the first color sub-pixel is a blue sub-pixel, the second color sub-pixel is a red sub-pixel, and the third color sub-pixel pair is a green sub-pixel pair.

[0025] For example, in an embodiment of this disclosure, the pixel circuit includes a second connection portion, a driving transistor, and a threshold compensation transistor located between the second electrode and the substrate. The second connection portion extends along the first direction. The first electrode of the threshold compensation transistor is electrically connected to the first electrode of the driving transistor, and the second electrode of the threshold compensation transistor is electrically connected to the gate of the driving transistor through the second connection portion. In the first pixel block, the minimum distance between the orthographic projection of the second connection portion on the straight line extending along the second direction and the orthographic projection of the effective light-emitting area of ​​the first pixel block on the straight line is a first distance. Alternatively, the minimum distance between the orthographic projection of the second connection portion on the straight line extending along the second direction and the first pixel block is a first distance. The effective light-emitting areas of the pixel block overlap on the straight line; in the second pixel block, the minimum distance between the orthographic projection of the second connecting portion on the straight line and the orthographic projection of the effective light-emitting area of ​​the second pixel block on the straight line is the second distance, and the first distance is less than the second distance; in the first pixel block, the overlap area between the orthographic projection of the second electrode on the substrate and the orthographic projection of the second connecting portion on the substrate is the first overlap area, and in the second pixel block, the overlap area between the orthographic projection of the second electrode on the substrate and the orthographic projection of the second connecting portion on the substrate is the second overlap area, and the ratio of the first overlap area to the second overlap area is 0.8 to 1.2.

[0026] For example, in embodiments of this disclosure, in the first pixel block, the second electrode covers 60-90% of the area of ​​the second connection portion; in the second pixel block, the second electrode covers 60-90% of the area of ​​the second connection portion.

[0027] For example, in an embodiment of this disclosure, in the first pixel block, the gate of the threshold compensation transistor is located on the side of the second connection portion away from the effective light-emitting area of ​​the first pixel block; in the second pixel block, the gate of the threshold compensation transistor is located on the side of the second connection portion close to the effective light-emitting area of ​​the second pixel block.

[0028] For example, in an embodiment of this disclosure, in the third color sub-pixel pair, the second electrode further includes an auxiliary electrode connecting the main electrode and the connecting electrode. The connecting electrode extends along the first direction. In the first pixel block, the auxiliary electrode is located on the side of the main electrode away from the effective light-emitting area of ​​the second pixel block. In the second pixel block, the auxiliary electrode is located on the side of the main electrode away from the effective light-emitting area of ​​the first pixel block. In the second pixel block, the first edge of the edge of the connecting electrode near the auxiliary electrode extending along the first direction, which is away from the effective light-emitting area of ​​the second pixel block, overlaps with the second connecting portion. The second edge of the auxiliary electrode away from the effective light-emitting area of ​​the second pixel block is located on the side of the second connecting portion away from the effective light-emitting area of ​​the second pixel block, so that the auxiliary electrode covers the second connecting portion.

[0029] For example, in the pixel circuit of each sub-pixel, the threshold compensation transistor includes a first gate and a second gate. In the first pixel block, the first gate is located on the side of the second gate near the effective light-emitting area of ​​the first pixel block. The third edge of the edge extending along the first direction of the portion of the connecting electrode near the auxiliary electrode overlaps with the first gate. The edge of the portion of the auxiliary electrode away from the connecting electrode away from the effective light-emitting area of ​​the first pixel block in the second direction is located on the side of the first gate away from the effective light-emitting area of ​​the first pixel block, so that the auxiliary electrode covers at least a portion of the first gate.

[0030] For example, in an embodiment of this disclosure, the display substrate further includes: a first power signal line, disposed on the same layer as the data line and extending along the first direction. The data line includes a first data line, and along a direction perpendicular to the substrate, the second electrode of each second color sub-pixel overlaps with the first data line, the first power signal line, and the second connection portion. In the overlapping portions of the first data line, the first power signal line, and the second connection portion with the second electrode, the first power signal line and the first data line are located on opposite sides of the second connection portion. The second connection portion includes a first sub-connection portion connected to each other and a first pad located on the side of the first sub-connection portion near the first power signal line. Both the first sub-connection portion and the first pad overlap with the second electrode. Along the first direction, the size of the first sub-connection portion is larger than the size of the first pad. The ratio of the minimum distance between the edges of the first sub-connection portion and the first data line that are close to each other to the minimum distance between the edges of the first pad and the first power signal line that are close to each other is 0.8 to 1.2.

[0031] For example, in an embodiment of this disclosure, a straight line extending along the first direction from the midpoint of the line connecting the two opposite endpoints of the effective light-emitting area of ​​the second color sub-pixel in the second direction overlaps with the second connecting portion.

[0032] For example, in an embodiment of this disclosure, the display substrate further includes: a second power signal line, which is on the same layer as the first power signal line and alternately arranged; the data line further includes a second data line, which is alternately arranged with the first data line and the second data line. Along a direction perpendicular to the substrate, the second electrode of each second color sub-pixel overlaps with the first data line, the first power signal line, the second connection portion, the second data line, and the second power signal line. In the overlapping portion, the second power signal line is located on the side of the first data line away from the second connection portion, and the second data line is located on the side of the first power signal line away from the second connection portion.

[0033] For example, in an embodiment of this disclosure, the shape of the first sub-connection portion is a rectangle extending along the first direction, and the straight line passing through the center of the effective light-emitting area of ​​the second color sub-pixel and extending along the first direction is located on the side of the straight line passing through the center of the first sub-connection portion and extending along the first direction that is close to the first pad.

[0034] For example, in an embodiment of this disclosure, the display substrate further includes: a reset power signal line extending along the second direction and located between the film layer containing the data line and the substrate. The pixel circuit further includes a third connection portion disposed on the same layer as the data line, the third connection portion extending along the first direction; the pixel circuit further includes a reset transistor, one of the first and second electrodes of the reset transistor being electrically connected to the reset power signal line through the third connection portion. Along a direction perpendicular to the substrate, the effective light-emitting area of ​​the second color sub-pixel overlaps with the third connection portion, and a straight line passing through the center of the effective light-emitting area of ​​the second color sub-pixel and extending along the first direction overlaps with the third connection portion. The second connection portion is located on one side of the straight line passing through the center of the effective light-emitting area of ​​the second color sub-pixel and extending along the second direction, and at least a portion of the third connection portion is located on the other side of the straight line.

[0035] At least one embodiment of this disclosure provides a display device including the above-described display substrate. Attached Figure Description

[0036] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure, and are not intended to limit this disclosure.

[0037] Figure 1 This is a partial planar structure schematic diagram of a display substrate provided according to an embodiment of the present disclosure;

[0038] Figure 2 for Figure 1 The equivalent diagram of the pixel circuit for each sub-pixel is shown.

[0039] Figure 3A This is a partial planar structural schematic diagram of the stacked structure of the active semiconductor layer and the first conductive layer of a pixel circuit according to an embodiment of the present disclosure;

[0040] Figure 3B This is a partial planar structural schematic diagram of the stacked structure of the active semiconductor layer, the first conductive layer, and the second conductive layer provided according to an embodiment of the present disclosure.

[0041] Figure 3C This is a schematic diagram showing the location of vias in each insulating layer according to embodiments of this disclosure;

[0042] Figure 3D This is a partial planar structure diagram of the source / drain metal layer provided according to an embodiment of the present disclosure;

[0043] Figure 3EThis is a schematic diagram of the stacked structure of an active semiconductor layer, a first conductive layer, a second conductive layer, and a source / drain metal layer according to an embodiment of the present disclosure;

[0044] Figure 4 This is a schematic diagram of the second electrode and the effective light-emitting area of ​​the light-emitting element of each sub-pixel according to embodiments of the present disclosure;

[0045] Figure 5A This is a schematic diagram of the stacked structure of the light-emitting element and source / drain metal layer of each sub-pixel according to an embodiment of the present disclosure;

[0046] Figure 5B This is a schematic diagram of the stacked structure of the light-emitting element of each sub-pixel with the active semiconductor layer, the first conductive layer and the source / drain metal layer according to the embodiments of this disclosure;

[0047] Figure 5C This is a schematic diagram of the stacked structure of the light-emitting element of each sub-pixel with the active semiconductor layer, the first conductive layer, the second conductive layer and the source / drain metal layer according to the embodiments of this disclosure;

[0048] Figure 5D For along Figure 5C The cross-sectional view of the section cut by line A1A2 shown;

[0049] Figure 5E For along Figure 5C The cross-sectional view of line A3A4 shown;

[0050] Figure 5F For along Figure 5C The cross-sectional view of line A5A6 shown;

[0051] Figure 5G For along Figure 5C The cross-sectional view of line A7A8 shown;

[0052] Figure 5H As an example of an embodiment of this disclosure, along Figure 5C The cross-sectional view of line A9A10 shown;

[0053] Figure 5I In another example of an embodiment of this disclosure, along Figure 5C The cross-sectional view of line A9A10 shown;

[0054] Figure 5J For along Figure 5C The cross-sectional view of the section cut by line A11A12 shown;

[0055] Figure 6 This is a schematic diagram of a partial cross-sectional structure of a display substrate;

[0056] Figure 7This is a schematic diagram of a partial cross-sectional structure of another display substrate; and

[0057] Figure 8 This is a schematic diagram of a pixel arrangement structure in a display substrate. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the described embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0059] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects.

[0060] The features such as "parallel," "perpendicular," and "identical" used in the embodiments of this disclosure include features in the strict sense of "parallel," "perpendicular," and "identical," as well as cases where "approximately parallel," "approximately perpendicular," and "approximately identical" include a certain degree of error. Taking into account measurement and errors associated with the measurement of a specific quantity (i.e., limitations of the measurement system), they represent the acceptable deviation range for a specific value as determined by a person skilled in the art. The term "center" in the embodiments of this disclosure can include a position strictly located at the geometric center as well as a position approximately at the center within a small area surrounding the geometric center. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the value.

[0061] This disclosure provides a display substrate and a display device. The display substrate includes a substrate; a plurality of sub-pixels located on the substrate, each sub-pixel including a light-emitting element and a pixel circuit for driving the light-emitting element, the light-emitting element including a first electrode, a light-emitting layer and a second electrode sequentially stacked along a direction close to the substrate, each second electrode including a main electrode and a connecting electrode, the plurality of sub-pixels including a plurality of first color sub-pixels and a plurality of second color sub-pixels, each first color sub-pixel including a first effective light-emitting area, the shape of the main electrode of the first color sub-pixel being the same as the shape of the first effective light-emitting area, and the orthographic projection of the first effective light-emitting area on the substrate being located at the orthographic projection of the main electrode on the substrate. Within the image, each second color sub-pixel includes a second effective light-emitting area, the shape of the main electrode of the second color sub-pixel is the same as the shape of the second effective light-emitting area, and the orthographic projection of the second effective light-emitting area on the substrate is located within the orthographic projection of the main electrode on the substrate; multiple data lines are located on the side of the second electrode facing the substrate, each data line extends along a first direction, and the main electrode of at least one of the first color sub-pixel and the second color sub-pixel overlaps with at least two data lines; a planarization layer is located between the film layer containing the multiple data lines and the film layer containing the second electrode; and an interlayer insulating layer is located between the film layer containing the multiple data lines and the substrate. Each sub-pixel includes a first connection portion disposed on the same layer as the data line. In the first color sub-pixel, the connection electrode is connected to the first connection portion through a first via penetrating the planarization layer. The first connection portion is electrically connected to the pixel circuit through a first connection hole penetrating the interlayer insulating layer. Along the direction perpendicular to the substrate, neither the first via nor the first connection hole overlaps with the main electrode. Moreover, the orthographic projections of the first via and the first connection hole on a first straight line extending along the first direction overlap, so as to ensure the planarity of the second electrode of the second color sub-pixel and the first color sub-pixel, so as to ensure the consistency of the light emission intensity of the effective light-emitting area in all directions and effectively improve color shift.

[0062] The display substrate and display device provided in the embodiments of this disclosure are described below with reference to the accompanying drawings.

[0063] Figure 1 This is a partial planar structural diagram of a display substrate provided according to an embodiment of the present disclosure. Figure 1 As shown, the display substrate includes a substrate 1 and a plurality of sub-pixels 10 located on the substrate 1. For example, as Figure 1As shown, multiple sub-pixels 10 are arranged into multiple repeating units 20. Each repeating unit 20 includes a second-color sub-pixel 200, a first-color sub-pixel pair 100, and a third-color sub-pixel 300 arranged along a first direction (the X direction shown in the figure). The first-color sub-pixel pair 100 includes two first-color sub-pixels 110 and 120 arranged along a second direction (the Y direction shown in the figure, which is different from the first direction). The multiple repeating units 20 are arranged along the first direction to form multiple repeating unit groups. The multiple repeating unit groups are arranged along the second direction, and adjacent repeating unit groups in the multiple repeating unit groups are staggered from each other along the first direction, that is, adjacent repeating unit groups have a certain offset along the first direction. Therefore, sub-pixels of the same color in adjacent repeating unit groups are not aligned in the second direction. The pixel arrangement is the same in odd-numbered repeating unit groups, and the pixel arrangement is the same in even-numbered repeating unit groups.

[0064] For example, the offset of adjacent repeating unit groups in the first direction is approximately half the size of the repeating unit 20 in the first direction. For example, the size of the repeating unit 20 in the first direction is the pitch of the repeating unit 20 in the first direction. Here, the pitch refers to the distance between the centers of the effective light-emitting areas of two second color sub-pixels 200 in two adjacent repeating units 20 along the first direction, where the center of the effective light-emitting area refers to the geometric center of the planar shape of the effective light-emitting area.

[0065] For example, the second direction and the first direction mentioned above are two directions in the same plane, and the angle between the two directions is in the range of 80° to 100°. For example, this plane is the plane in which pixels are arranged. The repeating unit here only refers to the repetition of sub-pixels; other structures can be different or the same. In addition, the above-mentioned repetition means that the approximate position, shape, and size are similar. In some cases, the shape may be slightly different for wiring or hole opening needs, such as holes in different positions.

[0066] For example, such as Figure 1 As shown, the effective light-emitting area 201 of the second color sub-pixel 200 is an elongated strip extending along the second direction. For example, the effective light-emitting area 301 of the third color sub-pixel 300 is also an elongated strip extending along the second direction. For example, the display substrate also includes a data line 420 located on the substrate 10, which extends along the first direction. Thus, the angle between the extending direction of the effective light-emitting area of ​​the second color sub-pixel and the extending direction of the data line is in the range of 80° to 100°. When the angle between the opening extending direction of the fine metal mask (FMM) used for vapor deposition of each color sub-pixel and the extending direction of the data line is in the range of 80° to 100°, for example, 90°, the extending direction of the effective light-emitting area of ​​the second color sub-pixel is the same as the extending direction of the FMM opening.

[0067] For example, such as Figure 1 As shown, the effective light-emitting areas 201 and 301 of the second color sub-pixel 200 and the third color sub-pixel 300 have shapes including hexagons or ellipses. Furthermore, although the shapes of the second and third color sub-pixels in the figure include strictly defined angles formed by two line segments, in some embodiments, the effective light-emitting areas of the second and third color sub-pixels can both be rounded shapes, such as ellipses. That is, based on the aforementioned hexagonal shape, the corners of the effective light-emitting areas of the second and third color sub-pixels are rounded. For example, when forming an opening in the pixel defining layer, the corners of the opening are rounded, resulting in a rounded shape for the formed effective light-emitting area. The hexagon in the embodiments of this disclosure can include a standard hexagon or an approximate hexagon, such as a rounded hexagon or a roughly hexagonal shape with a hexagonal outline.

[0068] For example, this embodiment of the present disclosure schematically shows that the first color sub-pixel pair 100 is a green sub-pixel pair, the second color sub-pixel 200 is a red sub-pixel, and the third color sub-pixel 300 is a blue sub-pixel. However, this is not a limitation, and the names of the color sub-pixels can be interchanged. In this embodiment of the present disclosure, a sub-pixel pair including two sub-pixels of the same color is a green sub-pixel pair; along the extension direction of the data line, the width of the effective light-emitting area of ​​the red sub-pixel is smaller than the width of the effective light-emitting area of ​​the blue sub-pixel; the length of the effective light-emitting area of ​​the red sub-pixel is greater than the length of the effective light-emitting area of ​​the blue sub-pixel.

[0069] For example, Figure 2 for Figure 1 The equivalent diagram of the pixel circuit for each sub-pixel is shown. (See attached diagram.) Figure 2 As shown, each sub-pixel 10 includes a light-emitting element 11 and a pixel circuit 12 for driving the light-emitting element 11 to emit light. The light-emitting element 11 includes a first electrode, a light-emitting layer, and a second electrode stacked sequentially, with the second electrode located between the light-emitting layer and the substrate. For example, Figure 5E The schematic diagram shows a light-emitting element including a first electrode 310, a light-emitting layer 330, and a second electrode 320, with the second electrode 320 located between the light-emitting layer 330 and the substrate 1. For example, the display substrate also includes a reset power signal line, a scan signal line, a power signal line, a reset control signal line, and a light-emitting control signal line located on the substrate 10. For example, in embodiments of this disclosure, the names of the first electrode and the second electrode can be interchanged.

[0070] For example, such as Figure 2As shown, each pixel circuit 12 includes a data writing transistor T4, a driving transistor T3, a threshold compensation transistor T2, and a first reset control transistor T7. The first terminal of the threshold compensation transistor T2 is connected to the first terminal of the driving transistor T3, and the second terminal of the threshold compensation transistor T2 is connected to the gate of the driving transistor T3. The first terminal of the first reset control transistor T7 is connected to the reset power supply signal line to receive the reset signal Vinit, and the second terminal of the first reset control transistor T7 is connected to the light-emitting unit. The first terminal of the data writing transistor T4 is connected to the second terminal of the driving transistor T3. For example, as... Figure 2 As shown, the pixel circuit of each sub-pixel also includes a storage capacitor C, a first light-emitting control transistor T6, a second light-emitting control transistor T5, and a second reset transistor T1. The gate of the data writing transistor T4 is electrically connected to the scan signal line to receive the scan signal Gate; the first terminal of the storage capacitor C is electrically connected to the power supply signal line, and the second terminal of the storage capacitor C is electrically connected to the gate of the driving transistor T3; the gate of the threshold compensation transistor T2 is electrically connected to the scan signal line to receive the compensation control signal; the gate of the first reset transistor T7 is electrically connected to the reset control signal line to receive the reset control signal Reset(N+1); the first terminal of the second reset transistor T1 is electrically connected to the reset power supply signal line to receive the reset signal Vinit, and the second terminal of the second reset transistor T5 is electrically connected to the gate of the driving transistor T3. The gates of the second reset transistor T1 and the first light-emitting control transistor T6 are electrically connected to the light-emitting control signal line to receive the reset control signal Reset(N). The gate of the first light-emitting control transistor T6 is electrically connected to the light-emitting control signal line to receive the light-emitting control signal EM. The first electrode of the second light-emitting control transistor T5 is electrically connected to the power supply signal line to receive the first power supply signal VDD. The second electrode of the second light-emitting control transistor T5 is electrically connected to the second electrode of the driving transistor T3. The gate of the second light-emitting control transistor T5 is electrically connected to the light-emitting control signal line to receive the light-emitting control signal EM. The first electrode of the light-emitting element 11 is connected to the voltage terminal VSS. The aforementioned power supply signal line refers to the signal line for the output voltage signal VDD, which can be connected to a voltage source to output a constant voltage signal, such as a positive voltage signal.

[0071] For example, the scan signal and the compensation control signal can be the same; that is, the gate of the data writing transistor T3 and the gate of the threshold compensation transistor T2 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. Alternatively, the gate of the data writing transistor T3 and the gate of the threshold compensation transistor T2 can be electrically connected to different signal lines; that is, the gate of the data writing transistor T3 is electrically connected to the first scan signal line, and the gate of the threshold compensation transistor T2 is electrically connected to the second scan signal line. The signals transmitted by the first scan signal line and the second scan signal line can be the same or different, thus allowing the gate of the data writing transistor T3 and the threshold compensation transistor T2 to be controlled separately, increasing the flexibility of the pixel circuit control.

[0072] For example, the first light-emitting control transistor T6 and the second light-emitting control transistor T5 can receive the same light-emitting control signal. That is, the gate of the first light-emitting control transistor T6 and the gate of the second light-emitting control transistor T5 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. Alternatively, the gate of the first light-emitting control transistor T6 and the gate of the second light-emitting control transistor T5 can be electrically connected to different light-emitting control signal lines, and the signals transmitted by the different light-emitting control signal lines can be the same or different.

[0073] For example, the reset control signals input to the first reset transistor T7 and the second reset transistor T1 can be the same; that is, the gates of the first reset transistor T7 and the second reset transistor T1 can be electrically connected to the same signal line to receive the same signal, reducing the number of signal lines. Alternatively, the gates of the first reset transistor T7 and the second reset transistor T1 can be electrically connected to different reset control signal lines, in which case the signals on the different reset control signal lines can be the same or different.

[0074] For example, such as Figure 2 As shown, when the display substrate is working, in the first stage of screen display, the second reset transistor T1 is turned on to initialize the voltage of node N1; in the second stage of screen display, data is stored in node N1 through data writing transistor T4, driving transistor T3 and threshold compensation transistor T2; in the third stage of light emission, the second light emission control transistor T5, driving transistor T3 and the first light emission control transistor T6 are all turned on, and the light emission element is forward-biased to emit light.

[0075] It should be noted that, in the embodiments of this disclosure, the pixel circuit of the sub-pixel can be, in addition to being, Figure 2Besides the 7T1C (seven transistors and one capacitor) structure shown, other structures with different numbers of transistors can also be used, such as 7T2C, 6T1C, 6T2C, or 9T2C structures. This disclosure does not limit the specific implementation of these structures. The solution is simply to connect the data writing transistors T4 of the two pixel circuits and connect the N4 nodes of the two pixel circuits to enable them to jointly drive the same light-emitting unit to emit light.

[0076] Figure 3A This is a partial planar structural diagram of the stacked structure of the active semiconductor layer and the first conductive layer of a pixel circuit according to an embodiment of this disclosure. Figure 3A As shown, the active semiconductor layer 3100 can be formed by patterning semiconductor material. The active semiconductor layer 3100 can be used to fabricate the active layers of the aforementioned second reset transistor T1, threshold compensation transistor T2, driving transistor T3, data writing transistor T4, second light-emitting control transistor T5, first light-emitting control transistor T6, and first reset control transistor T7. The active semiconductor layer 3100 includes the active layer pattern (channel region) and doped region pattern (source / drain doped region) of each transistor in each sub-pixel, and the active layer pattern and doped region pattern of each transistor in the same pixel circuit are integrally formed.

[0077] It should be noted that the active layer may include an integrally formed low-temperature polycrystalline silicon layer. The source and drain regions can be made conductive through doping to achieve electrical connections between the various structures. That is, the active semiconductor layer of each transistor in each sub-pixel is an integral pattern formed of p-silicon, and each transistor in the same pixel circuit includes a doped region pattern (i.e., source and drain regions) and an active layer pattern. The active layers of different transistors are separated by doped structures.

[0078] For example, the active semiconductor layer 3100 can be fabricated using amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the aforementioned source and drain regions can be regions doped with n-type or p-type impurities.

[0079] For example, the display substrate includes a gate insulating layer located on the side of the active semiconductor layer away from the substrate, used to insulate the aforementioned active semiconductor layer 3100 from the subsequently formed first conductive layer 3200 (i.e., gate metal layer). For example, the display substrate includes a first conductive layer 3200 disposed on the gate insulating layer, thereby isolating it from the active semiconductor layer 3100. The first conductive layer 3200 may include the second terminal CC2 of capacitor C, multiple scan signal lines 430 extending along a second direction (Y direction in the figure), multiple reset control signal lines 440, multiple light emission control signal lines 450, and the gates of a second reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a second light emission control transistor T5, a first light emission control transistor T6, and a first reset control transistor T7.

[0080] For example, such as Figure 3A As shown, the gate of the data writing transistor T3 can be the portion where the scan signal line 430 overlaps with the active semiconductor layer 3100; the gate of the first light-emitting control transistor T6 can be the first portion where the light-emitting control signal line 450 overlaps with the active semiconductor layer 3100, and the gate of the second light-emitting control transistor T5 can be the second portion where the light-emitting control signal line 450 overlaps with the active semiconductor layer 3100. The gate of the second reset transistor T1 is the first portion where the reset control signal line 440 overlaps with the active semiconductor layer 3100, and the gate of the first reset control transistor T7 is the second portion where the reset control signal line 440 overlaps with the active semiconductor layer 3100. The threshold compensation transistor T2 can be a thin-film transistor with a dual-gate structure. The first gate T2-g1 of the threshold compensation transistor T2 can be the portion where the protruding structure P protruding from the scan signal line 430 overlaps with the active semiconductor layer 3100, and the second gate T2-g2 of the threshold compensation transistor T2 can be the portion where the scan signal line 430 overlaps with the active semiconductor layer 3100. Figure 3A As shown, the gate of the driving transistor T1 can be the second terminal CC2 of the capacitor C.

[0081] It should be noted that, Figure 3A The dashed rectangles in the diagram illustrate the overlapping portions of the active semiconductor layer 3100 and the first conductive layer 3200, i.e., the channel regions. As the channel regions of each transistor, the active semiconductor layers on both sides of each channel region are conductiveized through processes such as ion doping, serving as the first and second electrodes of each transistor. The source and drain electrodes of a transistor can be structurally symmetrical, so their physical structures can be indistinguishable. In the embodiments of this disclosure, to distinguish transistors, except for the gate electrode which serves as the control electrode, one electrode is directly described as the first electrode and the other as the second electrode. Therefore, in the embodiments of this disclosure, the first and second electrodes of all or some transistors can be interchanged as needed.

[0082] For example, such as Figure 3A As shown, the scan signal line 430, reset control signal line 440, and light emission control signal line 450 are arranged along the first direction (X direction). The scan signal line 430 is located between the reset control signal line 440 and the light emission control signal line 450.

[0083] For example, in the first direction, the second terminal CC2 of capacitor C (i.e., the gate of driving transistor T1) is located between scan signal line 430 and light emission control signal line 450. The protruding structure P protruding from scan signal line 430 is located on the side of scan signal line 430 away from light emission control signal line 450.

[0084] For example, a first insulating layer is formed on the first conductive layer 3200 to insulate the first conductive layer 3200 from the subsequently formed second conductive layer 3300.

[0085] Figure 3B This is a partial planar structural schematic diagram of the stacked structure of the active semiconductor layer, the first conductive layer, and the second conductive layer according to an embodiment of this disclosure. Figure 3B As shown, the second conductive layer 330 includes a first electrode CC1 of capacitor C and multiple reset power signal lines 410 extending along a second direction. The first electrode CC1 of capacitor C and the second electrode CC2 of capacitor C at least partially overlap to form capacitor C.

[0086] For example, the second conductive layer 330 also includes a plurality of cover portions S, and each threshold compensation transistor T2 includes two gates T2-g1 and T2-g2 and an active semiconductor layer 3100 located between the orthogonal projections of the two gates onto the active semiconductor layer 3100. Along a direction perpendicular to the substrate, the cover portions S overlap with the active semiconductor layer 3100 between the two gates.

[0087] For example, a second insulating layer is formed on the second conductive layer 3300 to insulate the second conductive layer 3300 from the subsequently formed source-drain metal layer 3400.

[0088] For example, Figure 3C This is a schematic diagram showing the locations of vias in each insulating layer according to embodiments of this disclosure. Figure 3D This is a partial planar structure diagram of the source / drain metal layer provided according to an embodiment of the present disclosure. Figure 3E This is a schematic diagram of the stacked structure of an active semiconductor layer, a first conductive layer, a second conductive layer, and a source / drain metal layer according to an embodiment of this disclosure. Figures 3C to 3E As shown, the source / drain metal layer 3400 includes a data line 420 and a power signal line 460 extending along a second direction. The data line 420 passes through the gate insulating layer 2 ( Figures 5D to 5H As shown), the first insulating layer 3 ( Figures 5D to 5H (as shown) and the second insulating layer 4 ( Figures 5D to 5H The via 3005 (shown) is electrically connected to the second terminal of the data writing transistor T2. The power signal line 460 is electrically connected to the first terminal of the second light-emitting control transistor T5 through a via 3009 penetrating the gate insulating layer 2, the first insulating layer 3, and the second insulating layer 4. The power signal line 460 and the data line 420 are alternately arranged along a first direction. The power signal line 460 is electrically connected to the first terminal CC1 of capacitor C (e.g., the first terminal 120-CC1 of capacitor C in the second pixel block 120, or the first terminal 300-CC1 of capacitor C in the third color sub-pixel 300) through a via 3007 penetrating the second insulating layer 4. For example, the second insulating layer 4 is an interlayer insulating layer.

[0089] For example, a dual-gate threshold compensation transistor can reduce leakage current. For instance, the active semiconductor layer between the two channels of the dual-gate threshold compensation transistor T2 is in a floating state when T2 is off, making it susceptible to fluctuations due to surrounding line voltages. This affects the leakage current of T2 and consequently, the luminous brightness. To maintain a stable voltage in the active semiconductor layer between the two channels of T2, a capacitive capacitor is formed between the capacitive portion S and the active semiconductor layer. The capacitive portion S can be connected to the power signal line 460 to obtain a constant voltage, thus maintaining a stable voltage in the floating state. The overlap between the capacitive portion S and the active semiconductor layer between the two channels of T2 also prevents the active semiconductor layer between the two gates from being altered by illumination, such as preventing voltage changes in this portion of the active semiconductor layer to prevent crosstalk. For example, as... Figures 3C to 3E As shown, the power signal line 460 can be electrically connected to the cover part S through the through hole 3003 that penetrates the second insulating layer to provide a constant voltage to the cover part S.

[0090] For example, a passivation layer 5 and a planarization layer 6 can be sequentially disposed on the side of the source / drain metal layer 3400 away from the substrate. Figures 5D to 5H (As shown) is used to protect the aforementioned source / drain metal layer 3400. For example, the planarization layer 6 can be located on the side of the passivation layer 5 away from the substrate. Of course, the embodiments disclosed herein are not limited to this; for example, the positions of the planarization layer 6 and the passivation layer 5 can be interchanged, that is, the passivation layer can be located on the side of the planarization layer away from the source / drain metal layer, or, as shown... Figure 5I As shown, only the planarization layer 6 is provided, and the passivation layer 5 is not provided.

[0091] For example, such as Figures 3C to 3E , Figure 5DAs shown, the pixel circuit of each sub-pixel also includes a first connection portion 510 disposed on the same layer as the data line 420, and the first connection portion 510 extends along a first direction. The second terminal of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3 through the first connection portion 510. The first end of the first connection portion 510 is connected to the second terminal of the threshold compensation transistor T2 (e.g., the second terminal 110-T2-2 of the threshold compensation transistor T2 of the first pixel block 110, or the second terminal 120-T2-2 of the threshold compensation transistor T2 of the second pixel block 120, or the second terminal 200-T2-2 of the threshold compensation transistor T2 of the second color sub-pixel 200) through the first connection portion 510. The second end of the first connection portion 510 is connected to the gate of the driving transistor T3 (e.g., the gate 110-T3-g of the driving transistor T3 of the first pixel block 110, or the gate 120-T3-g of the driving transistor T3 of the second pixel block 120) through the first connection portion 3006. Each sub-pixel's pixel circuit also includes a second connection portion 520 and a third connection portion 530 disposed on the same layer as the data line 420. The second connection portion 520 is connected to the second terminal of the first light-emitting control transistor T6 through a via 3008 penetrating the gate insulating layer 1, the first insulating layer 2, and the second insulating layer 3. One end of the third connection portion 530 is connected to the first terminal of the first reset transistor T7 through a via 3002 penetrating the gate insulating layer 1, the first insulating layer 2, and the second insulating layer 3. The other end of the third connection portion 530 is connected to the reset power signal line 410 through a via 3001 penetrating the second insulating layer. For example, the first connection portion 510 overlaps with the first terminal CC1 of the capacitor C (e.g., the first terminal 110-CC1 of the first pixel block 110, or the first terminal 120-CC1 of the second pixel block 120).

[0092] For example, Figure 4 This is a schematic diagram of the second electrode and the effective light-emitting area of ​​the light-emitting element of each sub-pixel according to embodiments of the present disclosure. Figure 5A This is a schematic diagram of the stacked structure of the light-emitting element and source / drain metal layer of each sub-pixel according to an embodiment of this disclosure. Figure 5B This is a schematic diagram of the stacked structure of the light-emitting element of each sub-pixel with the active semiconductor layer, the first conductive layer, and the source / drain metal layer according to the embodiments of this disclosure. Figure 5C This is a schematic diagram of the stacked structure of the light-emitting element of each sub-pixel with the active semiconductor layer, the first conductive layer, the second conductive layer, and the source / drain metal layer according to embodiments of this disclosure. Figures 4 to 5CAs shown, each first color sub-pixel pair 100 includes a first pixel block 110 and a second pixel block 120 arranged along a second direction (Y direction). The first pixel block 110 includes a first effective light-emitting area 101, and the second pixel block 120 includes a second effective light-emitting area 102. In the first pixel block 110, the minimum distance between the orthographic projection of the first connecting portion 510 on the straight line extending along the second direction and the orthographic projection of the first effective light-emitting area 101 on the same straight line is a first distance, or the orthographic projection of the first connecting portion 510 on the straight line extending along the second direction overlaps with the orthographic projection of the first effective light-emitting area 101 on the same straight line. In the second pixel block 120, the minimum distance between the orthographic projection of the first connecting portion 510 on the same straight line and the orthographic projection of the second effective light-emitting area 102 on the same straight line is a second distance, and the first distance is less than the second distance. In the first pixel block 110, the overlapping area of ​​the orthographic projection of the second electrode 112 on the substrate and the orthographic projection of the first connection portion 510 on the substrate is the first overlapping area; in the second pixel block 120, the overlapping area of ​​the orthographic projection of the second electrode 122 on the substrate and the orthographic projection of the first connection portion 510 on the substrate is the second overlapping area, and the ratio of the first overlapping area to the second overlapping area is, for example, 0.8 to 1.2, or for example, 0.9 to 1.1.

[0093] In this embodiment of the disclosure, the display substrate further includes other color sub-pixels, and the minimum distance between the first pixel block and the second pixel block in each first color sub-pixel pair is no greater than the minimum distance between two sub-pixels of the same color among the plurality of other color sub-pixels. For example, if the first color sub-pixel pair is a green sub-pixel pair, and the other color sub-pixels include red sub-pixels, then the minimum distance between two green sub-pixels in the green sub-pixel pair is less than the minimum distance between two red sub-pixels.

[0094] For example, in the first pixel block 110, the minimum distance between the center of the orthographic projection of the first connecting portion 510 on the straight line extending along the second direction and the center of the orthographic projection of the first effective light-emitting area 101 on the straight line is the first distance; in the second pixel block 120, the minimum distance between the center of the orthographic projection of the first connecting portion 510 on the straight line and the center of the orthographic projection of the second effective light-emitting area 102 on the straight line is the second distance, and the first distance is less than the second distance.

[0095] In a first color sub-pixel pair, when the distance between the geometric center of the first effective light-emitting area and the edge of the first connecting portion of the first pixel block near the first effective light-emitting area is not equal to the distance between the geometric center of the second effective light-emitting area and the edge of the first connecting portion of the second pixel block near the second effective light-emitting area, it is easy for the two first connecting portions in the two first color sub-pixels to be covered by different areas of the two second electrodes. This results in different capacitances formed between the first connecting portions and the second electrodes in the two first color sub-pixels of the same first color sub-pixel pair, which in turn leads to differences in the gate node load of the driving transistors in the two first color sub-pixels, and differences in the brightness of the two first color sub-pixels when they emit light.

[0096] In this embodiment of the disclosure, the ratio of the overlapping area of ​​the two second electrodes and the two first connection portions in the two first color sub-pixels of the same first color sub-pixel pair is set to 0.8 to 1.2, for example, 0.9 to 1.1. For example, if the ratio of the overlapping area of ​​the two second electrodes and the two first connection portions in the two first color sub-pixels of the same first color sub-pixel pair is approximately equal, the difference in gate node load of the driving transistors in the two first color sub-pixels can be minimized, so as to ensure that the brightness of the two first color sub-pixels is as similar as possible when they emit light.

[0097] For example, the ratio of the first overlapping area to the second overlapping area is 1, meaning that the two overlapping areas are exactly the same, thus ensuring that the brightness of the two first color sub-pixels is the same when they emit light.

[0098] For example, in the first pixel block 110, the second electrode 112 covers 60-90% of the area of ​​the first connecting portion 510; in the second pixel block 120, the second electrode 122 covers 60-90% of the area of ​​the first connecting portion 510. For example, in the first pixel block 110, the second electrode 112 covers 70-80% of the area of ​​the first connecting portion 510 (these coverage areas offer advantages); in the second pixel block 120, the second electrode 122 covers 70-80% of the area of ​​the first connecting portion 510. For example, considering that a certain distance is maintained between the second electrode of the second pixel block and the second electrode of the third color sub-pixel (described later), the area of ​​the second electrode of the second pixel block covering the first connecting portion cannot be too large, for example, 70%. To ensure that the area of ​​the second electrode of the first pixel block covering the first connecting portion is approximately the same as the area of ​​the second electrode of the second pixel block covering the first connecting portion, the area of ​​the second electrode of the first pixel block covering the first connecting portion is set to, for example, 70%.

[0099] For example, such as Figures 4 to 5C As shown, the relative positions of the gate of the threshold compensation transistor T2 and the first connection portion 510 in each pixel circuit are basically the same. For example, the first connection portion 510 is located between the gate of the threshold compensation transistor T2 and the second terminal of the data writing transistor T4.

[0100] For example, the two effective light-emitting areas in the first color sub-pixel pair 100 have approximately the same shape and size, and are axially symmetrically distributed with a straight line extending along the first direction and passing through the midpoint of the line connecting the centers of the two effective light-emitting areas as the central axis.

[0101] For example, the shapes of the first effective light-emitting area 101 and the second effective light-emitting area 102 may include pentagons, circles, or teardrop shapes. For example, the shapes of the first effective light-emitting area 101 and the second effective light-emitting area 102 may be pentagons, comprising a set of parallel opposite sides (parallel to the second direction) and a perpendicular side (parallel to the first direction). The perpendicular side is perpendicular to the set of parallel opposite sides. The two perpendicular sides of the two effective light-emitting areas in each first color sub-pixel pair 100 are arranged adjacent to each other, and each pentagon includes a pointed corner opposite the perpendicular side. The two pointed corners of the two effective light-emitting areas in each first color sub-pixel pair 100 are far apart from each other. For example, the distance between the two pointed corners of the two effective light-emitting areas in the first color sub-pixel pair 100 is greater than the length of the effective light-emitting areas of the second color sub-pixel 200 and the third color sub-pixel 300.

[0102] Furthermore, although the shape of the effective light-emitting area of ​​the first color sub-pixel in the figure includes a strict angle formed by two line segments, in some embodiments, the shape of the effective light-emitting area of ​​the first color sub-pixel can be a rounded shape, such as a circle or a teardrop shape. That is, based on the above-mentioned pentagonal shape, the corners of the effective light-emitting area of ​​the first color sub-pixel are rounded. For example, when forming an opening in the pixel defining layer, the corners of the opening are rounded, thus forming a rounded light-emitting area.

[0103] For example, such as Figures 4 to 5C As shown, the first effective light-emitting area 101 and the second effective light-emitting area 102 are located between the two first connecting portions 510 in the first color sub-pixel pair 100, and the perpendicular bisector M1 of the line connecting the midpoints of the two vertical sides of the first effective light-emitting area 101 and the second effective light-emitting area 102 is located on the side of the perpendicular bisector M2 of the line connecting the midpoints of the two first connecting portions 510 closer to the first connecting portion 510 of the first pixel block 110. Therefore, the distance from the center of the first effective light-emitting area to the corresponding first connecting portion is less than the distance from the center of the second effective light-emitting area to the corresponding first connecting portion.

[0104] For example, such as Figures 4 to 5CAs shown, in the first pixel block 110, the gate of the threshold compensation transistor T2 is located on the side of the first connection portion 510 away from the first effective light-emitting area 101. That is, in the first pixel block 110, the first connection portion 510 is closer to the first effective light-emitting area 101 than the gate of the threshold compensation transistor T2. In the second pixel block 120, the gate of the threshold compensation transistor T2 is located on the side of the first connection portion 510 closer to the second effective light-emitting area 102. That is, in the second pixel block 120, the gate of the threshold compensation transistor T2 is closer to the second effective light-emitting area 102 than the first connection portion 510. Therefore, the distance from the first connection portion of the second pixel block to the center of the second effective light-emitting area is greater than the distance from the first connection portion of the first pixel block to the first effective light-emitting area.

[0105] For example, such as Figures 4 to 5C As shown, the maximum length of the second electrode 122 of the second pixel block 120 along the second direction is greater than the maximum length of the second electrode 112 of the first pixel block 110 along the second direction, so that the overlap area of ​​the second electrodes of the two first color sub-pixels with the corresponding first connection portion is substantially equal.

[0106] For example, such as Figures 4 to 5C As shown, the second electrode of each sub-pixel includes a main electrode and a connecting electrode. For example, the second electrode 112 in the first pixel block 110 includes a main electrode 1121 and a connecting electrode 1122. The shape of the main electrode 1121 is approximately the same as the shape of the first effective light-emitting area 101, for example, a pentagon. For example, the orthographic projection of the first effective light-emitting area on the substrate is located within the orthographic projection of the main electrode on the substrate. For example, the orthographic projection of the main electrode 1121 on the substrate overlaps with the orthographic projection of the first connecting portion 510 on the substrate. For example, the second electrode 122 in the second pixel block 120 includes a main electrode 1221 and a connecting electrode 1122. The shape of the main electrode 1221 is approximately the same as the shape of the second effective light-emitting area 102, for example, a pentagon. For example, the orthographic projection of the second effective light-emitting area on the substrate is located within the orthographic projection of the main electrode on the substrate. For example, the orthographic projection of the main electrode 1221 on the substrate does not overlap with the orthographic projection of the first connecting portion 510 on the substrate.

[0107] For example, such as Figures 4 to 5C As shown, in the first color sub-pixel pair 100, the second electrode further includes an auxiliary electrode connecting the main electrode and the connecting electrode. For example, the second electrode 112 in the first pixel block 110 further includes an auxiliary electrode 1123 connecting the main electrode 1121 and the connecting electrode 1122, with the connecting electrode 1122 extending along a first direction. For example, the second electrode 121 in the second pixel block 120 further includes an auxiliary electrode 1223 connecting the main electrode 1221 and the connecting electrode 1222.

[0108] For example, such as Figures 4 to 5C As shown, in the first pixel block 110, the auxiliary electrode 1123 is located on the side of the main electrode 1121 away from the second effective light-emitting area 102, and in the second pixel block 120, the auxiliary electrode 1223 is located on the side of the main electrode 1221 away from the first effective light-emitting area 101. That is, the two auxiliary electrodes of the first color sub-pixel pair are located on the side of the two effective light-emitting areas that are far away from each other.

[0109] For example, such as Figures 4 to 5C As shown, the second electrode in each first color sub-pixel is an integral structure, that is, the second electrode includes a main electrode, an auxiliary electrode, and a connecting electrode as an integral structure. To clearly describe the shape of the second electrode in the first color sub-pixel and its relationship with other structures, this embodiment divides the second electrode in the first color sub-pixel into a main electrode, an auxiliary electrode, and a connecting electrode.

[0110] For example, such as Figures 4 to 5C As shown, in the first color sub-pixel pair 100, the two main electrodes 1121 and 1221 have basically the same shape and size, the two auxiliary electrodes 1123 and 1223 have different shapes, and the two connecting electrodes 1122 and 1222 have different shapes.

[0111] For example, such as Figures 4 to 5C As shown, for example, the orthographic projection of the first edge 1001 of the portion of the connecting electrode 1222 near the auxiliary electrode 1223 extending in the first direction away from the second effective light-emitting area 102 on the substrate overlaps with the orthographic projection of the first connecting portion 510 on the substrate. For example, in the second pixel block 120, the second edge 1002 of the portion of the auxiliary electrode 1223 away from the connecting electrode, which is away from the second effective light-emitting area 102 in the Y direction, is located on the side of the first connecting portion 510 away from the second effective light-emitting area 102, so that the auxiliary electrode 1223 covers at least a portion of the first connecting portion 510. For example, the portion of the connecting electrode 1222 away from the auxiliary electrode 1223 is configured to connect to the second connecting portion 520. Based on the size of the via provided in the planarization layer, the width of the portion of the connecting electrode 1222 away from the auxiliary electrode 1223 along the Y direction is greater than the width of the portion of the connecting electrode 1222 close to the auxiliary electrode 1223 along the Y direction. As a result, the edge of the edge of the portion of the connecting electrode 1222 away from the auxiliary electrode 1223 extending along the first direction that is away from the second effective light-emitting area 102 is not on a straight line with the first edge 1001.

[0112] For example, such as Figures 4 to 5CAs shown, in the first pixel block 110, the straight line containing the third edge 1003 of the edge extending along the first direction of the portion of the connecting electrode 1122 near the auxiliary electrode 1123, which is away from the first effective light-emitting area 101, is located on the side of the first connecting portion 510 away from the first effective light-emitting area 101. For example, the orthographic projection of the third edge 1003 of the portion of the connecting electrode 1122 near the auxiliary electrode 1123 on the substrate does not overlap with the orthographic projection of the first connecting portion 510 on the substrate. For example, the portion of the connecting electrode 1122 away from the auxiliary electrode 1123 is configured to connect to the second connecting portion 520. Depending on the size of the via provided in the planarization layer, the width of the portion of the connecting electrode 1122 away from the auxiliary electrode 1123 along the Y direction is greater than the width of the portion of the connecting electrode 1122 near the auxiliary electrode 1123 along the Y direction. Therefore, the edge of the edge extending along the first direction of the portion of the connecting electrode 1122 away from the auxiliary electrode 1123 that is away from the first effective light-emitting area 101 and the third edge 1003 are not on the same straight line.

[0113] For example, such as Figures 4 to 5C As shown, in the first pixel block 110, the fourth edge 1004 of the auxiliary electrode 1123 that is connected to the connecting electrode 1122 (e.g., the first part 1123-1 of the auxiliary electrode 1123 described later) away from the first effective light-emitting area 101 is on the same straight line as the third edge 1003 of the connecting electrode 1122, so as to facilitate the fabrication of the second electrode.

[0114] For example, in the second pixel block 120, the edge of the auxiliary electrode 1223 near the connecting electrode 1222, away from the second effective light-emitting area 102, is not collinear with the first edge 1001 of the connecting electrode 1222. For example, in the second pixel block 120, the second edge 1002 of the auxiliary electrode 1223, away from the connecting electrode 1222 and extending along the first direction, is not collinear with the first edge 1001 of the connecting electrode 1222. For example, in the second pixel block 120, the line containing the second edge 1002 of the auxiliary electrode 1223 is located on the side of the line containing the first edge 1001 of the connecting electrode 1221 away from the second effective light-emitting area 102 to cover the first connecting portion 510. For example, the connecting edge between the first edge 1001 and the second edge 1002 can be a straight line intersecting the X direction, but is not limited to this; it can also be a broken line or a curved edge.

[0115] This embodiment of the invention illustrates that the first edge, second edge, third edge and fourth edge are all straight edges for ease of manufacturing, but it is not limited to this. They can also be curved edges or broken edges, as long as the extension direction is along the X direction.

[0116] Since the third edge of the connecting electrode of the first pixel block is located on the side of the connecting electrode away from the first effective light-emitting area, the edge of the auxiliary electrode that connects with the connecting electrode and the third edge of the connecting electrode are on the same straight line, which can also cover the first connecting part. Therefore, the edges of the auxiliary electrode and the connecting electrode that are close to each other and away from the first connecting part can be designed to be on the same straight line for easy manufacturing.

[0117] If the first edge of the connecting electrode of the second pixel block overlaps with the first connecting portion, and the second edge of the auxiliary electrode of the second pixel block is on the same straight line as the first edge of the connecting electrode, then the area covered by the auxiliary electrode of the second pixel block in the first connecting portion will be different from the area covered by the auxiliary electrode of the first pixel block in the corresponding first connecting portion, resulting in a difference in brightness between the two first color sub-pixels. Therefore, in this embodiment, the first edge of the connecting electrode of the second pixel block and the second edge of the auxiliary electrode are not on the same side, and the straight line containing the second edge of the auxiliary electrode is located on the side of the straight line containing the first edge of the connecting electrode that is far away from the second effective light-emitting area, so that the overlap area between the auxiliary electrode and the first connecting portion in the two first color sub-pixels of the first color sub-pixel pair is substantially the same, reducing the load difference of the gate nodes of the driving transistors in the two first color sub-pixels, thereby reducing the brightness difference between the two first color sub-pixels and improving the display characteristics of the display substrate.

[0118] For example, such as Figures 3C to 5C As shown, the pixel circuit of each sub-pixel also includes a second connection portion 520 disposed on the same layer as the first connection portion 510. The second connection portion 520 is electrically connected to the second electrode of the first light-emitting control transistor T6 through a via 3008 penetrating the gate insulating layer, the first insulating layer, and the second insulating layer. The connection electrode of the second electrode of each sub-pixel is connected to the second connection portion through a via penetrating the planarization layer, thereby realizing the connection with the first light-emitting control transistor.

[0119] For example, in the first pixel block 110, the second connecting portion 520 is further away from the first effective light-emitting area 101 in the second direction than the first connecting portion 510, and thus, the connecting electrode 1122 is further away from the first effective light-emitting area 101 in the second direction than the first connecting portion 510. For example, in the second pixel block 120, the second connecting portion 520 is closer to the second effective light-emitting area 102 in the second direction than the first connecting portion 510, and thus, the connecting electrode 1222 is closer to the second effective light-emitting area 102 in the second direction than the first connecting portion 510.

[0120] For example, such as Figures 3C to 5CAs shown, a planarization layer is provided between the film layer containing the second connection portion 520 and the film layer containing the connection electrode, or a passivation layer and a planarization layer are provided between the film layer containing the second connection portion 520 and the film layer containing the connection electrode. The planarization layer includes a plurality of vias 3010 extending through it, and the connection electrode in each sub-pixel is electrically connected to the second connection portion 520 through the vias 3010. For example, the via 3010 corresponding to the first pixel block 110 is farther away from the first effective light-emitting area 101 in the second direction than the first connection portion 510 in the first pixel block 110, thereby the connection electrode 1122 is farther away from the first effective light-emitting area 101 in the second direction than the first connection portion 510. For example, the via 3010 corresponding to the second pixel block 120 is closer to the second effective light-emitting area 102 in the second direction than the first connection portion 510 in the second pixel block 120, thereby the connection electrode 1222 is closer to the second effective light-emitting area 102 in the second direction than the first connection portion 510.

[0121] For example, such as Figures 4 to 5J As shown, in the first pixel block 110, the first gate 110-T2-g1 of the threshold compensation transistor T2 is located on the side of the second gate 110-T2-g2 closer to the first effective light-emitting area 101 in the second direction. The straight line containing the third edge 1003 of the connecting electrode 1122 overlaps with the first gate T2-g1, and the edge of the auxiliary electrode 1123 (e.g., the second part 1123-2 of the auxiliary electrode 1123 described later) away from the first effective light-emitting area 101 is located on the side of the first gate T2-g1 away from the first effective light-emitting area 101, so that the auxiliary electrode 1123 covers the first gate T2-g1. For example, as Figure 5G As shown, both the protruding structure P and the covering portion S (described later) overlap with the active semiconductor layer of the threshold compensation transistor T2. In this embodiment of the present disclosure, by providing an auxiliary electrode covering the first gate of the threshold compensation transistor in the first pixel block, it is possible to prevent external light from directly hitting the channel region of the threshold compensation transistor and to avoid characteristic shift of the threshold compensation transistor caused by illumination during display of the display substrate.

[0122] For example, such as Figures 4 to 5CAs shown, in the first pixel block 110, the auxiliary electrode 1123 includes a first part 1123-1 and a second part 1123-2 connected to each other. The first part 1123-1 is connected to the connecting electrode 1122. The second part 1123-2 covers at least a portion of the first gate T2-g1 of the threshold compensation transistor T2. The fourth edge 1004 of the first part 1123-1 extending in a first direction is on the same straight line as the third edge 1003 of the connecting electrode 1122, and the edge of the second part 1123-2 extending in the first direction is further away from the first effective light-emitting area 101 in the Y direction than the fourth edge 1004. For example, the second part 1123-2 is located on the side of the second gate T2-g2 of the threshold compensation transistor T2 that is away from the connecting electrode 1122 in the first direction. For example, in the first pixel block 110, the auxiliary electrode 1123 covers a portion of the active layer between the first gate T2-g1 and the second gate T2-g2 of the threshold compensation transistor T2.

[0123] In this embodiment, a protrusion is provided in the auxiliary electrode of the first pixel block, protruding away from the first effective light-emitting area to cover the first gate of the threshold compensation transistor and part of the active layer between the first gate and the second gate. This ensures that even if there is a certain degree of alignment offset during the formation of the second electrode of the first pixel block, it can still cover one channel region of the threshold compensation transistor, preventing the transistor characteristics from shifting due to illumination, and thus preventing the writing that affects the gate potential of the driving transistor.

[0124] In this embodiment of the disclosure, the threshold compensation transistor has a dual-gate structure with two channel regions. The second gate of the threshold compensation transistor in the first pixel block is not covered by the second electrode. In order to ensure that at least one channel region of the threshold compensation transistor is in a blocked state to ensure the characteristics of the threshold compensation transistor, a protrusion protruding away from the first effective light-emitting area is provided in the auxiliary electrode of the first pixel block. This can ensure that the first gate of the threshold compensation transistor is completely covered by the second electrode.

[0125] For example, the second electrode of the first pixel block covers one of the two gates of the threshold compensation transistor, and the second electrode of the second pixel block covers both gates of the threshold compensation transistor.

[0126] For example, along a direction perpendicular to the substrate, the main electrode of the second electrode of the first pixel block overlaps with the cover portion S, and the main electrode of the second electrode of the second pixel block overlaps with the cover portion S.

[0127] For example, such as Figures 1 to 5CAs shown, the second electrode 320 of the third color sub-pixel 300 also includes an auxiliary electrode 323 located on the side of the main electrode 321 away from the connecting electrode 322 and connected to the main electrode 321. The shape of the main electrode 321 of the third color sub-pixel 300 is the same as the shape of the effective light-emitting area 301, for example, both are hexagonal or elliptical. The connecting electrode 322 is connected to the second connecting portion 520 through a via 3010 penetrating the planarization layer to achieve connection with the first light-emitting control transistor T6.

[0128] For example, such as Figures 1 to 5H As shown, in the third color sub-pixel 300, the second gate 300-T2-g2 of the threshold compensation transistor T2 is located on the side of the first gate 300-T2-g1 near the effective light-emitting area 301 of the third color sub-pixel 300, and the auxiliary electrode 323 covers a portion of the active layer between the second gate T2-g2 and the first gate T2-g1. For example, as... Figure 5H As shown, both the protruding structure P and the covering portion S (described later) overlap with the active semiconductor layer of the threshold compensation transistor T2. In this embodiment, the threshold compensation transistor is a dual-gate structure with two channel regions. The first gate of the threshold compensation transistor in the third color sub-pixel is not covered by the second electrode. In order to ensure that at least one channel region of the threshold compensation transistor is in a shielded state to ensure the characteristics of the threshold compensation transistor, a protruding protrusion is provided on the side of the main electrode of the third color sub-pixel away from the connecting electrode to form an auxiliary electrode. Thus, even if there is a certain degree of alignment offset during the formation of the second electrode, one channel region of the threshold compensation transistor can still be completely covered, preventing the transistor characteristics from shifting due to illumination, and thus preventing the writing that affects the gate potential of the driving transistor.

[0129] For example, the light-emitting element mentioned above can be a light-emitting element or an inorganic light-emitting element.

[0130] For example, such as Figure 5D As shown, a pixel defining layer 7 is provided on the side of the second electrode of each color sub-pixel away from the substrate. The pixel defining layer 7 includes an opening 070 to expose a portion of the second electrode. When the subsequent organic light-emitting layer is formed in the opening 070 of the pixel defining layer 7, the organic light-emitting layer contacts the second electrode, thereby enabling this portion to drive the organic light-emitting layer to emit light.

[0131] For example, Figure 6 This is a schematic diagram of a partial cross-sectional structure of a display substrate. (Example) Figure 6As shown, the display substrate includes a film layer 010, which includes a substrate, an active semiconductor layer on the substrate, and at least one conductive layer on the side of the active semiconductor layer away from the substrate. The display substrate also includes a source / drain metal layer 011 on the film layer 010, which may include traces such as data lines or power signal lines. The display substrate further includes a planarization layer 012 on the side of the source / drain metal layer 011 away from the film layer 010, an anode 013 on the side of the planarization layer 012 away from the source / drain metal layer 011, and a pixel defining layer 014 on the side of the anode 013 away from the planarization layer 012. The pixel defining layer 014 includes a plurality of openings 015-017 for defining the light-emitting area of ​​a sub-pixel. The plurality of openings 015-017 expose portions of the anode 013. When a subsequent organic light-emitting layer is formed in the openings 015-017 of the pixel defining layer 014, the organic light-emitting layer contacts the anode 013, thereby enabling this portion to drive the organic light-emitting layer to emit light.

[0132] like Figure 6 As shown, the source / drain metal layer 011 has a relatively large thickness, for example, 0.6-0.9 micrometers, which causes the surface of the planarization layer 012 on the source / drain metal layer 011 facing the anode 013 to be uneven. For example, the distance between the surface of the planarization layer 012 away from the film layer 010 and the surface of the film layer 010 away from the planarization layer 012 located directly above the source / drain metal layer 011 (e.g., data lines, power signal lines, and patterns of the same material as it), is h1. The distance between the surface of the planarization layer 012 away from the film layer 010 and the surface of the film layer 010 away from the planarization layer 012 located directly above the area where the source / drain metal layer 011 is not located, is h2, where h1>h2.

[0133] like Figure 6As shown, within the opening 016, a source / drain metal layer 011 is disposed directly below a portion of the planarization layer 012, while no source / drain metal layer 011 is disposed directly below the other portion. Consequently, the surface of the planarization layer 012 facing the anode 013 within the opening 016 is not flat, resulting in an uneven surface on the anode 013 located on the planarization layer 012. For example, for the anode 013 located within the opening 016, the distance between the surface of the anode 013 directly above the source / drain metal layer 011 that is away from the film layer 010 and the surface of the film layer 010 that is away from the anode 013 is h3. The distance between the surface of the anode 013 located where no source / drain metal layer 011 is disposed and the surface of the film layer 010 that is away from the anode 013 is h4, where h3 > h4. Therefore, the anode 013 within the opening 016 is "tilted". Similarly, the anode 013 within opening 015 will also be "tilted," and depending on the position of the source / drain metal layer 011, the "tilt direction" of the anode 013 within opening 015 is different from that within opening 016, resulting in inconsistent light intensity emitted by the sub-pixels corresponding to openings 015 and 016 in different directions. Taking the direction indicated by the arrow in the Y direction as right, the light intensity emitted by the sub-pixel light-emitting areas defined by openings 015 and 016 is inconsistent to the left and right. Since there is no source / drain metal layer 011 directly below the anode 013 within opening 017, the surface of the anode 013 within opening 017 is basically flat and does not "tilt," resulting in consistent light intensity emitted by the sub-pixel light-emitting area defined by opening 017 in different directions. For the light-emitting areas of three adjacent sub-pixels of different colors defined by openings 015-017, the anode 013 in opening 015 is "tilted" to the left, the anode 013 in opening 016 is "tilted" to the right, and the anode 013 in opening 017 is not tilted. Therefore, the "tilting" directions of the anodes 013 of the different colored sub-pixels are different, resulting in a mismatch in light intensity emitted from the light-emitting areas of the three sub-pixels to the left and right sides. Display devices using such a display substrate will experience large-viewing-angle color shift, which, when viewed by the human eye, appears as a color shift phenomenon similar to one side appearing red and the other bluish.

[0134] For example, in the first pixel block, the orthographic projection of the second electrode on the substrate overlaps with the orthographic projection of the gate of the driving transistor on the substrate; in the second pixel block, the orthographic projection of the second electrode on the substrate overlaps with the orthographic projection of the gate of the driving transistor on the substrate.

[0135] For example, in each color sub-pixel, the overlap area between the orthographic projection of the second connection portion on the substrate and the orthographic projection of the first electrode of the capacitor on the substrate is very small.

[0136] For example, such as Figure 5C and Figure 5JAs shown, the second electrode of the second color sub-pixel covers vias 3009 and 3021 that connect the source / drain metal layer and the active semiconductor layer.

[0137] In another example of the embodiments of this disclosure, such as Figures 3A to 5C As shown, the multiple data lines 420 include multiple first data lines 421, and the multiple power signal lines 460 include multiple first power signal lines 461. For example, along a third direction perpendicular to the substrate, the second electrode 220 of the second color sub-pixel 200 overlaps with the first data lines 421, the first power signal lines 461, and the second connection portion 520. In the overlapping portions of the first data lines 421, the first power signal lines 461, and the second connection portion 520 with the second electrode 220, the first power signal lines 461 and the first data lines 421 are located on opposite sides of the second connection portion 520, and the minimum distance d1 between the edges of the second connection portion 520 and the first power signal lines 461 that are close to each other is... Figure 5B (As shown) The minimum distance d2 between the edges of the second connecting part 520 and the first data line 421 that are close to each other. Figure 5B The ratio (as shown) is 0.8 to 1.2. For example, the ratio of the minimum distance between the edges of the second connection portion 520 and the first power signal line 461 that are close to each other to the minimum distance between the edges of the second connection portion 520 and the first data line 421 that are close to each other is 0.9 to 1.1. For example, the ratio of the minimum distance between the edges of the second connection portion 520 and the first power signal line 461 that are close to each other to the minimum distance between the edges of the second connection portion 520 and the first data line 421 that are close to each other is 1.

[0138] In this embodiment of the disclosure, setting the distance between the second connection portion and the adjacent data line and power signal line to be approximately equal can reduce the height difference between the middle region (the region that does not overlap with the data line and power signal line) and the two side regions (the regions that overlap with the data line and power signal line) of the second electrode of the second color sub-pixel, thereby improving the flatness of the second electrode of the second color sub-pixel and improving color shift.

[0139] For example, the minimum distance between the first data line 421 and the first power signal line 461 can be 20-25 micrometers, and the maximum dimension of the second connection portion 520 along the Y direction can be 15-20 micrometers. This embodiment is not limited to these dimensions; any distance between the first data line, the second connection portion, and the first power signal line can be at least 3 micrometers.

[0140] For example, such as Figures 3A to 5CAs shown, along the third direction, the effective light-emitting area 202 of each second color sub-pixel 200 overlaps with the first data line 421, the first power signal line 461, and the second connecting portion 520. In the overlapping portions of the first data line 421, the first power signal line 461, and the second connecting portion 520 with the effective light-emitting area 201 of the second color sub-pixel 200, the ratio of the distance between the edges of the second connecting portion 520 and the first power signal line 461 that are close to each other to the distance between the edges of the second connecting portion 520 and the first data line 421 that are close to each other is 0.8 to 1.2, for example, 0.9 to 1.1. Therefore, the height difference between the middle region and the two side regions of the second electrode of the second color sub-pixel can be reduced, improving the flatness of the second electrode in the effective light-emitting area of ​​the second color sub-pixel, thereby improving color shift.

[0141] For example, such as Figures 3A to 5C As shown, in the portion of the second connection portion 520 that overlaps with the effective light-emitting area 202 of the second color sub-pixel 200, the distance between the second connection portion 520 and the first data line 421 is approximately equal to the distance between the second connection portion 520 and the first power signal line 461. This can further ensure the flatness of the second electrode located within the effective light-emitting area of ​​the second color sub-pixel, thereby improving color shift.

[0142] For example, such as Figures 3A to 5C As shown, the orthographic projection of a straight line extending along the X direction from the two endpoints of the effective light-emitting area 201 of the second color sub-pixel 200 in the Y direction (the direction intersecting the data line extension direction) to the substrate overlaps with the orthographic projection of the second connecting portion 520 on the substrate. For example, the orthographic projection of a straight line extending along the X direction from the midpoint of the line connecting the two opposite endpoints of the effective light-emitting area 201 of the second color sub-pixel 200 in the Y direction overlaps with the orthographic projection of the second connecting portion 520 on the substrate. For example, the orthographic projection of a straight line extending along the X direction from the midpoint of the line connecting the two endpoints of the effective light-emitting area 201 of the second color sub-pixel 200 in the Y direction (the direction intersecting the data line extension direction) to the substrate overlaps with the orthographic projection of the second connecting portion 520 on the substrate. Therefore, relative to the distribution positions of the first data line and the first power signal line, in this embodiment of the present disclosure, the center line of the effective light-emitting area 201 of the second color sub-pixel 200 extending along the first direction overlaps with the second connecting portion, which can improve the symmetry of the second electrode and improve color shift.

[0143] For example, such as Figures 3A to 5CAs shown, the second connection portion 520 includes a first sub-connection portion 521 connected to each other and a first pad 522 located on the side of the first sub-connection portion 521 near the first power signal line 461. The second electrode 220 of the second color sub-pixel 200 is electrically connected to the second electrode of the first light-emitting control transistor T6 through the first sub-connection portion 521. For example, the first pad and the first sub-connection portion are an integral structure. The schematic division of the second connection portion into the first sub-connection portion and the first pad in the embodiments of this disclosure clearly illustrates the positional relationship between the second connection portion, the second electrode of the second color sub-pixel, and the effective light-emitting area.

[0144] For example, such as Figures 3A to 5C As shown, the first sub-connector 521 is a rectangle extending along the X direction. A straight line extending along the X direction through the center of the effective light-emitting area 201 of the second color sub-pixel 200 does not coincide with a second straight line extending along the X direction through the center of the first sub-connector 521. For example, the center line passing through the center of the effective light-emitting area 201 of the second color sub-pixel 200 is located on the side of the center line passing through the center of the first sub-connector 521 closer to the first pad 522. Therefore, the entire first sub-connector is offset to the left relative to the center line extending along the X direction of the second color sub-pixel (to the right, as indicated by the arrow in the Y direction). Without the first pad, the height difference between the two sides of the center line of the second electrode of the second color sub-pixel would be large, resulting in poor symmetry of the second electrode and a tendency for color shift in the Y direction. In this embodiment of the present disclosure, by setting a first pad between the first sub-connection portion and the first power signal line, the overlapping position of the second connection portion and the second electrode of the second color sub-pixel is located in the middle region of the effective light-emitting area of ​​the second color sub-pixel. This reduces the height difference between the middle region and the two sides of the second electrode of the second color sub-pixel and improves the symmetry, which helps to ensure that the light emission intensity of the effective light-emitting area is consistent in all directions, thereby improving color deviation.

[0145] For example, such as Figures 3A to 5CAs shown, the second connecting portion 520 in the second color sub-pixel 200 is L-shaped, and along the X direction, the size of the first sub-connecting portion 521 is larger than the size of the first pad 522. For example, the second electrode 220 of the second color sub-pixel 200 includes a main electrode 221 and a connecting electrode 222 connected to each other. The shape of the main electrode 221 is the same as the shape of the effective light-emitting area 201, for example, both are hexagonal or elliptical. For example, the orthographic projection of the effective light-emitting area of ​​the second color sub-pixel on the substrate is located within the orthographic projection of the main electrode on the substrate. For example, along the direction perpendicular to the substrate, a portion of the first sub-connecting portion 521 overlaps with the main electrode 221, and another portion of the first sub-connecting portion 521 overlaps with the connecting electrode 222 and is connected to the connecting electrode 222 through a via 3010 in the planarization layer. The first pad 521 only overlaps with the main electrode 221 and does not overlap with the connecting electrode 222. For example, via 3010 (e.g., the first via 3011 described later) is further away from the effective light-emitting area 201 of the second color sub-pixel 200 than the first pad 522. For example, more than 90% of the orthographic projection of the second connection portion 520 of the second color sub-pixel 200 onto the substrate falls within the orthographic projection of the second electrode 220 onto the substrate. In embodiments of this disclosure, the first pad may be provided only at the location of the second electrode of the first color sub-pixel to cooperate with the first sub-connection portion to improve the flatness and symmetry of the second electrode. The embodiments of this disclosure schematically show that no first pad is provided outside the location of the second electrode, but this is not a limitation; the shape of the second connection portion in the second color sub-pixel can also be designed according to the process and actual product requirements.

[0146] For example, such as Figures 3A to 5CAs shown, along the third direction, the effective light-emitting area 201 of the second color sub-pixel 200 overlaps with the third connecting portion 530, and a straight line extending in the X direction through the geometric center of the effective light-emitting area 201 overlaps with the third connecting portion 530. For example, the connecting electrode 222 is located on the side away from the third connecting portion 530 on the straight line extending in the Y direction through the geometric center of the effective light-emitting area 201. For example, the third connecting portion 530 is basically located in the middle region of the effective light-emitting area 201 of the second color sub-pixel 200. For example, the second connecting portion 520 and the third connecting portion 530 are respectively located on both sides of the straight line extending in the Y direction through the center of the effective light-emitting area 201 of the second color sub-pixel 200, that is, the second connecting portion 520 and the third connecting portion 530 are respectively located on both sides of the center line extending in the Y direction of the effective light-emitting area 201 of the second color sub-pixel 200. For example, the second connection portion 520 is located on one side of a straight line extending along the Y direction through the center of the effective light-emitting area 201 of the second color sub-pixel 200, and at least a portion of the third connection portion 530 is located on the other side of the straight line. Compared to data lines and power signal lines distributed on both sides of the effective light-emitting area, in this embodiment of the disclosure, the source / drain metal layer covering the middle region of the second electrode of the second color sub-pixel is less. By providing a first pad and placing the third connection portion and the portion of the second connection portion including the first pad that overlaps with the effective light-emitting area of ​​the second color sub-pixel in the middle region of the effective light-emitting area, the height difference between the middle region and the two sides of the second electrode located in the effective light-emitting area can be reduced, improving flatness and thus improving color shift.

[0147] For example, such as Figures 3A to 5C As shown, the multiple data lines 420 also include multiple second data lines 422, which are arranged alternately on the same layer as the multiple first data lines 421. The multiple power signal lines 460 also include multiple second power signal lines 462, which are arranged alternately on the same layer as the multiple first power signal lines 461. For example, along a third direction, the second electrode 220 of each second color sub-pixel 200 overlaps with the first data line 421, the first power signal line 461, the second connection portion 520, the second data line 422, and the second power signal line 462. In the overlapping portion, the second power signal line 462 is located on the side of the first data line 421 away from the second connection portion 520, and the second data line 422 is located on the side of the first power signal line 461 away from the second connection portion 520. That is, the second electrode 220 of the second color sub-pixel 200 overlaps with two data lines 420 and two power signal lines 460, and the first data line 421 and the second power signal line 462 are provided on one side of the second connection portion 520, and the second data line 422 and the first power signal line 461 are provided on the other side of the second connection portion 520.

[0148] For example, such as Figures 3A to 5C As shown, the effective light-emitting area 201 of each second color sub-pixel 200 overlaps with the first data line 421, the first power signal line 461, the second data line 422, and the second power signal line 462. In the overlapping portion, the ratio of the sum of the overlapping areas of the first power signal line 461 and the second data line 422 with the effective light-emitting area 201 to the sum of the overlapping areas of the second power signal line 462 and the first data line 421 with the effective light-emitting area 201 is 0.8 to 1.2, for example, 0.9 to 1.1. In this embodiment, both sides of the effective light-emitting area of ​​the second color sub-pixel overlap with the data lines and power signal lines, and the overlapping areas of the source / drain metal layers on both sides of the second connection portion of the second color sub-pixel with the effective light-emitting area are approximately equal. Therefore, the overlapping portion of the effective light-emitting area of ​​the second color sub-pixel with the source / drain metal layers can be guaranteed to have good symmetry, which is beneficial for preventing color shift.

[0149] For example, such as Figures 3A to 5C As shown, the first data line 421, which overlaps with the second electrode 220 of the second color sub-pixel 200, is electrically connected to the second electrode of the data writing transistor T4 of the first pixel block 110. The second power signal line 462, which also overlaps with the second electrode 220 of the second color sub-pixel 200, is electrically connected to the first electrode of the second light-emitting control transistor T5 of the first pixel block 110. For example, both the first data line 421 and the second power signal line 420, which overlap with the second electrode 220 of the second color sub-pixel 200, overlap with the second electrode 112 of the first pixel block 110. For example, the second electrode 112 of the first pixel block 110 has two overlapping portions with the first data line 421 and the second power signal line 462, and these two overlapping portions are located on either side of a straight line extending along a first direction, dividing the effective light-emitting area of ​​the first pixel block 110 into two equal parts. Therefore, the second electrode of the first pixel block has good symmetry and flatness in the Y direction, which helps prevent color shift.

[0150] For example, such as Figures 3A to 5C As shown, the first power signal line 461, which overlaps with the second electrode 220 of the second color sub-pixel 200, is electrically connected to the first electrode of the second light-emitting control transistor T5 of the second color sub-pixel 200. The second data line 422, which also overlaps with the second electrode 220 of the second color sub-pixel 200, is electrically connected to the second electrode of the data writing transistor T4 of the second color sub-pixel. For example, the second electrode 122 of the second pixel block 120 has two overlapping portions with the second data line 422 and the first power signal line 461, and these two overlapping portions are located on opposite sides of a straight line extending along the X direction from the center of the second effective light-emitting area 201 of the second pixel block 120. Therefore, the second electrode of the second pixel block has good symmetry and flatness in the Y direction, which helps prevent color shift.

[0151] For example, such as Figures 3A to 5C As shown, along the direction perpendicular to the substrate, the edge of the main electrode 1221 of the second pixel block 120 away from the auxiliary electrode 1223 overlaps with the first connection portion 510 of the second color sub-pixel 200.

[0152] For example, such as Figures 3A to 5C As shown, along the direction perpendicular to the substrate, the second electrode 320 of each third color sub-pixel 300 overlaps with the first data line 421, the first power signal line 461, the second data line 422, and the second power signal line 462. For example, along the direction perpendicular to the substrate, the effective light-emitting area 301 of each third color sub-pixel 300 overlaps with the first data line 421, the first power signal line 461, the second data line 422, and the second power signal line 462. For example, the first data line 421 and the second power signal line 462 are located on one side of the center line extending in the X direction of the effective light-emitting area 301 of the third color sub-pixel 300, and the second data line 422 and the first power signal line 461 are located on the other side of the aforementioned center line. For example, along a direction perpendicular to the substrate, in the overlapping portions of the second electrode 320 of each third color sub-pixel 300 with the first data line 421, the first power signal line 461, the second data line 422, and the second power signal line 462, the ratio of the sum of the overlapping areas of the first power signal line 461 and the second data line 442 with the effective light-emitting area 301 to the sum of the overlapping areas of the second power signal line 462 and the first data line 421 with the effective light-emitting area 301 is 0.8 to 1.2, for example, 0.9 to 1.1. Then, the portions of the second electrode 320 of the third color sub-pixel 300 located in the regions on both sides (the areas where the data lines and power signal lines overlap with the second electrode) overlap with both the source and drain metal layers, and the overlapping portions are approximately symmetrically distributed, which is beneficial for reducing color shift.

[0153] For example, the second electrode 320 and the effective light-emitting area 301 of the third color sub-pixel 300 both overlap with the second connecting portion 520. In the overlapping portions of the first data line 421, the first power signal line 461, and the second connecting portion 520 and the second electrode 320, the first power signal line 461 and the first data line 421 are located on opposite sides of the second connecting portion 520. The ratio of the minimum distance between the edges of the second connecting portion 520 and the first power signal line 461 approaching each other to the minimum distance between the edges of the second connecting portion 520 and the first data line 421 approaching each other is not greater than 2.5, for example, not greater than 2. For example, a straight line passing through the center of the effective light-emitting area 301 of the third color sub-pixel 300 and extending along the X direction overlaps with the second connecting portion 520. In this embodiment, by placing the second connecting portion of the third color sub-pixel in the middle region of the effective light-emitting area, the height difference between the second electrode at the middle region and the two side regions (the areas where the data line and power signal line overlap with the effective light-emitting area) of the effective light-emitting area can be reduced, which is beneficial for reducing color shift.

[0154] For example, such as Figures 3A to 5C As shown, the second connection portion 520 of the third color sub-pixel 300 includes a second sub-connection portion 523 and a second pad 524 connected to each other. The second pad 524 is located on the side of the second sub-connection portion 523 near the center of the effective light-emitting area 301 of the third color sub-pixel 300. For example, along the direction perpendicular to the substrate, the second pad 524 overlaps with the effective light-emitting area 301, while the second sub-connection portion 523 does not overlap with the effective light-emitting area 301. For example, the second sub-connection portion and the second pad are an integral structure. The schematic division of the second connection portion into the second sub-connection portion and the second pad in the embodiments of this disclosure clearly illustrates the positional relationship between the second connection portion and the second electrode and the effective light-emitting area of ​​the third color sub-pixel.

[0155] For example, such as Figures 3A to 5C As shown, the second electrode 320 of the third color sub-pixel 300 includes a main electrode 321 and a connecting electrode 322 connected to each other. The shape of the main electrode 321 of the third color sub-pixel 300 is the same as the shape of the effective light-emitting area 301, for example, both are hexagonal or elliptical. For example, the orthographic projection of the effective light-emitting area of ​​the third color sub-pixel onto the substrate lies within the orthographic projection of the main electrode onto the substrate. For example, along the direction perpendicular to the substrate, the main electrode 321 overlaps with the second pad 524, and the connecting electrode 322 overlaps with and is connected to the second sub-connecting portion 523. For example, along the direction perpendicular to the substrate, the main electrode 321 and the second sub-connecting portion 523 do not substantially overlap.

[0156] For example, such as Figures 3A to 5CAs shown, along a direction perpendicular to the substrate, the first connecting portion 510 of the third color sub-pixel 300 overlaps with the effective light-emitting area 301. At least a portion of the first connecting portion 510 of the third color sub-pixel 300 and the second pad 524 are located on both sides of a fourth straight line extending along the Y direction through the center of the effective light-emitting area 301. In this embodiment, the effective light-emitting area and the second electrode of the third color sub-pixel overlap with the first connecting portion. By providing the second pad at the edge of the effective light-emitting area away from the first connecting portion, the height difference of the middle region of the second electrode of the third color sub-pixel in the X direction can be reduced, which is beneficial to improving the color shift of the third color sub-pixel.

[0157] For example, such as Figures 3A to 5C As shown, the second sub-connection portion 523 in the second connection portion 520 of the third color sub-pixel 300 is rectangular in shape. The side of the second sub-connection portion 523 near the first power signal line 461 is connected to the second electrode 320 through a via 3010 in the planarization layer. The side of the second sub-connection portion 523 near the first data line 421 is connected to the second electrode of the first light-emitting control transistor T6 through a via 3008 passing through the gate insulating layer, the first insulating layer, and the second insulating layer. The rectangular shape in this embodiment includes a standard rectangular shape and an approximate rectangular shape. For example, an approximate rectangular shape may include a rounded rectangle or a shape whose overall outline is approximately rectangular.

[0158] For example, such as Figures 3A to 5C As shown, the second pad 524 in the second connecting portion 520 of the third color sub-pixel 300 is rectangular in shape, and the two sides of the second pad 524 extending along the X direction are respectively flush with the two sides of the second sub-connecting portion 523 extending along the X direction, so that the shape of the second connecting portion of the third color sub-pixel is rectangular. In this embodiment of the present disclosure, by adding the second pad to reduce the height difference of the middle region of the second electrode of the third color sub-pixel in the X direction and the height difference of the second electrode in the Y direction, while setting the shape of the second connecting portion to be rectangular, it is convenient to manufacture.

[0159] Figure 7 This is a schematic diagram of a partial cross-sectional structure of another type of display substrate. Figure 7 The display substrate shown includes Figure 6 The diagram shows a film layer 010, a source / drain metal layer 011, a planarization layer 012, an anode 013, and a pixel defining layer 014. (Example) Figure 7 As shown, the planarization layer 012 in the display substrate includes a via 018 to allow the anode 013 to be electrically connected to the source / drain metal layer 011. The pixel defining layer 014 includes an opening 019 to expose a portion of the anode 013. When a subsequent organic light-emitting layer is formed in the opening 019, the organic light-emitting layer contacts the anode 013 to form an effective light-emitting area.

[0160] like Figure 7 As shown, via 018 is located outside the effective light-emitting area. Since the anode 013 located around via 018 is tilted, a certain distance should be set between the effective light-emitting area and via 018 to ensure the flatness of the anode 013 in the effective light-emitting area, thereby avoiding color shift of the display substrate.

[0161] Figure 8 This is a schematic diagram of a pixel arrangement structure in a display substrate. Figure 8 As shown, the display substrate includes a data line 042 extending along the X direction. The display substrate also includes a red sub-pixel 021, a green sub-pixel pair 022, and a blue sub-pixel 023. The effective light-emitting areas of the red sub-pixel 021 and the blue sub-pixel 023 extend along the Y direction. For example, each sub-pixel includes a light-emitting element and a pixel circuit for driving the light-emitting element to emit light. The light-emitting element includes an anode, a light-emitting layer, and a cathode sequentially stacked along a direction away from the substrate. The anode is connected to a connection portion 031 through a via 0310 to achieve connection with a thin-film transistor in the pixel circuit. For example, the vias 0310 corresponding to the red sub-pixel 021, the green sub-pixel pair 022, and the blue sub-pixel 023 are arranged in a straight line along the Y direction. For example, the anode 0211 of the red sub-pixel 021 is connected to the connecting part 031 through a via 0310. A notch is provided on the long side of the effective light-emitting area 0211 of the red sub-pixel 021 near the via 0310 to avoid the via 0310, ensuring a suitable distance (preset distance) between the effective light-emitting area 0211 and the via 0310, for example, 3 micrometers. Similarly, the long side of the effective light-emitting area of ​​the blue sub-pixel 023 near the via 0310 also needs to have a notch to avoid the via 0310, ensuring a preset distance between the effective light-emitting area and the via 0310. This preset distance refers to the minimum distance (e.g., 3 micrometers) between the edge of the effective light-emitting area and the edge of the via, to ensure that the via does not affect the light emission direction of the edge of the effective light-emitting area.

[0162] For example, the minimum distance between the edge of the third via of the first pixel block and the edges of the effective light-emitting areas of the second and fourth color sub-pixels is approximately equal and greater than 3 micrometers. Similarly, the minimum distance between the fourth via of the second pixel block and the edges of the effective light-emitting areas of the second and fourth color sub-pixels is also greater than 3 micrometers.

[0163] For example, the orthographic projection of the second electrode of the second color sub-pixel onto the substrate overlaps with the orthographic projection of the reset power signal line onto the substrate.

[0164] In another example of the embodiments of this disclosure, such as Figures 4 to 5FAs shown, the second electrode 220 of the second color sub-pixel 200 is connected to the second connection portion 520 through a first via 3011 penetrating the planarization layer, and the second electrode 320 of the third color sub-pixel 300 is connected to the second connection portion 520 through a second via 3012 penetrating the planarization layer. The minimum distance between the orthographic projection of the effective light-emitting area 201 of the second color sub-pixel 200 onto a straight line along the X direction (the extension direction of the data line 420) and the orthographic projection of the effective light-emitting area 301 of the third color sub-pixel 300 onto the same straight line is less than the sum of the dimensions of the projection of the first via and the preset distance between the edge of the first via and the edge of the effective light-emitting area onto the same straight line. The first via 3011 is located in the X direction on the side of the effective light-emitting area 201 of the second color sub-pixel 200 near the effective light-emitting area 301 of the third color sub-pixel 300. The second via 3012 is located in the X direction on the side of the effective light-emitting area 301 of the third color sub-pixel 300 near the effective light-emitting area 201 of the second color sub-pixel 200. The first connecting line 3101 connecting the first via 3011 and the second via 3012 is not parallel to the Y direction. For example, the orthographic projections of the first via 3011, the fourth via 3014, and the third via 3013 on the substrate overlap with the orthographic projection of the light-emitting control signal line 450 on the substrate. For example, the orthographic projection of the second via 3012 on the substrate does not overlap with the orthographic projection of the light-emitting control signal line 450 on the substrate. The aforementioned first connecting line is a straight line.

[0165] For example, the first line 3101 connecting the first via 3011 and the second via 3012 can refer to the line connecting the center of the first via and the center of the second via; it can also refer to the line connecting the point of the first via closest to the effective light-emitting area of ​​the second color sub-pixel and the point of the second via furthest from the effective light-emitting area of ​​the third color sub-pixel; or it can refer to the line connecting the point of the first via furthest from the effective light-emitting area of ​​the second color sub-pixel and the point of the second via closest to the effective light-emitting area of ​​the third color sub-pixel.

[0166] For example, the second electrode of the second color sub-pixel and the second electrode of the third color sub-pixel do not overlap in the second direction.

[0167] In this embodiment, the distance in the X direction between the effective light-emitting area of ​​the second color sub-pixel and the effective light-emitting area of ​​the third color sub-pixel is small, for example, less than the sum of the dimensions of the first via and the preset spacing. Therefore, if the first via is provided within the X-direction spacing between the effective light-emitting areas of the second and third color sub-pixels, the position of the first via will conflict with the effective light-emitting area of ​​the second color sub-pixel, affecting the light emission of the second color sub-pixel. In this embodiment, the position of the via (e.g., at least one of the first and second vias) located in the planarization layer is adjusted according to the positions of the effective light-emitting areas of the second and third color sub-pixels. For example, the line connecting the first and second vias corresponding to the second and third color sub-pixels is not parallel to the extension direction of the scan signal line. This ensures the flatness of the second electrodes of the second and third color sub-pixels, guaranteeing the consistency of the light emission intensity of the effective light-emitting area in all directions and effectively improving color shift.

[0168] For example, such as Figures 4 to 5C As shown, the angle between the first connecting line 3101 and the Y direction is 5° to 15°. In this embodiment of the present disclosure, by adjusting the positions of the first via and the second via, the probability of color shift in the second color sub-pixel and the third color sub-pixel can be reduced.

[0169] For example, such as Figures 4 to 5C As shown, the second via 3012 is located on the side of the second straight line 3102 extending along the Y direction through the first via 3011, close to the effective light-emitting area 201 of the second color sub-pixel 200. For example, the orthographic projection of the first via 3011 on the straight line extending along the X direction and the orthographic projection of the second via 3012 on the same straight line do not overlap. In this embodiment, the distances between the effective light-emitting area of ​​the second color sub-pixel and the first via, and between the effective light-emitting area of ​​the third color sub-pixel and the second via, are set to be relatively large. This ensures that the vias do not affect the flatness of the second electrode located within the effective light-emitting area, thereby making the light emission intensity of the effective light-emitting area consistent in all directions and effectively improving color shift.

[0170] For example, such as Figures 4 to 5CAs shown, in the second color sub-pixel 200, the second connection portion 520 is electrically connected to the second electrode of the first light-emitting control transistor T6 through a first connection hole 3021 penetrating the gate insulating layer, the first insulating layer, and the second insulating layer; in the third color sub-pixel 300, the second connection portion 520 is electrically connected to the second electrode of the first light-emitting control transistor T6 through a second connection hole 3022 penetrating the gate insulating layer, the first insulating layer, and the second insulating layer, and the second connection line 3200 connecting the first connection hole 3021 and the second connection hole 3022 is parallel to the Y direction. For example, the second connection line 3200 connecting the first connection hole 3021 and the second connection hole 3022 can refer to the line connecting the center of the first connection hole and the center of the second connection hole; it can also refer to the line connecting the point of the first connection hole closest to the effective light-emitting area of ​​the second color sub-pixel and the point of the second connection hole furthest from the effective light-emitting area of ​​the third color sub-pixel; it can also refer to the line connecting the point of the first connection hole furthest from the effective light-emitting area of ​​the second color sub-pixel and the point of the second connection hole closest to the effective light-emitting area of ​​the third color sub-pixel.

[0171] For example, such as Figures 4 to 5C As shown, the effective light-emitting area 201 of the second color sub-pixel 200 includes a first long side 1011 and a second long side 1012 extending along the Y direction. The second long side 1012 is located on the side of the first long side 1011 away from the first via 3011. Along a third direction perpendicular to the substrate, the extension line of the first long side 1011 overlaps with the second via 3012. For example, the orthographic projection of the second via 3012 on a straight line extending along the X direction overlaps with the orthographic projection of the second connection hole 3022 on the same straight line. In this embodiment, when adjusting the position of the second via, considering the position of the second connection hole, the position of the second via penetrating the planarization layer is not significantly adjusted in the X direction relative to the position of the second connection hole penetrating the gate insulating layer, the first insulating layer, and the second insulating layer, thereby reducing the impact on the overall pixel circuit structure.

[0172] For example, such as Figures 4 to 5CAs shown, the effective light-emitting area 301 of the third color sub-pixel 300 includes a third long side 1013 and a fourth long side 1014 extending along the Y direction. The fourth long side 1014 is located on the side of the third long side 1013 away from the second via 3012, and along the direction perpendicular to the substrate, the extension line of the fourth long side 1014 overlaps with the first via 3011. For example, along the direction perpendicular to the substrate, the first connecting hole 3021 overlaps with the effective light-emitting area 201 of the second color sub-pixel 200. The first via 3011 is further away from the effective light-emitting area 201 of the second color sub-pixel 200 than the first connecting hole 3021, and the orthographic projection of the first via 3011 on a straight line extending along the X direction does not overlap with the orthographic projection of the first connecting hole 3021 on the same straight line. In this embodiment of the disclosure, when adjusting the position of the first via, it is necessary to consider that the position of the first via penetrating the planarization layer is slightly adjusted in the X direction relative to the position of the first connection hole penetrating the gate insulating layer, the first insulating layer and the second insulating layer, and also to ensure the distance between the first via and the effective light-emitting area of ​​the second color sub-pixel to prevent affecting the consistency of the light emission intensity of the effective light-emitting area in all directions.

[0173] For example, such as Figures 4 to 5C As shown, the shortest distance between the first long side 1011 of the effective light-emitting area 201 of the second color sub-pixel 200 and the orthogonal projection of the first via 3011 on the substrate is the first distance, and the shortest distance between the third long side 1013 of the effective light-emitting area 301 of the third color sub-pixel 300 and the orthogonal projection of the second via 3012 on the substrate is the second distance. The ratio of the first distance to the second distance is 0.8 to 1.2, for example, 0.9 to 1.1. For example, the first distance and the second distance are completely equal. For example, both the first distance and the second distance are greater than 3 micrometers. The aforementioned "shortest distance between the first long side 1011 and the orthogonal projection of the first via 3011 on the substrate" refers to the distance between the point where the orthogonal projection of the first via is closest to the orthogonal projection of the first long side and the orthogonal projection of the first long side. The aforementioned "shortest distance between the orthographic projections of the third long side 1013 and the second via 3012 on the substrate" refers to the distance between the point of the orthographic projection of the second via closest to the orthographic projection of the third long side and the orthographic projection of the third long side. In this embodiment, by setting a larger distance between the vias provided in the planarization layer and the edge of the effective light-emitting area of ​​the sub-pixel, the vias can be prevented from affecting the planarity of the second electrode within the effective light-emitting area, thereby ensuring the consistency of light emission intensity in all directions and effectively improving color shift.

[0174] For example, such as Figures 4 to 5CAs shown, the first long side 1011 of the effective light-emitting area 201 of the second color sub-pixel 200 is a straight side, and the third long side 1013 of the effective light-emitting area 301 of the third color sub-pixel 300 is a straight side. In this embodiment, by adjusting the positions of the first via and the second via, while ensuring that the via positions do not affect the effective light-emitting area, it is also possible to avoid designing the edge of the effective light-emitting area with a notch shape to avoid the via, thus avoiding the design of irregularly shaped openings in the pixel limiting layer and reducing problems in the manufacturing process.

[0175] For example, such as Figures 4 to 5C As shown, the second electrode 112 of the first pixel block 110 in the first color sub-pixel pair 100 is connected to the second connection portion 520 through a third via 3013 penetrating the planarization layer, and the second electrode 122 of the second pixel block 120 in the first color sub-pixel pair 100 is connected to the second connection portion 520 through a fourth via 3014 penetrating the planarization layer. The first connecting line 3103 connecting the third via 3013 and the fourth via 3014 is approximately parallel to the Y direction. In this embodiment, the third and fourth vias are arranged on a straight line extending along the Y direction, which ensures the distance between the vias and the corresponding effective light-emitting areas while also facilitating the manufacturing process.

[0176] For example, the first line 3103 connecting the third via 3013 and the fourth via 3014 can refer to the line connecting the center of the third via and the center of the fourth via; it can also refer to the line connecting the point of the third via closest to the first effective light-emitting area and the point of the fourth via closest to the second effective light-emitting area; or it can refer to the line connecting the point of the third via furthest from the first effective light-emitting area and the point of the fourth via furthest from the second effective light-emitting area.

[0177] For example, such as Figures 4 to 5C As shown, the straight line containing the first connecting line 3103 passes through the first via 3011 but not through the second via 3012. In this embodiment, the first via connected to the second electrode of the second color sub-pixel, the third via connected to the second electrode of the first color sub-pixel pair, and the fourth via are approximately located on a straight line parallel to the scan signal line. This ensures that the distance between the first via and the corresponding effective light-emitting area is greater than 3 micrometers, while also facilitating fabrication.

[0178] For example, such as Figures 4 to 5C As shown, along a third direction perpendicular to the substrate, the straight line containing the third long side 1013 of the effective light-emitting area 301 of the second color sub-pixel 300 overlaps with both the third via 3013 and the fourth via 3014.

[0179] For example, such as Figures 4 to 5CAs shown, along the Y direction, a third via 3013 or a fourth via 3014 is provided between the first via 3011 and the second via 3012. That is, the third via and the fourth via are provided on both sides of the first via in the Y direction, or the third via and the fourth via are provided on both sides of the second via in the Y direction.

[0180] For example, such as Figures 4 to 5C As shown, in the first sub-pixel block 110, the second connection portion 520 is electrically connected to the second electrode of the first light-emitting control transistor T6 through a third connection hole 3023 penetrating the gate insulating layer, the first insulating layer, and the second insulating layer; in the second sub-pixel block 120, the second connection portion 520 is electrically connected to the second electrode of the first light-emitting control transistor T6 through a fourth connection hole 3024 penetrating the gate insulating layer, the first insulating layer, and the second insulating layer, and the fourth connection line 3400 connecting the third connection hole 3023 and the fourth connection hole 3024 substantially overlaps with the second connection line 3200.

[0181] For example, the fourth connecting line 3400 connecting the third connecting hole 3023 and the fourth connecting hole 3024 can refer to the line connecting the center of the third connecting hole and the center of the fourth connecting hole; it can also refer to the line connecting the point of the third connecting hole closest to the first effective light-emitting area and the point of the fourth connecting hole closest to the second effective light-emitting area; or it can refer to the line connecting the point of the third connecting hole furthest from the first effective light-emitting area and the point of the fourth connecting hole furthest from the second effective light-emitting area.

[0182] It should be noted that, in this embodiment of the present disclosure, the first direction represents the extension direction of the data line, and the second direction represents the extension direction of the scan signal line. The names of the two directions can be interchanged. In this embodiment of the present disclosure, the first connection part represents the connection part connecting the second electrode of the threshold compensation transistor to the gate of the driving transistor, the second connection part represents the connection part connecting the second electrode of the first light-emitting control transistor to the second electrode of the light-emitting element, and the third connection part represents the connection part connecting the first electrode of the first reset transistor to the reset power supply signal line. The names of the three connection parts can be interchanged.

[0183] Another embodiment of this disclosure provides a display device, which includes any of the above-described display substrates.

[0184] For example, the display device provided in the embodiments of this disclosure can be an organic light-emitting diode display device.

[0185] For example, in the display device provided in the embodiments of this disclosure, the ratio of the overlapping area of ​​the second electrodes of the two light-emitting elements to the corresponding two first connecting portions in the two first color sub-pixels, such as the green sub-pixel pair, is 0.8 to 1.2, for example, 0.9 to 1.1. This can reduce the load difference of the gate nodes of the driving transistors in the two first color sub-pixels, thereby reducing the brightness difference of the two first color sub-pixels and improving the display characteristics of the display substrate.

[0186] For example, in the display device provided in the embodiments of this disclosure, by providing an auxiliary electrode covering one of the two gates of the threshold compensation transistor in a green sub-pixel of a first color sub-pixel pair, such as a green sub-pixel pair, it is possible to prevent external light from directly shining on the channel region of the threshold compensation transistor and to avoid the characteristic shift of the threshold compensation transistor caused by the illumination during display of the display substrate, thereby preventing the writing that affects the gate potential of the driving transistor.

[0187] For example, in the display device provided in the embodiments of this disclosure, by setting the distance between the second connecting portion of the second color sub-pixel, such as the red sub-pixel, and the adjacent data line and power signal line to be approximately equal, the height difference between the middle region (the region that does not overlap with the data line and power signal line) and the two side regions (the regions that overlap with the data line and power signal line) of the second electrode of the second color sub-pixel can be reduced, thereby improving the flatness of the second electrode of the second color sub-pixel and improving color shift.

[0188] For example, in the display device provided in the embodiments of this disclosure, the effective light-emitting area and the second electrode of the third color sub-pixel, such as the blue sub-pixel, overlap with the first connecting portion. By providing a second pad at the edge of the effective light-emitting area away from the first connecting portion, the height difference between the middle region of the second electrode of the third color sub-pixel in the scanning signal line extension direction and the data line extension direction can be reduced, which is beneficial to improving the color deviation of the third color sub-pixel.

[0189] For example, in the display device provided in this disclosure embodiment, the position of the via (e.g., at least one of the first via and the second via) located in the planarization layer is adjusted according to the position of the effective light-emitting area of ​​the second color sub-pixel and the third color sub-pixel. For example, the line connecting the first via and the second via corresponding to the second color sub-pixel and the third color sub-pixel is not parallel to the extension direction of the scan signal line, which can ensure the planarity of the second electrode of the second color sub-pixel and the third color sub-pixel, so as to ensure the consistency of the light emission intensity of the effective light-emitting area in all directions and effectively improve the color shift.

[0190] The following points need to be explained:

[0191] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0192] (2) Where there is no conflict, features of the same embodiment and different embodiments of this disclosure may be combined with each other.

[0193] The above description is merely an exemplary embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure, which is determined by the appended claims.

Claims

1. A display substrate, comprising: Substrate; Multiple sub-pixels are located on the substrate. Each sub-pixel includes a light-emitting element and a pixel circuit for driving the light-emitting element. The light-emitting element includes a first electrode, a light-emitting layer, and a second electrode stacked sequentially along a direction close to the substrate. Each second electrode includes a main electrode and a connecting electrode. The multiple sub-pixels include multiple first-color sub-pixels and multiple second-color sub-pixels. Each first-color sub-pixel includes a first effective light-emitting area. The shape of the main electrode of the first-color sub-pixel is the same as the shape of the first effective light-emitting area, and the orthographic projection of the first effective light-emitting area on the substrate is located within the orthographic projection of the main electrode on the substrate. Each second-color sub-pixel includes a second effective light-emitting area. The shape of the main electrode of the second-color sub-pixel is the same as the shape of the second effective light-emitting area, and the orthographic projection of the second effective light-emitting area on the substrate is located within the orthographic projection of the main electrode on the substrate. Multiple data lines are located on the side of the second electrode facing the substrate. Each data line extends along a first direction, and the main electrode of at least one of the first color sub-pixel and the second color sub-pixel overlaps with at least two data lines. The main electrode of the same first color sub-pixel is a continuous electrode. Along a direction perpendicular to the substrate, the continuous electrode overlaps with the at least two data lines. The first power signal line is disposed on the same layer as the data line and extends along the first direction; The second power signal line is arranged on the same layer as the first power signal line and alternately therewith. A planarization layer is located between the film layer containing the multiple data lines and the film layer containing the second electrode; as well as An interlayer insulating layer is located between the film layer containing the multiple data lines and the substrate. Each of the sub-pixels includes a first connection portion disposed on the same layer as the data line. In the first color sub-pixel, the connecting electrode is connected to the first connecting portion through a first via penetrating the planarization layer, and the first connecting portion is electrically connected to the pixel circuit through a first connecting hole penetrating the interlayer insulating layer. Along the direction perpendicular to the substrate, neither the first via nor the first connecting hole overlaps with the main electrode, and the orthographic projections of the first via and the first connecting hole on a first straight line extending along the first direction overlap. In the second color sub-pixel, the connecting electrode is connected to the first connecting portion through a second via penetrating the planarization layer, and the first connecting portion is electrically connected to the pixel circuit through a second connecting hole penetrating the interlayer insulating layer. The orthographic projection of the first via on the first straight line and the orthographic projection of the second via on the first straight line do not overlap. The data lines include a first data line and a second data line, which are alternately arranged along a direction perpendicular to the substrate. The second electrode of each second color sub-pixel overlaps with the first data line, the first power signal line, the second data line, the second power signal line, and the first connecting portion. In the overlapping portions of the first data line, the first power signal line, the second data line, the second power signal line, and the first connecting portion with the second electrode, the first power signal line and the first data line are located on opposite sides of the first connecting portion, and the second power signal line is located on the side of the first data line away from the first connecting portion. The second data line is located on the side of the first power signal line away from the first connecting portion. The first connecting portion... The device includes a first sub-connection portion connected to each other and a first pad located on the side of the first sub-connection portion near the first power signal line. Both the first sub-connection portion and the first pad overlap with the second electrode and the effective light-emitting area. Along the first direction, the size of the first sub-connection portion is larger than the size of the first pad. The ratio of the minimum distance between the edges of the first sub-connection portion and the first data line that are close to each other to the minimum distance between the edges of the first pad and the first power signal line that are close to each other is 0.8 to 1.

2. The shape of the first sub-connection portion is a rectangle extending along the first direction. A straight line passing through the center of the effective light-emitting area of ​​the second color sub-pixel and extending along the first direction is located on the side of the straight line passing through the center of the first sub-connection portion and extending along the first direction that is close to the first pad. The plurality of sub-pixels also include a plurality of third color sub-pixel pairs. In the third color sub-pixel pairs, the second electrode also includes an auxiliary electrode connecting the main electrode and the connecting electrode. The connecting electrode extends along the first direction. Each third color sub-pixel pair includes a first pixel block and a second pixel block arranged along the second direction. The main electrode of the first pixel block and the main electrode of the second pixel block have basically the same shape and size. The auxiliary electrode of the first pixel block and the auxiliary electrode of the second pixel block have different shapes. In the first pixel block, the edge of the auxiliary electrode connected to the connecting electrode away from the second pixel block and the edge of the connecting electrode away from the second pixel block both extend along the first direction and are on the same straight line. The pixel circuit includes a threshold compensation transistor, the threshold compensation transistor includes a first gate, the auxiliary electrode of the first pixel block covers the first gate of the threshold compensation transistor to prevent external light from directly hitting the channel region of the threshold compensation transistor, and the second electrode of the second pixel block covers the two gates of the threshold compensation transistor. The pixel circuit includes a second connection portion and a driving transistor located between the second electrode and the substrate. The second connection portion extends along the first direction. The first electrode of the threshold compensation transistor is electrically connected to the first electrode of the driving transistor. The second electrode of the threshold compensation transistor is electrically connected to the gate of the driving transistor through the second connection portion. The display substrate also includes a cover portion. Each threshold compensation transistor includes two gates along a direction perpendicular to the substrate. The cover portion overlaps with the active semiconductor layer between the two gates. The cover portion is configured to be connected to a power signal line. 2.The display substrate of claim 1, wherein, At least one of the first effective light-emitting area and the second effective light-emitting area is elongated and extends along the second direction, with the angle between the second direction and the first direction in the range of 80° to 100°. 3.The display substrate of claim 1, wherein, The first via is located in the first direction on the side of the first effective light-emitting area close to the second effective light-emitting area, the second via is located in the first direction on the side of the second effective light-emitting area close to the first effective light-emitting area, and the first line connecting the first via and the second via is not parallel to the second direction, and the second electrode of the first color sub-pixel and the second electrode of the second color sub-pixel do not overlap in the second direction. 4.The display substrate of claim 3, wherein, The second line connecting the first connecting hole and the second connecting hole is parallel to the second direction. 5.The display substrate of claim 4, wherein, The angle between the first connecting line and the second direction is 5~15°.

6. The display substrate according to claim 4, wherein, The first via is located on the side of the second straight line that passes through the second via and extends along the second direction, close to the first effective light-emitting area. 7.The display substrate of claim 4, wherein, The second effective light-emitting area includes a first long side and a second long side extending along the second direction. The second long side is located on the side of the first long side away from the second via. Along a third direction perpendicular to the substrate, the extension line of the first long side overlaps with the first via. 8.The display substrate of claim 7, wherein, The first effective light-emitting area includes a third long side and a fourth long side extending along the second direction. The fourth long side is located on the side of the third long side away from the first via, and the extension line of the third long side overlaps with the second via along the third direction. 9.The display substrate of claim 8, wherein, The first long side is a straight line, and the third long side is a straight line. 10.The display substrate of claim 9, wherein, The shortest distance between the first long side and the orthographic projection of the second via on the substrate is the first distance, and the shortest distance between the third long side and the orthographic projection of the first via on the substrate is the second distance. The ratio of the first distance to the second distance is 0.8 to 1.

2. 11.The display substrate of claim 10, wherein, Both the first distance and the second distance are greater than 3 micrometers. 12.The display substrate of claim 3, wherein, The pixel circuit includes a first light-emitting control transistor, which includes an active semiconductor layer, and the interlayer insulating layer is located between the active semiconductor layer and the first connection portion. In the first color sub-pixel, the first connecting portion is electrically connected to the first electrode of the first light-emitting control transistor through the first connecting hole; in the second color sub-pixel, the first connecting portion is electrically connected to the first electrode of the first light-emitting control transistor through the second connecting hole. 13.The display substrate of claim 12, wherein, Along a third direction perpendicular to the substrate, the second connecting hole overlaps with the second effective light-emitting area, the second via is farther away from the second effective light-emitting area than the second connecting hole, and the orthographic projection of the second via on the first straight line does not overlap with the orthographic projection of the second connecting hole on the first straight line. 14.The display substrate of claim 12, wherein, The second electrode of the first pixel block is connected to the first connection portion through a third via penetrating the planarization layer, and the second electrode of the second pixel block is connected to the first connection portion through a fourth via penetrating the planarization layer. The third line connecting the third via and the fourth via is parallel to the second direction. 15.The display substrate of claim 14, wherein, Along a third direction perpendicular to the substrate, the line containing the third connecting line passes through the second via but not through the first via. 16.The display substrate of claim 14, wherein, The first effective light-emitting area includes a third long side and a fourth long side extending along the second direction. The fourth long side is located on the side of the third long side away from the first via. Along a third direction perpendicular to the substrate, the line containing the third long side overlaps with both the third via and the fourth via. 17.The display substrate of claim 14, wherein, The second line connecting the first connecting hole and the second connecting hole is parallel to the second direction; In the first pixel block, the first connecting portion is electrically connected to the first electrode of the first light-emitting control transistor through a third connecting hole penetrating the interlayer insulating layer. In the second pixel block, the first connecting portion is electrically connected to the first electrode of the first light-emitting control transistor through a fourth connecting hole penetrating the interlayer insulating layer, and the fourth connecting line connecting the third connecting hole and the fourth connecting hole substantially coincides with the second connecting line.

18. The display substrate according to claim 14, wherein, Along the second direction, a third or fourth via is provided between the first and second vias.

19. The display substrate of claim 14, wherein, The first color sub-pixel is a blue sub-pixel, the second color sub-pixel is a red sub-pixel, and the third color sub-pixel pair is a green sub-pixel pair.

20. The display substrate according to any one of claims 14-19, wherein, In the first pixel block, the minimum distance between the orthographic projection of the second connecting portion on the straight line extending along the second direction and the orthographic projection of the effective light-emitting area of ​​the first pixel block on the straight line is a first distance; or, the orthographic projection of the second connecting portion on the straight line extending along the second direction and the orthographic projection of the effective light-emitting area of ​​the first pixel block on the straight line overlap; in the second pixel block, the minimum distance between the orthographic projection of the second connecting portion on the straight line and the orthographic projection of the effective light-emitting area of ​​the second pixel block on the straight line is a second distance, and the first distance is less than the second distance; In the first pixel block, the overlapping area of ​​the orthographic projection of the second electrode on the substrate and the orthographic projection of the second connection portion on the substrate is the first overlapping area. In the second pixel block, the overlapping area of ​​the orthographic projection of the second electrode on the substrate and the orthographic projection of the second connection portion on the substrate is the second overlapping area. The ratio of the first overlapping area to the second overlapping area is 0.8 to 1.

2. 21.The display substrate of claim 20, wherein, In the first pixel block, the second electrode covers 60-90% of the area of ​​the second connection portion; in the second pixel block, the second electrode covers 60-90% of the area of ​​the second connection portion.

22. The display substrate of claim 20, wherein, In the first pixel block, the gate of the threshold compensation transistor is located on the side of the second connection portion away from the effective light-emitting area of ​​the first pixel block; in the second pixel block, the gate of the threshold compensation transistor is located on the side of the second connection portion closer to the effective light-emitting area of ​​the second pixel block.

23. The display substrate according to claim 20, wherein, In the first pixel block, the auxiliary electrode is located on the side of the main electrode away from the effective light-emitting area of ​​the second pixel block; in the second pixel block, the auxiliary electrode is located on the side of the main electrode away from the effective light-emitting area of ​​the first pixel block. In the second pixel block, the first edge of the effective light-emitting area of ​​the second pixel block, which extends along the first direction in the portion of the connecting electrode near the auxiliary electrode, overlaps with the second connecting portion. The second edge of the auxiliary electrode, which is away from the effective light-emitting area of ​​the second pixel block, is located on the side of the second connecting portion away from the effective light-emitting area of ​​the second pixel block, so that the auxiliary electrode covers the second connecting portion.

24. The display substrate of claim 20, wherein, In the pixel circuit of each sub-pixel, the threshold compensation transistor further includes a second gate. In the first pixel block, the first gate is located on the side of the second gate near the effective light-emitting area of ​​the first pixel block. The third edge of the edge extending along the first direction of the portion of the connecting electrode near the auxiliary electrode, which is away from the first effective light-emitting area, overlaps with the first gate. The edge of the portion of the auxiliary electrode away from the connecting electrode in the second direction, which is away from the effective light-emitting area of ​​the first pixel block, is located on the side of the first gate away from the effective light-emitting area of ​​the first pixel block, so that the auxiliary electrode covers at least a portion of the first gate. 25.The display substrate of claim 1, wherein, The line that passes through the effective light-emitting area of ​​the second color sub-pixel at the midpoint of the line connecting the two opposite endpoints in the second direction and extends along the first direction overlaps with the second connecting portion.

26. The display substrate according to claim 1, further comprising: A reset power signal line extends along the second direction and is located between the film layer containing the data line and the substrate. The pixel circuit further includes a third connection portion disposed on the same layer as the data line, and the third connection portion extends along the first direction; The pixel circuit also includes a reset transistor, one of the first and second terminals of which is electrically connected to the reset power signal line via the third connection portion. Along a direction perpendicular to the substrate, the effective light-emitting area of ​​the second color sub-pixel overlaps with the third connecting portion, and a straight line passing through the center of the effective light-emitting area of ​​the second color sub-pixel and extending along the first direction overlaps with the third connecting portion. The first connecting portion is located on one side of the straight line passing through the center of the effective light-emitting area of ​​the second color sub-pixel and extending along the second direction, and at least a portion of the third connecting portion is located on the other side of the straight line.

27. A display device comprising the display substrate according to any one of claims 1-26.

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