Storage device and method of operating the same

Abstract

A method of operating a storage device including a non-volatile memory device and a controller that controls operations of the non-volatile memory device, the method including issuing, by the controller, a first command to the non-volatile memory device, reading, by the non-volatile memory device in response to the first command, first data from an array of memory cells into a page buffer of the non-volatile memory device, issuing, by the controller, a second command to the non-volatile memory device, and outputting, by the non-volatile memory device in response to the second command, to the controller, status information indicating whether a read operation according to the first command has completed and second data obtained from the page buffer of the non-volatile memory device.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0000484, filed on January 2, 2020, with the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The embodiments of the present invention are directed to storage devices, and more specifically, to storage devices including non-volatile memory devices and controllers and methods of operating thereof. Background Technology

[0004] Recently, storage devices such as solid-state drives (SSDs) have become widely used. A storage device corresponds to a memory system that includes non-volatile memory devices such as flash memory and a controller that controls the non-volatile memory devices. With improvements in storage device performance, the data input / output speed between the non-volatile memory devices and the controller within the storage device has increased. Therefore, data can be transferred or received at high speed between the controller and the non-volatile memory devices.

[0005] During a read operation, the controller can issue a status command CMD after issuing a read command CMD to identify whether the non-volatile memory device has completed the read operation, and only issue a read command CMD after the status command indicates READY, in order to read the data written to the storage device. When commands are sent from the controller to the non-volatile memory device according to timing parameters with predefined fixed time values, the input / output efficiency of data transfer will decrease even if the data input / output speed is increased. Summary of the Invention

[0006] An embodiment of the present invention provides a storage device and a method of operating the same, the storage device comprising a non-volatile memory device and a controller, the storage device being able to improve or maintain the efficiency of input / output operations between the non-volatile memory device and the controller.

[0007] According to an embodiment of the present invention, a method for operating a storage device is provided, the storage device including a non-volatile memory device and a controller for controlling the operation of the non-volatile memory device. The method includes the controller issuing a first command to the non-volatile memory device, the non-volatile memory device responding to the first command by reading first data from a memory cell array into a page buffer of the non-volatile memory device, the controller issuing a second command to the non-volatile memory device, and the non-volatile memory device responding to the second command by outputting status information indicating whether the read operation according to the first command has been completed and the second data obtained from the page buffer of the non-volatile memory device to the controller.

[0008] According to another embodiment of the present invention, a storage device is provided, comprising a non-volatile memory device and a controller for controlling the non-volatile memory device and issuing a plurality of commands. The non-volatile memory device includes: a memory cell array comprising a plurality of memory cells and reading first data in response to a first command; control logic that controls the read operation of the memory cell array based on the plurality of commands; a page buffer that buffers the first data; and an input / output interface that, in response to a second command, outputs status information indicating whether the read operation has been completed and second data obtained by buffering the first data to the controller.

[0009] According to another embodiment of the present invention, a method for operating a storage device is provided, the storage device including a non-volatile memory device and a controller for controlling the operation of the non-volatile memory device. The method includes issuing a first command to the non-volatile memory device by the controller, the non-volatile memory device reading first data from a memory cell array in response to the first command, issuing a second command by the controller in a second read mode, the second command being used to transmit status information indicating whether the read operation of the memory cell array according to the first command has been completed and the first data to the controller, and the controller issuing a third command for outputting the status information and a fourth command for transmitting the first data in the first read mode. Attached Figure Description

[0010] Figure 1 This is a block diagram illustrating a storage device according to an embodiment.

[0011] Figure 2 This is a timing diagram illustrating the timing of signals and commands generated and issued in a storage device according to an embodiment.

[0012] Figure 3 A non-volatile memory device according to an embodiment is shown.

[0013] Figure 4 This is a block diagram of the controller according to an embodiment.

[0014] Figure 5 A block diagram of the controller according to an embodiment is shown in more detail.

[0015] Figure 6 A block diagram of a controller according to another embodiment is shown in more detail.

[0016] Figure 7 This is a timing diagram illustrating the timing of signals and commands generated and issued in a first read mode according to an embodiment.

[0017] Figure 8 This is a timing diagram illustrating the timing of signals and commands generated and issued in the second read mode according to an embodiment.

[0018] Figure 9 This is a timing diagram illustrating the timing of signals and commands generated and issued in a second read mode according to another embodiment.

[0019] Figure 10 A data stream generated by a non-volatile memory device according to an embodiment is shown.

[0020] Figure 11 and 12 A table is shown, according to an embodiment, in which signals and commands issued for each mode are categorized.

[0021] Figure 13 This is a flowchart of a method for operating the controller according to an embodiment.

[0022] Figure 14 This is a detailed flowchart of a method for operating a storage device, including a controller and a non-volatile memory device, according to an embodiment.

[0023] Figure 15 This is a block diagram of a storage device including a controller and a non-volatile memory device according to an embodiment. Detailed Implementation

[0024] In the following, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0025] Figure 1 This is a block diagram illustrating a memory device according to an embodiment. (Reference) Figure 1 The storage device 10 includes a nonvolatile memory device (NVM) 100 and a controller 200.

[0026] According to an embodiment of the present invention, the controller 200 can issue a second read command CMD, which allows the non-volatile memory device 100 to transmit a status information signal Status and read data Data to the controller 200, and the non-volatile memory device 100 transmits the status information signal Status and read data Data to the controller 200 in response to the second read command CMD. The status information signal Status includes a signal or data indicating whether the non-volatile memory device 100 has completed the read operation from the memory cell array 130 in response to the read command CMD. The status information signal Status includes a ready state READY and a busy state BUSY, wherein the ready state READY indicates that the read operation from the memory cell array 130 has been completed, and the busy state BUSY indicates that the read operation from the memory cell array 130 is in progress, i.e., has not yet been completed.

[0027] According to an embodiment, storage device 10 can be implemented as a storage device such as a solid state drive (SSD). However, embodiments of the inventive concept are not limited thereto, and therefore storage device 10 can be implemented as any of various types of devices, such as embedded multimedia card (eMMC), universal flash storage (UFS), compact flash (CF), secure digital (SD), micro secure digital (micro-SD), mini secure digital (mini-SD), extreme digital (xD), Memory Stick, etc.

[0028] According to an embodiment, storage device 10 can communicate with a host via any of a variety of interfaces. The host can request data processing operations from storage device 10, such as data read operations or data write operations. In an embodiment, the host corresponds to a CPU, processor, microprocessor, application processor, etc. According to an embodiment, the host is implemented as a system-on-a-chip (SoC).

[0029] According to the embodiment, the interface used for communication between the storage device 10 and the host can be any of various interface types, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnection (PCI), PCI-express (PCI-E), IEEE 1394, Universal Serial Bus (USB), SD digital card, Multimedia Card (MMC), Embedded MMC (eMMC), CF card interface, etc.

[0030] According to an embodiment, the non-volatile memory device 100 receives a command CMD and a read enable signal REB generated by the controller in response to a request received from the host. The non-volatile memory device 100 includes control logic 110, a memory cell array 130, a page buffer 150, and an input / output interface 170.

[0031] According to an embodiment, control logic 110 controls the overall operation of the non-volatile memory device 100. Control logic 110 controls the operation of a plurality of memory cells included in the non-volatile memory device 100 based on a command CMD received from controller 200. Furthermore, control logic 110 receives an address and controls the plurality of memory cells based on the command CMD and that address.

[0032] According to an embodiment, control logic 110 receives a command CMD from input / output interface 170 or a command buffer where a command CMD and / or an address are buffered. In this case, the command buffer or input / output interface 170 operates at a first operating speed corresponding to the data input / output speed between non-volatile memory device 100 and controller 200, and control logic 110 operates at a second operating speed lower than the first operating speed. That is, the internal operating speed of non-volatile memory device 100 corresponds to the second operating speed. However, for ease of explanation, Figure 1 The diagram does not show configurations such as additional input / output interfaces.

[0033] According to an embodiment, control logic 110 receives a read enable signal REB from controller 200. In this embodiment, during a read operation of memory cell array 130, the controller 200 enables the read enable signal REB, for example, by toggling the read enable signal REB to indicate a state transition. Furthermore, the read enable signal REB synchronizes signals such as data strobe signals for transmitting read data. Here, the operation of the enable signal represents an operation in which the signal level transitions to a different logic level; therefore, the phase of the signal can change from 0 degrees to 180 degrees or from 180 degrees to 0 degrees.

[0034] According to an embodiment, control logic 110 controls programming, reading, and erasing operations for the memory cell array 130. (Refer to...) Figure 3 The control logic 110 is described in more detail.

[0035] According to an embodiment, the memory cell array 130 includes a plurality of memory cells. Each of the plurality of memory cells serves as a unit storage device for writing and reading information. A memory bank may exist, wherein the memory bank is a logical partition in which predefined memory cells among the plurality of memory cells are grouped. Data can be written to or read from the memory cell array 130 on a memory bank-by-memory bank basis, but the embodiment is not limited thereto.

[0036] In some embodiments, the plurality of memory cells include a plurality of flash memory cells. For example, the plurality of flash memory cells include NAND flash memory cells. However, embodiments of the present invention are not limited thereto, and therefore, the plurality of memory cells may include resistive memory cells, such as resistive random access memory (ReRAM), phase change random access memory (PRAM), or magnetic random access memory (MRAM).

[0037] According to an embodiment, the memory cell array 130 writes data to or reads data from a memory cell selected from the plurality of memory cells based on the control of the control logic 110. The read data is output to the page buffer 150, and the output read data is buffered in the page buffer 150.

[0038] According to an embodiment, page buffer 150 buffers received read data. Page buffer 150 temporarily stores the received data and includes at least one register. In an embodiment, page buffer 150 uses multiple sets of page buffers to buffer data sequentially. (See reference...) Figure 3 The page buffer 150 is described in more detail.

[0039] According to an embodiment, the input / output interface 170 receives a status information signal "Status" from control logic 110 and read data "Data" from page buffer 150. In an embodiment conceived according to the invention, the input / output interface 170, in response to a second read command from controller 200, transmits the status information signal "Status" and the read data "Data" to controller 200. In this embodiment, the input / output interface 170 transmits the status information signal "Status" to controller 200 before transmitting the read data "Data".

[0040] According to an embodiment, the input / output interface 170 is electrically connected to the controller 200 via an input / output channel. In other words, depending on the data input / output speed, the status information signal "Status" and the read data "Data" are transmitted to the controller 200.

[0041] According to an embodiment, controller 200 receives a status information signal (Status) and read data (Data) from non-volatile memory device 100. According to an embodiment, controller 200 is referred to as a memory controller or storage controller.

[0042] According to an embodiment, controller 200 controls non-volatile memory device 100 to read data stored in or write data to non-volatile memory device 100, i.e., programming data, in response to a request from host or a predefined read / write signal. In an embodiment, controller 200 provides command CMD to non-volatile memory device 100 to control programming, reading, and erasing operations of non-volatile memory device 100. Furthermore, data to be programmed (Data) and data to be read (Data) are transferred / received between controller 200 and non-volatile memory device 100. For example, command CMD is one of a write command, a read command, an erase command, etc. The read command includes read command CMD_R, status read command CMD_SR, and a first read command CMD_O1, and also includes a second read command CMD_O2. The second read command CMD_O2 is a smart read command because it is issued to receive both status information signal Status and read data (Data).

[0043] According to an embodiment, the controller 200 receives both the status information signal Status and the read data Data by issuing a second read command CMD_O2, and the controller 200 continues to receive data from the non-volatile memory device 100 or stops receiving data based on the received status information signal Status.

[0044] In an embodiment, based on the set read mode, the controller 200 operates in a second read mode, wherein in the second read mode, a second read command CMD_O2 is issued at a predetermined time after the read command CMD_R is issued; or it operates in a first read mode, wherein in the first read mode, a status read command CMD_SR is issued at a predetermined time after the read command CMD_R is issued. In the first read mode, the non-volatile memory device 100, in response to the status read command CMD_SR, sends a status information signal Status to the controller 200 separately from the read data Data, and the controller 200 may also issue a first read command CMD_O1 or may reissue the status read command CMD_SR based on the received status information signal Status. (Refer to...) Figures 7 to 12 The storage device 10, including the controller 200 and the non-volatile memory device 100, is described in more detail in conjunction with read commands. In an embodiment, the read mode is set based on a mode signal received from an external device, such as a host. However, the embodiment is not limited to this, and therefore, the read mode can be preset when the storage device 10 is manufactured.

[0045] According to an embodiment, controller 200 generates a read enable signal REB and sends it to non-volatile memory device 100. The read enable signal REB synchronizes signals such as a data strobe signal for transmitting read data Data. Here, in response to the read enable signal REB, non-volatile memory device 100 generates a data strobe signal DQS (data strobe signal). In an embodiment, the data strobe signal DQS serves as a clock signal for outputting data from non-volatile memory device 100. In other words, the read enable signal REB is associated with a clock signal that drives the output of read data Data and a status information signal Status.

[0046] According to an embodiment, the non-volatile memory device 100 and the controller 200 are electrically connected via input / output interfaces respectively included therein, wherein the input / output interfaces are connected by pins. That is, each of the non-volatile memory device 100 and the controller 200 includes a plurality of input / output pins DQ.

[0047] According to an embodiment, in each of the multiple input / output pins DQ in the non-volatile memory device 100 and the controller 200, the first pin is an input / output pin, the second pin is a clock pin, the third pin is a command latch enable signal, and the fourth pin is an address latch enable signal. Additionally, a separate pin for a data strobe signal DQS associated with the output of read data Data is included. However, the embodiment is not limited to this; therefore, at least one of the multiple pins DQ can be used as a data pin through which data is transmitted, or all of the multiple pins DQ can be used as data pins through which data is transmitted.

[0048] According to an embodiment, since the command CMD has a predefined fixed duration, the ratio of the predefined fixed duration to the total data processing time gradually increases with the increase of data input / output speed, thus leading to a decrease in input / output efficiency. According to an embodiment of the present invention, since the non-volatile memory device 100 transmits both the status information signal Status and the read data Data to the controller 200, the controller 200 can immediately check the status of the non-volatile memory device 100, thereby reducing the waiting time for issuing the command CMD. Here, transmitting both the status information signal Status and the read data Data does not mean simultaneous transmission; rather, the status information signal Status and the read data Data are transmitted separately via the same channel. That is, the status information signal Status and the read data Data are transmitted in response to the same second read command CMD received from the controller 200. Therefore, the data input / output efficiency between the non-volatile memory device 100 and the controller 200 is improved.

[0049] According to an embodiment, storage device 10 and host constitute a storage system, wherein the storage system is implemented as, for example, a personal computer (PC), a data server, a network-attached storage device, an Internet of Things (IoT) device, or a mobile electronic device. The mobile electronic device may be a laptop computer, mobile phone, smartphone, tablet PC, personal digital assistant (PDA), enterprise digital assistant (EDA), digital still camera, digital camcorder, audio equipment, portable multimedia player (PMP), personal navigation device (PND), MP3 player, handheld game console, e-reader, wearable device, etc.

[0050] Figure 2 This is a timing diagram illustrating the timing of signals and commands generated and issued by the storage device according to an embodiment. Figure 2 In the timing diagram, the horizontal axis represents time, and the vertical axis represents the high (or data "1") / low (or data "0") signal level.

[0051] refer to Figure 1 and Figure 2 According to an embodiment, the controller 200 issues a read command CMD_R, a status read command CMD_SR, a first read command CMD_O1, and a second read command CMD_O2, and transmits the issued CMD commands to the non-volatile memory device 100. In response to the status read command CMD_SR or the second read command CMD_O2, the non-volatile memory device 100 transmits a status information signal (such as a READY state indicating that reading has been completed or a BUSY state indicating that reading has not yet been completed) to the controller 200. In other words, the READY state indicates the state of the non-volatile memory device 100, in which the non-volatile memory device 100 is ready to perform an operation corresponding to a request from the controller 200. The BUSY state indicates the state of the memory cell being operated, such as a state where the operation corresponding to a request from the controller 200 cannot be performed.

[0052] According to an embodiment, the controller 200 generates a read enable signal REB and a write enable signal WEB based on the status information signal Status. The write enable signal WEB is enabled during write operations of the memory cell array 130 and is synchronized with the data strobe signal DQS to write data.

[0053] According to an embodiment of the present invention, controller 200 issues a second read command CMD_O2 and transmits it to non-volatile memory device 100. The second read command CMD_O2 is used to transmit read data Data from memory cell array 130 along with a status information signal Status about memory cell array 130. Controller 200 switches the write enable signal transmitted to non-volatile memory device 100 and writes the second read command CMD_O2 during the time of the write enable signal switch. For example, the second read command CMD_O2 can be synchronized with the rising edge of the write enable signal WEB. Although... Figure 2 The second read command CMD_O2 is shown to be synchronized with the rising edge of the write enable signal WEB, but the second read command CMD_O2 can also be synchronized with the falling edge of the write enable signal WEB.

[0054] According to an embodiment, the non-volatile memory device 100 receives a second read command CMD_O2 from the controller 200 and generates a status information signal Status. If the non-volatile memory device 100 is in a state indicated by the READY state, the non-volatile memory device 100 generates read data Data by reading data. If the non-volatile memory device 100 is not in a state indicated by the READY state, that is, in a state indicated by the BUSY state, the non-volatile memory device 100 generates additional information INFO including power information or fault information about the memory cell array, and sends a data stream including the status information signal Status and read data Data or the status information signal Status and additional information INFO to the controller 200.

[0055] According to an embodiment, the controller 200 can determine whether the non-volatile memory device 100 is ready by receiving a status information signal, Status. The controller 200 can confirm that the Status information signal indicates a ready state (READY) and begin switching the read enable signal, REB. Switching of the read enable signal REB begins after a predetermined time has elapsed following the transition of the write enable signal, WEB, to a logic high level. In other words, after the write enable signal WEB transitions to a logic high level, and after a time period corresponding to the status information reception process of the non-volatile memory device 100 has passed, the switching of the read enable signal REB begins.

[0056] According to an embodiment, the non-volatile memory device 100, in response to the switching of the received read enable signal REB, begins switching the data strobe signal DQS. The data strobe signal DQS serves as a clock signal for outputting data from the non-volatile memory device 100. That is, the read data Data read from the non-volatile memory device 100 is output to the controller 200 synchronously with the switching of the data strobe signal DQS. The read enable signal REB and the data strobe signal DQS will be switched until the status information signal Status and the read data Data are transmitted. In an embodiment, the read data Data and the status information signal Status are synchronized with the falling edge of the data strobe signal DQS. In another embodiment, the read data Data and the status information signal Status are synchronized with the rising and falling edges of the data strobe signal DQS, and are therefore transmitted to the non-volatile memory device 100 in double data rate (DDR) mode. Therefore, not only can the transmission speed of the read data Data and the status information signal Status be increased, but the transmission speed of the command CMD and the address can also be increased.

[0057] According to an embodiment, the input / output interface 170 of the non-volatile memory device 100 transmits a status information signal (Status) and read data (Data) to the controller 200. The data stream, including the status information signal (Status) and read data (Data), is transmitted to the controller 200 via multiple pins (DQ) of the input / output interface 170, and the controller 200 receives the data stream via multiple pins of the input / output interface corresponding to the multiple pins (DQ) of the input / output interface 170.

[0058] According to an embodiment, the status information signal Status is output synchronously with a first edge via multiple pins DQ of the input / output interface 170. In this embodiment, a ready state READY, indicating that data can be read from the non-volatile memory device 100, is transmitted to the controller 200 via multiple pins DQ. Continuously, read data Data is transmitted to the controller 200 synchronously with a second edge via multiple pins DQ (D0). Continuously, read data Data is transmitted to the controller 200 synchronously with a third edge via multiple pins DQ (D1). Similarly, read data Data is transmitted to the controller 200 synchronously with the (N+2)th edge via multiple pins DQ (DN), where N is a natural number greater than or equal to 1.

[0059] Figure 3 A non-volatile memory device according to an embodiment is shown.

[0060] refer to Figure 1 and Figure 3 According to an embodiment, the non-volatile memory device 100 includes control logic 110, a row decoder 120, a memory cell array 130, a voltage generator 140, a page buffer 150, and an input / output interface 170, wherein the page buffer 150 further includes a plurality of page buffer cells PB1 151 to PBn 15n. The non-volatile memory device 100 according to this embodiment corresponds to... Figure 1 The above refers to an embodiment of the storage device 10. Figure 1 and Figure 2 The above description applies to this embodiment. References to the above are omitted below. Figure 1 and Figure 2 The given description.

[0061] According to an embodiment, control logic 110 receives command CMD, reads enable signal REB, and writes enable signal WEB from controller 200. For convenience, Figure 3The illustration shows control logic 110 directly receiving command CMD, read enable signal REB, and write enable signal WEB. However, the embodiment is not limited to this, and therefore, in other embodiments, control logic 110 receives command CMD, read enable signal REB, and write enable signal WEB via different channels (such as separate input / output interfaces).

[0062] According to an embodiment, control logic 110 generates a voltage control signal V_CTRL and sends it to a voltage generator 140 that controls the supply of power, and generates a row address signal X-ADDR and sends it to a memory cell array 130 (this row address signal controls the memory cell array 130 on a per-string select line (SSL) and per-word line (WL) basis), and generates a column address signal Y-ADDR, which controls the buffering of a page buffer 150 on a per-bit line (BL) basis. Therefore, control logic 110 controls various operations of the non-volatile memory device 100.

[0063] According to an embodiment, the row decoder 120 selects some of a plurality of word lines WL based on the row address signal X-ADDR and activates the selected word lines WL. The row decoder 120 receives word line voltages V_WL corresponding to the operating mode from the voltage generator 140 and applies the word line voltages V_WL to the word lines WL of the selected memory cells or memory blocks. During a programming operation, the row decoder 120 applies a programming voltage Vpgm and a programming verification voltage Vpgm_vfy to the selected word lines WL, and applies a programming pass voltage Vpgm_pass to the unselected word lines. During an erase operation, the row decoder 120 applies an erase voltage Vera and an erase verification voltage Vera_vfy to the selected word lines WL, and applies an erase pass voltage Vera_pass to the unselected word lines. During a read operation, the row decoder 120 transmits a read voltage Vr to the selected word lines WL, and transmits a read pass voltage Vr_pass to the unselected word lines. Although the read operation is described as being performed by providing a read voltage Vr, the read operation according to embodiments of the present invention can be performed not only by the read voltage Vr, but also by the programming verification voltage Vpgm_vfy and the erase verification voltage Vera_vfy for the erase operation.

[0064] According to an embodiment, the memory cell array 130 includes a plurality of memory cells, which constitute a plurality of memory pages or a plurality of memory banks. The memory cell array 130 is connected to a row decoder 120 via word lines WL and select lines SSL and GSL (ground select lines), and to a page buffer 150 via bit lines BL. Each of the plurality of memory cells includes a plurality of memory cells arranged in a region where the plurality of word lines and the plurality of bit lines intersect. The memory cells can be programmed, erased, or read by voltages supplied to the bit lines BL and word lines WL.

[0065] In one embodiment, the memory cell array 130 includes a three-dimensional memory cell array, wherein the three-dimensional memory cell array includes a plurality of NAND strings, wherein each NAND string includes memory cells respectively connected to word lines vertically stacked on a substrate. In some embodiments, the memory cell array 130 includes a two-dimensional memory cell array, wherein the two-dimensional memory cell array includes a plurality of NAND strings arranged in rows and columns.

[0066] According to an embodiment, voltage generator 140 generates word line voltages V_WL that drive multiple word lines WL based on control signals received from control logic 110. The word line voltages V_WL include programming voltages, read voltages, erase voltages, or pass voltages. The generated word line voltages V_WL are sent to line decoder 120 to select some word lines and activate the selected word lines WL.

[0067] According to an embodiment, page buffer 150 includes a plurality of page buffer cells 151 to 15n, where n is a natural number greater than or equal to 2. Page buffer 150 stores data to be recorded in or read from memory cell array 130. Page buffer 150 may include a plurality of page buffer groups, each of which includes page buffer cells 151 to 15n. In an embodiment, the number of page buffer groups corresponds to the number of memory pages or memory banks, and the number of page buffer cells 151 to 15n in each of the page buffer groups corresponds to the number of bit lines BL in each of the plurality of memory banks or plurality of memory pages.

[0068] According to an embodiment, when a read operation is performed on the non-volatile memory device 100, the page buffer 150 stores data of the selected memory cells based on a read signal provided to a word line of some memory cells selected from a plurality of memory cells in the memory cell array 130. For example, each of the plurality of page buffers includes at least one latch, and latches the data of the memory cell when a latch signal is provided to the at least one latch.

[0069] According to an embodiment, page buffer 150 responds to some of the column address signal Y-ADDR select bit lines BL. Specifically, page buffer 150 operates as a write driver or a sense amplifier depending on the operating mode. For example, page buffer 150 operates as a sense amplifier to output data stored in memory cell array 130 during a read operation, and page buffer 150 operates as a write driver to input data to be stored into memory cell array 130 during a programming operation.

[0070] In one embodiment, page buffer 150 includes a plurality of page buffer groups, each of which includes a plurality of page buffer cells 151 to 15n. For example, the number of the plurality of page buffer groups corresponds to the number of memory banks or memory pages in the memory cell array.

[0071] According to an embodiment, the input / output interface 170 receives a status information signal "Status" from the control logic 110 and read data "Data" from the page buffer 150. In an embodiment conceived according to the invention, the input / output interface 170, in response to a second read command "CMD_O2" received from the controller 200, transmits the status information signal "Status" and the read data "Data" to the controller 200. In this embodiment, the input / output interface 170 transmits the status information signal "Status" to the controller 200 before transmitting the read data "Data".

[0072] Figure 4 This is a block diagram of the controller according to an embodiment.

[0073] According to an embodiment, the controller 200 includes a host interface (I / F) 210, a central processing unit (CPU) 220, random access memory (RAM) 230, read-only memory (ROM) 240, a buffer 250, and a non-volatile memory device interface (NVM I / F) 260, wherein the aforementioned components communicate via a bus.

[0074] According to an embodiment, controller 200 generates addresses and command CMDs (such as programming commands, read commands, or erase commands) to control the operation of non-volatile memory device 100 (such as programming operations, read operations, or erase operations). Programming and read operations are performed on a page-by-page basis, and erase operations are performed on a block-by-block basis, but the embodiment is not limited thereto.

[0075] According to an embodiment, the controller 200 receives a status information signal (Status) and read data (Data) from the non-volatile memory device 100. The controller 200 provides a command (CMD) to the non-volatile memory device 100 to control programming, reading, and erasing operations on the non-volatile memory device 100. In an embodiment of the present invention, the controller 200 receives both the status information signal (Status) and the read data (Data) by issuing a second read command (CMD_O2), and the controller 200 continues to receive data from the non-volatile memory device 100 or stops data reception based on the received status information signal (Status).

[0076] According to an embodiment, the controller 200 outputs a command CMD to the non-volatile memory device 100 to control the operation of the non-volatile memory device 100. The non-volatile memory device 100 and the memory controller 200 are electrically connected via multiple input / output pins DQ, and the command CMD, data, address signals, status information signals, etc., are transmitted / received via the multiple DQ pins. For convenience, the following description focusing on the read operation is provided as an embodiment.

[0077] According to an embodiment, the CPU 220 controls data exchange between the host interface 210, RAM 230, ROM 240, buffer 250, and memory interface 260 via a bus. The CPU 220 generates CMD commands to program data into or read data from the non-volatile memory device 100. Furthermore, the CPU 220 generates programming commands, read commands, and erase commands.

[0078] According to an embodiment, RAM 230 is the operating memory of CPU 220 and can be implemented as dynamic RAM (DRAM) or static RAM (SRAM). ROM 240 stores program code for operating controller 200. The program code can be stored in ROM 240 in the form of firmware. Buffer 250 can be implemented as volatile memory, such as DRAM, SRAM, or dual-port SRAM.

[0079] According to an embodiment, communication between the host (HOST) and controller 200 is performed via host interface 210. In this embodiment, in response to a programming request, the host transmits data to be programmed into the non-volatile memory device 100 to the controller 200 via host interface 210, and the controller 200, in response to the programming request, generates a page address and / or a word line address corresponding to the page in the non-volatile memory device 100 where the data is to be stored. In this embodiment, in response to a read request, the host transmits a logical region of data to be read from the non-volatile memory device 100 to the controller 200 via host interface 210, and the controller 200 generates a page address corresponding to the physical region of that logical region.

[0080] According to an embodiment, the controller 200 and the non-volatile memory device 100 communicate with each other via a memory interface 260. The memory interface 260 corresponds to the one described above. Figure 1 The input / output interface 170 is described, and the memory interface 260 and the input / output interface 170 are electrically connected to each other via a plurality of pins DQ.

[0081] Figure 5 This is a block diagram illustrating the controller according to an embodiment in more detail. Also refer to... Figure 1 , Figure 3 and Figure 4 .

[0082] According to an embodiment, the controller 200a includes a command generator 270a and a signal generator 280a. The command generator 270a and the signal generator 280a constitute a... Figure 4 The memory interface 260 is shown. However, the embodiments are not limited to this; therefore, the command generator 270a and the signal generator 280a can be implemented as, for example, software or firmware and executed by the CPU 220.

[0083] According to an embodiment, the controller 200a receives a read request via the host interface 210 and receives a status information signal Status and read data Data via the memory interface 260.

[0084] According to an embodiment, command generator 270a issues a read command CMD_R in response to a read request received from the host. Furthermore, command generator 270a issues a second read command CMD_O2 after a first time interval following the generation of read command CMD_R. Read command CMD_R includes a command allowing non-volatile memory device 100 to read data from the memory cell array, and the second read command CMD_O2 includes a command to output read data Data and a status information signal Status indicating whether the non-volatile memory device 100 has completed the read operation to controller 200. Status information signal Status includes a READY state indicating that the read operation of non-volatile memory device 100 has been completed and a BUSY state indicating that the read operation of non-volatile memory device 100 has not yet been completed.

[0085] According to an embodiment of the present invention, a second read command CMD_O2 generated by command generator 270a is output to non-volatile memory device 100, and non-volatile memory device 100, in response to the second read command CMD_O2, outputs both read data Data and a status information signal Status about non-volatile memory device 100 to controller 200.

[0086] According to an embodiment, signal generator 280a generates a read enable signal REB and a write enable signal WEB in response to a read request received from the host, and outputs the read enable signal REB and the write enable signal WEB to the non-volatile memory device 100 via memory interface 260.

[0087] According to an embodiment, the write enable signal WEB is switched to issue multiple commands CMD. Furthermore, the read enable signal REB is synchronized with the data strobe signal DQS, which serves as a reference clock for outputting data from the non-volatile memory device 100. In other words, the read enable signal REB is generated to output data from the non-volatile memory device 100.

[0088] According to an embodiment, the controller 200a can receive data or stop receiving data based on a status information signal. Specifically, the controller 200a continues to receive read data (Data) in response to receiving a READY status, and stops receiving data in response to receiving a BUSY status. In the case of a BUSY status, the read data received up to the point where the controller 200a acknowledges the BUSY status can be discarded. According to an embodiment, in the case of data read up to the point where the BUSY status is acknowledged, the data may include faulty memory cell address information or power information about the non-volatile memory device 100, rather than the read data of the non-volatile memory device 100, thereby making the received data usable.

[0089] In this embodiment, the same input / output channel as the data (Data) is used to transmit the command CMD from the controller 200 to the non-volatile memory device 100. For example, the controller 200 transmits the command CMD to the non-volatile memory device 100 via the input / output channel, and subsequently, via the input / output channel, transmits the data to be programmed (Data) to the non-volatile memory device 100, or receives read data (Data) read from the non-volatile memory device 100. However, embodiments of the inventive concept are not limited to this, and in other embodiments, the channel for transmitting the command CMD is separate from the channel for transmitting the data (Data). For convenience, Figure 1 and Figure 5 The channel is shown as implemented via the input / output interface.

[0090] Figure 6 This is a block diagram illustrating a controller according to another embodiment. Reference is also made to... Figure 1 , Figure 3 and Figure 4 .

[0091] According to an embodiment, the controller 200b includes a command generator 270b and a signal generator 280b, and also includes a mode selector 290b. The command generator 270b and the signal generator 280b have... Figure 5 The command generator 270a and signal generator 280a have similar functions, therefore, further details regarding the above references are omitted below. Figure 5 The given description is repeated.

[0092] According to an embodiment, controller 200b receives read requests and read modes via host interface 210. The read modes include a first read mode and a second read mode.

[0093] According to an embodiment, mode selector 290b applies a mode signal MODE to command generator 270b and signal generator 280b based on the received read mode. Command generator 270b and signal generator 280b control the non-volatile memory device 100 to operate in a first read mode or a second read mode based on the mode signal MODE.

[0094] According to the embodiment, in addition to the aforementioned read command CMD_R and second read command CMD_O2, the command generator 270b also issues a status read command CMD_SR and a first read command CMD_O1. The status read command CMD_SR is issued to allow the non-volatile memory device 100 to output a status information signal, Status, indicating whether the read operation has been completed, after the read command CMD_R is issued. When the READY status indicates that the read operation of the non-volatile memory device 100 has been completed, the first read command CMD_O1 is issued to allow the non-volatile memory device 100 to output the read data, Data.

[0095] According to an embodiment, the controller 200b issues a read command CMD_R, a status read command CMD_SR, and a first read command CMD_O1 in a first read mode, and issues a read command CMD_R and a second read command CMD_O2 in a second read mode. However, the embodiment is not limited thereto, and in other embodiments, the read mode may include combinations of various commands CMD.

[0096] According to an embodiment, the host can respond to a user input request to read the mode, or determine the read mode based on predetermined criteria. The read mode determines whether the storage device 10 operates in a first read mode or a second read mode.

[0097] Figures 7 to 9 This is a timing diagram showing the signals and commands generated according to the read pattern. Figures 7 to 9 In the timing diagram, the horizontal axis represents time, and the vertical axis represents the high (or data "1") / low (or data "0") signal level. The storage device 10 according to this embodiment can correspond to... Figure 1 The above refers to an embodiment of the storage device 10. Figure 1 , Figure 3 , Figure 5 and Figure 6 The description provided applies to this embodiment. References to the above are omitted below. Figure 1 , Figure 3 , Figure 5 and Figure 6 The given description.

[0098] Figure 7This is a timing diagram illustrating the timing of signals and commands generated and issued in a first read mode according to an embodiment.

[0099] According to an embodiment, a command latch enable signal CLE is transmitted from controller 200 to non-volatile memory device 100. As described above, commands CMD generated by command generators 270a and 270b, signals generated by signal generators 280a and 280b, and additional information INFO and data read from non-volatile memory device 100 are transmitted / received via the same input / output pin DQ. Controller 200 uses the command latch enable signal CLE to distinguish data items transmitted / received via the same input / output pin DQ, such as commands CMD, signals, data Data, and additional information INFO.

[0100] According to an embodiment, at time point t1, the controller 200 switches the command latch enable signal CLE for the read operation. After a predetermined time, the controller 200 switches the write enable signal WEB, and at time point t2, which is a transition point (such as rising or falling edge) of the write enable signal WEB, a read command CMD_R is issued and transmitted to the non-volatile memory device 100. Although Figure 7 The diagram shows that the read command CMD_R is issued synchronously with the first rising edge of the write enable signal WEB (i.e., time point t2), but the read command CMD_R can also be issued synchronously with the falling edge of the write enable signal WEB.

[0101] According to an embodiment, the non-volatile memory device 100 reads data from the memory cell array 130 in response to a read command CMD_R. A predetermined time may be required to read the written data.

[0102] According to an embodiment, after issuing the read command CMD_R and waiting for a first time interval Ta at time point t3, the controller 200 issues a status read command CMD_SR. The status read command CMD_SR is issued on the second rising edge of the write enable signal WEB. Here, the first time interval Ta corresponds to the estimated time for reading data written to the non-volatile memory device 100.

[0103] According to an embodiment, in response to the status read command CMD_SR, the non-volatile memory device 100 outputs a status information signal Status to the controller 200, which indicates whether the read operation of the memory cell array has been completed.

[0104] In the following, according to an embodiment, it is assumed that the status information signal Status indicates the busy status BUSY.

[0105] According to an embodiment, controller 200 switches the level of the read enable signal REB to receive the status information signal Status. Therefore, controller 200 receives the busy status BUSY at time t4 on the rising edge of the read enable signal REB.

[0106] According to an embodiment, after confirming that the read operation of the non-volatile memory device 100 has not yet been completed, the controller 200 reissues the status read command CMD_SR at time point t5 after waiting for the second time interval Tb. Here, the second time interval Tb is obtained by subtracting the time difference between the time of issuing the read command CMD_R (i.e., time point t2) and the time of confirming the busy state BUSY (i.e., time point t4) from the estimated time for reading data written to the non-volatile memory device 100.

[0107] According to an embodiment, in response to the status read command CMD_SR received at time t5, the non-volatile memory device 100 outputs a status information signal Status to the controller 200 at time t6, indicating whether the read operation of the memory cell array 130 has been completed. Specifically, the non-volatile memory device 100 outputs a READY status to the controller 200 at time t6, indicating that the read from the memory cell array 130 has been completed.

[0108] According to the embodiment, at time point t6, the controller 200 confirms that the read operation of the non-volatile memory device 100 has been completed, and at time point t7, the controller 200 issues a first read command CMD_O1 to receive the read data Data. Since the first read command CMD_O1 has been issued, the controller 200 begins to switch the read enable signal REB.

[0109] According to an embodiment, the non-volatile memory device 100 outputs read data Data to the controller 200 in response to a first read command CMD_O1. The non-volatile memory device 100 outputs the read data Data based on the rising and / or falling edge of the data strobe signal DQS, which is synchronized with the read enable signal REB. Since all necessary commands CMD have been issued, the level of the write enable signal WEB will not change until a new read or write operation is performed.

[0110] According to the embodiments, the operation of the storage device 10 has been described under the assumption that the status information signal Status indicates the busy state BUSY.

[0111] According to an embodiment, when the status information signal Status indicates the READY state, the operations described above at time points t4 and t5 can be skipped. For example, after issuing the status read command CMD_SR at time point t3, when it is confirmed that the status information signal Status received by the controller 200 indicates the READY state, the controller 200 issues the first read command CMD_O1 instead of the status read command CMD_SR.

[0112] Figure 8 This is a timing diagram illustrating the timing of signals and commands generated and issued in the second read mode according to an embodiment. The command latch enable signal CLE and the write enable signal WEB are omitted below from the above references. Figure 7 The given description. Furthermore, it is assumed that a read command CMD_R has been issued for a read operation on the memory cell array.

[0113] According to an embodiment, controller 200 issues and transmits a second read command CMD_O2 to non-volatile memory device 100. Controller 200 switches the level of the write enable signal to issue the second read command CMD_O2. The second read command CMD_O2 is issued at time t1 on the first rising edge of the write enable signal WEB.

[0114] According to an embodiment, after the second read command CMD_O2 has been issued, the controller 200 begins to switch the read enable signal REB.

[0115] According to an embodiment, the non-volatile memory device 100 starts at time t2 and outputs a data stream via the input / output pin DQ based on the rising and / or falling edges of the data strobe signal DQS synchronized with the read enable signal REB.

[0116] For example, according to an embodiment, the non-volatile memory device 100 may output a busy state (BUSY) status information signal (Status) in response to a second read command (CMD_O2). While the read operation of the memory cell array 130 is not yet complete, the non-volatile memory device 100 outputs additional information (INFO) (I0-I3) about the non-volatile memory device 100 and a status information signal (Status) indicating the busy state (BUSY) to the controller. For example, the additional information (INFO) may include power information about the non-volatile memory device 100 or the address of a faulty memory cell. Furthermore, the additional information (INFO) may include various information other than the written data indicating the status of the non-volatile memory device 100.

[0117] According to an embodiment, the controller 200 receives a status information signal, Status, indicating a busy state (BUSY), at time point t2, and subsequently receives additional information, INFO. After confirming the busy state (BUSY), the controller 200 reissues the second read command CMD_O2 at time point t3, after a total waiting time of a third time interval Tc. The second read command CMD_O2 is issued at time point t3 on the second rising edge of the write enable signal WEB. Here, the third time interval Tc is obtained by subtracting the time of the first issuance of the second read command CMD_O2 (i.e., time point t1) from the estimated time for reading data written to the non-volatile memory device 100.

[0118] According to an embodiment, since the second read command CMD_O2 has been reissued, the controller 200 starts switching the read enable signal REB again. In response to the second read command CMD_O2, the non-volatile memory device 100 outputs a status information signal Status and read data Data to the controller 200.

[0119] In one embodiment, the non-volatile memory device 100 outputs a status information signal, Status, indicating a READY state, and read data, Data, based on the rising and / or falling edge of a data strobe signal DQS synchronized with the read enable signal REB. The controller 200 confirms that the status information signal Status indicates a READY state and receives the data stream completely. In this embodiment, both the read data Data and the status information signal Status are included in the data stream, and the read data Data is transmitted on each edge of the data strobe signal DQS. The read data Data is output via a plurality of pins DQ included in the input / output interface 170 of the non-volatile memory device 100. Figure 8 Each of the data items D0-D4 shown is simultaneously transmitted to the controller 200 via multiple pins DQ.

[0120] Figure 9 This is a timing diagram illustrating the timing of signals and commands generated and issued in a second read mode according to another embodiment. (The above references are omitted below.) Figure 7 and Figure 8 The given description. Furthermore, it is assumed that a read command CMD_R has been issued for a read operation on the memory cell array. Execute as described in the above reference. Figure 8 The same operation is performed until time point t2.

[0121] Figure 9The operation of the storage device 10 in a second read mode according to an embodiment is illustrated. In the second read mode, the non-volatile memory device 100 generates a status information signal, but does not output the status information signal to the controller 200, and uses the status information signal to control internal signals. That is, the status information signal is an internal signal generated in the control logic 110 as a result of predicting whether the read operation of the non-volatile memory device 100 has been completed.

[0122] According to the embodiment, after the second read command CMD_O2 is issued at time t2, the controller 200 starts switching the read enable signal REB at time t3.

[0123] According to an embodiment of the present invention, the non-volatile memory device 100 generates read data Data in response to a second read command CMD_O2. The non-volatile memory device 100 acknowledges the busy state BUSY and delays switching the data strobe signal DQS for a fourth time interval Td. The controller 200 continues to switch the read enable signal REB regardless of the status information signal Status. Here, the fourth time interval Td is obtained by subtracting the time difference between issuing the second read command CMD_O2 (i.e., time point t2) and switching the read enable signal REB (i.e., time point t3) from the estimated time for reading data written to the non-volatile memory device 100.

[0124] According to an embodiment, after the delayed switching data strobe signal DQS reaches the fourth time interval Td, the non-volatile memory device 100 begins switching the data strobe signal DQS at time point t4. The controller 200 sequentially receives read data items Data (D0-D4).

[0125] Figure 10 A data stream generated by a non-volatile memory device according to an embodiment is shown. Reference is also made to… Figure 1 , Figure 3 and Figure 5 .

[0126] According to an embodiment, the data stream output from the non-volatile memory device 100 to the controller 200 via the input / output interface 170 includes a status information signal Status and read data Data.

[0127] According to an embodiment, the status information signal Status may include a READY state indicating that the operation of reading from the memory cell array 130 has been completed and a BUSY state indicating that the operation of reading from the memory cell array 130 has not yet been completed.

[0128] According to an embodiment, the status information signal Status is output to the controller 200 via at least one pin DQ of the input / output interface 170. The data size of the status information signal Status can be, but is not limited to, from one bit to several bytes.

[0129] According to an embodiment, data is read from memory cell array 130 and output via multiple pins DQ of input / output interface 170. The read data may include multiple datasets and may include signals output simultaneously via multiple pins DQ, for example.

[0130] According to an embodiment, the read data Data may include first to fifth datasets. The read data Data is output individually in units of at least one word to constitute a dataset. For example, each of the first to fifth datasets may be a signal simultaneously output via multiple data pins DQ.

[0131] According to the embodiment, the first data Data0 is additional information INFO in addition to the read data Data. For example, in the case of a busy state BUSY, the non-volatile memory device 100 generates additional information INFO including the address of a faulty memory cell or the power status of the non-volatile memory device 100, outputs a status information signal Status indicating the busy state BUSY to the controller 200, and simultaneously or subsequently outputs additional information to the controller 200.

[0132] Figure 11 and 12 A table is shown, according to an embodiment, in which signals and commands issued for each mode are categorized.

[0133] Figure 11 Table T1 is shown, in which commands issued for each mode are categorized.

[0134] refer to Figure 11 According to the embodiment, the controller 200 issues a read command CMD_R, a status read command CMD_SR, and a first read command CMD_O1 in the first read mode Mode1.

[0135] According to an embodiment, the controller 200 issues a read command CMD_R and a second read command CMD_O2 in the second mode Mode2.

[0136] In other words, according to the embodiment, the controller 200 issues a read command CMD_R, regardless of the read mode, to read data written to the memory cell array 130. Furthermore, the controller 200 generates a read enable signal REB to read the data.

[0137] Figure 12Table T2 is shown, which categorizes the signals and commands issued for each mode in more detail. (The above reference is omitted below.) Figures 1 to 11 The given description. Furthermore, it is assumed that a read command CMD_R has already been issued. Also referenced are... Figure 1 , Figure 5 and Figure 12 .

[0138] In the first read mode (Mode1), according to the embodiment, the status information signal (Status) has been acknowledged since the status read command (CMD_SR) was issued. When the status information signal (Status) indicates the busy state (BUSY), the status read command (CMD_SR) is reissued. Here, the read enable signal (REB) is in the off state (REB_off), i.e., not toggling. When the status information signal (Status) indicates the ready state (READY), the first read command (CMD_O1) is issued. Here, the read enable signal (REB) begins to toggle.

[0139] In the second read mode (Mode2), according to the embodiment, after the second read command CMD_O2 is issued, the status information signal Status has been confirmed, and the read enable signal REB begins to switch. When the status information signal Status indicates the busy state (BUSY), the second read command CMD_O2 is reissued. Here, the read enable signal REB stops switching. When the status information signal Status indicates the ready state (READY), no additional commands are issued, and the switching of the read enable signal REB remains unchanged.

[0140] Figure 13 This is a flowchart of a method for operating the controller according to an embodiment. Reference is also made to... Figure 1 , Figure 3 , Figure 5 and Figure 8 .

[0141] According to an embodiment, controller 200 receives a read request from the host. Controller 200 issues a read command CMD_R in response to the read request (S10).

[0142] The controller 200 waits for the estimated first time interval t1' (S20) for the complete reading and writing of data for the memory cell array 130.

[0143] The controller 200 issues a second read command CMD_O2, which allows the non-volatile memory device 100 to output both the status information signal Status and the read data Data (S30). When the second read command CMD_O2 is issued, the controller 200 begins to switch the read enable signal REB.

[0144] In response to the second read command CMD_O2, the controller 200 receives a status information signal Status from the non-volatile memory device 100 and confirms whether the received status information signal Status indicates a busy state (BUSY) or a ready state (READY) (S40). Additionally, additional information INFO or read data Data can be received from the non-volatile memory device 100 along with the status information signal Status.

[0145] When the confirmed status information signal Status indicates the busy state BUSY, the controller 200 stops switching the read enable signal REB (S50) and waits for the second time interval t2' (S60) corresponding to the time required to complete the read operation.

[0146] When the confirmed status information signal Status indicates READY, the controller 200 receives the read data Data and transmits the read data Data to the host (S70).

[0147] Figure 14 This is a detailed flowchart illustrating a method for operating a storage device, including a controller and a non-volatile memory device, according to an embodiment. Reference is also made to... Figure 1 , Figure 3 , Figure 5 , Figure 8 and Figure 13 And the references above are omitted below. Figure 1 , Figure 3 , Figure 5 , Figure 8 and Figure 13 The given description.

[0148] According to an embodiment, the controller 200 issues a read command CMD_R (S210) in response to a read request from the host (HOST), and the read command CMD_R is transmitted to the non-volatile memory device 100.

[0149] The controller 200 waits for an estimated first time interval t1' for the complete reading and writing of data for the memory cell array 130 (S220). The non-volatile memory device 100 obtains a read command CMD_R and decodes the address of the memory cell to be read according to the read command CMD_R (S110). The non-volatile memory device 100 selects a page address and outputs the data from the selected memory cell of the memory cell array (MCA) 130 to the page buffer 150 (S120). For example, operation S120 can be performed during the first time interval t1'.

[0150] After the first time interval t1', the controller 200 issues a second read command CMD_O2, which allows the non-volatile memory device 100 to output both the status information signal Status and the read data Data (S230), and the issued second read command CMD_O2 is transmitted to the non-volatile memory device 100.

[0151] In response to receiving the second read command CMD_O2, the non-volatile memory device 100 generates a data stream for transmitting the status information signal Status and the read data Data to the controller 200 via multiple pins DQ in the input / output interface 170 (S130).

[0152] When the second read command CMD_O2 is issued, the controller 200 starts to switch the read enable signal REB (S240) and confirm the status information signal Status (S250).

[0153] When the confirmed status information signal Status indicates the busy state BUSY, the controller 200 stops switching the read enable signal REB (S260), waits for the second time interval t2' corresponding to the time required to complete the read operation (S270), and reissues the second read command CMD_O2 after waiting for the second time interval t2' (to S230).

[0154] When the confirmed status information signal Status indicates the READY state, the controller 200 receives the read data Data and transmits the read data Data to the host (S280).

[0155] Figure 15 This is a block diagram of a storage device including a controller and a non-volatile memory device according to an embodiment.

[0156] refer to Figure 15 According to an embodiment, the SSD system 1000 includes a host 1100 and an SSD 1200. The SSD 1200 exchanges signals SIG with the host 1100 via a signal connector, and the host 1100 receives power PWR via a power connector. The SSD 1200 includes an SSD controller 1210, an auxiliary power supply 1220, and memory devices 1230, 1240, and 1250. Memory devices 1230-1, 1230-2, ..., and 1230-n are connected to the SSD controller 1210 via channels Ch1, Ch2, ..., and Chn, respectively.

[0157] According to an embodiment, the SSD controller 1210 can use the above reference. Figures 1 to 14The controllers 200, 200a, and 200b described herein are implemented. Specifically, the SSD controller 1210 receives commands (CMD) and various signals via the same input / output channel as the input / output channel used for data, and transmits the commands (CMD) to memory devices 1230, 1240, and 1250 synchronously with the write enable signal (WEB). For example, the SSD controller 1210 issues a second read command (CMD) to transmit both the status information signal (Status) and the read data (Data) of memory devices 1230, 1240, and 1250, and memory devices 1230, 1240, and 1250, in response to receiving the second read command (CMD), transmit both the status information signal (Status) and the read data (Data) to the SSD controller 1210.

[0158] According to the embodiments, memory devices 1230, 1240, and 1250 use the above reference. Figures 1 to 14 The non-volatile memory device 100 described herein is used for implementation. Specifically, each of memory devices 1230, 1240, and 1250 receives a command CMD from SSD controller 1210 via the same input / output channel used for data. For example, memory devices 1230, 1240, and 1250 receive a status information signal Status from their respective control logic circuitry and receive read data Data from their respective page buffers. In response to receiving a second read command CMD_O2 from SSD controller 1210, memory devices 1230, 1240, and 1250 transmit the status information signal Status and the read data Data to SSD controller 1210. Memory devices 1230, 1240, and 1250 transmit the status information signal Status to SSD controller 1210 before transmitting the read data Data.

[0159] While embodiments of the inventive concept have been specifically illustrated and described with reference to exemplary embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the appended claims.

Claims

1. A method of operating a storage device, the storage device comprising a non-volatile memory device and a controller for controlling the operation of the non-volatile memory device, the method comprising: The controller issues a first command to the non-volatile memory device; In response to the first command, the non-volatile memory device reads the first data from the memory cell array into the page buffer of the non-volatile memory device; The controller issues a second command to the non-volatile memory device; as well as In response to the second command, the non-volatile memory device outputs status information indicating whether the read operation according to the first command has been completed and second data obtained from the page buffer of the non-volatile memory device to the controller. Both the status information and the second data are sequentially sent to the controller via the same channel. The output also includes outputting third data during a busy state where the read operation of the memory cell array has not yet been completed, wherein the third data is data about the non-volatile memory device.

2. The method of claim 1, further comprising: When the received status information indicates that the read operation of the memory cell array has been completed and is ready, the controller continuously receives second data from the non-volatile memory device. as well as When the received status information indicates a busy state where the read operation of the memory cell array has not yet been completed, the controller stops receiving the second data from the non-volatile memory device.

3. The method of claim 2, further comprising the controller re-issuing the second command after waiting for a first time interval after stopping the reception of the second data.

4. The method of claim 1, further comprising: After the second command is issued, the controller switches the read enable signal provided to the non-volatile memory device; as well as After outputting the status information and the second data, when the received status information indicates a busy state in which the read operation has not yet been completed, the controller stops switching the read enable signal.

5. The method of claim 4, further comprising generating a data strobe signal synchronized with the read enable signal by the non-volatile memory device, and outputting second data synchronized with the rising edge and / or falling edge of the data strobe signal.

6. The method of claim 1, wherein, The third data is at least one of the faulty memory cell address or power status of the memory cell array.

7. The method of claim 1, wherein, The output also includes outputting the second data after outputting the status information.

8. The method of claim 1, wherein, When the controller is set to the second read mode, the controller issues the first command and the second command. When the controller is set to the first read mode, the controller issues the first command, the third command for outputting the status information, and the fourth command for transmitting the second data.

9. A storage device, comprising: Non-volatile memory devices; and The controller controls the non-volatile memory device and issues multiple commands. The non-volatile memory device includes: A memory cell array, comprising a plurality of memory cells, and reading first data in response to a first command; Control logic, which controls the read operation of the memory cell array based on the plurality of commands; A page buffer, which buffers the first data; and An input / output interface, in response to a second command, outputs to the controller status information indicating whether the read operation has been completed and second data obtained by buffering the first data. Both the status information and the second data are sequentially sent to the controller via the same channel. The output of the status information further includes outputting third data during a busy state in which the read operation of the memory cell array has not yet been completed, wherein the third data is data about the non-volatile memory device.

10. The storage device of claim 9, wherein, The non-volatile memory device outputs the status information and the second data synchronously with the data strobe signal, outputs the status information synchronously with the first edge of the data strobe signal, and outputs the first data synchronously with the second edge of the data strobe signal.

11. The storage device of claim 9, wherein, After issuing the first command, the controller waits for a first time interval before issuing the second command, and when the status information received from the non-volatile memory device indicates a busy state in which the read operation of the memory cell array has not yet been completed, the controller reissues the second command after waiting for a second time interval.

12. The storage device of claim 9, wherein, The controller outputs a read enable signal to the non-volatile memory device, begins to switch the read enable signal after issuing the second command, and stops switching the read enable signal when the received status information indicates a busy state in which the read operation has not yet been completed.

13. The storage device of claim 9, wherein, The input / output interface outputs the second data after outputting the status information.

14. A method of operating a storage device, the storage device comprising a non-volatile memory device and a controller for controlling the operation of the non-volatile memory device, the method comprising: The controller issues a first command to the non-volatile memory device, wherein the first command is to read first data from the non-volatile memory device; The non-volatile memory device reads the first data from the memory cell array in response to the first command; The controller issues a second command to the non-volatile memory device in the second read mode, wherein the second command is to read the first data from the non-volatile memory device; The second command includes a command for outputting the first data to the controller and status information indicating whether reading the first data from the non-volatile memory device has been completed. Wherein, the second command is issued at a predetermined time after the first command is issued; and In response to the second command, the non-volatile memory device transmits the first data to the controller. The transmission includes delaying the output of the first data for a first time interval while the first data has not yet been read from the memory cell array according to the first command in a busy state, and outputting status information indicating the busy state during the first time interval.

15. The method of claim 14, wherein, The delay also includes the non-volatile memory device completing the reading of the first data from the memory cell array within the first time interval after receiving the second command.

16. The method of claim 14, wherein, Issuing the second command includes, after issuing the second command, the controller switching the read enable signal for a second time interval. The read enable signal is synchronized with the data strobe signal that transmits the first data.

17. The method of claim 16, wherein, The delay also includes: Determine the busy state; and The data strobe signal is kept at a constant level, regardless of the read enable signal.

18. The method of claim 16, wherein, The non-volatile memory device outputs the first data at each rising edge and / or each falling edge of the data strobe signal.

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