Light-emitting display devices

Abstract

A light-emitting display device is provided, in which a pixel circuit detects and compensates for a threshold voltage of a driving transistor in each of a plurality of sub-pixels arranged in a matrix. The light-emitting display device includes: a threshold voltage estimation section that generates a threshold voltage estimation value by estimating the threshold voltage of the driving transistor by a data counting method; a reference voltage modification section that generates a reference voltage modification value by modifying a reference voltage for detecting the threshold voltage based on the threshold voltage estimation value; an image data voltage modification section that generates an image data voltage modification value by adding a data voltage corresponding to image data to the threshold voltage detection value; and a cumulative degradation calculation section that calculates cumulative degradation by accumulating degradation data of a function of the data voltage.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority from Japanese Patent Application No. 2019-225309 filed in the Japan Patent Office on December 13, 2019, the entire contents of which are incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0003] The present disclosure relates to a light emitting display device, and in particular to a light emitting display device including a driving transistor. Background Art

[0004] Recently, there is a demand for light-emitting display devices that stably display high-quality images.

[0005] In the light emitting display device of the related art, since the threshold voltage of the driving thin film transistor in the sub-pixel is shifted due to degradation, stable high-quality image display cannot be obtained.

[0006] As a result, an internal compensation pixel circuit has been proposed, which detects a threshold voltage of a driving transistor and compensates for a data voltage by adding the detected threshold voltage in a sub-pixel of a light emitting display device.

[0007] For example, in Japanese Patent Publication No. 2011-242767, a technology of applying a voltage to a reference voltage line and detecting a threshold voltage is disclosed.

[0008] In Korean Patent Publication No. 10-2014-0116702, an internal compensation pixel circuit is disclosed as another example.

[0009] However, in the internal compensation pixel circuit, when the threshold voltage shift of the driving transistor progresses, the current flowing through the driving transistor is insufficient in the initial detection state. As a result, the threshold voltage cannot be detected.

[0010] In US Pat. No. 9,349,317, a data counting method is disclosed in which a shift amount of a threshold voltage is estimated from accumulation of image data, and compensation is performed based on the estimated value.

[0011] However, the accuracy of the estimated value of the threshold voltage is lower than the accuracy of the detected value of the threshold voltage. Summary of the invention

[0012] Accordingly, embodiments of the present disclosure are directed to a display control device, a display device, and a method of controlling a display device that substantially obviate one or more of the problems due to limitations and disadvantages of the related art.

[0013] An object of the present disclosure is to provide a light emitting display device in which a threshold voltage is detected in an initial detection state of a driving transistor, and compensation is performed based on the detection value of the threshold voltage.

[0014] Additional features and aspects will be described in the following description, and in part will become apparent from the description, or may be learned by practicing the inventive concepts provided herein. Other features and aspects of the inventive concepts may be realized and obtained by structures specifically pointed out in the written description or derived therefrom, and in the claims and drawings thereof.

[0015] To achieve these and other aspects of the present inventive concept, as embodied and broadly described herein, a light-emitting display device, in which a pixel circuit detects and compensates for a threshold voltage of a driving transistor in each of a plurality of sub-pixels arranged in a matrix, includes: a threshold voltage estimating section, which generates a threshold voltage estimation value by estimating the threshold voltage of the driving transistor by a data counting method; a reference voltage modifying section, which generates a reference voltage modification value by modifying a reference voltage used to detect the threshold voltage based on the threshold voltage estimation value; an image data voltage modifying section, which generates an image data voltage modification value by adding a data voltage corresponding to image data to the threshold voltage detection value; and a cumulative degradation calculating section, which calculates cumulative degradation by accumulating degradation data of a function of the data voltage.

[0016] In another aspect, a light-emitting display device includes: a plurality of sub-pixels arranged in a matrix, each of the plurality of sub-pixels including a voltage-compensated pixel circuit having a driving transistor and a light-emitting element that emits light due to control of the voltage-compensated pixel circuit, the voltage-compensated pixel circuit detecting a threshold voltage of the driving transistor as a threshold voltage detection value and compensating for the threshold voltage of the driving transistor; a timing controller, the timing controller supplies a control signal to a data driving circuit and a gate driving circuit connected to the plurality of sub-pixels based on a timing synchronization signal and a data current; and a storage unit, the storage unit memorizing one of degradation data of each of the plurality of sub-pixels and average degradation data of the plurality of sub-pixels, wherein the timing controller modifies a reference voltage using a threshold voltage estimation value of an offset of the threshold voltage obtained by a data counting method, and modifies an image data voltage using the threshold voltage detection value.

[0017] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the inventive concepts as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this application, illustrate embodiments of the present disclosure and together with the description serve to explain various principles. In the drawings:

[0019] Figure 1 is a view showing a light emitting display device according to a first embodiment of the present disclosure;

[0020] Figure 2 is a view showing a timing controller, a storage part, and a sub-pixel of a light emitting display device according to a first embodiment of the present disclosure;

[0021] Figure 3 is a pixel circuit diagram showing a sub-pixel of a light-emitting display device according to a first embodiment of the present disclosure;

[0022] Figure 4 is a timing chart showing signals of a pixel circuit of a light emitting display device according to a first embodiment of the present disclosure;

[0023] Figure 5 is a pixel circuit diagram showing a sub-pixel of a light-emitting display device according to a second embodiment of the present disclosure;

[0024] Figure 6 is a timing chart showing signals of a pixel circuit of a light emitting display device according to a second embodiment of the present disclosure;

[0025] Fig. 7A is a diagram showing a sense voltage with respect to time in a case where a reference voltage is a sum of a threshold voltage and 1V (Vref=Vth+1V) according to a first embodiment of the present disclosure;

[0026] Figure 7B is a diagram showing a sense voltage with respect to time in a case where a reference voltage is a sum of a threshold voltage and 3V (Vref=Vth+3V) according to a first embodiment of the present disclosure;

[0027] Fig. 8A is a diagram showing a sense voltage relative to a threshold voltage in a case where a reference voltage is a sum of a threshold voltage and 1V (Vref=Vth+1V) according to a first embodiment of the present disclosure;

[0028] Figure 8B is a diagram showing a sense voltage relative to a threshold voltage in a case where a reference voltage is a sum of a threshold voltage and 3V (Vref=Vth+3V) according to a first embodiment of the present disclosure;

[0029] Fig.9Ais a diagram showing a sensed voltage with respect to time in a case where a reference voltage is 3 V (Vref=3 V) according to a comparative example;

[0030] Fig. 9B is a diagram showing a sense voltage with respect to time in a case where a reference voltage is 5 V (Vref=5 V) according to a comparative example;

[0031] Fig. 10A is a diagram showing a sense voltage relative to a threshold voltage in a case where a reference voltage is 3 V (Vref=3 V) according to a comparative example;

[0032] Fig. 10B is a diagram showing a sense voltage relative to a threshold voltage in a case where a reference voltage is 5 V (Vref=5 V) according to a comparative example;

[0033] Fig.11 is a view showing a timing controller, a storage part, and a sub-pixel of a light emitting display device according to a third embodiment of the present disclosure; and

[0034] Fig.12 2 is a view showing a timing controller, a memory part, and sub-pixels of a light emitting display device according to a fourth embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] Reference will now be made in detail to embodiments of the present disclosure, examples of which may be illustrated in the accompanying drawings. In the following description, when it is determined that a detailed description of a known function or configuration associated with this document unnecessarily obscures the main points of the present invention, its detailed description will be omitted. The progress of the described processing steps and / or operations is an example; however, the order of the steps and / or operations is not limited to the order set forth herein, and may be changed in a manner known in the art, except for the steps and / or operations that must occur in a specific order. Throughout the text, the same reference numerals represent the same elements. The names of the various elements used in the following description are selected only for the convenience of writing the specification, and therefore may be different from the names used in the actual product.

[0036] The advantages and features of the present disclosure and methods for implementing the same will be explained by the following example embodiments described with reference to the accompanying drawings. However, the present disclosure may be embodied in different forms and should not be construed as being limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that the present disclosure may be sufficiently thorough and complete to help those skilled in the art fully understand the scope of the present disclosure. In addition, the present disclosure is limited only by the scope of the claims.

[0037] Reference will now be made in detail to the present disclosure, examples of which are illustrated in the accompanying drawings.

[0038] Figure 1 is a view showing a light emitting display device according to a first embodiment of the present disclosure.

[0039] exist Figure 1 In the embodiment, the light emitting display device 100 includes a timing controller 110, a data driving circuit 120, a gate driving circuit 130, a storage part 140, and a plurality of sub-pixels 200 arranged in a matrix.

[0040] The timing controller 110 outputs a control signal to the data driving circuit 120 and the gate driving circuit 130 based on the timing synchronization signal TSS and the data current Idata.

[0041] The timing synchronization signal TSS includes a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a clock signal, and the like.

[0042] The data driving circuit 120 outputs signals to the first to n-th data signal lines D1 to Dn and the first to n-th merged signal lines MS1 to MSn based on the control signal from the timing controller 110, supplies the initial voltage Vini to the first to n-th initial voltage lines Ini1 to Inin, and supplies the reference voltage Vref to the reference voltage line Ref. Here, n is a natural number.

[0043] The gate driving circuit 130 outputs signals to the high level voltage line Vdd, the first scanning signal line (gate signal line) SS1 to the m-th scanning signal line (gate signal line) SSm, and the first reset signal line RS1 to the m-th reset signal line RSm based on the control signal from the timing controller 110. Here, m is a natural number.

[0044] The storage part 140 memorizes average degradation data of at least one sub-pixel 200 or all sub-pixels 200 in the panel.

[0045] A plurality of sub-pixels 200 defined by first data signal lines D1 to nth data signal lines Dn, first merge signal lines MS1 to nth merge signal lines MSn, first initial voltage lines Ini1 to nth initial voltage lines Inin, reference voltage lines Ref, reference voltage lines Ref, high-level voltage lines Vdd, first scan signal lines SS1 to mth scan signal lines SSm, and first reset signal lines RS1 to mth reset signal lines RSm are arranged in a matrix.

[0046] Each of the plurality of sub-pixels 200 includes a light emitting element 220 and a pixel circuit for causing the light emitting element 220 to emit light.

[0047] The light emitting element 220 emits light according to a current from the power line Vdd of a high level voltage to the power line Vss of a low level voltage through a driving transistor in a pixel circuit.

[0048] Figure 2 is a view showing a timing controller, a memory part, and sub-pixels of a light emitting display device according to a first embodiment of the present disclosure.

[0049] exist Figure 2 In the embodiment, the timing controller 110 includes a sub-pixel reference voltage modifying section 111 , a sub-pixel threshold voltage estimating section 112 , an image data voltage modifying section 113 and a sub-pixel cumulative degradation calculating section 114 .

[0050] The sub-pixel reference voltage modification section 111 modifies the reference voltage Vref by adding the reference voltage Vref in each sub-pixel 200 to the threshold voltage estimation value Vthe of the driving transistor.

[0051] The sub-pixel threshold voltage estimation section 112 generates a threshold voltage estimation value Vthe by estimating the threshold voltage of the driving transistor in each sub-pixel 200 .

[0052] The sub-pixel threshold voltage estimation section 112 estimates the amount of shift in the threshold voltage in a degraded state based on the sub-pixel degradation data from the storage section 140 , and generates a threshold voltage estimation value Vthe based on the amount of shift in the threshold voltage.

[0053] The image data voltage modification section 113 modifies the image data voltage by adding a data voltage Vdata based on the image data to a threshold voltage detection value Vthd.

[0054] The sub-pixel cumulative degradation calculation section 114 calculates the cumulative degradation of the sub-pixel by adding the sub-pixel degradation data in each sub-pixel 200 to a function f(Vdata) of the data voltage Vdata.

[0055] The storage section 140 includes a sub-pixel degradation data storage section 141 .

[0056] The sub-pixel degradation data storage section 141 memorizes degradation data for each sub-pixel 200 .

[0057] The sub-pixel 200 includes a voltage compensation pixel circuit 210 having a driving transistor and a light emitting element 220 .

[0058] The voltage compensation pixel circuit 210 includes a threshold voltage detection section 211 and a threshold voltage compensation section 212 .

[0059] The threshold voltage detection section 211 generates a threshold voltage detection value Vthd by detecting the threshold voltage of the driving transistor in each sub-pixel 200 .

[0060] The threshold voltage compensating part 212 compensates the data voltage Vdata by adding the data voltage Vdata to the threshold voltage detection value Vthd in each sub-pixel 200 .

[0061] The light emitting element 220 includes an anode connected to the driving transistor in each sub-pixel 200 , a cathode connected to the low-level voltage line Vss, and a light emitting layer between the anode and the cathode.

[0062] The light emitting layer includes an electron injection layer, an electron transport layer, a light emitting material layer, a hole transport layer and a hole injection layer which are sequentially stacked between the cathode and the anode.

[0063] When a forward bias is applied between the anode and the cathode, electrons from the cathode are supplied to the light emitting material layer through the electron injection layer and the electron transport layer, and holes from the anode are supplied to the light emitting material layer through the hole injection layer and the hole transport layer.

[0064] The fluorescent material or phosphorescent material of the light emitting material layer emits light with a brightness proportional to the current density through recombination of electrons and holes.

[0065] When a reverse bias is applied, the light emitting element 220 functions as a capacitor storing electric charge.

[0066] Figure 3 is a pixel circuit diagram showing a sub-pixel of a light emitting display device according to a first embodiment of the present disclosure.

[0067] exist Figure 3 , the sub-pixel 200 includes first to sixth transistors 301 , 302 , 303 , 304 , 305 and 306 of negative (N) type thin film transistors (TFTs), a first capacitor 307 and a second capacitor 308 , and a light emitting element 309 .

[0068] The first transistor 301 is a reference TFT, the second transistor 302 is a data TFT, the third transistor 303 is a driving TFT, the fourth transistor 304 is a merged TFT, and the fifth transistor 305 and the sixth transistor 306 are reset TFTs.

[0069] The first capacitor 307 is a storage capacitor.

[0070] The light emitting element 309 and Figure 2 Corresponding to the light emitting element 220.

[0071] The subpixel 200 includes a reference voltage line Ref, an nth data signal line Dn, an mth scan signal line SSm, an nth merge signal line MSn, an mth reset signal line RSm, a high level voltage line Vdd, a low level voltage line Vss, and an nth initial voltage line Inin.

[0072] The m-th reset signal line RSm may be replaced by the (m-1)-th scan signal line SSm-1.

[0073] During the initialization period, the fifth transistor 305 and the sixth transistor 306 may be switched (turned on and off) according to a signal of the (m-1)th scan signal line SSm-1.

[0074] The nth merge signal line MSn supplies a signal having an opposite polarity to the signal of the mth scan signal line SSm.

[0075] A high level voltage line Vdd supplying a high level voltage, a low level voltage line Vss supplying a low level voltage less than the high level voltage, and a reference voltage line Ref supplying a reference voltage less than the high level voltage and greater than the low level voltage have fixed potentials.

[0076] The reference voltage line Ref may be replaced by a low-level voltage line Vss.

[0077] The nth initial voltage line Inin may be replaced by the (n-1)th merged signal line MSn-1.

[0078] During the initialization period, the gate-off voltage Voff may be supplied through the (n-1)th merge signal line MSn-1.

[0079] The voltage of the nth initial voltage line Inin is lower than the voltage of the low level voltage line Vss.

[0080] The sub-pixel 200 includes a first node N1, a second node N2, and a third node N3.

[0081] The first node N1 is connected to the first of the source and the drain of the first transistor 301, the gate of the third transistor 303, one of the source and the drain of the fourth transistor 304, and one of the source and the drain of the fifth transistor 305.

[0082] The second node N2 is connected to a second one of the source and the drain of the second transistor 302 , a second one of the source and the drain of the fourth transistor 304 , and a first electrode of the first capacitor 307 .

[0083] The third node N3 is connected to the first of the source and the drain of the third transistor 303, the second of the source and the drain of the fifth transistor 305, the first of the source and the drain of the sixth transistor 306, the second electrode of the first capacitor 307, the first electrode of the second capacitor 308 and the first electrode of the light-emitting element 309.

[0084] A gate of the first transistor 301 is connected to the mth scan signal line SSm, a first one of a source and a drain of the first transistor 301 is connected to the first node N1, and a second one of a source and a drain of the first transistor 301 is connected to the reference voltage line Ref.

[0085] During the programming period, the first transistor 301 supplies the reference voltage modification value Vref+Vthe to the first node N1 according to the signal of the mth scan signal line SSm.

[0086] The reference voltage modification value Vref+Vthe is obtained by the sub-pixel reference voltage modification section 111 .

[0087] A gate of the second transistor 302 is connected to the mth scan signal line SSm, a first one of a source and a drain of the second transistor 302 is connected to the nth data signal line Dn, and a second one of a source and a drain of the second transistor 302 is connected to the second node N2.

[0088] During the programming period, the second transistor 302 supplies the data voltage modification value Vdata+Vthd to the second node N2 according to the signal of the mth scan signal line SSm.

[0089] The data voltage modification value Vdata+Vthd is obtained by the image data voltage modification unit 113 .

[0090] A gate of the third transistor 303 is connected to the first node N1, a first one of a source and a drain of the third transistor 303 is connected to the third node, and a second one of a source and a drain of the third transistor 303 is connected to the high level voltage line Vdd.

[0091] The third transistor 303 adjusts the current supplied from the high level voltage line Vdd to the light emitting element 309 through the third node N3 according to the voltage supplied to the first node N1, and drives the light emitting element 309.

[0092] A gate of the fourth transistor 304 is connected to the nth merge signal line MSn, a first one of a source and a drain of the fourth transistor 304 is connected to the first node N1, and a second one of a source and a drain of the fourth transistor 304 is connected to the second node N2.

[0093] During the initialization period and the light emitting period, the fourth transistor 304 connects the first node N1 and the second node N2 according to the signal of the nth merge signal line MSn.

[0094] A gate of the fifth transistor 305 is connected to the mth reset signal line RSm, a first one of a source and a drain of the fifth transistor 305 is connected to the first node N1, and a second one of a source and a drain of the fifth transistor 305 is connected to the third node N3.

[0095] A gate of the sixth transistor 306 is connected to the mth reset signal line RSm, a first one of a source and a drain of the sixth transistor 306 is connected to the third node N3, and a second one of a source and a drain of the sixth transistor 306 is connected to the nth initial voltage line Inin.

[0096] During the initialization period, the fifth transistor 305 and the sixth transistor 306 adjust each of the first node N1, the second node N2, and the third node N3 to have a voltage of the nth initial voltage line Inin according to a signal of the mth reset signal line RSm.

[0097] A first electrode of the first capacitor 307 is connected to the second node N2 , and a second electrode of the first capacitor 307 is connected to the third node N3 .

[0098] A first electrode of the second capacitor 308 and an anode of the light emitting element 309 are connected to the third node, and a second electrode of the second capacitor 308 and a cathode of the light emitting element 309 are connected to the low-level voltage line Vss.

[0099] The second capacitor 308 indicates that the light emitting element 309 functions as a capacitor when a reverse bias is applied.

[0100] Figure 4 : is a timing chart showing signals of a pixel circuit of the light emitting display device according to the first embodiment of the present disclosure.

[0101] exist Figure 4 In the embodiment, the pixel circuit is sequentially driven during the initialization period, the programming period and the light emitting period.

[0102] During the initialization period, each of the first node N1 , the second node N2 , and the third node N3 has an initial voltage Vini due to active driving of the fourth transistor 304 , the fifth transistor 305 , and the sixth transistor 306 .

[0103] During the programming period, due to active driving of the first transistor 301 , the second transistor 302 , and the third transistor 303 , the threshold voltage of the third transistor 303 is detected and a voltage corresponding to the data voltage compensation value Vdata+Vthd is stored to the first capacitor 307 .

[0104] During the light emission period, due to active driving of the third transistor 303 and the fourth transistor 304 , the light emitting element 309 emits light according to the voltage supplied from the first capacitor 307 through the third transistor 303 .

[0105] <Initialization period>

[0106] The gate-on voltage Von of the reset signal is supplied to the mth reset signal line RSm, the gate-on voltage Von of the merge signal is supplied to the nth merge signal line MSn, and the gate-off voltage Voff of the scan signal is supplied to the mth scan signal line SSm.

[0107] As a result, the fourth transistor 304, the fifth transistor 305, and the sixth transistor 306 have an on state according to the gate-on voltage Von.

[0108] The first transistor 301 and the second transistor 302 have a turned-off state according to the gate-off voltage Voff, and the third transistor 303 has a turned-off state according to the voltage of the nth initial voltage line Inin supplied to the first node N1.

[0109] As a result, the voltage of the nth initial voltage line Inin is supplied to the first node N1, the second node N2 and the third node N3 through the fourth transistor 304, the fifth transistor 305 and the sixth transistor 306 in the on state, and the first node N1, the second node N2 and the third node N3 are initialized to have the voltage of the nth initial voltage line Inin.

[0110] A voltage lower than the voltage of the low-level voltage line Vss is supplied as the voltage of the nth initial voltage line Inin.

[0111] For example, when the (n-1)th merge signal line MSn-1 is used as the initial voltage line Inin, the gate-off voltage Voff of the (n-1)th merge signal line MSn-1 may be supplied as the voltage of the nth initial voltage line Inin.

[0112] As a result, a voltage of the nth initial voltage line Inin less than the voltage of the low level voltage line Vss is supplied to the third node N3 , the light emitting element 309 does not emit light due to reverse bias, and charges are accumulated in the second capacitor 308 and the light emitting element 309 .

[0113] During the initialization period, the (m-1)th scan signal line SSm-1 supplying the gate-on voltage Von may be used as the mth reset signal line RSm.

[0114] The effective period of the reset signal of the mth reset signal line RSm, in which the gate-on voltage Von is supplied to the mth reset signal line RSm to prevent the light emitting element 309 from emitting light, is determined as a relatively short time interval in the initialization period in which the initial voltage is in a low state.

[0115] The effective period of the scanning signal of the (m-1)th scanning signal line SSm-1 (during the effective period, the gate-on voltage Von is supplied to the (m-1)th scanning signal line SSm-1) is determined during the invalid period of the merge signal of the (n-1)th merge signal line MSn-1 (during the invalid period, the gate-off voltage Voff is supplied to the (n-1)th merge signal line MSn-1), so that the effective period of the scanning signal of the (m-1)th scanning signal line SSm-1 is shorter than the invalid period of the merge signal of the (n-1)th merge signal line MSn-1.

[0116] <Programming Period>

[0117] During the programming period, since the first transistor 301 , the second transistor 302 , and the third transistor 303 have an on state and the light emitting element 309 functions as the second capacitor 308 , the threshold voltage of the third transistor 303 is detected.

[0118] At the same time, a voltage corresponding to the data voltage compensation value Vdata+Vthd is stored in the first capacitor 307 .

[0119] The gate-on voltage Von of the scan signal is supplied to the mth scan signal line SSm, the gate-off voltage Voff of the merge signal is supplied to the nth merge signal line MSn, and the gate-off voltage Voff of the reset signal is supplied to the mth reset signal line RSm.

[0120] As a result, the first transistor and the second transistor have a turned-on state according to the gate-on voltage Von, the third transistor 303 has a turned-on state according to the reference voltage modification value Vref+Vthe supplied to the first node N1 until the source-drain current is sufficiently reduced, and the fourth transistor 304, the fifth transistor 305 and the sixth transistor 306 have a turned-off state according to the gate-off voltage Voff.

[0121] When the data voltage modification value Vdata+Vthd is supplied by the second transistor 302 in the on state, the voltage of the second node N2 changes from the gate-off voltage Voff of the nth initial voltage line Inin to the data voltage modification value Vdata+Vthd, and the voltage of the third node N3 also changes in proportion to the voltage change of the second node N2.

[0122] Here, since the voltage of the third node N3 is lower than the low level voltage of the low level voltage line Vss, the light emitting element 309 functions as the second capacitor 308 due to application of the reverse bias.

[0123] Charge is accumulated in the light-emitting element 309 serving as the second capacitor 308 through the third transistor 303 until the potential of the third node N3 becomes a voltage obtained by subtracting the threshold voltage of the third transistor 303 from the voltage Vref of the reference voltage line, that is, until the source-drain current Ids of the third transistor 303 is sufficiently reduced.

[0124] As a result, a voltage obtained by subtracting the threshold voltage, ie, the threshold voltage of the third transistor 303 from the reference voltage may be detected at the third node N3.

[0125] Specifically, since the threshold voltage is detected using the light emitting element 309 as the second capacitor 308, even a negative threshold voltage can be accurately detected.

[0126] Therefore, since the first capacitor 307 stores the difference between the data voltage Vdata supplied through the second transistor 302 in the on state and the voltage applied to the third node N3, the first capacitor 307 remembers the voltage corresponding to the data voltage compensation value.

[0127] The effective period of the scan signal supplied to the m-th scan signal line SSm is determined to be shorter than the ineffective period of the merge signal of the n-th merge signal line MSn.

[0128] During the programming period, the scan signal supplied to the (m-1)th scan signal line SSm-1 may be used as a reset signal of the mth reset signal line RSm.

[0129] <Luminous period>

[0130] During the light emission period, the fourth transistor 304 has an on state, and the light emitting element 309 emits light according to the voltage of the first capacitor 307 through the third transistor 303 .

[0131] The gate-on voltage Von of the merge signal is supplied to the nth merge signal line MSn, the gate-off voltage of the reset signal is supplied to the mth reset signal line RSm, and the gate-off voltage of the scan signal is supplied to the mth scan signal line SSm.

[0132] As a result, the fourth transistor 304 has a turned-on state according to the gate-on voltage Von, so that the first node N1 and the second node N2 are connected to each other, and the first transistor 301, the second transistor 302, the fifth transistor 305 and the sixth transistor 306 have a turned-off state according to the gate-off voltage Voff.

[0133] The third transistor 303 adjusts the output current Ids supplied from the high level voltage line Vdd to the light emitting element 309 according to the voltage of the first capacitor 307 supplied to the first node N1 through the fourth transistor 304, so that the light emitting element 309 emits light.

[0134] The light emitting element 309 emits light with a brightness proportional to the current density of the output current Ids of the third transistor 303 .

[0135] Although the pixel circuit includes an N-type TFT in the first embodiment, the present disclosure is not limited thereto, and the pixel circuit may include a positive-type TFT in another embodiment.

[0136] Figure 5 is a pixel circuit diagram showing a sub-pixel of a light emitting display device according to a second embodiment of the present disclosure.

[0137] exist Figure 5 , the sub-pixel 200 includes first to fourth transistors 401 , 402 , 403 , and 404 of positive (P) type TFTs, a first capacitor 405 and a second capacitor 406 , and a light emitting element 407 .

[0138] The third transistor 403 is a driving TFT.

[0139] The light emitting element 407 and Figure 2 Corresponding to the light emitting element 220.

[0140] The sub-pixel 200 includes an nth data signal line Dn, an mth scanning signal line SSm, and a replacement Figure 3 The nth emission signal line EMn, the high level voltage line Vdd, the low level voltage line Vss and the initial voltage line Inin are configured according to the nth merge signal line MSn.

[0141] The sub-pixel 200 includes a first node N1, a second node N2, and a third node N3.

[0142] The first node N1 is connected to a first one of a source and a drain of the first transistor 401 , a first one of a source and a drain of the second transistor 402 , a gate of the third transistor 403 , and a first electrode of the second capacitor 406 .

[0143] The second node N2 is connected to a second one of the source and the drain of the second transistor 402 , a first one of the source and the drain of the third transistor 403 , and an anode of the light emitting element 407 .

[0144] The third node N3 is connected to the first electrode of the first capacitor 405 , the second electrode of the second capacitor 406 , the second of the source and the drain of the third transistor 403 , and the first of the source and the drain of the fourth transistor 404 .

[0145] A gate of the first transistor 401 is connected to the mth scan signal line SSm, a first one of a source and a drain of the first transistor 401 is connected to the first node, and a second one of a source and a drain of the first transistor 401 is connected to the nth data signal line Dn.

[0146] The first transistor 401 has a turned-on state according to the scan signal of the mth scan signal line SSm to connect the nth data signal line Dn to the first node N1.

[0147] A gate of the second transistor 402 is connected to the nth initial voltage line Inin, a first one of a source and a drain of the second transistor 402 is connected to the first node N1, and a second one of a source and a drain of the second transistor 402 is connected to the second node N2.

[0148] The second transistor 402 has a turned-on state according to the initial signal of the nth initial signal line Inin to connect the first node N1 with the second node N2.

[0149] A gate of the third transistor 403 is connected to the first node N1, a first one of a source and a drain of the third transistor 403 is connected to the second node N2, and a second one of a source and a drain of the third transistor 403 is connected to the high level voltage line Vdd.

[0150] A first electrode of the first capacitor 405 is connected to the third node N3 , and a second electrode of the first capacitor 405 is connected to the high-level voltage line Vdd.

[0151] The first capacitor 405 may stabilize the voltage of the third node N3 .

[0152] A first electrode of the second capacitor 406 is connected to the first node N1 , and a second electrode of the second capacitor 406 is connected to the third node N3 .

[0153] An anode of the light emitting element 407 is connected to the second node N2, and a cathode of the light emitting element 407 is connected to the low-level voltage line Vss.

[0154] Figure 6 : is a timing chart showing signals of a pixel circuit of a light emitting display device according to a second embodiment of the present disclosure.

[0155] exist Figure 6 In the embodiment, the pixel circuits are sequentially driven during the initialization and sampling period, the writing period, and the light emitting period.

[0156] <Initialization and sampling period>

[0157] During the initialization and sampling period, the reference voltage modification value Vref+Vthe of a high level voltage is supplied to the nth data signal line Dn, the gate low voltage VGL of a low level voltage is supplied to the mth scan signal line SSm, the gate low voltage VGL of a low level voltage is supplied to the nth initial voltage line Inin, and the gate high voltage VGH of a high level voltage is supplied to the nth emission signal line EMn.

[0158] As a result, the first transistor 401 and the second transistor 402 have an on state, and the fourth transistor 404 has an off state.

[0159] Since the reference voltage modification value Vref+Vthe is supplied to the first node N1 and the second node N2 through the first transistor 401 and the second transistor 402 in the on state, the first node N1 and the second node N2 are initialized to have the reference voltage modification value Vref+Vthe.

[0160] When the voltage of the third node N3 becomes the reference voltage modification value Vref+Vthe, the third transistor 403 has a turned-off state, and the discharge of the third node N3 stops.

[0161] The voltage of the third node N3 is stored in the first capacitor 405 and the second capacitor 406 .

[0162] <Write Period>

[0163] During the writing period, the data voltage modification value Vdata+Vthd of a low level voltage is supplied to the nth data signal line Dn, the gate low voltage VGL of a low level voltage is supplied to the mth scanning signal line SSm, the gate high voltage VGH of a high level voltage is supplied to the nth initial voltage line Inin, and the gate high voltage VGH of a high level voltage is supplied to the nth emission signal line EMn.

[0164] As a result, the first transistor 401 has an on state, and the second transistor 402, the third transistor 403, and the fourth transistor 404 have an off state.

[0165] Since the data voltage modification value Vdata+Vthd is supplied to the first node N1 through the first transistor 401 in the on state, the voltage of the first node N1 becomes the data voltage modification value Vdata+Vthd.

[0166] <Luminous period>

[0167] During the light-emitting period, a reference voltage modification value Vref+Vthe of a high level voltage is supplied to the nth data signal line Dn, a gate high voltage VGH of a high level voltage is supplied to the mth scanning signal line SSm, a gate high voltage VGH of a high level voltage is supplied to the nth initial voltage line Inin, and a gate low voltage VGL of a low level voltage is supplied to the nth light-emitting signal line EMn.

[0168] As a result, the first transistor 401 and the second transistor 402 have an off state, and the fourth transistor 404 has an on state, so that the light emitting element 407 emits light.

[0169] Since the gate of the third transistor 403 connected to the first node N1 has the data voltage modification value Vdata+Vthd of the low level voltage, the third transistor 403 has a turned-on state and the voltage of the high level voltage line Vdd is supplied to the third node N3.

[0170] Simulation results of the pixel circuits of the first embodiment and the comparative example are shown below. The pixel circuit of the first embodiment uses the reference voltage modification value as the reference voltage and the data voltage modification value as the data voltage, and the pixel circuit of the comparative example uses the original reference voltage and the original data voltage.

[0171] In the simulation, the driving transistor has a threshold voltage Vth.

[0172] Fig. 7A is a diagram showing a sensed voltage with respect to time in a case where a reference voltage is a sum of a threshold voltage and 1V (Vref=Vth+1V) according to a first embodiment of the present disclosure. Fig. 7A In FIG. 1 , since the sensing voltages are the same as each other regardless of the threshold voltage Vth, the lines for sensing the voltages overlap each other.

[0173] Figure 7B is a diagram showing a sensed voltage with respect to time in a case where the reference voltage is the sum of the threshold voltage and 3V (Vref=Vth+3V) according to the first embodiment of the present disclosure. Figure 7B In FIG. 1 , since the sensing voltages are the same as each other regardless of the threshold voltage Vth, the lines for sensing the voltages overlap each other.

[0174] Fig. 8A is a view showing a sense voltage with respect to a threshold voltage in a case where a reference voltage is a sum of a threshold voltage and 1V (Vref=Vth+1V) according to the first embodiment of the present disclosure.

[0175] Figure 8Bis a view showing a sense voltage with respect to a threshold voltage in a case where a reference voltage is a sum of the threshold voltage and 3V (Vref=Vth+3V) according to the first embodiment of the present disclosure.

[0176] Fig.9A is a graph showing a sense voltage with respect to time in a case where a reference voltage is 3 V (Vref=3 V) according to a comparative example.

[0177] Fig. 9B is a graph showing a sense voltage with respect to time in a case where a reference voltage is 5 V (Vref=5 V) according to a comparative example.

[0178] Fig. 10A is a diagram showing a sense voltage with respect to a threshold voltage in a case where a reference voltage is 3 V (Vref=3 V) according to a comparative example.

[0179] Fig. 10B is a diagram showing a sense voltage with respect to a threshold voltage in a case where a reference voltage is 5 V (Vref=5 V) according to a comparative example.

[0180] exist Fig. 8A and Fig. 10A In the comparative example, the driving transistor does not have a conductive state when Vth>5V, whereas the driving transistor has a conductive state when Vth≥5V in the first embodiment.

[0181] exist Figure 8B and Fig. 10B In the comparative example, the light emitting element emits light when Vth<1V, but the light emitting element does not emit light when Vth<1V in the first embodiment.

[0182] As a result, voltage compensation is appropriately performed, and a light-emitting display device with stable high-quality display is obtained.

[0183] Since the reference voltage modification value of the sum of the reference voltage and the threshold voltage estimation value of the driving transistor is used as the updated reference voltage, the threshold voltage in the detection initial state is detected. Since the data voltage modification value of the sum of the data voltage and the threshold voltage detection value of the driving transistor is used as the updated data voltage, the threshold voltage detection value is compensated.

[0184] Therefore, appropriate voltage compensation is obtained, and a light-emitting display device with stable high quality is obtained.

[0185] Although the threshold voltage estimation is performed by a data counting method based on degradation of each sub-pixel in the first embodiment, the present disclosure is not limited thereto, and the threshold voltage estimation may be performed based on degradation of the entire panel in another embodiment.

[0186] Fig.11 is a view showing a timing controller, a memory part, and sub-pixels of a light emitting display device according to a third embodiment of the present disclosure.

[0187] exist Fig.11 In the embodiment, the timing controller 110a includes a Figure 2 The panel average threshold voltage estimation unit 112a of the sub-pixel threshold voltage estimation unit 112 and the panel average threshold voltage estimation unit 112a of the sub-pixel threshold voltage estimation unit 112 are replaced by Figure 2 The panel cumulative degradation calculation unit 114 a of the sub-pixel cumulative degradation calculation unit 114 .

[0188] The storage unit 140a includes a Figure 2 The sub-pixel degradation data storage section 141 includes the panel average degradation data storage section 141 a.

[0189] The panel average threshold voltage estimation section 112 a generates a threshold voltage estimation value Vthe by estimating the average value of the threshold voltages of the driving transistors in the entire panel.

[0190] The panel cumulative degradation calculation section 114 a calculates the average cumulative degradation of the entire panel by adding the degradation data in the entire panel to the function f(Vdata) of the data voltage Vdata.

[0191] The panel average degradation data storage unit 141 a stores degradation data of the entire panel.

[0192] Therefore, a light emitting display device with stable high quality is obtained by detecting degradation of the entire panel instead of detecting degradation of each sub-pixel and appropriate voltage compensation is obtained.

[0193] Although threshold voltage estimation is performed based on degradation of the entire panel and threshold voltage detection and data writing are performed simultaneously in the third embodiment, the present disclosure is not limited thereto, and threshold voltage detection and data writing may be performed at different timings in another embodiment.

[0194] Fig.12 2 is a view showing a timing controller, a memory part, and sub-pixels of a light emitting display device according to a fourth embodiment of the present disclosure.

[0195] exist Fig.12 In the embodiment, sub-pixel 200a includes a Fig.11 The voltage-compensated pixel circuit 210 is a voltage-compensated pixel circuit 210a.

[0196] The voltage compensation pixel circuit 210 a includes a capacitor 213 between a threshold voltage detection section 211 and a threshold voltage compensation section 212 .

[0197] The capacitor 213 stores the threshold voltage detection value detected by the threshold voltage detection section 211 , and the threshold voltage compensation section 212 reads the threshold voltage detection value stored in the capacitor 213 .

[0198] Although the capacitor 213 is used to store the threshold voltage detection value in the fourth embodiment, the present disclosure is not limited thereto, and a different storage element may be used instead of the capacitor 213 in another embodiment.

[0199] Therefore, a light emitting display device with stable high quality is obtained by performing threshold voltage detection and data writing at different timings and appropriate voltage compensation is obtained.

[0200] Therefore, in the light emitting display device, the threshold voltage is detected in a detection initial state of the driving transistor, and the data voltage is compensated by the threshold voltage detection value.

[0201] It will be apparent to those skilled in the art that various modifications and variations may be made in the present disclosure without departing from the technical concept or scope of the present disclosure. Therefore, the present disclosure is intended to cover modifications and variations of the present disclosure as long as they fall within the scope of the appended claims and their equivalents.

Claims

1. A light emitting display device, wherein a pixel circuit detects and compensates for a threshold voltage of a driving transistor in each of a plurality of sub-pixels arranged in a matrix, the light emitting display device comprising: a threshold voltage estimation section that generates a threshold voltage estimation value by estimating the threshold voltage of the driving transistor by a data counting method; a reference voltage modification section that generates a reference voltage modification value by modifying a reference voltage used for detecting the threshold voltage based on the threshold voltage estimation value; an image data voltage modification section that generates an image data voltage modification value by adding a data voltage corresponding to the image data to the threshold voltage detection value; as well as a cumulative degradation calculation unit that calculates cumulative degradation by accumulating degradation data of a function of the data voltage, wherein, in order to detect the threshold voltage of the driving transistor, the light emitting display device is configured to supply the reference voltage modification value to the gate of the driving transistor and to supply the image data voltage modification value to a node coupled to the source of the driving transistor, and wherein the node is not at the gate of the driving transistor, and The reference voltage modification value is the sum of the reference voltage and the threshold voltage estimation value.

2. The light emitting display device according to claim 1, wherein: The threshold voltage is detected using the reference voltage as the threshold voltage detection value.

3. The light emitting display device according to claim 1, wherein: The threshold voltage estimation section estimates the threshold voltage of the driving transistor in each of the plurality of sub-pixels, and The cumulative degradation calculation unit calculates the cumulative degradation by accumulating the degradation data of the driving transistor of each of the plurality of sub-pixels.

4. The light emitting display device according to claim 3, wherein: The detecting and compensating for the threshold voltage of the driving transistor are performed simultaneously.

5. The light emitting display device according to claim 1, wherein: The threshold voltage estimation unit estimates an average value of the threshold voltages of the driving transistors of all the sub-pixels among the plurality of sub-pixels, and The cumulative degradation calculation unit calculates the cumulative degradation of the driving transistors of all the sub-pixels among the plurality of sub-pixels.

6. The light emitting display device according to claim 5, wherein: The detecting and compensating for the threshold voltage of the driving transistor are performed simultaneously.

7. The light emitting display device according to claim 5, wherein: The detecting and compensating for the threshold voltage of the driving transistor are performed at different timings.

8. The light emitting display device according to claim 1, wherein: Each of the plurality of sub-pixels includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor, a capacitor, and a light emitting element, wherein the third transistor is the driving transistor, wherein the gate of the first transistor is connected to a scan signal line, the source of the first transistor is connected to a first node, and the drain of the first transistor is connected to a reference voltage line, wherein the gate of the second transistor is connected to the scan signal line, the source of the second transistor is connected to the second node, and the drain of the second transistor is connected to the data line, wherein the gate of the third transistor is connected to the first node, the source of the third transistor is connected to the third node, and the drain of the third transistor is connected to the high level voltage line, wherein the gate of the fourth transistor is connected to the merge signal line, the source of the fourth transistor is connected to the second node, and the drain of the fourth transistor is connected to the first node, wherein the gate of the fifth transistor is connected to the reset signal line, the source of the fifth transistor is connected to the third node, and the drain of the fifth transistor is connected to the first node, wherein the gate of the sixth transistor is connected to the reset signal line, the source of the sixth transistor is connected to the third node, and the drain of the sixth transistor is connected to the initial voltage line, wherein the capacitor is connected between the second node and the third node, and Wherein, the light emitting element is connected between the third node and the low level voltage line.

9. The light emitting display device according to claim 1, wherein: Each of the plurality of sub-pixels includes a first transistor, a second transistor, a third transistor, and a fourth transistor, a first capacitor and a second capacitor, and a light emitting element, wherein the third transistor is the driving transistor, The gate of the first transistor is connected to the scan signal line, the source of the first transistor is connected to the data line, and the drain of the first transistor is connected to the first node. wherein the gate of the second transistor is connected to the initial voltage line, the source of the second transistor is connected to the first node, and the drain of the second transistor is connected to the second node, wherein the gate of the third transistor is connected to the first node, the source of the third transistor is connected to the third node, and the drain of the third transistor is connected to the second node, The gate of the fourth transistor is connected to the light emitting signal line, the source of the fourth transistor is connected to the high level voltage line, and the drain of the fourth transistor is connected to the third node. Wherein, the first capacitor is connected between the high level voltage line and the third node, wherein the second capacitor is connected between the third node and the first node, and Wherein, the light emitting element is connected between the second node and a low level voltage line.

10. A light-emitting display device, comprising: a plurality of sub-pixels arranged in a matrix, each of the plurality of sub-pixels including a voltage compensation pixel circuit having a driving transistor and a light emitting element that emits light due to control of the voltage compensation pixel circuit, the voltage compensation pixel circuit detecting a threshold voltage of the driving transistor as a threshold voltage detection value and compensating for the threshold voltage of the driving transistor; a timing controller that supplies a control signal to a data driving circuit and a gate driving circuit connected to the plurality of sub-pixels based on a timing synchronization signal and a data current; as well as a storage unit that memorizes one of degradation data of each of the plurality of sub-pixels and average degradation data of the plurality of sub-pixels, wherein the timing controller modifies the reference voltage using the threshold voltage estimation value of the offset of the threshold voltage obtained by the data counting method, and modifies the image data voltage using the threshold voltage detection value, wherein, in order to detect the threshold voltage of the driving transistor, the light emitting display device is configured to supply a modified reference voltage to the gate of the driving transistor and to supply a modified image data voltage to a node coupled to the source of the driving transistor, and wherein the node is not at the gate of the driving transistor, and Herein, using the threshold voltage estimation value to modify the reference voltage is to add the reference voltage to the threshold voltage estimation value, and using the threshold voltage detection value to modify the image data voltage is to add the image data voltage to the threshold voltage detection value.

11. The light emitting display device according to claim 10, wherein: The timing controller calculates cumulative degradation by accumulating degradation data of the driving transistor of each of the plurality of sub-pixels, and estimates the threshold voltage of the driving transistor of each of the plurality of sub-pixels.

12. The light emitting display device according to claim 11, wherein: The detecting and compensating for the threshold voltage of the driving transistor are performed simultaneously.

13. The light emitting display device according to claim 10, wherein: The timing controller calculates cumulative degradation by accumulating degradation data of the driving transistor of each of the plurality of sub-pixels, and estimates an average value of threshold voltages of the driving transistors of the plurality of sub-pixels.

14. The light emitting display device according to claim 13, wherein: The detecting and compensating for the threshold voltage of the driving transistor are performed simultaneously.

15. The light emitting display device according to claim 13, wherein: The detecting and compensating for the threshold voltage of the driving transistor are performed at different timings.

16. The light emitting display device according to claim 10, wherein: The voltage compensation pixel circuit includes a threshold voltage detection unit and a threshold voltage compensation unit. The threshold voltage detection section generates the threshold voltage detection value by detecting the threshold voltage of the driving transistor, and The threshold voltage compensating part compensates the threshold voltage of the driving transistor by updating an image data voltage to an image data voltage modified using the threshold voltage detection value.

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