Display device and method for manufacturing a display device

Abstract

A display device and a method of manufacturing the display device are provided. The display device includes: a semiconductor layer disposed on a substrate; a gate insulating layer disposed on the substrate and covering the semiconductor layer; a gate electrode disposed on the gate insulating layer and at least partially overlapping with the semiconductor layer; an interlayer insulating layer disposed on the gate electrode; and an electrode layer disposed on the interlayer insulating layer and electrically connected to the semiconductor layer, wherein the interlayer insulating layer includes a first portion and a second portion extending from the first portion, and the electrode layer is disposed on the first portion of the interlayer insulating layer, and a step is provided by a difference between a thickness of the first portion and a thickness of the second portion.

Description

[0001] This application claims the priority and benefit of Korean Patent Application No. 10-2020-0000491, filed on Jan. 2, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Aspects of one or more embodiments relate to a display device and a method of manufacturing the same. Background Art

[0003] A display device is a device that visually displays data. The display device may be used as a display unit in various applications, for example, for small products such as mobile phones or for large products such as televisions (TVs).

[0004] The display device may include a substrate divided into a display area and a non-display area, and gate lines and data lines are formed in the display area and are insulated from each other. The gate lines and the data lines cross each other such that a plurality of pixel areas are defined in the display area, and the plurality of pixel areas emit light by receiving an electrical signal to display an image to the outside. Thin film transistors corresponding to each of the pixel areas and pixel electrodes electrically connected to the thin film transistors may be used, and a counter electrode may be commonly used for the pixel areas. Various wirings for transmitting an electrical signal to the display area, a gate driving unit, a data driving unit, and a controller may be disposed in the non-display area.

[0005] With the advancement of technology, various applications and uses of display devices are being diversified. In addition, the thickness of the display device is generally becoming thinner, and the weight of the display device is becoming lighter, such that the range of use of the display device has become wider. Accordingly, research on the production of display devices is rapidly progressing, and various attempts have been made to reduce additional devices and improve the yield.

[0006] The above information disclosed in this background art section is only for enhancing the understanding of the background art, and thus the information discussed in this background art section does not necessarily constitute the prior art. Summary of the Invention

[0007] Aspects of one or more embodiments relate to a display device and a method of manufacturing the same, for example, to a display device having an ensured transmittance and a method of manufacturing the same.

[0008] Aspects of one or more embodiments include a display device having a relatively high-quality transmittance and a method of manufacturing the same. However, this characteristic is only an example, and the scope of embodiments according to the present disclosure is not limited thereto.

[0009] Other aspects will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the disclosed exemplary embodiments.

[0010] According to one or more exemplary embodiments, a display device includes: a semiconductor layer disposed on a substrate; a gate insulating layer disposed on the substrate and covering the semiconductor layer; a gate electrode disposed on the gate insulating layer such that a portion of the gate electrode overlaps with the semiconductor layer; an interlayer insulating layer disposed on the gate electrode; and an electrode layer disposed on the interlayer insulating layer and electrically connected to the semiconductor layer, wherein the interlayer insulating layer includes a first portion and a second portion extending from the first portion, and the electrode layer is disposed on the first portion of the interlayer insulating layer, and a step is provided by a difference between a thickness of the first portion and a thickness of the second portion.

[0011] According to some exemplary embodiments, the thickness of the first portion may be greater than the thickness of the second portion.

[0012] According to some exemplary embodiments, a width of a top surface of the first portion may be greater than a width of a bottom surface of the electrode layer.

[0013] According to some exemplary embodiments, the width of the top surface of the first portion may be the same as the width of the bottom surface of the electrode layer.

[0014] According to some exemplary embodiments, the interlayer insulating layer may have a single-layer structure and may include silicon oxide.

[0015] According to some exemplary embodiments, the interlayer insulating layer may include a first interlayer insulating layer and a second interlayer insulating layer, and the first interlayer insulating layer and the second interlayer insulating layer may be sequentially disposed on the gate electrode.

[0016] According to some exemplary embodiments, the first interlayer insulating layer may include silicon oxide, and the second interlayer insulating layer may include silicon nitride.

[0017] According to some exemplary embodiments, the thickness of the first portion of the second interlayer insulating layer may be greater than the thickness of the second portion of the second interlayer insulating layer.

[0018] According to some exemplary embodiments, a top surface of the first interlayer insulating layer corresponding to the second portion of the second interlayer insulating layer may be exposed.

[0019] According to some exemplary embodiments, the substrate may include a first region, a second region surrounding the first region, and a third region between the first region and the second region, and the interlayer insulating layer may have a first opening corresponding to the first region, and the gate insulating layer may have a second opening corresponding to the first region.

[0020] According to some example embodiments, the display device may further include a buffer layer disposed between the substrate and the semiconductor layer, and the buffer layer may have a third opening corresponding to the first region.

[0021] According to some example embodiments, the display device may further include a component disposed under the substrate corresponding to the first region.

[0022] According to one or more example embodiments, a method of manufacturing a display device includes: forming a semiconductor layer on a substrate; forming a gate insulating layer to cover the semiconductor layer; forming a gate electrode on the gate insulating layer, at least a portion of the gate electrode overlapping with the semiconductor layer; forming an interlayer insulating layer on the gate electrode; forming a contact hole that penetrates the gate insulating layer and the interlayer insulating layer and exposes a portion of the semiconductor layer; forming an electrode layer on a first portion of the interlayer insulating layer, the electrode layer being electrically connected to the semiconductor layer through the contact hole; forming a photoresist pattern on the electrode layer; etching the electrode layer by using the photoresist pattern as a mask; and etching a portion of a second portion of the interlayer insulating layer, the second portion extending from the first portion of the interlayer insulating layer.

[0023] According to some example embodiments, the substrate may include a first region, a second region surrounding the first region, and a third region between the first region and the second region, and when forming the contact hole, the gate insulating layer and the interlayer insulating layer positioned on the first region may be removed together.

[0024] According to some example embodiments, the method may further include forming a buffer layer between the substrate and the semiconductor layer, and when etching the portion of the interlayer insulating layer, the buffer layer positioned on the first region may be etched together.

[0025] According to some example embodiments, the method may further include cleaning the electrode layer, and the cleaning of the electrode layer and the etching of the portion of the interlayer insulating layer may be performed simultaneously (or concurrently).

[0026] According to some example embodiments, when etching the portion of the interlayer insulating layer, carbon tetrafluoride (CF 4 ) may be used.

[0027] According to some example embodiments, a bias voltage may be applied when etching the portion of the interlayer insulating layer.

[0028] According to some example embodiments, the method may further include removing the photoresist pattern.

[0029] According to some example embodiments, the width of the top surface of the first portion may be greater than the width of the bottom surface of the electrode layer.

[0030] Other aspects, features, and characteristics, in addition to the above - mentioned aspects, features, and characteristics, will become more apparent by referring to the detailed description, claims, and drawings for implementing the embodiments that are disclosed. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects, features, and characteristics of certain example embodiments disclosed will become more apparent from the following description taken in conjunction with the drawings, in which:

[0032] Figure 1 is a perspective view schematically showing a display device according to some example embodiments;

[0033] Figure 2A is schematically showing along Figure 1 a cross - sectional view of the display device taken along line II - II';

[0034] Figure 2B is schematically showing along Figure 1 a cross - sectional view of the display device taken along line II - II';

[0035] Figure 2C is schematically showing along Figure 1 a cross - sectional view of the display device taken along line II - II';

[0036] Figure 2D is schematically showing along Figure 1 a cross - sectional view of the display device taken along lines I - I', II - II', and IV - IV';

[0037] Figure 3 is a plan view schematically showing a display panel according to some example embodiments;

[0038] Figure 4 is an equivalent circuit diagram of a pixel of a display device according to some example embodiments;

[0039] Figure 5A is schematically showing along Figure 3 a cross - sectional view of the display panel taken along line III - III';

[0040] Figure 5B is schematically showing along Figure 3 a cross - sectional view of the display panel taken along line III - III';

[0041] Figure 5C is schematically showing along Figure 3 a cross - sectional view of the display panel taken along line III - III';

[0042] Figure 6A is schematically showing along Figure 3A cross-sectional view of a display panel taken along line III-III'.

[0043] Figure 6B is a schematic cross-sectional view of a display panel taken along Figure 3 line III-III' of ; and

[0044] Figures 7A to 7E is a cross-sectional view showing a method of manufacturing a display device according to some example embodiments. Detailed Description

[0045] Now, aspects of some example embodiments will be described in more detail with reference to the accompanying drawings, in which some example embodiments are shown, where like reference numerals always denote like elements. In this regard, the present embodiments may have different forms and should not be construed as limited to the descriptions set forth herein. Therefore, the embodiments will be described below only by referring to the drawings to explain aspects of the present specification. As used herein, the term "and / or" includes any combination and all combinations of one or more of the related listed items. Throughout the disclosure, the expression "at least one of a, b, and c" means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0046] Since the invention allows for various changes and many embodiments, specific embodiments will be shown in the drawings and described in more detail in the written description. The effects and features of the present disclosure and the methods for achieving them will become apparent by referring to the embodiments and the drawings that will be described in more detail below. However, the scope of the embodiments according to the present disclosure is not limited to the example embodiments below, but may be implemented in various forms.

[0047] Hereinafter, aspects of some example embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings below. Regardless of the drawing numbers, the same or corresponding elements are given the same reference numerals, and redundant descriptions thereof are omitted.

[0048] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0049] As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms unless the context clearly indicates otherwise.

[0050] It will also be understood that the terms "comprises / include" and variations thereof as used herein specify the presence of the stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0051] It will be understood that when a layer, region, or element is referred to as being "formed on" another layer, region, or element, the layer, region, or element may be formed directly or indirectly on the other layer, region, or element. That is, for example, there may be intermediate layers, regions, or elements.

[0052] For ease of explanation, the dimensions of the elements in the drawings may be exaggerated or reduced. In other words, since the dimensions and thicknesses of the components in the drawings are arbitrarily shown for ease of explanation, the following embodiments are not limited thereto.

[0053] When a certain embodiment can be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to the described order.

[0054] In this specification, "A and / or B" means A, B, or A and B, and "at least one of A and B" means A, B, or A and B.

[0055] It will be understood that when a layer, region, or element is referred to as being "connected to" another layer, region, or element, the layer, region, or element may be directly or indirectly connected to the other layer, region, or element. That is, for example, there may be intermediate layers, regions, or elements. For example, it will be understood that when a layer, region, or element is referred to as being "electrically connected to" another layer, region, or element, the layer, region, or element may be directly or indirectly connected to the other layer, region, or element. That is, for example, there may be intermediate layers, regions, or elements.

[0056] The x-axis, y-axis, and z-axis are not limited to the three axes of a rectangular coordinate system and may be interpreted in a broad sense. For example, the x-axis, y-axis, and z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0057] Hereinafter, example embodiments of the present disclosure will be described in more detail with reference to the drawings.

[0058] Figure 1 is a perspective view schematically showing a display device according to some example embodiments.

[0059] Referring to Figure 1 , the display device 1 may include a first region AR1, a second region AR2, a third region AR3, and a fourth region AR4.

[0060] According to some example embodiments, the third region AR3 and the fourth region AR4 may be arranged adjacent to the second region AR2, and the display device 1 may provide or display certain images by using light emitted from a plurality of pixels arranged in the second region AR2. The second region AR2 may be a display region where light is emitted, and the third region AR3 and the fourth region AR4 may be non-display regions where no light is emitted.

[0061] The display device 1 may include a first region AR1 that is at least partially surrounded by the second region AR2. According to some example embodiments, Figure 1 it is shown that the first region AR1 is completely surrounded by the second region AR2. The third region AR3 may completely surround the first region AR1, the second region AR2 may completely surround the third region AR3, and the fourth region AR4 may completely surround the second region AR2.

[0062] According to some example embodiments, as will be described in more detail later with reference to Figure 2A the first region AR1 may be a location where electronic components are arranged. That is, the first region AR1 will be understood as a transmissive region through which light and / or sound output from the electronic components to the outside or traveling from the outside toward the electronic components can pass through.

[0063] Hereinafter, an organic light-emitting display device will be described as an example of the display device 1 according to some example embodiments. However, the display device according to the present disclosure is not limited thereto. According to some example embodiments, various types of display devices, such as inorganic electroluminescent (EL) display devices and quantum dot light-emitting display devices, may be used.

[0064] Figures 2A to 2C is a cross-sectional view of the display device schematically showing a cut along the line II-II’, and Figure 1 is a cross-sectional view of the display device schematically showing cuts along the lines I-I’, II-II’ and IV-IV’. Figure 2D is a cross-sectional view of the display device schematically showing a cut along the line II-II’, and Figure 1 is a cross-sectional view of the display device schematically showing cuts along the lines I-I’, II-II’ and IV-IV’.

[0065] Referring to Figure 2A , the display device (see 1 in Figure 1 ) may include a display panel 10 including display elements and a component 20 corresponding to the first region AR1.

[0066] The display panel 10 may include a substrate 100, a package substrate 300 as a package member facing the substrate 100, and a display element layer 200 between the substrate 100 and the package substrate 300. A sealing member (sealant) 350 may be arranged between the substrate 100 and the package substrate 300 to cover the side surfaces of the display element layer 200. Figure 2AThe sealing member 350 is shown disposed on both sides of the first region AR1. However, it will be understood that when viewed from a direction perpendicular to the main surface of the substrate 100 (e.g., the normal direction with respect to the display surface or display plane of the display panel 10), the first region AR1 is completely surrounded by the sealing member 350.

[0067] The substrate 100 may include a glass material, a ceramic material, a metal material, or a flexible or bendable material. The substrate 100 may have a single-layer or multi-layer structure of the above materials, and in the case where the substrate 100 has a multi-layer structure, the substrate 100 may further include an inorganic layer. In some exemplary embodiments, the substrate 100 may have a structure of organic material / inorganic material / organic material.

[0068] The encapsulation substrate 300 may be disposed to face the substrate 100 and may include glass or a polymer resin described below.

[0069] The display element layer 200 may include a circuit layer including thin film transistors TFTs, an organic light emitting diode OLED as a display element connected to the thin film transistors TFTs, and an insulating layer IL between the thin film transistors TFTs and the organic light emitting diode OLED. The thin film transistors TFTs and the organic light emitting diode OLED connected to the thin film transistors TFTs may be disposed in the second region AR2, and some wirings WL of the display element layer 200 may be located in the third region AR3. The second region AR2 may be a display region where light is emitted, and the third region AR3 may be a non-display region where no light is emitted.

[0070] The wiring WL may supply a specific signal or voltage to the pixels, which are separated from each other, and the first region AR1 is located between the pixels. In Figure 2A this, the wiring WL does not overlap with the sealing member 350 in the third region AR3. However, according to some exemplary embodiments, a portion of the sealing member 350 may be disposed on the wiring WL.

[0071] The display panel 10 may include a through hole 10H corresponding to the first region AR1. For example, the substrate 100 and the encapsulation substrate 300 may respectively include a through hole 100H and a through hole 300H both corresponding to the first region AR1. The display element layer 200 may also include a through hole corresponding to the first region AR1.

[0072] According to some exemplary embodiments, elements such as an input sensing member for sensing a touch input, an antireflection member including a polarizer and a retarder or a color filter and a black matrix, and a transparent window may also be disposed on the display panel 10.

[0073] The component 20 can be positioned in the first region AR1. The component 20 can be an electronic component that utilizes light or sound. For example, the electronic component can include a sensor for receiving and utilizing light (such as an infrared sensor), a camera for receiving light to capture (take) an image, a sensor for outputting and sensing light or sound to measure distance or identify fingerprints, a small lamp for outputting light, or a speaker for outputting sound. The electronic component that utilizes light can utilize light with various wavelength bands, such as visible light, infrared light, ultraviolet (UV) light. As Figure 2A shown in

[0074] When the display panel 10 includes a through hole 10H corresponding to the first region AR1, the light or sound output or received by the electronic component can be utilized more effectively. Figure 2A Different from the case where the display panel 10 includes a through hole 10H corresponding to the first region AR1, some elements of the display panel 10 may not include through holes. For example, as Figure 2B shown in

[0075] Optionally, as Figure 2C and Figure 2D shown in Figure 2C neither the base 100 nor the encapsulation base 300 may include a through hole corresponding to the first region AR1. In

[0076] In addition, in Figure 2D shown in Figure 2C different from Figures 2A to 2C the sealing member 350 may not be provided around the first region AR1. The sealing member 360 can be positioned in the fourth region AR4, and by bonding the base 100 to the encapsulation base 300, the display element layer 200 can be sealed against external air. According to some example embodiments,

[0077] Figure 2D the insulating layer IL may have an opening IL-OP corresponding to the first region AR1. According to some example embodiments, no component may be arranged between the base 100 and the encapsulation base 300 corresponding to the first region AR1. According to some example embodiments, some inorganic insulating layers (such as a buffer layer) may remain in the first region AR1 of the base 100.

[0078] As Figures 2B to 2D shown in even if the base 100 does not include a through hole 100H, the portion of the display element layer 200 corresponding to the first region AR1 can be removed to ensure light transmissibility for the electronic component. When the display device 1 includesFigures 2B to 2D When the display panel 10 shown in FIG. is used, it may be appropriate to use an optical element as the electronic element.

[0079] As Figures 2A to 2D As shown in FIG., the component 20 is positioned below the display panel 10, that is, positioned at one side of the substrate 100. However, at least a part of the component 20 may be inserted into the through hole 10H to overlap with the side surface of the display panel 10 that defines the through hole 10H.

[0080] The component 20 may be a member other than the above-mentioned electronic element. According to some example embodiments, when the display panel 10 is used as a smart watch or a dashboard for a vehicle, the component 20 may be a member including clock hands or hands indicating certain information (e.g., vehicle speed, etc.). Optionally, the component 20 may include elements such as accessories for enhancing the aesthetic appearance of the display panel 10.

[0081] Figure 3 is a plan view schematically showing a display panel according to some example embodiments, and Figure 4 is an equivalent circuit diagram of one pixel of a display device according to an embodiment.

[0082] Referring to Figure 3 , the display panel 10 may include a first region AR1, a second region AR2, a third region AR3, and a fourth region AR4. Figure 3 It will be understood as the outer shape of the substrate 100 of the display panel 10. For example, the substrate 100 will be understood to have a first region AR1, a second region AR2, a third region AR3, and a fourth region AR4.

[0083] The display panel 10 may include a plurality of pixels P arranged in the second region AR2. As Figure 4 shown in FIG., each pixel P may include a pixel circuit PC and an organic light-emitting diode OLED as a display element connected to the pixel circuit PC. The pixel circuit PC may include a driving thin film transistor (TFT) T1, a switching thin film transistor (TFT) T2, and a storage capacitor Cst. Each pixel P may emit red light, green light, blue light, or white light through the organic light-emitting diode OLED, for example.

[0084] The switching thin film transistor (TFT) T2 may be connected to a scan line SL and a data line DL, and may transfer the data voltage input from the data line DL to the driving thin film transistor (TFT) T1 according to the switching voltage input from the scan line SL. The storage capacitor Cst may be connected to the switching thin film transistor (TFT) T2 and a driving voltage line PL, and may store a voltage corresponding to the voltage difference between the voltage transferred from the switching thin film transistor (TFT) T2 and the first power supply voltage ELVDD supplied to the driving voltage line PL.

[0085] The driving thin film transistor (TFT) T1 can be connected to a driving voltage line PL and a storage capacitor Cst, and can control a driving current flowing from the driving voltage line PL to the organic light emitting diode OLED in response to the voltage stored in the storage capacitor Cst. The organic light emitting diode OLED can emit light with a certain brightness by using the driving current. The counter electrode (e.g., cathode) of the organic light emitting diode OLED can receive a second power supply voltage ELVSS.

[0086] Figure 4 It is shown that the pixel circuit PC includes two thin film transistors and one storage capacitor, but the embodiments are not limited thereto. The number of thin film transistors and the number of storage capacitors can be changed in various ways according to the design of the pixel circuit PC.

[0087] Returning to the reference Figure 3 , the third region AR3 can surround the first region AR1. The third region AR3 is a region where no display element for emitting light (such as the organic light emitting diode OLED) is located, and a signal line for supplying a signal to the pixel P around the first region AR1 can pass through the third region AR3.

[0088] A scan driver 1100 for supplying a scan signal to each pixel P, a data driver 1200 for supplying a data signal to each pixel P, and main power supply lines for supplying a first power supply voltage ELVDD and a second power supply voltage ELVSS can be arranged in the fourth region AR4. Figure 3 It is shown that the data driver 1200 is adjacent to one side of the substrate 100. However, according to some example embodiments, the data driver 1200 can be arranged on a flexible printed circuit board (FPCB) that is electrically connected to a pad (or called "bond pad" or "landing pad") arranged on one side of the display panel 10.

[0089] Figures 5A to 5C is a schematic cross-sectional view of the display panel taken along the Figure 3 line III-III'. Figure 5B and Figure 5C correspond to Figure 5A some modified embodiments, so will be described based on Figure 5A , and will be described below based on Figure 5B and Figure 5C the differences between Figure 5A and Figure 5B and Figure 5C .

[0090] Referring to Figure 5A , a display device according to some example embodiments (seeFigure 1 1) may include a semiconductor layer A, gate insulating layers 112 and 113, an interlayer insulating layer ILD, and an organic light-emitting diode OLED as a display element. The semiconductor layer A is disposed on a substrate 100. The interlayer insulating layer ILD may include a first interlayer insulating layer 114 and a second interlayer insulating layer 115.

[0091] According to some exemplary embodiments, the display device 1 may further include an electrode layer E disposed on the second interlayer insulating layer 115 and electrically connected to the semiconductor layer A. The second interlayer insulating layer 115 may include a first portion 115a and a second portion 115b extending from the first portion 115a, and the electrode layer E may be disposed on the first portion 115a of the second interlayer insulating layer 115. At this time, a step t1 and t1' may be provided by a difference between a thickness ta1 of the first portion 115a and a thickness tb1 of the second portion 115b of the second interlayer insulating layer 115.

[0092] In addition, according to some exemplary embodiments, the thickness ta1 of the first portion 115a of the second interlayer insulating layer 115 may be greater than the thickness tb1 of the second portion 115b of the second interlayer insulating layer 115.

[0093] According to some exemplary embodiments, a width W2 of a top surface of the first portion 115a of the second interlayer insulating layer 115 may be greater than a width W1 of a bottom surface of the electrode layer E.

[0094] Hereinafter, a configuration included in the display device 1 will be described in more detail with reference to Figure 5A the stacking order.

[0095] The substrate 100 includes a first region AR1, a second region AR2, and a third region AR3 located between the first region AR1 and the second region AR2. A thin film transistor TFT and an organic light-emitting diode OLED connected to the thin film transistor TFT may be disposed in the second region AR2, and some wirings WL1 and WL2 may be located in the third region AR3. The second region AR2 may be a display region where light is emitted, and the third region AR3 may be a non-display region where no light is emitted. Hereinafter, a description will be given focusing on the second region AR2.

[0096] The substrate 100 may include a glass material, a ceramic material, a metal material, or a flexible or bendable material. When the substrate 100 is flexible or bendable, the substrate 100 may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

[0097] The substrate 100 may have a single-layer or multi-layer structure of the above materials, and when the substrate 100 has a multi-layer structure, the substrate 100 may further include an inorganic layer. In some exemplary embodiments, the substrate 100 may have a structure of organic material / inorganic material / organic material.

[0098] The buffer layers 110 and 111 may be disposed on the substrate 100 and may have a single-layer or multi-layer structure. The buffer layers 110 and 111 may include silicon oxide (SiO 2 ), silicon nitride (SiN X ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), or zinc oxide (ZnO).

[0099] According to some exemplary embodiments, the buffer layers 110 and 111 may include a first buffer layer 110 and a second buffer layer 111, and the first buffer layer 110 may include silicon nitride (SiN x ), and the second buffer layer 111 may include silicon oxide (SiO 2 ). At this time, the second buffer layer 111 may be thicker than the first buffer layer 110.

[0100] A barrier layer may also be included between the substrate 100 and the buffer layers 110 and 111. The barrier layer may prevent impurities from penetrating from the substrate 100 into the semiconductor layer A, or may minimize the penetration. The barrier layer may include an inorganic material such as an oxide or a nitride, an organic material, or an organic / inorganic composite material, and may have a single-layer or multi-layer structure of an inorganic material and / or an organic material.

[0101] The semiconductor layer A may be disposed on the buffer layers 110 and 111. The semiconductor layer A may include amorphous silicon or polycrystalline silicon. According to some exemplary embodiments, the semiconductor layer A may include an oxide of at least one selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).

[0102] The semiconductor layer A may include a channel region and source and drain regions located on both sides of the channel region. The semiconductor layer A may have a single-layer or multi-layer structure.

[0103] The first gate insulating layer 112 and the second gate insulating layer 113 may be stacked on the substrate 100 to cover the semiconductor layer A. The first gate insulating layer 112 and the second gate insulating layer 113 may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), or zinc oxide (ZnO).

[0104] The gate electrode G may be disposed on the first gate insulating layer 112 such that at least a portion of the gate electrode G may overlap with the semiconductor layer A. That is, the first gate insulating layer 112 may be disposed between the semiconductor layer A and the gate electrode G.

[0105] In the drawings, the gate electrode G is disposed on the first gate insulating layer 112. However, according to some example embodiments, the gate electrode G may be disposed on the top surface of the second gate insulating layer 113. In addition, the gate electrodes G of multiple thin film transistors TFT may be disposed on the same layer or different layers.

[0106] The lower electrode CE1 of the storage capacitor Cst made of the same material as the gate electrode G may be disposed on the first gate insulating layer 112. The upper electrode CE2 of the storage capacitor Cst may overlap with the lower electrode CE1 and the second gate insulating layer 113 is located between the upper electrode CE2 and the lower electrode CE1, thereby forming a capacitor. In this case, the second gate insulating layer 113 may be used as the dielectric layer of the storage capacitor Cst.

[0107] As Figure 5A shown, the lower electrode CE1 of the storage capacitor Cst may overlap with the thin film transistor TFT. For example, the gate electrode G of the thin film transistor TFT may be used as the lower electrode CE1 of the storage capacitor Cst.

[0108] The interlayer insulating layer ILD may be provided on the second gate insulating layer 113 to cover the upper electrode CE2 of the storage capacitor Cst. The interlayer insulating layer ILD may include silicon oxide (SiO 2 ), silicon nitride (SiN X ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), hafnium oxide (HfO 2), or zinc oxide (ZnO).

[0109] According to some example embodiments, the interlayer insulating layer ILD may include a first interlayer insulating layer 114 and a second interlayer insulating layer 115, and the first interlayer insulating layer 114 may include silicon oxide (SiO 2 ), and the second interlayer insulating layer 115 may include silicon nitride (SiN x ). At this time, the second interlayer insulating layer 115 may be thicker than the first interlayer insulating layer 114.

[0110] In addition, according to some example embodiments, the second interlayer insulating layer 115 may include a first portion 115a and a second portion 115b extending from the first portion 115a, and the thickness ta1 of the first portion 115a may be greater than the thickness tb1 of the second portion 115b.

[0111] The electrode layer E may be disposed on the interlayer insulating layer ILD. The electrode layer E may include a source electrode S, a drain electrode D, and a data line (see Figure 3 DL).

[0112] The source electrode S, the drain electrode D, and the data line DL may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may have a single-layer or multi-layer structure including the above materials. According to some example embodiments, the source electrode S, the drain electrode D, and the data line DL may have a multi-layer structure of Ti / Al / Ti. The source electrode S and the drain electrode D may be connected to the source region or the drain region of the semiconductor layer A through contact holes CNT.

[0113] The source electrode S and the drain electrode D may be covered with an inorganic protection layer. The inorganic protection layer may be a single layer or multi-layers of silicon nitride (SiN x ), and / or silicon oxide (SiO x ). The inorganic protection layer may be introduced to cover and protect some wirings disposed on the interlayer insulating layer ILD.

[0114] A planarization layer 116 may be disposed to cover the source electrode S and the drain electrode D, and an organic light emitting diode OLED may be disposed on the planarization layer 116.

[0115] The planarization layer 116 may have a single-layer or multi-layer structure of an organic material, and may provide a flat top surface. The planarization layer 116 may include a general polymer (such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene (PS)), a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a parylene polymer, a vinyl alcohol polymer, and a blend thereof.

[0116] An organic light-emitting diode (OLED) can be disposed on the planarization layer 116. The organic light-emitting diode (OLED) can include a pixel electrode 210, an intermediate layer 220 including an organic emission layer, and a counter electrode 230.

[0117] The pixel electrode 210 can be a (semi)transparent electrode or a reflective electrode. In some exemplary embodiments, the pixel electrode 210 can include a reflective layer formed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and their composites, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer can include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In some exemplary embodiments, the pixel electrode 210 can include ITO / Ag / ITO.

[0118] In the second region AR2 of the substrate 100, a pixel defining layer 117 can be disposed on the planarization layer 116. In addition, the pixel defining layer 117 can increase the distance between the edge of the pixel electrode 210 and the counter electrode 230 above the pixel electrode 210, thereby preventing or reducing the occurrence of arcing at the edge of the pixel electrode 210.

[0119] The pixel defining layer 117 can be formed of one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, BCB, and phenolic resin by a method such as spin coating.

[0120] The intermediate layer 220 of the organic light-emitting diode (OLED) can include an organic emission layer. The organic emission layer can include an organic material, and the organic material includes a fluorescent material or a phosphorescent material that emits red light, green light, blue light, or white light. The organic emission layer can include a small molecular weight organic material or a polymeric organic material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), or an electron injection layer (EIL) can be selectively further disposed below and above the organic emission layer. The intermediate layer 220 can be arranged to correspond to each of the plurality of pixel electrodes 210. However, the embodiments according to the present disclosure are not limited thereto. The intermediate layer 220 can be variously modified, such as including a layer integrated throughout the plurality of pixel electrodes 210.

[0121] The counter electrode 230 may be a transparent electrode or a reflective electrode. In some example embodiments, the counter electrode 230 may be a transparent or semi-transparent electrode and may be formed of a thin metal layer having a small work function and including lithium (Li), calcium (Ca), LiF / Ca, LiF / Al, Al, Ag, Mg, and composites thereof. In addition, a transparent conductive oxide (TCO) layer such as ITO, IZO, ZnO, or In 2 O 3 may be further disposed on the thin metal layer. The counter electrode 230 may be disposed throughout the second region AR2 and may be disposed on the intermediate layer 220 and the pixel defining layer 117. The counter electrode 230 may be integrally formed throughout the plurality of organic light emitting diodes OLEDs and may correspond to the plurality of pixel electrodes 210.

[0122] According to some example embodiments, the second interlayer insulating layer 115 may include a first portion 115a and a second portion 115b extending from the first portion 115a. This will be described in more detail with reference to Figures 5A to 5C the configuration.

[0123] The interlayer insulating layer ILD may include a first interlayer insulating layer 114 and a second interlayer insulating layer 115, and the second interlayer insulating layer 115 may include a first portion 115a and a second portion 115b extending from the first portion 115a. In addition, steps t1, t1', t2, and t2' may be provided by the difference between the thickness ta1 of the first portion 115a and the thickness tb1 of the second portion 115b.

[0124] As shown in the drawings, the second interlayer insulating layer 115 may include a first portion 115a and a second portion 115b, and the shape having steps t1, t1', t2, and t2' may be repeated.

[0125] Figure 5A and Figure 5B show that in steps t1 and t1' of the first portion 115a and the second portion 115b of the second interlayer insulating layer 115, the step t1' of portion B' is greater than the step t1 of portion B.

[0126] Like the first interlayer insulating layer 114, the second interlayer insulating layer 115 may have a curved shape by the patterned gate electrode G. The curved shape may be reflected in steps t1 and t1' such that the step t1 of portion B may be different from the step t1' of portion B'.

[0127] According to some example embodiments, the step t1 of portion B and the step t1' of portion B' may be the same, such that steps t1 and t1' of the first portion 115a and the second portion 115b of the second interlayer insulating layer 115 may be uniformly formed.

[0128] Although described based on Figure 5A and Figure 5B as in Figure 5C the steps t2 and t2' of the first part 115a and the second part 115b of the second interlayer insulating layer 115 can be formed to be different from each other as the step t2 of part B and the step t2' of part B', respectively. In addition, different from the drawings, the steps t2 and t2' of the first part 115a and the second part 115b of the second interlayer insulating layer 115 can be uniform.

[0129] According to some exemplary embodiments, the first interlayer insulating layer 114 may include silicon oxide (SiO 2 ), and the second interlayer insulating layer 115 may include silicon nitride (SiN x ). At this time, the second interlayer insulating layer 115 may be thicker than the first interlayer insulating layer 114. According to some exemplary embodiments, the thickness of the first interlayer insulating layer 114 may be about 1000 Å to about 3000 Å, for example, about 2000 Å. In addition, the thickness of the second interlayer insulating layer 115 may be about 2000 Å to about 4000 Å, for example, about 3000 Å.

[0130] The contact hole CNT may be provided to pass through the gate insulating layers 112 and 113 and the interlayer insulating layer ILD and expose a part of the semiconductor layer A. The electrode layer E may be provided to be electrically connected to the semiconductor layer A through the contact hole CNT. At this time, the electrode layer E may be disposed on the first part 115a of the second interlayer insulating layer 115.

[0131] Referring to Figure 5A the enlarged view, since the electrode layer E may have a trapezoidal shape, the bottom surface and the top surface of the electrode layer E facing each other may be parallel. At this time, the wider part of the bottom surface and the top surface of the electrode layer E corresponds to the bottom surface of the electrode layer E.

[0132] In addition, the bottom surface of the electrode layer E may be in contact with the top surface of the first part 115a of the second interlayer insulating layer 115. According to some exemplary embodiments, the width W2 of the top surface of the first part 115a of the second interlayer insulating layer 115 may be greater than the width W1 of the bottom surface of the electrode layer E.

[0133] Figure 5A shows that the width W2 of the top surface of the first part 115a of the second interlayer insulating layer 115 is different from the width W1 of the bottom surface of the electrode layer E. However, referring to Figure 5B the enlarged view, the width W4 of the top surface of the first part 115a of the second interlayer insulating layer 115 may be the same as the width W3 of the bottom surface of the electrode layer E. That is, the side surface of the electrode layer E and the side surface of the first part 115a of the second interlayer insulating layer 115 may be located in the same plane.

[0134] According to some example embodiments, the thickness ta1 of the first portion 115a of the second interlayer insulating layer 115 may be greater than the thickness tb1 of the second portion 115b of the second interlayer insulating layer 115. According to some example embodiments, the thickness ta1 of the first portion 115a of the second interlayer insulating layer 115 may be from about 2000 Å to about 4000 Å, for example, about 3000 Å. In addition, the thickness tb1 of the second portion 115b of the second interlayer insulating layer 115 may be about 1500 Å or less.

[0135] Figure 5C The step t2 between the first portion 115a and the second portion 115b of the second interlayer insulating layer 115 shown in Figure 5A may be greater than the step t1 between the first portion 115a and the second portion 115b of the second interlayer insulating layer 115 shown in. In this case, the top surface of the first interlayer insulating layer 114 corresponding to the second portion 115b of the second interlayer insulating layer 115 may be exposed.

[0136] As Figure 5C shown in, a portion of the top surface of the first interlayer insulating layer 114 corresponding to the second portion 115b of the second interlayer insulating layer 115 may be removed. According to some example embodiments, all of the second portion 115b of the second interlayer insulating layer 115 may be removed such that the second portion 115b of the second interlayer insulating layer 115 and the top surface of the first interlayer insulating layer 114 corresponding to the second portion 115b may coincide with each other.

[0137] Figures 5A to 5C It is shown that the first portion 115a of the second interlayer insulating layer 115 has a trapezoidal shape, but the first portion 115a of the second interlayer insulating layer 115 may have a rectangular shape or may be variously modified.

[0138] As described above in Figures 2A to 2D shown, the component 20 may be positioned in the first region AR1. That is, the first region AR1 will be understood as a transmission region through which light and / or sound output from the component 20 to the outside or traveling from the outside toward the component 20 may pass through. The component 20 may be an electronic component that utilizes light or sound, and may be a member other than an electronic component. Optionally, the component 20 may include elements such as accessories for enhancing the aesthetic appearance of the display panel 10.

[0139] According to some example embodiments, the buffer layers 110 and 111, the gate insulating layers 112 and 113, and all of the interlayer insulating layer ILD in the first region AR1 may be removed such that the top surface of the substrate 100 corresponding to the first region AR1 may be exposed. That is, corresponding to the first region AR1, the interlayer insulating layer ILD may have first openings OP1 and OP1', the gate insulating layers 112 and 113 may have second openings OP2 and OP2', the buffer layers 110 and 111 may have third openings OP3 and OP3', and light and / or sound may be transmitted through the openings OP1, OP1', OP2, OP2', OP3, and OP3'.

[0140] In addition, according to some example embodiments, the buffer layers 110 and 111 may include a first buffer layer 110 and a second buffer layer 111, and the first buffer layer 110 may include silicon nitride (SiN x ), and the second buffer layer 111 may include silicon oxide (SiO 2 ). At this time, the second buffer layer 111 may be thicker than the first buffer layer 110.

[0141] As a comparative example, the buffer layer may be formed of a single layer including silicon oxide (SiO 2 ), and the buffer layer may be retained on the substrate corresponding to the transmission region. In this case, the refractive index of the retained buffer layer is similar to that of the substrate, such that there is no influence on the transmission of light and / or sound.

[0142] However, when the buffer layer has a high temperature due to laser during the "amorphous silicon laser crystallization" process, impurities present in the substrate are diffused. At this time, when the buffer layer has a single-layer structure, it may not be possible to prevent impurities, resulting in unstable device characteristics and a low yield.

[0143] In contrast, according to some example embodiments, the buffer layers 110 and 111 include a first buffer layer 110 containing silicon nitride (SiN x ), and a second buffer layer 111 containing silicon oxide (SiO 2 ), and when the top surface of the substrate 100 corresponding to the first region AR1 is exposed, there is no obstacle to the travel of light and / or sound, the refractive index does not change, and there is no influence on the transmittance.

[0144] In addition, when the buffer layers 110 and 111 have a high temperature due to laser during the "amorphous silicon laser crystallization" process, impurities present in the substrate 100 are diffused. However, when the first buffer layer 110 and the second buffer layer 111 are disposed on the substrate 100, penetration of impurities from the substrate 100 may be sufficiently prevented or reduced by the first buffer layer 110 and the second buffer layer 111.

[0145] Figure 6A and Figure 6B is a schematic cross-sectional view of a display panel taken along line III-III' of Figure 3 . In Figure 6A and Figure 6B , the same reference numerals as those in Figures 5A to 5C denote the same elements, and thus some redundant descriptions thereof will be omitted.

[0146] The substrate 100 may include a first region AR1, a second region AR2, and a third region AR3 located between the first region AR1 and the second region AR2. The second region AR2 may be a display region where light is emitted, and the third region AR3 may be a non-display region where no light is emitted.

[0147] The buffer layers 110 and 111, the gate insulating layers 112 and 113, the thin film transistors TFT, the storage capacitors Cst, the interlayer insulating layer ILD, the planarization layers 116, and the organic light emitting diodes OLED as display elements may be disposed on the substrate 100.

[0148] The buffer layers 110 and 111, the gate insulating layers 112 and 113, and the interlayer insulating layer ILD may include silicon oxide (SiO 2 ), and silicon nitride (SiN x ), and the planarization layer 116 may include a general polymer, a polymer derivative having a phenolic group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluoropolymer, a parylene polymer, a polyvinyl alcohol polymer, and blends thereof.

[0149] Figures 5A to 5C It is shown that the interlayer insulating layer ILD includes a first interlayer insulating layer 114 and a second interlayer insulating layer 115. However, referring to Figure 6A and Figure 6B , according to some exemplary embodiments, the interlayer insulating layer ILD may have a single-layer structure and may include silicon oxide (SiO 2 ).

[0150] The interlayer insulating layer ILD may include a first portion ILDa and a second portion ILDb extending from the first portion ILDa, and the steps t3 and t3' may be provided by the difference between the thickness ta2 of the first portion ILDa and the thickness tb2 of the second portion ILDb.

[0151] As shown in the drawings, the interlayer insulating layer ILD may include a first portion ILDa and a second portion ILDb, and the shape having the steps t3 and t3' may be repeated.

[0152] The interlayer insulating layer ILD may have a curved shape through the patterned gate electrode G. The curved shape may be reflected in the steps t3 and t3', such that the step t3 of the part B and the step t3' of the part B' may be different from each other.

[0153] According to some example embodiments, the step t3 of the part B and the step t3' of the part B' may be the same, such that the steps t3 and t3' of the first part ILDa and the second part ILDb of the interlayer insulating layer ILD may be formed uniformly.

[0154] By removing the gate insulating layers 112 and 113 and a part of the interlayer insulating layer ILD, a contact hole CNT may be provided, such that a part of the semiconductor layer A may be exposed through the contact hole CNT. The electrode layer E may be provided to be electrically connected to the semiconductor layer A through the contact hole CNT. At this time, the electrode layer E may be disposed on the first part ILDa of the interlayer insulating layer ILD.

[0155] Referring to Figure 6A the enlarged view, the electrode layer E may have a trapezoidal shape. Thus, the bottom surface and the top surface of the electrode layer E facing each other may be parallel. At this time, the wider part of the bottom surface and the top surface of the electrode layer E corresponds to the bottom surface of the electrode layer E.

[0156] In addition, the bottom surface of the electrode layer E may be in contact with the top surface of the first part ILDa of the interlayer insulating layer ILD. According to some example embodiments, the width W6 of the top surface of the first part ILDa of the interlayer insulating layer ILD may be greater than the width W5 of the bottom surface of the electrode layer E.

[0157] Figure 6A It shows that the width W6 of the top surface of the first part ILDa of the interlayer insulating layer ILD is different from the width W5 of the bottom surface of the electrode layer E. However, referring to Figure 6B the enlarged view, the width W8 of the top surface of the first part ILDa of the interlayer insulating layer ILD and the width W7 of the bottom surface of the electrode layer E may be the same. That is, the side surface of the electrode layer E and the side surface of the first part ILDa of the interlayer insulating layer ILD may be located in the same plane.

[0158] According to some example embodiments, the thickness ta2 of the first part ILDa of the interlayer insulating layer ILD may be greater than the thickness tb2 of the second part ILDb of the interlayer insulating layer ILD. According to some example embodiments, the thickness ta2 of the first part ILDa of the interlayer insulating layer ILD may be about 4000 Å to about 6000 Å, for example, about 5000 Å. In addition, the thickness tb2 of the second part ILDb of the interlayer insulating layer ILD may be about 3000 Å or less.

[0159] Figure 5AThe step t1 of the first part 115a and the second part 115b of the second interlayer insulating layer 115 shown in Figure 6A may be greater than the step t3 of the first part ILDa and the second part ILDb of the interlayer insulating layer ILD shown in x (t1 > t3). The second interlayer insulating layer 115 may include silicon nitride (SiN 2 ), and a single interlayer insulating layer ILD may include silicon oxide (SiO

[0160] Figure 6A and Figure 6B shows that the first part ILDa of the interlayer insulating layer ILD has a trapezoidal shape, but the first part ILDa of the interlayer insulating layer ILD may have a rectangular shape and may be variously modified.

[0161] According to some example embodiments, the buffer layers 110 and 111, the gate insulating layers 112 and 113, and all of the interlayer insulating layer ILD in the first region AR1 may be removed such that the top surface of the substrate 100 corresponding to the first region AR1 may be exposed. That is, corresponding to the first region AR1, the interlayer insulating layer ILD may have a first opening OP1, and the gate insulating layers 113 and 112 may have second openings OP2 and OP2', and the buffer layers 110 and 111 may have third openings OP3 and OP3', and light or / and sound may be transmitted through the openings OP1, OP2, OP2', OP3, and OP3'.

[0162] When the top surface of the substrate 100 corresponding to the first region AR1 is exposed, there is no obstacle to the travel of light or / and sound, there is no change in the refractive index, and there is no effect on the transmittance.

[0163] So far, only the display device 1 has been mainly described, but the embodiments are not limited thereto. For example, a method of manufacturing a display device for manufacturing such a display device 1 will also fall within the scope of the present disclosure.

[0164] Figures 7A to 7E is a cross-sectional view showing a method of manufacturing a display device for each step according to some example embodiments, and is taken as an example in Figure 5A In Figures 7A to 7E the same reference numerals as those in Figures 5A to 5C denote the same elements, and thus redundant descriptions thereof will be omitted.

[0165] Reference Figure 7A , first, a buffer layer 110 and 111, a semiconductor layer A, gate insulating layers 112 and 113, a gate electrode G of a thin film transistor TFT, a lower electrode CE1 and an upper electrode CE2 of a storage capacitor Cst, some wirings WL1 and WL2, and an interlayer insulating layer ILD can be sequentially formed on a substrate 100.

[0166] The buffer layers 110 and 111 may include silicon oxide (SiO 2 ), or silicon nitride (SiN x ), and can be formed by a deposition method such as chemical vapor deposition (CVD), sputtering, etc.

[0167] The semiconductor layer A can be formed by patterning a pre-semiconductor layer. The pre-semiconductor layer may include amorphous silicon or an oxide semiconductor, and can be deposited by CVD. In addition, when the pre-semiconductor layer is an amorphous silicon layer, after the amorphous silicon layer has been formed, various methods (such as rapid thermal annealing (RTA), solid phase crystallization (SPC), excimer laser annealing (ELA), metal-induced crystallization (MIC), metal-induced lateral crystallization (MILC), and sequential lateral solidification (SLS)) can be used to crystallize the amorphous silicon layer, so that the amorphous silicon layer can be formed into a polycrystalline silicon layer.

[0168] The gate insulating layers 112 and 113 may include silicon oxide (SiO 2 ), silicon nitride (SiN X ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), or zinc oxide (ZnO), and can be formed by a deposition method such as CVD, sputtering, etc., and the embodiments are not limited thereto.

[0169] The gate electrode G, the lower electrode CE1 of the storage capacitor Cst, and the first wiring WL1 may include the same material. To form the gate electrode G, the lower electrode CE1 of the storage capacitor Cst, and the first wiring WL1, a metal layer can be formed on the entire surface of the substrate 100, and then the metal layer can be patterned. A deposition method (such as plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), physical vapor deposition (PVD), sputtering, atomic layer deposition (ALD)) can be used to form the metal layer. The embodiments are not limited thereto.

[0170] A second gate insulating layer 113 may be formed over the entire surface of the substrate 100 to cover the gate electrode G, the lower electrode CE1 of the storage capacitor Cst, and the first wiring WL1, and an upper electrode CE2 of the storage capacitor Cst and a second wiring WL2 may be formed over the second gate insulating layer 113. The method of forming the upper electrode CE2 of the storage capacitor Cst and the second wiring WL2 is the same as the method of forming the gate electrode G, the lower electrode CE1 of the storage capacitor Cst, and the first wiring WL1 described above.

[0171] An interlayer insulating layer ILD may be formed over the entire surface of the substrate 100 to cover the upper electrode CE2 of the storage capacitor Cst and the second wiring WL2. The interlayer insulating layer ILD may include silicon oxide (SiO 2 ), silicon nitride (SiN X ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), or zinc oxide (ZnO), and may be formed by a deposition method such as CVD, sputtering, etc. The embodiments are not limited thereto.

[0172] According to some example embodiments, the interlayer insulating layer ILD may include a first interlayer insulating layer 114 and a second interlayer insulating layer 115, and the first interlayer insulating layer 114 may include silicon oxide (SiO 2 ), and the second interlayer insulating layer 115 may include silicon nitride (SiN x ).

[0173] Referring to Figure 7B , a contact hole CNT may be formed through the gate insulating layers 112 and 113 and the interlayer insulating layer ILD such that a source region and / or a drain region of the semiconductor layer A may be exposed through the contact hole CNT.

[0174] When forming the contact hole CNT, the gate insulating layers 112 and 113 and the interlayer insulating layer ILD located in the first region AR1 may be removed together. That is, corresponding to the first region AR1, the interlayer insulating layer ILD may have first openings OP1 and OP1', and the gate insulating layers 112 and 113 may have second openings OP2 and OP2'.

[0175] In addition, as shown in the accompanying drawings, a portion of the second buffer layer 111 can be removed together. According to some example embodiments, the total thickness of the gate insulating layers 112 and 113, the interlayer insulating layer ILD, and the portion of the second buffer layer 111 that are removed together when forming the contact hole CNT can be from about 7000 Å to about 11000 Å.

[0176] Referring Figure 7C , after forming the electrode layer E buried in the contact hole CNT, the electrode layer E can be etched using the photoresist pattern PR as a mask, and the source electrode S and / or the drain electrode D can be formed.

[0177] The source electrode S and the drain electrode D can include a conductive material containing Mo, Al, Cu, and Ti, and can have a single-layer or multi-layer structure including the above materials. According to some example embodiments, the source electrode S and the drain electrode D can have a multi-layer structure of Ti / Al / Ti.

[0178] After etching the electrode layer E, a step of cleaning the electrode layer E to remove by-products around the electrode layer E generated during the etching process can be included. At this time, when cleaning the electrode layer E, oxygen (O 2 ), and carbon tetrafluoride (CF 4 ), and carbon tetrafluoride (CF 4 ) can be used to remove inorganic layers such as the interlayer insulating layer ILD, the gate insulating layers 112 and 113, and the buffer layers 110 and 111.

[0179] According to some example embodiments, the ratio of oxygen (O 2 ) and carbon tetrafluoride (CF 4 ) can be close to each other, and a bias voltage can be applied.

[0180] As a comparative example, oxygen (O 2 ) and carbon tetrafluoride (CF 4 ) are used in the post-treatment operation of electrode layer etching. However, compared with oxygen (O 2 ), the amount of carbon tetrafluoride (CF 4 ) will be a very small amount. In this case, by-products around the electrode layer E generated during the etching process can be removed, but the buffer layer located in the transmission region will not be removed. That is, a separate mask process is required to etch the buffer layer located in the transmission region, which increases the cost and time.

[0181] In contrast, according to some example embodiments, in the post-treatment operation of electrode layer E etching, as conditions different from the comparative example, the ratio of oxygen (O 2 ) and carbon tetrafluoride (CF 4 ) can be close to each other, and a bias voltage can be applied.

[0182] In this case, the first part of the second interlayer insulating layer 115 (see Figure 7D 115a) can be protected by the photoresist pattern PR, while the second part of the second interlayer insulating layer 115 (see Figure 7D 115b) and the buffer layers 110 and 111 positioned in the first region AR1 can be etched with carbon tetrafluoride (CF 4 ). That is, a part of the second part 115b of the second interlayer insulating layer 115 can be etched, so that steps t1 and t1' can be provided, and the buffer layers 110 and 111 can have third openings OP3 and OP3' corresponding to the first region AR1.

[0183] Since the cleaning of the electrode layer E and the etching of the buffer layers 110 and 111 positioned in the first region AR1 can be performed simultaneously (or concurrently), costs and time can be reduced, and the top surface of the substrate 100 corresponding to the first region AR1 can be exposed, thereby ensuring transmittance as well.

[0184] Referring to Figure 7D , as described above in Figure 5A , the second interlayer insulating layer 115 can include a first part 115a and a second part 115b extending from the first part 115a, and the steps t1 and t1' can be provided by the difference between the thickness ta1 of the first part ILDa and the thickness tb1 of the second part ILDb.

[0185] Figure 7D It is shown that in the steps t1 and t1' of the first part 115a and the second part 115b of the second interlayer insulating layer 115, the step t1' of the part B' is greater than the step t1 of the part B.

[0186] As Figure 7C shown, like in the first interlayer insulating layer 114, the second interlayer insulating layer 115 can have a curved shape by the patterned gate electrode G. The part of the second interlayer insulating layer 115 can be etched using the photoresist pattern PR disposed on the electrode layer E. At this time, the etching thickness can be the same as the step t1 of the part B, but the curved shape can be reflected in the steps t1 and t1', such that the step t1 of the part B and the step t1' of the part B' can be different from each other.

[0187] According to some example embodiments, the step t1 of the part B and the step t1' of the part B' can be the same, such that the steps t1 and t1' of the first part 115a and the second part 115b of the second interlayer insulating layer 115 can be formed uniformly.

[0188] Referring to Figure 7E, a planarization layer 116 and an organic light-emitting diode OLED as a display element on the planarization layer 116 can be formed on the interlayer dielectric layer ILD.

[0189] The planarization layer 116 can have a single-layer or multi-layer structure of organic materials and / or inorganic materials. The planarization layer 116 can be a general polymer (such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethyl methacrylate (PMMA), or polystyrene), a polymer derivative having phenolic groups, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a parylene polymer, a polyvinyl alcohol polymer, and their blends. In addition, the planarization layer 116 can include silicon oxide (SiO 2 ), silicon nitride (SiN X ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), tantalum oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), or zinc oxide (ZnO). After forming the planarization layer 116, chemical mechanical polishing can be performed to provide a flat top surface.

[0190] According to some of the above exemplary embodiments of the present disclosure, a display device in which transmittance is ensured and a method of manufacturing the display device can be realized. The scope of the embodiments according to the present disclosure is not limited by these effects.

[0191] It should be understood that the embodiments described herein should be considered only in a descriptive sense and not for the purpose of limitation. The description of features or aspects within each embodiment should generally be considered available for other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the figures, those of ordinary skill in the art will understand that various changes in form and detail can be made therein without departing from the spirit and scope as defined by the claims and their equivalents.

Claims

1. A display device, the display device comprising: a semiconductor layer located on a substrate; a gate insulating layer located on the substrate and covering the semiconductor layer; a gate electrode located on the gate insulating layer and at least partially overlapping with the semiconductor layer; an interlayer insulating layer located on the gate electrode; an electrode layer located on the interlayer insulating layer and electrically connected to the semiconductor layer; a pixel electrode provided on the interlayer insulating layer and electrically connected to the electrode layer; and a pixel defining layer provided on an edge of the pixel electrode and exposing a center of the pixel electrode, wherein the interlayer insulating layer includes: a first portion; a second portion extending from the first portion and vertically overlapping with the center of the pixel electrode; and a third portion extending from the first portion and vertically overlapping with the pixel defining layer, the electrode layer is located on the first portion of the interlayer insulating layer, a first step is provided by a difference between a thickness of the first portion and a thickness of the second portion, a second step is provided by a difference between the thickness of the first portion and a thickness of the third portion, and the second step is larger than the first step.

2. The display device according to claim 1, wherein, the thickness of the first portion is greater than the thickness of the second portion, wherein a top surface of the second portion of the interlayer insulating layer is disposed at a higher level than a top surface of the third portion of the interlayer insulating layer, and wherein the third portion of the interlayer insulating layer does not vertically overlap with the center of the pixel electrode.

3. The display device according to claim 2, wherein, a width of a top surface of the first portion is greater than a width of a bottom surface of the electrode layer.

4. The display device according to claim 2, wherein, a width of a top surface of the first portion is the same as a width of a bottom surface of the electrode layer.

5. The display device according to claim 1, wherein, the interlayer insulating layer has a single-layer structure and includes silicon oxide.

6. The display device according to claim 1, wherein, the interlayer insulating layer includes a first interlayer insulating layer and a second interlayer insulating layer, and the first interlayer insulating layer and the second interlayer insulating layer are sequentially disposed on the gate electrode, wherein the second interlayer insulating layer includes the first portion and the second portion, and a thickness of the first portion of the second interlayer insulating layer is greater than a thickness of the second portion of the second interlayer insulating layer.

7. The display device according to claim 6, wherein, a top surface of the first interlayer insulating layer corresponding to the second portion of the second interlayer insulating layer is exposed.

8. The display device according to claim 1, wherein, the substrate includes a first region, a second region surrounding the first region, and a third region located between the first region and the second region, the interlayer insulating layer has a first opening corresponding to the first region, and the gate insulating layer has a second opening corresponding to the first region.

9. A method of manufacturing a display device, the method comprising: A buffer layer is formed on a substrate, the substrate including a first region, a second region surrounding the first region, and a third region located between the first region and the second region; A semiconductor layer is formed on the buffer layer; A gate insulating layer is formed to cover the semiconductor layer; A gate electrode is formed on the gate insulating layer such that the gate electrode at least partially overlaps with the semiconductor layer; An interlayer insulating layer is formed on the gate electrode; A contact hole is formed through the gate insulating layer and the interlayer insulating layer to expose a portion of the semiconductor layer; An electrode layer is formed on a first portion of the interlayer insulating layer, the electrode layer being electrically connected to the semiconductor layer through the contact hole; A photoresist pattern is formed on the electrode layer; The electrode layer is etched using the photoresist pattern as a mask; And While cleaning the electrode layer, a portion of the buffer layer in the first region is etched and a second portion of the interlayer insulating layer, which extends from the first portion of the interlayer insulating layer, is etched using the photoresist pattern.

10. The method according to claim 9, wherein, When forming the contact hole, the gate insulating layer and the interlayer insulating layer positioned on the first region are removed together.

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