Polar code decoding method and decoding device

Abstract

The present application provides a polar code decoding method and decoding device. Based on the SCL decoding algorithm for polar codes, the decoding end can improve the decoding performance of polar codes by rearranging the LLR sequence of the polar codes once or multiple times and calculating the decoding result based on the rearranged sequence.

Description

Technical Field

[0001] The present application relates to the field of channel coding, and more specifically, to a decoding method and decoding device for polar codes. Background Art

[0002] Polar code is currently the only channel coding technology that can be theoretically proven to reach the Shannon limit and has practical linear complexity coding and decoding capabilities. It is identified as the fifth generation. th The coding scheme for the control channel of the 5G (5G generation) communication system is proposed. The serial cancellation (SC) decoding algorithm is the most basic decoding algorithm for polar codes. When the code length approaches infinity, good asymptotic performance can be achieved. However, when the code length is medium or short, the performance of the SC decoding algorithm is not ideal. In order to improve the decoding performance of the SC decoding algorithm, the serial cancellation list (SCL) decoding algorithm was proposed. The SCL decoding algorithm introduces a breadth-first search strategy into the code tree search mechanism, and each decoding decision retains a very small list of candidate paths. Finally, the path with the highest likelihood probability is selected from the candidate path list as the decision path.

[0003] Cyclic redundancy check (CRC) is a channel error detection technique that has been widely used in practical digital communication systems. For polar codes, a set of candidate paths is obtained at the end of SCL decoding. This can be combined with CRC for detection and decoding with very low complexity. Candidate sequences that pass the CRC check are selected as the decoder output sequence, thereby improving the error correction capability of the decoding algorithm. Therefore, the CRC-aided SCL (CA-SCL) decoding algorithm has been proposed.

[0004] However, the decoding performance of the CA-SCL decoding algorithm is affected by the list size L. When L is small, the bit error rate is high, and the decoding performance remains suboptimal. Furthermore, according to the CA-SCL decoding algorithm, the decoder needs to sort 2L metric values ​​for each bit decoded. Increasing L to improve decoding performance rapidly increases the number of sorting operations, which in turn increases decoding delay and directly impacts decoder throughput. Therefore, how to reduce the bit error rate without increasing decoding delay to further improve the decoding performance of polar codes remains an open question. Summary of the Invention

[0005] The present application provides a polar code decoding method and apparatus, which can improve the decoding performance of polar codes.

[0006] In a first aspect, the present application provides a polar code decoding method, the method comprising: performing SCL decoding on an LLR sequence of the polar code to obtain a first estimated sequence of an information bit sequence; if the first estimated sequence fails a CRC, rearranging the LLR sequence j times to obtain a j-th rearranged sequence of the LLR sequence; determining a second estimated sequence of the information bit sequence based on the j-th rearranged sequence; and if the second estimated sequence passes the CRC, outputting the second estimated sequence as a decoding result, where j ≥ 1 and j is an integer.

[0007] In the technical solution of the present application, the decoding end first performs SCL decoding on the obtained log-likelihood ratio (LLR) sequence of the polar code to obtain an estimated value of the information bit sequence. If this estimated value cannot pass the CRC, the decoding end rearranges the LLR sequence to obtain a rearranged sequence of the LLR sequence. Based on the rearranged sequence, the decoding end re-determines the estimated value of the information bit sequence. If the estimated value of the information bit sequence determined according to the rearranged sequence can pass the CRC, the decoding end outputs the estimated value as the decoding result. If the estimated value of the information bit sequence determined according to the rearranged sequence cannot pass the CRC, the decoding end rearranges the LLR sequence again and re-determines the estimated value of the information bit sequence. This cycle is repeated until the estimated value of the information bit sequence determined according to a certain rearranged sequence passes the CRC, and the decoding is successful.

[0008] Based on the rearrangement characteristics of polar codes, by rearranging the LLR sequence, the bit error rate can be reduced and the decoding performance can be improved without increasing the list size L of the CA-SCL decoding algorithm.

[0009] Since L is not increased, there is no additional decoding delay and the throughput of the decoder is not affected.

[0010] It can be understood that the j-th rearranged sequence in this solution refers to a sequence obtained by performing the j-th rearrangement on the LLR sequence of the polar code, and may also be referred to as a sequence corresponding to the j-th rearrangement.

[0011] In this article, if the LLR sequence is rearranged for the jth time, it means that the estimated value of the information bit sequence determined based on the rearranged sequence obtained by the previous (j-1) rearrangements cannot pass the CRC.

[0012] For any rearrangement that does not pass CRC, the corresponding rearrangement sequence can be saved until the estimated value of the information bit sequence determined according to the rearrangement sequence obtained by the jth rearrangement (that is, the second estimated sequence) can pass CRC, and then the estimated value of the information bit sequence determined according to the rearrangement sequence obtained by the jth rearrangement is output as the decoding result.

[0013] Alternatively, after the first rearrangement, the decoding end obtains the first rearrangement sequence. If the estimated value of the information bit sequence determined according to the first rearrangement sequence cannot pass the CRC, a second rearrangement is performed, and the second rearrangement sequence obtained by the second rearrangement is used to cover the first rearrangement sequence. Similarly, if the estimated value of the information bit sequence determined according to the rearrangement sequence corresponding to the mth rearrangement cannot pass the CRC, the m+1th rearrangement is performed to obtain the m+1th rearrangement sequence, and the m+1th rearrangement sequence is used to cover the mth rearrangement sequence. Then, the estimated value of the information bit sequence is determined based on the m+1th rearrangement sequence, and it is determined whether the estimated value can pass the CRC, until the estimated value of the information bit sequence determined according to the rearrangement sequence corresponding to the jth rearrangement can pass the CRC. At this time, the decoding end saves the rearrangement sequence obtained by the jth rearrangement. Wherein, 1≤m≤j-1, j>1, and m is an integer.

[0014] It should be noted that, in this article, the numbering of the rearrangement sequence is only for the purpose of clearly describing the rearrangement process. Therefore, the rearrangement sequences corresponding to each rearrangement are numbered in sequence. For example, the rearrangement sequence corresponding to the mth rearrangement is called the mth rearrangement sequence, and the rearrangement sequence corresponding to the jth rearrangement is called the jth rearrangement sequence. However, for the decoding end, during the decoding process, the j rearrangement sequences obtained by the jth rearrangement can all be saved in the decoding process until the decoding is successful. Alternatively, the decoding end can also use the latter rearrangement sequence to overwrite the previous rearrangement sequence until the decoding is successful. In this case, the decoding end can only save the latest rearrangement sequence during the decoding process. When the estimated value of the information bit sequence determined according to the rearrangement sequence obtained by the jth rearrangement passes the CRC, the decoding end saves the rearrangement sequence obtained by the jth rearrangement, which can be specifically described as the above process.

[0015] Alternatively, during the decoding process, the decoding end only outputs the final decoding result without saving the rearranged sequence, which is not limited in this document.

[0016] In conjunction with the first aspect, in certain implementations of the first aspect, rearranging the LLR sequence j times includes:

[0017] (1) performing an m-th rearrangement on the LLR sequence to obtain an m-th rearranged sequence of the LLR sequence;

[0018] (2) determining an nth estimated sequence of the information bit sequence based on the mth rearranged sequence;

[0019] (3) determining whether the nth estimated sequence passes CRC;

[0020] (4) If the nth estimated sequence fails the CRC, set m=m+1, n=n+1, and return to (1), where 1≤m≤j-1, n≥1, j>1, and m and n are both integers.

[0021] In combination with the first aspect, in certain implementations of the first aspect, before performing j rearrangement on the LLR sequence, the method further includes: obtaining a set of rearrangement matrices of the LLR sequence, each rearrangement matrix in the set of rearrangement matrices being used to uniquely determine a rearrangement sequence of the LLR sequence; and, performing j rearrangement on the LLR sequence, including: using different rearrangement matrices in the set of rearrangement matrices for the m-th rearrangement and the q-th rearrangement of the LLR sequence, respectively, and obtaining different rearrangement sequences, wherein the m-th rearrangement and the q-th rearrangement refer to any two rearrangements of the LLR sequence, q≤j, and q is an integer.

[0022] In combination with the first aspect, in certain implementations of the first aspect, determining a second estimated sequence of the information bit sequence based on the j-th reordering sequence includes: determining an intermediate sequence based on the j-th reordering sequence; and obtaining the second estimated sequence based on the intermediate sequence, a generator matrix of a polar code, and a first reordering matrix in the set of reordering matrices, where the first reordering matrix is ​​different from a reordering matrix used in any of the previous (j-1) reorderings.

[0023] It should be noted that, in this document, the first permutation matrix refers to the permutation matrix used for the jth permutation. The first permutation matrix is ​​one of the set of permutation matrices. However, since each permutation uses one of the set of permutation matrices, the permutation matrices used in any two permutations are different. Therefore, for any permutation, the permutation matrix used only needs to be different from the permutation matrix used in any previous permutation.

[0024] With reference to the first aspect, in certain implementations of the first aspect, obtaining the second estimated sequence based on the intermediate sequence, a generator matrix of the polar code, and a first rearranged matrix in the set of rearranged matrices includes calculating the second estimated sequence according to the following formula:

[0025]

[0026] in, represents the second estimation sequence, represents the intermediate sequence, G represents a generator matrix of the polar code, and Q represents the first rearrangement matrix.

[0027] In combination with the first aspect, in certain implementations of the first aspect, obtaining a set of rearrangement matrices of the LLR sequence includes: representing the i-th bit in the codeword of the polar code as a binary vector b i , i≤N, N is the code length of the polar code; according to the rearrangement characteristics of the polar code, determine the binary vector b of the position index i' of the i-th bit in a set of rearranged code words i' , wherein the rearrangement characteristic of the polar code refers to a specific rearrangement of the bit positions of the polar code codeword, and the codeword obtained after the rearrangement is still the codeword of the polar code; according to the b i and the group b i' , and obtain the set of rearranged matrices.

[0028] In conjunction with the first aspect, in certain implementations of the first aspect, the b i and the group b i' Each b in i' Satisfies the following formula:

[0029] b i' =1-(P·(1-b i )+a)

[0030] Where P is a random reversible matrix and a is a constant vector.

[0031] In combination with the first aspect, in certain implementations of the first aspect, the i and the group b i' , obtaining the set of rearrangement matrices, including:

[0032] According to the b i and the group b i' Each b in i' , get each b i' The corresponding rearrangement function i'=p(i);

[0033] According to the set b i' The corresponding rearrangement functions i'=p(i) are used to obtain the set of rearrangement matrices.

[0034] In a second aspect, the present application provides a polar code decoding device, wherein the decoding device has the function of implementing the method of the first aspect or any possible implementation thereof. The function can be implemented by hardware or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above-mentioned functions.

[0035] In a third aspect, the present application provides a decoder comprising one or more processors coupled to one or more memories. The one or more memories are configured to store computer programs, and the one or more processors are configured to call and execute the computer programs stored in the one or more memories to perform the method of the first aspect or any possible implementation thereof.

[0036] Optionally, the chip may be a channel decoder.

[0037] In a fourth aspect, the present application provides a chip comprising one or more processors. The one or more processors are configured to read and execute computer programs stored in one or more memories to perform the method of the first aspect or any possible implementation thereof. The one or more memories are independently disposed outside the chip.

[0038] Optionally, the chip further includes one or more memories, and the one or more memories are connected to the one or more processors via circuits or wires.

[0039] Further optionally, the chip also includes a communication interface.

[0040] In a fifth aspect, the present application also provides a decoding device, comprising a processor and an interface circuit, wherein the interface circuit is used to receive computer code or instructions and transmit them to the processor, and the processor is used to run the computer code or instructions to execute the method in the first aspect or any possible implementation thereof.

[0041] In a sixth aspect, the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions. When the computer instructions are executed on a computer, the computer executes the method in the first aspect or any possible implementation thereof.

[0042] In a seventh aspect, the present application provides a computer program product, comprising computer program code, which, when executed on a computer, enables the computer to execute the method in the first aspect or any possible implementation thereof.

[0043] In an eighth aspect, the present application provides a communication device comprising the decoder described in the third aspect.

[0044] In a ninth aspect, the present application provides a wireless communication system, comprising the communication device described in the seventh aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 Schematic diagram of the architecture of a wireless communication system applicable to the present application.

[0046] Figure 2 Schematic diagram of the basic flow of wireless communication.

[0047] Figure 3 This is an example of the SCL decoding algorithm for L=2.

[0048] Figure 4 Flowchart of a polar code decoding method 300 provided in this application.

[0049] Figure 5 A flowchart of the polar code decoding method provided in this application is shown.

[0050] Figure 6 Schematic diagram of the system structure of CRC-polar cascade coding and decoding.

[0051] Figure 7 This is a simulation diagram of the BLER of the CA-SCL decoding algorithm and the polar code rearrangement decoding algorithm of this application.

[0052] Figure 8 This is a comparison chart of BLER between the polar code rearrangement decoding algorithm of this application and the CA-SCL decoding algorithm under the same number of decoding times.

[0053] Figure 9 This is a schematic diagram of a decoding device 900 provided in this application.

[0054] Figure 10 This is a schematic structural diagram of the decoding device 900 provided in this application.

[0055] Figure 11 1 is a schematic structural diagram of a decoder 1000 according to an embodiment of the present application. DETAILED DESCRIPTION

[0056] The technical solution in this application will be described below with reference to the accompanying drawings.

[0057] See also Figure 1 , Figure 1 FIG is a schematic diagram of the architecture of a wireless communication system applicable to the present application. Figure 1 As shown, the wireless communication system may include at least one network device 110 and at least one terminal device (eg, Figure 1 111, 112, and 113 shown in FIG. ). Network device 110 and terminal device communicate wirelessly. When network device 110 sends a signal to a terminal device, network device 110 acts as an encoder and the terminal device acts as a decoder. When a terminal device sends a signal to network device 110, the terminal device acts as an encoder and the network device acts as a decoder.

[0058] The wireless communication systems mentioned in the embodiments of the present application include but are not limited to: wireless local access network (WLAN) system, narrowband Internet of Things (NB-IoT) system, long term evolution (LTE) system, fifth generation (5G) system, th generation, 5G) communication system or communication system after 5G, etc.

[0059] The network device mentioned in this application can be any device with wireless transceiver functions. The network device includes but is not limited to: node B (NB), evolved node base (eNB) in the long term evolution (LTE) system, radio network controller (RNC), evolved LTE (eLTE) base station, next generation node B (gNB) in the 5G system, and can also be a base station controller (BSC), base transceiver station (BTS), access point (AP), wireless backhaul node, transmission point (TP), transmission and reception point (TRP), home node B (HNB), etc. Alternatively, it can also be a network node constituting a gNB or a transmission point, such as a baseband unit (BBU) or a distributed unit (DU), etc., which is not limited in this application.

[0060] The terminal device mentioned in this application may also be referred to as user equipment (UE), mobile station, access terminal, user unit, user station, mobile station, remote station, remote terminal, mobile device, terminal, wireless communication device, user agent, station (STA) in WLAN, cellular phone, cordless phone, session initiation protocol (SIP) phone, wireless local loop (WLL) station, personal digital assistant (PDA), handheld device with wireless communication function, computing device, other processing equipment connected to a wireless modem, vehicle-mounted device, wearable device, mobile station in 5G network and terminal device in the future evolved public land mobile network (PLMN) network, etc.

[0061] See also Figure 2 , Figure 2 The following is a basic flow chart of wireless communication. Figure 2 As shown in the figure, at the transmitter, the signal undergoes source coding, channel coding, and digital modulation before being transmitted. At the receiver, the received signal undergoes digital demodulation, channel decoding, and source decoding, and then outputs to the destination. Channel coding and decoding are core technologies in wireless communications. Currently, polar codes are a channel coding technique that has been theoretically proven to reach the Shannon limit and possesses practical linear complexity coding and decoding capabilities.

[0062] Polar codes are linear block codes. Among Polar code decoding algorithms, the serial cancellation (SC) decoding algorithm is the most basic. As the code length approaches infinity, the SC decoding algorithm achieves excellent asymptotic performance. With finite code lengths, due to the imperfect polarization channel, some information bits may still not be correctly decoded. According to the coding principle of polar codes, polarization channels are not independent but rather dependent on each other: a polarization channel with a higher channel number depends on all polarization channels with lower numbers. Based on this dependency between polarization channels, the SC decoding algorithm makes a decoding decision for each bit in ascending order of channel number. Furthermore, when making the decision for the i-th bit, it assumes that the decoding decisions for all the previous (i-1) bits were correct. As the code length approaches infinity, since the split channel approaches complete polarization (the channel capacity is either 0 or 1), every information bit is correctly decoded. However, with finite code lengths, some information bits may not be correctly decoded due to incomplete channel polarization. The SC decoding algorithm uses estimates of previous information bits when decoding subsequent information bits. Furthermore, the SC decoding algorithm is a greedy algorithm that searches for the optimal path at each level of the code tree before proceeding to the next level. Therefore, if the decoding of the first i-1 information bits is incorrect, it will result in severe error transmission.

[0063] To address the shortcomings of the SC decoding algorithm, the successive cancellation list (SCL) decoding algorithm was proposed. In the SCL decoding algorithm, the number of candidate paths allowed to be retained at each level of the code tree is increased, changing the SC decoding algorithm's principle of selecting only the best path for the next level to selecting the best path for the next level. Specifically, the SCL decoding algorithm begins at the root node of the decoding tree and searches for paths layer by layer toward the leaf nodes. Unlike SC, the SCL decoding algorithm uses a breadth-first search strategy, incorporating expansion and pruning into the code tree to ultimately reach the leaf nodes. At each level, the decoding decision maintains a small list of surviving paths, ultimately selecting the path with the highest likelihood from this list as the decision path. Given a list length L, the SCL decoding algorithm has a complexity of O(LNlogN), and its performance approaches that of maximum likelihood (ML) decoding.

[0064] See also Figure 3 , Figure 3 This is an example of the SCL decoding algorithm for L=2. Figure 3 As shown, assuming that the list size of the SCL decoding algorithm is L, when the decoding end performs SCL decoding, it starts from the root node of the code tree, retains L surviving paths at each layer, and enters the path expansion of the next layer until it reaches the leaf node of the code tree. When the SCL decoding of the polar code is completed, a set of candidate paths will be obtained. Finally, the decoding end selects the path with the best metric value from the L candidate paths as the decoding path output. It should be understood that in the code tree, the path formed from the root node to any node corresponds to a path metric (PM) value, and the PM value can be used as a reference for judging the quality of the path. The decoding end retains L candidate paths with reference to the PM value at each layer of the code tree. Therefore, according to the SCL decoding algorithm, the decoding process of the polar code is also Figure 3 Find the appropriate decoding path on the full binary tree shown in Figure 3 As shown in Figure 2, when the list size L of the SCL decoding algorithm is 2, starting from the root node, 2 candidate paths are retained at each layer and extended to the next layer until the leaf node is reached. Figure 3 As shown in the example, when the SCL decoding algorithm completes decoding, two candidate paths,

[0011] and

[1000] , are retained in the candidate list. Ultimately, the decoder selects the one with the best metric from these two candidate paths as the decoding path.

[0065] The CRC-aided-SCL (CA-SCL) decoding algorithm builds on the SCL decoding algorithm by adding CRC check bits to the information bit sequence. During decoding, the decoder uses the SCL decoding algorithm to obtain L candidate paths. Using the prior knowledge that the correct information bits can pass the CRC, the decoder selects these L candidate paths and outputs the optimal decoding path as the decoding result.

[0066] by Figure 3 As shown in the example, the decoding end inputs the two candidate paths retained into the CRC module for CRC, and outputs the candidate path that passes the CRC as the decoding result. Figure 3 The candidate path 0011 shown in passes the CRC, while the candidate

[1000] fails the CRC, then the candidate path

[0011] will be output as the decoding result.

[0067] Compared with the SCL decoding algorithm, the CA-SCL decoding algorithm can improve decoding performance with lower complexity. However, the bit error rate of the CA-SCL decoding algorithm still needs to be reduced.

[0068] Therefore, the present application provides a polar code decoding method, aiming to reduce the bit error rate of the CA-SCL decoding algorithm.

[0069] See also Figure 4 , Figure 4 This is a flowchart of a polar code decoding method 400 provided in this application. The method 400 can be executed by a decoding end (i.e., a decoding device), or can be executed by a device or component such as a chip or processing circuit installed in the decoding end that has the function of implementing the following method. Optionally, the decoding end can be Figure 1 The network device shown in may also be a terminal device.

[0070] 410. Perform SCL decoding on the LLR sequence of the polar code to obtain a first estimated sequence of the information bit sequence.

[0071] For the convenience of description, the LLR sequence obtained by the decoding end is denoted as y, and the information bit sequence is denoted as u.

[0072] According to the polar code encoding and decoding process, the encoder performs polar encoding on the information bit sequence to obtain a polar codeword (or polar code). The encoder sends the polar codeword to the decoder. The decoder demodulates the signal received on the polarized channel to obtain an LLR sequence (also known as a soft value sequence). Of course, the polar codeword obtained through polar encoding can also undergo modulation, mapping, and other channel coding processes, which are not detailed here.

[0073] The decoding end performs SCL decoding on y with a list size of L to obtain an estimated sequence of u, hereinafter referred to as the first estimated sequence.

[0074] Optionally, the specific value of the list size L is not limited.

[0075] In step 410, the process of performing SCL decoding of the LLR sequence with a list size of L can refer to the above introduction of the SCL decoding algorithm, for example Figure 3 , I will not go into details here.

[0076] 420. If the first estimated sequence fails CRC, rearrange the LLR sequence j times to obtain a j-th rearranged sequence of the LLR sequence.

[0077] It should be noted that in coding theory, the rearrangement property of a codeword refers to a specific rearrangement of the bit positions of a codeword of a code, and the codeword obtained after the rearrangement is still the codeword of this code.

[0078] Therefore, in step 420, the decoding end rearranges the LLR sequence, which means that the decoding end rearranges the bit positions in the LLR sequence. The LLR sequence after the rearrangement is called a rearranged sequence.

[0079] In step 420, j ≥ 1, where j is an integer. In other words, if the first estimated sequence fails the CRC, the LLR sequence can be rearranged one or more times. Each rearrangement of the LLR sequence yields a rearranged sequence. Therefore, after the jth rearrangement, the jth rearranged LLR sequence is obtained.

[0080] It should be noted that the j-th rearrangement of the LLR sequence is performed sequentially. After the j-1th rearrangement, the j-1th rearranged sequence of the LLR sequence is obtained. Whether to perform the j-th rearrangement depends on whether the estimated value of the information bit sequence obtained based on the j-1th rearranged sequence passes the CRC.

[0081] Specifically, based on the j-1th rearranged sequence, an estimate of the information bit sequence can be obtained. If the estimate passes the CRC, the decoder outputs it as the decoding result, and decoding ends. If the estimate fails the CRC and the number of decoding attempts has not reached the maximum number of set decoding attempts, the decoder needs to perform the jth rearrangement of the LLR sequence.

[0082] Therefore, if the LLR sequence is rearranged j times, it means that the estimated values ​​of the information bit sequence determined based on the rearranged sequence obtained by the previous (j-1) rearrangements all fail to pass the CRC.

[0083] For example, taking the mth rearrangement in the previous (j-1) rearrangements as an example, the LLR sequence is rearranged for the mth time to obtain a rearranged sequence. Based on the rearranged sequence, an estimated sequence of the information bit sequence is calculated. If the estimated sequence can pass the CRC, the estimated sequence is output as the decoding result, and the decoding ends. If the estimated sequence does not pass the CRC, the m+1th rearrangement is performed to obtain another rearranged sequence of the LLR sequence. Then, based on the rearranged sequence obtained from the m+1th rearrangement, another estimated sequence of the information bit sequence is calculated. If the further estimated sequence passes the CRC, the further estimated sequence is output as the decoding result. If the further estimated sequence does not pass the CRC, the next rearrangement is performed, and so on.

[0084] Of course, before each reordering, it is necessary to determine whether the current number of decoding times has reached the set maximum number of decoding times. If the current number of decoding times has not reached the set maximum number of decoding times, the next reordering will be continued. Otherwise, the decoding fails.

[0085] 430. Determine a second estimated sequence of the information bit sequence according to the jth rearranged sequence of the LLR sequence.

[0086] Here, the second estimated sequence refers to the jth rearranged sequence of the LLR sequence obtained by performing the jth rearrangement on the LLR sequence, and then determining the estimated sequence (or estimated value) of the information bit sequence based on the jth rearranged sequence.

[0087] In addition, the second estimation sequence is numbered to distinguish it from the first estimation sequence mentioned above and has no other special meaning.

[0088] It should also be noted that the decoding end performs j rearrangements on the LLR sequence, and each rearrangement will obtain a rearranged sequence of the LLR sequence. Furthermore, based on each rearranged sequence, an estimated value of the information bit sequence can be calculated. If the decoder performs the first (j-1) rearrangements and the estimated value of the information bit sequence calculated does not pass the CRC, the LLR sequence will be rearranged for the jth time to obtain the jth rearranged sequence, and another estimated value of the information bit sequence will be obtained based on the jth rearranged sequence. In this article, the estimated value of the information bit sequence calculated based on the jth rearranged sequence is referred to as the second estimated sequence.

[0089] The process of rearranging the LLR sequence mentioned in steps 420-430 and determining the estimated value of the information bit sequence based on the rearranged sequence will be described in detail below.

[0090] 440. When the second estimated sequence passes CRC, output the second estimated sequence as a decoding result.

[0091] As described above, based on the jth rearranged sequence, a second estimated sequence of the information bit sequence is calculated. If the second estimated sequence passes the CRC, the decoding end determines that the second estimated sequence is the best decoding path and outputs the second estimated sequence as the decoding result.

[0092] It can be understood that, in another case, if the second estimated sequence fails to pass the CRC, the j-th rearrangement is the same as any of the first (j-1) rearrangements described above, and the decoding end performs the j+1-th rearrangement on the LLR sequence, and so on, and no further details are given.

[0093] If, after the mth reordering, the estimated value of the information bit sequence determined based on the mth reordering sequence fails the CRC, and the current number of decoding attempts has reached the set maximum number of decoding attempts, the decoding end determines that the decoding has failed. If the estimated value of the information bit sequence determined based on the mth reordering sequence fails the CRC, and the current number of decoding attempts is less than the set maximum number of decoding attempts, the m+1th reordering is performed.

[0094] According to the above description, the polar code decoding method of the present application first performs SCL decoding on the LLR sequence to obtain an estimated value of the information bit sequence. If this estimated value cannot pass the CRC, the decoding end rearranges the LLR sequence to obtain a rearranged sequence of the LLR sequence. Based on the rearranged sequence, the decoding end re-determines the estimated value of the information bit sequence. If the estimated value of the information bit sequence determined based on the rearranged sequence can pass the CRC, the decoding end outputs the estimated value as the decoding result. If the estimated value of the information bit sequence determined based on the rearranged sequence cannot pass the CRC, the decoding end rearranges the LLR sequence again and re-determines the estimated value of the information bit sequence. This cycle continues until the estimated value of the information bit sequence determined based on a certain rearranged sequence passes the CRC, and the decoding is successful.

[0095] The following combination Figure 5 , giving an example of the detailed process of the decoding method proposed in this application.

[0096] like Figure 5 As shown, Figure 5 The flowchart of the polar code decoding method provided by the present application is shown. Figure 5 The process shown can be executed by the decoding end.

[0097] 510. Initialization.

[0098] Initialization mainly includes the initialization of the channel model. For example, the code length N of the polar code, the generator matrix G of the polar code, the length K of the information bit sequence, and the selection strategy of the information bit in the information bit sequence (denoted as u). n .

[0099] It should be understood that the information bit sequence u includes information bits and frozen bits.

[0100] In addition, step 510 may also include selection of a channel model, selection of a modulation method, etc.

[0101] For example, the channel type may be additive white Gaussian noise (AWGN), and the modulation method may be binary phase shift keying (BPSK).

[0102] Optionally, as an example, for an AWGN channel and BPSK modulation, the transmitted bit sequence may be x=1-2c, and the LLR sequence may be y=x+n, where n represents the AWGN noise sequence.

[0103] 520. Determine a set of rearrangement matrices Q of polar codes.

[0104] The rearrangement matrix is ​​used to rearrange the LLR sequence to obtain a rearranged sequence.

[0105] It is understood that different rearrangement schemes correspond to different rearrangement matrices Q. Therefore, there are multiple rearrangement matrices for the LLR sequence. In other words, the decoder needs to determine a set of rearrangement matrices Q for the polar code, each of which corresponds to a specific rearrangement scheme.

[0106] The number of rearrangement matrices is equal to the maximum number of rearrangement attempts preset by the decoder, which can be determined by the preset capability of the decoder.

[0107] Each time the decoder rearranges the LLR sequence, it must select a different rearrangement matrix from the previous one. In other words, when the decoder rearranges the LLR sequence for the jth time, it selects a different rearrangement matrix from the previous (j-1) rearrangements. This means that the jth rearranged sequence obtained from the jth rearrangement will be different from the j-1th rearranged sequence obtained from the previous (j-1) rearrangements.

[0108] For example, the above set of rearranged matrices can be represented as Q1, Q2, ..., Q j ,…,Q M . Use Q1 to rearrange the LLR sequence for the first time to get the first rearranged sequence. Use Q2 to rearrange the LLR sequence for the second time to get the second rearranged sequence. And so on, use Q j Perform the j-th rearrangement on the LLR sequence to obtain the j-th rearranged sequence.

[0109] In one implementation, the decoding end may calculate the rearrangement matrix of the polar code offline and store it in advance.

[0110] In another implementation, the decoding end may also calculate the rearrangement matrix of the polar code through online calculation.

[0111] Regardless of whether offline or online calculation is used, the calculation method of the rearrangement matrix can be the same, which is described in detail below.

[0112] Assume that the rearrangement function of the i-th bit in the codeword c of the polar code can be expressed as:

[0113] i'=p(i) (1)

[0114] Then, the rearranged codeword c' obtained according to the rearrangement function satisfies the following formula (2):

[0115] c'=(c p(0) ,c p(1) ,...,c p(N-1) ) (2)

[0116] Here is how to get the rearrangement function i'=p(i):

[0117] Assume that the binary vector of i is represented as the following formula (3):

[0118] b i =(b i,0 ,b i,1 ,...,b i,n-1 ) T (3)

[0119] The binary vector of i' is denoted as b i' , according to the rearrangement characteristics of polar codes, we can get:

[0120] b i' =1-(P(1-b i )+a) (4)

[0121] Where P is a random reversible matrix, a is a constant vector, and the size of P is equal to the code length N of the polar code.

[0122] Therefore, according to formula (4), the rearrangement process of the polar code can be expressed as i'=p(i).

[0123] Furthermore, according to the rearrangement process of the polar code i′=p(i), the rearrangement matrix Q of the polar code can be obtained, as shown in the following formula (5):

[0124] c'=c·Q (5)

[0125] 530. Decode according to a polar code rearrangement decoding algorithm.

[0126] As described above, in the technical solution of this application, the decoding end performs SCL decoding on the LLR sequence with a list size of L. If the estimated value of the information bit sequence obtained fails the CRC, it is necessary to re-determine the estimated value of the information bit sequence by rearranging the LLR sequence. Therefore, the polar code decoding algorithm provided in this application will be referred to as the polar code rearrangement decoding algorithm below.

[0127] The following describes in detail the reordering and decoding process of step 530 in conjunction with steps 531-537.

[0128] It should be understood that step 530 is a summary of steps 531-537, or in other words, steps 531-537 are a specific implementation of the polar code rearrangement decoding algorithm.

[0129] 531. Set the current decoding times j = 0, the maximum decoding times is J max .

[0130] 532. Perform SCL decoding of the LLR sequence y with a list size of L to obtain an estimated value of u And record j=j+1.

[0131] 533. Judgment Is it possible to pass CRC?

[0132] if If the CRC is passed, step 540 is executed.

[0133] if If the CRC fails, go to step 534.

[0134] 534. Determine whether j is less than or equal to J max .

[0135] If j is less than J max , then execute step 535, otherwise execute step 540.

[0136] 535. According to step 420, a rearrangement matrix Q of the polar code is obtained, and the LLR sequence y of the polar code is rearranged to obtain y'=y·Q.

[0137] It should be understood that y' is the rearranged sequence of the LLR sequence described above.

[0138] 536. Perform SCL decoding of the rearranged sequence y' with a list size of L to obtain

[0139] in, This is what is referred to as the intermediate sequence in this article.

[0140] It can be understood that, based on the rearrangement characteristics of the polar code described above, the encoding formula for the polar code is:

[0141] c=u·G (6)

[0142] According to the rearrangement matrix Q of the polarization code, c'=c·Q.

[0143] Assume that c'=u'G, where u' represents the rearranged information bit sequence corresponding to the rearranged codeword of the polar code.

[0144] In other words, the mapping relationship between the codeword c' obtained after the polar code rearrangement and the polar code generator matrix G can be expressed as c' = u'G (7)

[0145] If it is assumed that u' and u satisfy the following formula (8):

[0146] u'=uT (8)

[0147] And c'=cQ=uGQ=u'G=uTG, from which we can get:

[0148] T=GQG=u'G=uTG (9)

[0149] 537. Using formula (9) to get T, according to the formula get Return to step 433.

[0150] 540, Output As the decoding result.

[0151] The above describes in detail the decoding method of the polar code provided in this application.

[0152] Here is an example to help you understand.

[0153] For example, assuming that the indices of the bits in the codeword c of the polar code are i = 0, 1, 2, 3, 4, 5, 6, 7, respectively, if p(i) = 0, 2, 4, 6, 1, 3, 5, 7.

[0154] Then, the binary vector b of the position index of each bit in the codeword c is i' =(000,001,010,011,100,101,110,111), then the binary vector b of the position index of each bit in the code word c in a set of rearranged code words i' =(000,010,100,110,001,011,101,111).

[0155] In an example, one of the rearrangement matrices in the above set of rearrangement matrices can be expressed as formula (10):

[0156]

[0157] The matrix T can be expressed as formula (11):

[0158]

[0159] When applying channel coding technology in practice, many practical factors must be considered, such as efficiency, performance, and latency. Channel coding theory shows that as the code length N increases, the probability of decoding errors exponentially approaches zero. Therefore, to improve the effectiveness of error-correcting codes, long codes must be used. However, as the code length increases, the code rate decreases, and the complexity and computational effort of the decoder also increase. Concatenated codes were proposed to address this contradiction. They divide the encoding process into several stages, meeting the code length requirements of channel error correction, achieving error correction capabilities and high coding gain close to or even equal to those of long codes. Furthermore, the resulting increase in encoding and decoding complexity is not significant. In other words, if a system includes multiple (at least two) encoding steps, these steps are considered concatenated codes.

[0160] Concatenated coding involves outer code and inner code. The outer code input is the information bit sequence to be encoded, and the output of the outer code serves as the input for the inner code. The output of the inner code is the codeword after the concatenated coding is completed. For example, in CRC-polar concatenated coding, the outer code uses CRC coding, and the inner code uses polar coding. Figure 6 The basic flow of CA-SCL encoding and decoding is shown.

[0161] See also Figure 6 , Figure 6 Figure 1 is a schematic diagram of the system structure of CRC-polar cascade coding and decoding. Figure 6 As shown in the figure, when performing concatenated CRC and polar coding, assuming the code length of the polar code is N and the code length of the CRC is m, if the length of the polar code information bits is K and the length of the coded information bits is k, then K = k + m. The CA-SCL decoding algorithm first uses the SCL decoding algorithm to obtain L candidate paths. Then, using the prior information that "correct information bits can pass the CRC," it selects these L candidate paths and outputs the optimal decoding path.

[0162] It should be understood that the CA-SCL decoding algorithm is an enhancement of the SCL algorithm. The core of SCL remains unchanged, but a CRC is added to the information bits before Polar encoding. After SCL decoding obtains the candidate path, a CRC check is performed to assist in path selection, which can improve Polar decoding performance with lower complexity.

[0163] exist Figure 6 In the CA-SCL decoding shown, the rearrangement decoding algorithm provided by this application can be used.

[0164] See also Figure 7 , Figure 7 This is a simulation diagram of the BLER of the CA-SCL decoding algorithm and the polar code rearrangement decoding algorithm of this application. Figure 7In this paper, it is assumed that the polar code length N = 32, the information bit length K = 16, and the CRC bit sequence length is 8. The polar code is constructed using polar weight (PW) and the simulated channel is an AWGN channel. The polar code is reordered and decoded 50 times.

[0165] from Figure 7 It can be seen that under the condition that the list size L is the same (such as Figure 7 As shown in , L = 1, 2, 4), the block error rate (BLER) of the polar code reordering decoding algorithm of the present application is lower than the BLER of the CA-SCL decoding algorithm. Figure 7 The legend in the figure is CA-SCL permutation.

[0166] See also Figure 8 , Figure 8 This is a comparison chart of the BLER of the polar code rearrangement decoding algorithm and the CA-SCL decoding algorithm under the same number of decoding times. Figure 7 It can be found that when the average number of decoding times is the same, the BLER of the polar code rearrangement decoding algorithm is lower than the BLER of the CA-SCL decoding algorithm.

[0167] Simulation data shows that compared to traditional CA-SCL decoding, the polar code reordering decoding algorithm can achieve performance gains when the list size L remains the same. Furthermore, in terms of complexity, as the signal-to-noise ratio increases, the average number of decoding times required by the polar code reordering decoding algorithm of this application gradually decreases, approaching 1.

[0168] It can be seen that the polar code rearrangement decoding algorithm provided in this application can improve the decoding performance of polar codes.

[0169] The polar code rearrangement decoding algorithm provided by the present application has been described in detail above. The decoding device provided by the present application is described below.

[0170] See also Figure 9 , Figure 9 Schematic diagram of the decoding device 900 provided in this application. Figure 9 As shown, the decoding device 900 includes a processing unit 910 and a communication unit 920 .

[0171] The processing unit 910 is configured to perform SCL decoding on the LLR sequence to obtain a first estimated sequence of the information bit sequence;

[0172] The processing unit 910 is further configured to, if the first estimated sequence fails to pass the CRC, rearrange the LLR sequence j times to obtain a j-th rearranged sequence of the LLR sequence; and determine a second estimated sequence of the information bit sequence based on the j-th rearranged sequence;

[0173] The communication unit 920 is configured to output the second estimated sequence as a decoding result if the processing unit 910 determines that the second estimated sequence passes CRC.

[0174] Optionally, in one embodiment, the processing unit 910 is specifically configured to:

[0175] (1) performing an m-th rearrangement on the LLR sequence to obtain an m-th rearranged sequence of the LLR sequence;

[0176] (2) determining an nth estimated sequence of the information bit sequence based on the mth rearranged sequence;

[0177] (3) determining whether the nth estimated sequence passes CRC;

[0178] (4) If the nth estimated sequence fails the CRC, set m=m+1, n=n+1, and return to (1), where 1≤m≤j-1, n≥1, j>1, and m and n are both integers.

[0179] Optionally, in one embodiment, the processing unit 910 is specifically configured to:

[0180] A set of rearrangement matrices of the LLR sequence is obtained, each rearrangement matrix in the set of rearrangement matrices is used to uniquely determine a rearrangement sequence of the LLR sequence; and the performing of j rearrangements on the LLR sequence includes: using different rearrangement matrices in the set of rearrangement matrices for the m-th rearrangement and the q-th rearrangement of the LLR sequence, respectively, to obtain different rearrangement sequences, wherein the m-th rearrangement and the q-th rearrangement refer to any two rearrangements of the LLR sequence, q≤j, and q is an integer.

[0181] Optionally, in one embodiment, the processing unit 910 is specifically configured to:

[0182] Determining an intermediate sequence according to the j-th rearranged sequence;

[0183] The second estimated sequence is obtained according to the intermediate sequence, a generator matrix of the polar code, and a first rearrangement matrix in the set of rearrangement matrices, wherein the first rearrangement matrix is ​​different from a rearrangement matrix used in any of the previous (j-1) rearrangements.

[0184] Optionally, in one embodiment, the processing unit 910 is specifically configured to:

[0185] The second estimated sequence is calculated according to the following formula:

[0186]

[0187] in, represents the second estimation sequence, represents the intermediate sequence, G represents a generator matrix of the polar code, and Q represents the first rearrangement matrix.

[0188] Optionally, the processing unit 910 is specifically configured to:

[0189] The i-th bit in the codeword of the polar code is represented as a binary vector b i , i≤N, N is the code length of the polar code;

[0190] According to the rearrangement characteristics of the polar code, the binary vector b of the position index i' of the i-th bit in a set of rearranged code words is determined. i' , wherein the rearrangement characteristic of the polar code refers to performing a specific rearrangement on the bit positions of the polar code codeword, and the codeword obtained after the rearrangement is still the codeword of the polar code;

[0191] According to the b i and the group b i' , and obtain the set of rearranged matrices.

[0192] Optionally, in one embodiment, the b i and the group b i' Each b in i' Satisfies the following formula:

[0193] b i' =1-(P·(1-b i )+a)

[0194] Where P is a random reversible matrix and a is a constant vector.

[0195] Optionally, in one embodiment, the processing unit 910 is specifically configured to:

[0196] According to the b i and the group b i' Each b in i' , get each b i' The corresponding rearrangement function i'=p(i);

[0197] According to the set b i' The corresponding rearrangement functions i'=p(i) are used to obtain the set of rearrangement matrices.

[0198] In one possible design, the above functions of the decoding device 900 can be implemented through hardware, or through hardware executing corresponding software implementation.

[0199] As an embodiment, the decoding device 900 may include one or more processors, and the one or more processors are used to execute a computer program stored in a memory, so that the decoding device 900 performs any one of the method embodiments provided in this application.

[0200] Optionally, the memory for storing the computer program is located outside the decoding device 900, and the one or more processors are connected to the memory via circuits and / or wires. There may be one or more memories.

[0201] Optionally, the decoding device 900 further includes one or more memories.

[0202] Further optionally, the decoding device 900 further includes one or more communication interfaces.

[0203] As some examples, the one or more communication interfaces may be input / output interfaces, or input / output circuits, which is not limited in this application.

[0204] As another embodiment, the decoding device 900 may also be implemented by hardware.

[0205] See also Figure 10 , Figure 10 This is a schematic structural diagram of the decoding device 900 provided in this application. Figure 10 As shown, the decoding device 900 includes an input interface circuit 901 , a logic circuit 902 and an output interface circuit 903 .

[0206] The input interface circuit 901 is used to obtain an LLR sequence; the logic circuit 902 is used to decode the LLR sequence using the polar code rearrangement decoding algorithm provided in this application; and the output interface circuit 903 is used to output the decoding result.

[0207] Optionally, the decoding device 900 may be a chip or an integrated circuit. For example, the chip may be a system on chip (SOC) or a baseband chip.

[0208] Optionally, the decoding device 900 may also be a device or module in a decoding end for implementing channel decoding, such as a channel decoder or a channel decoding circuit.

[0209] Figure 11 Schematic diagram of the structure of the decoder 1000 according to the embodiment of the present application. Figure 11As shown, decoder 1000 includes: one or more processors 1100, one or more memories 1200, and one or more communication interfaces 1300. Communication interface 1300 is used to obtain an LLR sequence, memory 1200 is used to store a computer program, and processor 1100 is used to call and execute the computer program from memory 1200, so that decoder 1000 uses the polar code rearrangement decoding method provided in this application to complete decoding of the LLR sequence.

[0210] Furthermore, the communication interface 1300 is also used to output the decoding result.

[0211] in addition, Figure 9 The decoding device 900 shown in FIG can be Figure 11 The decoder 1000 shown in FIG.

[0212] For example, the communication unit 930 may be composed of Figure 11 The communication interface 1300 in the embodiment is implemented, the processing unit 910 can be implemented by the processor 1100, etc.

[0213] Optionally, the memory and processor in the device embodiment may be integrated together, or may be physically separate units.

[0214] In addition, the present application also provides a decoding device, including a processor and an interface circuit, wherein the interface circuit is used to receive computer code or instructions and transmit them to the processor, and the processor is used to run the computer code or instructions to perform the polar code rearrangement decoding method provided in the present application.

[0215] In addition, the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed on a computer, the polar code rearrangement decoding method of the present application is implemented.

[0216] The present application also provides a computer program product, which includes computer program code. When the computer program code is executed on a computer, the polar code rearrangement decoding method of the present application is implemented.

[0217] The present application also provides a chip, comprising one or more memories and one or more processors. The one or more memories are used to store computer programs, and the one or more processors are used to call and execute the computer programs from the one or more memories, so that a device equipped with the chip executes the polar code rearrangement decoding method of the present application.

[0218] The present application also provides a communication device, including the above-mentioned decoder 1000.

[0219] The decoding end in this article is also the receiving end of signals and / or data. Correspondingly, the party that sends signals and / or data is the transmitting end. Optionally, the decoding end can be a network device in the communication system (for example, a 5G gNB) or a terminal device, and the solution of this application is not limited to this.

[0220] In the above embodiments, the processor may be a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, a microprocessor, or one or more integrated circuits for controlling the execution of the program of the present application. For example, the processor may include a digital signal processor device, a microprocessor device, an analog-to-digital converter, a digital-to-analog converter, etc. The processor may distribute the control and signal processing functions of the mobile device among these devices according to their respective functions. In addition, the processor may include the function of operating one or more software programs, which may be stored in a memory. The functions of the processor may be implemented by hardware or by hardware executing corresponding software implementations. The hardware or software includes one or more units corresponding to the above functions.

[0221] The memory may be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, an optical disc storage (including compact discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer.

[0222] As used in this specification, the terms "component," "module," "system," and the like are used to refer to computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. Both applications running on a computing device and a computing device can be components. One or more components can reside in a process and / or an execution thread. Components can be located on a computer and / or distributed between two or more computers. In addition, these components can be executed from various computer-readable media having various data structures stored thereon. Components can communicate through local and / or remote processes based on signals having one or more data packets (e.g., data from two components interacting with another component across a local system, a distributed system, and / or a network, such as the Internet interacting with other systems via signals).

[0223] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented using electronic hardware, or a combination of computer software and electronic hardware, depending on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application.

[0224] In the several embodiments provided in this application, the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0225] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected according to actual needs to achieve the objectives of the embodiments of the present application.

[0226] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0227] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application.

[0228] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A polar code decoding method, characterized in that: include: Performing serial cancellation list (SCL) decoding on the log-likelihood ratio (LLR) sequence of the polar code to obtain a first estimated sequence of the information bit sequence; If the first estimated sequence fails a cyclic redundancy check (CRC), rearrange the LLR sequence j times to obtain a j-th rearranged sequence of the LLR sequence; performing the SCL decoding on the j-th rearranged sequence to determine a second estimated sequence of the information bit sequence; In a case where the second estimated sequence passes the CRC, the second estimated sequence is output as a decoding result, where j≥1 and j is an integer.

2. The method according to claim 1, characterized in that The step of rearranging the LLR sequence j times includes: (1) performing an m-th rearrangement on the LLR sequence to obtain an m-th rearranged sequence of the LLR sequence; (2) determining an nth estimated sequence of the information bit sequence based on the mth rearranged sequence; (3) determining whether the nth estimated sequence passes CRC; (4) If the nth estimated sequence fails the CRC, set m=m+1, n=n+1, and return to (1), where 1≤m≤j-1, n≥1, j>1, and m and n are both integers.

3. The method according to claim 1 or 2, characterized in that Before rearranging the LLR sequence j times, the method further includes: Obtaining a set of rearrangement matrices of the LLR sequence, wherein each rearrangement matrix in the set of rearrangement matrices is used to uniquely determine a rearrangement sequence of the LLR sequence; And, rearranging the LLR sequence j times includes: For the m-th rearrangement and the q-th rearrangement of the LLR sequence, different rearrangement matrices in the set of rearrangement matrices are respectively used to obtain different rearrangement sequences, wherein the m-th rearrangement and the q-th rearrangement refer to any two rearrangements of the LLR sequence, q≤j, and q is an integer.

4. The method according to claim 3, characterized in that The performing the SCL decoding on the j-th rearranged sequence to obtain a second estimated sequence of the information bit sequence includes: Determine an intermediate sequence according to the j-th rearranged sequence, wherein the intermediate sequence is an output result obtained by decoding the j-th rearranged sequence using a serial cancellation list (SCL) decoding algorithm; The second estimated sequence is obtained according to the intermediate sequence, a generator matrix of the polar code, and a first rearrangement matrix in the set of rearrangement matrices, wherein the first rearrangement matrix is ​​different from a rearrangement matrix used in any of the previous (j-1) rearrangements.

5. The method according to claim 4, characterized in that The obtaining the second estimated sequence according to the intermediate sequence, a generator matrix of a polar code, and a first rearrangement matrix in the set of rearrangement matrices includes: The second estimated sequence is calculated according to the following formula: in, represents the second estimation sequence, represents the intermediate sequence, G represents a generator matrix of the polar code, and Q represents the first rearrangement matrix.

6. The method according to claim 3, characterized in that Obtaining a set of rearrangement matrices of the LLR sequence, comprising: The i-th bit in the codeword of the polar code is represented as a binary vector b i , i≤N, N is the code length of the polar code; According to the rearrangement characteristics of the polar code, the binary vector b of the position index i' of the i-th bit in a set of rearranged code words is determined. i' , wherein the rearrangement characteristic of the polar code refers to performing a specific rearrangement on the bit positions of the codeword of the polar code, and the codeword obtained after the rearrangement is still the codeword of the polar code; According to the b i and the group b i' , and obtain the set of rearranged matrices.

7. The method according to claim 6, characterized in that The b i and the group b i' Each b in i' Satisfies the following formula: b i' =1-(P·(1-b i )+a) Where P is a random reversible matrix and a is a constant vector.

8. The method according to claim 7, characterized in that According to the b i and the group b i' , obtaining the set of rearrangement matrices, including: According to the b i and the group b i' Each b in i' , get each b i' The corresponding rearrangement function i'=p(i); According to the set b i' The corresponding rearrangement functions i'=p(i) are used to obtain the set of rearrangement matrices.

9. A decoding device, characterized in that: include: A processing unit for: Performing serial cancellation list (SCL) decoding on the LLR sequence of the polar code to obtain a first estimated sequence of the information bit sequence; If the first estimated sequence fails a cyclic redundancy check (CRC), rearrange the LLR sequence j times to obtain a j-th rearranged sequence of the LLR sequence; performing the SCL decoding on the j-th rearranged sequence to determine a second estimated sequence of the information bit sequence, and determining whether the second estimated sequence passes CRC; and A communication unit is configured to output the second estimated sequence as a decoding result if the processing unit determines that the second estimated sequence passes CRC, wherein j≥1 and j is an integer.

10. The decoding device according to claim 9, characterized in that The processing unit is used for: (1) performing an m-th rearrangement on the LLR sequence to obtain an m-th rearranged sequence of the LLR sequence; (2) determining an nth estimated sequence of the information bit sequence based on the mth rearranged sequence; (3) determining whether the nth estimated sequence passes CRC; (4) If the nth estimated sequence fails the CRC, set m=m+1, n=n+1, and return to (1), where 1≤m≤j-1, n≥1, j>1, and m and n are both integers.

11. The decoding device according to claim 9 or 10, characterized in that: The processing unit is used for: Obtaining a set of rearrangement matrices of the LLR sequence, wherein each rearrangement matrix in the set of rearrangement matrices is used to uniquely determine a rearrangement sequence of the LLR sequence; And, the processing unit is further configured to: For the m-th rearrangement and the q-th rearrangement of the LLR sequence, different rearrangement matrices in the set of rearrangement matrices are respectively used to obtain different rearrangement sequences, wherein the m-th rearrangement and the q-th rearrangement refer to any two rearrangements of the LLR sequence, q≤j, and q is an integer.

12. The decoding device according to claim 11, wherein: The processing unit is used for: Determine an intermediate sequence according to the j-th rearranged sequence, wherein the intermediate sequence is an output result obtained by decoding the j-th rearranged sequence using a serial cancellation list (SCL) decoding algorithm; The second estimated sequence is obtained according to the intermediate sequence, a generator matrix of the polar code, and a first rearrangement matrix in the set of rearrangement matrices, wherein the first rearrangement matrix is ​​different from a rearrangement matrix used in any of the previous (j-1) rearrangements.

13. The decoding device according to claim 12, wherein: The processing unit is specifically configured to calculate the second estimated sequence according to the following formula: in, represents the second estimation sequence, represents the intermediate sequence, G represents a generator matrix of the polar code, and Q represents the first rearrangement matrix.

14. The decoding device according to claim 11, wherein: The processing unit is specifically configured to: The i-th bit in the codeword of the polar code is represented as a binary vector b i , i≤N, N is the code length of the polar code; According to the rearrangement characteristics of the polar code, the binary vector b of the position index i' of the i-th bit in a set of rearranged code words is determined. i' , wherein the rearrangement characteristic of the polar code refers to performing a specific rearrangement on the bit positions of the codeword of the polar code, and the codeword obtained after the rearrangement is still the codeword of the polar code; According to the b i and the group b i' , and obtain the set of rearranged matrices.

15. The decoding device according to claim 14, characterized in that The b i and the group b i' Each b in i' Satisfies the following formula: b i' =1-(P·(1-b i )+a) Where P is a random reversible matrix and a is a constant vector.

16. The decoding device according to claim 15, wherein: The processing unit is used for: According to the b i and the group b i' Each b in i' , get each b i' The corresponding rearrangement function i'=p(i); According to the set b i' The corresponding rearrangement functions i'=p(i) are used to obtain the set of rearrangement matrices.

17. A decoding device, characterized in that: The device comprises at least one processor coupled to at least one memory, and is configured to execute a computer program or instruction stored in the at least one memory, so that the decoding device performs the method according to any one of claims 1 to 8.

18. A decoding device, characterized in that: The system comprises a processor and an interface circuit, wherein the interface circuit is used to receive computer codes or instructions and transmit the instructions to the processor, and the processor is used to run the computer codes or instructions to execute the method according to any one of claims 1 to 8.

19. A computer-readable storage medium, characterized in that The invention comprises a computer program, and when the computer program is run on a computer, the method according to any one of claims 1 to 8 is implemented.

20. A computer program product, characterized in that The method comprises instructions for executing the method according to any one of claims 1 to 8.

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