Conductive pattern forming method

Abstract

The present application discloses a conductive pattern forming method. The conductive pattern forming method according to an embodiment includes: forming a first conductive pattern on a substrate; sequentially forming a release layer and a conductive layer on a transfer substrate including a mask; irradiating intense pulsed light (IPL) to the substrate in which the first conductive pattern is formed; placing the transfer substrate on the substrate; transferring a portion of the conductive layer corresponding to the opening of the mask to the substrate by irradiating the IPL to the transfer substrate to form a second conductive pattern on the substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0169822 filed on December 18, 2019, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a conductive pattern forming method and a display device including the conductive pattern, and more particularly, the present disclosure relates to a method for forming a minute conductive pattern and a display device including the conductive pattern. Background Art

[0004] A display device, such as a light-emitting display device, a liquid crystal display (LCD), etc., includes a display panel that displays an image. The display panel may be manufactured by forming several layers and elements on a substrate.

[0005] The display panel may include a display area through which an image is displayed and a non-display area in which a driving circuit, a signal line, etc. are disposed. Since a wider screen can be provided as the non-display area is reduced, efforts are being made to reduce the non-display area. However, miniaturization of conductive patterns (such as wiring or pads) in the non-display area may lead to deterioration in the reliability of the display device. Summary of the invention

[0006] Embodiments have been made in an effort to provide a method of forming a minute conductive pattern, and a display device including such a conductive pattern.

[0007] According to an embodiment, a conductive pattern forming method includes: sequentially forming a release layer and a conductive layer on a transfer substrate including a mask; irradiating intense pulsed light (IPL) to the substrate; placing the transfer substrate on the substrate; and transferring a portion of the conductive layer corresponding to the opening of the mask to the substrate by irradiating the IPL to the transfer substrate to form a conductive pattern on the substrate.

[0008] The conductive layer may be formed by applying a metal paste or a metal ink.

[0009] The conductive layer may be a metal layer.

[0010] The release layer may be a dynamic release layer.

[0011] The conductive pattern may be a conductive layer corresponding to the opening of the mask.

[0012] Placing the transfer substrate on the substrate may include placing a surface of the transfer substrate on which the conductive layer is located to face the substrate.

[0013] The conductive pattern forming method may further include sintering the conductive pattern by irradiating the IPL to the substrate in which the conductive pattern is formed.

[0014] The conductive pattern may have a width of about 10 μm or less, and a thickness of about 10% or more of the width.

[0015] According to an embodiment, a conductive pattern forming method includes: forming a first conductive pattern on a substrate; sequentially forming a release layer and a conductive layer on a transfer substrate including a mask; irradiating intense pulsed light (IPL) to the substrate in which the first conductive pattern is formed; placing the transfer substrate on the substrate; and transferring a portion of the conductive layer corresponding to the opening of the mask to the substrate by irradiating the IPL to the transfer substrate to form a second conductive pattern on the substrate.

[0016] The conductive layer may be formed by applying a metal paste or metal ink, or by metal deposition.

[0017] The release layer may be a dynamic release layer.

[0018] The second conductive pattern may be a conductive layer corresponding to the opening of the mask.

[0019] Placing the transfer substrate on the substrate may include placing a surface of the transfer substrate on which the conductive layer is located to face the substrate.

[0020] The conductive pattern forming method may further include sintering the conductive pattern by irradiating the IPL to the substrate in which the second conductive pattern is formed.

[0021] The first conductive pattern may be a terminal electrode or a wiring, and the second conductive pattern may be a bump.

[0022] The conductive pattern may have a width of 10 μm or less, and a thickness of about 10% or more of the width.

[0023] According to an embodiment, a minute conductive pattern having a predetermined thickness may be formed, and a display device including the minute conductive pattern may be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a side view of a display device according to an embodiment.

[0025] Figure 2 is a side view of a display device according to an embodiment.

[0026] Figure 3 yes Figure 2 A top view of the display device shown in FIG.

[0027] Figure 4 , Figure 5 and Figure 6 A conductive pattern forming method according to an embodiment is shown.

[0028] Figure 7 , Figure 8 , Fig. 9 , Fig.10 , Fig.11 and Fig.12 A conductive pattern forming method according to an embodiment is shown.

[0029] Fig.13 and Fig.14 A conductive pattern forming method according to an embodiment is shown.

[0030] Fig.15 is a cross-sectional view of a display device according to an embodiment.

[0031] Fig.16 is a cross-sectional view of a display device according to an embodiment. DETAILED DESCRIPTION

[0032] The present invention will be described more fully below with reference to the accompanying drawings, in which embodiments of the present invention are shown. As will be appreciated by those skilled in the art, the described embodiments may be modified in various different ways without departing from the spirit or scope of the present invention.

[0033] The drawings and description should be regarded as illustrative in nature and not restrictive. Like reference numerals refer to like elements throughout the specification.

[0034] Further, in the drawings, for better understanding and ease of description, the size and thickness of each element are arbitrarily indicated, but the inventive concept is not limited thereto. In the drawings, for clarity, the thickness of layers, films, panels, regions, etc. are exaggerated. In addition, in the drawings, for better understanding and ease of description, the thickness of some layers and regions are exaggerated.

[0035] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements.

[0036] In addition, unless explicitly described to the contrary, the word “comprise” and variations such as “comprises” or “comprising” will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

[0037] In the drawings, symbol "x" is used to indicate a first direction, symbol "y" indicates a second direction perpendicular to the first direction, and symbol "z" indicates a third direction perpendicular to the first direction and the second direction. The first direction x, the second direction y, and the third direction z may correspond to a horizontal direction, a vertical direction, and a thickness direction of the electronic device, respectively.

[0038] Unless otherwise specified in the specification, “overlap” refers to overlap in the third direction z in a plan view.

[0039] Figure 1 is a side view of a display device according to an embodiment.

[0040] refer to Figure 1 , a display device 1 according to an embodiment includes a display panel 10. The display panel 10 includes a display area DA in which an image is displayed, and a non-display area NA which is disposed at the periphery of the display area DA and in which elements and / or wirings for generating and / or transmitting various signals applied to the display area DA are formed.

[0041] A plurality of pixels (PX) are arranged in a display area DA, for example, in a matrix format. Signal lines (such as gate lines (not shown), data lines (not shown), etc.) are also arranged in the display area DA. The data lines can extend substantially in a first direction x (i.e., the column direction), and the gate lines can extend substantially in a second direction y (i.e., the row direction) intersecting with the first direction x. Each pixel (PX) is connected to the gate line and the data line, and a gate signal and a data voltage (also referred to as a data signal) can be received from the signal line. In the case of a light-emitting display device, a driving voltage line for transmitting a driving voltage to a pixel can be arranged in the display area DA, and a light emission control line for transmitting a light emission control signal and / or an initialization voltage line for transmitting an initialization voltage can be further arranged in the display area DA.

[0042] The display panel 10 may include a touch electrode (also referred to as a touch sensor layer) for sensing a contact touch or a non-contact touch of a user, and the touch electrode may be mainly located in the display area DA.

[0043] The display panel 10 may include a first substrate 100 and a second substrate 200. When the display device 1 is provided as a liquid crystal display (LCD), a liquid crystal layer may be provided between the first substrate 100 and the second substrate 200. When the display device 1 is provided as a light-emitting display device, a light-emitting diode may be provided between the first substrate 100 and the second substrate 200.

[0044] A pad portion PP, in which the pad P is arranged to receive a signal from the outside of the display panel 10, may be located at a side surface of the display panel 10. The pad P of the pad portion PP may be connected to a signal line 101, which may be located between the first substrate 100 and the second substrate 200 in the non-display area NA. Thus, a signal input to the pad P may be transmitted to the signal line 101 provided in the display panel 10. The signal line 101 may be connected to a signal line 102 of the display area DA, or may be an extension of the signal line 102 of the display area DA.

[0045] The pad P may be located on at least one of the side surface of the first substrate 100 and the side surface of the second substrate 200. In the illustrated embodiment, the pad P includes a portion located at the side surface of the first substrate 100 and includes a portion extending onto the top surface of the first substrate 100 to connect with the signal line 101.

[0046] The display device 1 may include a printed circuit film 20 bonded to the pad portion PP. The printed circuit film 20 may include a lead portion LP in which leads are arranged, and the leads L of the lead portion LP may be electrically connected to the pads P of the pad portion PP. One end of the printed circuit film 20 is connected to a printed circuit board (not shown) or the like to receive signals such as image data, a drive signal, a drive voltage, and the like. The printed circuit film 20 may be flexible and may be bent so that most of the printed circuit film 20 (excluding the lead portion LP) may be located at the rear side of the display panel 10. As described, when the pad portion PP is located at the side surface of the display panel 10 and the printed circuit film 20 is bonded to the side surface of the display panel 10, a non-display area NA for bonding the printed circuit film 20 is not required, thereby reducing the frame of the display device 1.

[0047] A driving device that generates and / or processes various signals for driving the display panel 10 may be located on the printed circuit film 20 or the non-display area NA. The driving device may include a data driver that applies a data voltage to a data line, a gate driver that applies a gate signal to a gate line, and a signal controller that controls the data driver and the gate driver.

[0048] The data driver may be provided as an IC chip 30. The IC chip 30 may be located on the printed circuit film 20. Figure 1As shown in , the printed circuit film 20 may be bent, and the IC chip 30 may be located on the rear side of the display panel 10. The gate driver may be integrated as a driving circuit on the non-display area NA of the display panel 10. The gate driver may be provided in the form of an IC chip, and in this case, the gate driver may be provided on the printed circuit film, and the printed circuit film may be bonded to the display panel 10. The signal controller may be provided in the form of an IC chip, and may be located on a printed circuit board connected to the printed circuit film 20.

[0049] Figure 2 is a side view of a display device according to an exemplary embodiment.

[0050] and Figure 1 In different implementations, Figure 2 In the embodiment of the present invention, the printed circuit film 20 is bonded to the rear side of the display panel 10. To this end, the pad P includes a first portion, which is disposed on the rear surface of the first substrate 100, adjacent to one edge of the first substrate 100; a second portion, which is disposed on the side surface of the first substrate 100; and a third portion, which is disposed on the top surface of the first substrate 100. As described, when the printed circuit film 20 is bonded to the rear side of the display panel 10, the pad P is bonded to the rear side of the display panel 10. Figure 1 Compared with the embodiment of FIG. 1 , the width of the non-display area NA can be further reduced by at least the thickness of the printed circuit film 20 .

[0051] Figure 3 for Figure 2 A top view of the display device 1 is shown in FIG.

[0052] Figure 3 Shows Figure 2 The periphery of the pad portion PP in the display device 1. Figure 1 In addition to the printed circuit film 20 in the display device 1, Figure 3 The display device 1 may have Figure 1 The display device 1 has the same planar structure.

[0053] In order to correspond to high resolution, it is necessary to increase the number of signals transmitted to the display panel 10, so that the number of pads P also needs to be increased. It is required to reduce the pad pitch p to increase the number of pads P in the limited area of ​​the pad portion PP. For example, the pad pitch p may be about 20 μm or less, or about 10 μm or less. For such a pad pitch p, the pad width w may be about 10 μm or less or about 5 μm or less, and the pad gap s may be about 10 μm or less or about 5 μm or less. The pad thickness t may be about 10% or more, about 20% or more, or about 30% or more of the pad width w. For example, when the pad width w is 10 μm, the pad thickness t may be 1 μm or more.

[0054] It may be difficult to form the pad P to surround the side surface of the display panel 10 by a typical method including forming a conductive layer and then patterning the conductive layer by a photolithography process. The pad P may be formed by printing and drying an inkjet method using a conductive ink. When the pad P is formed by using an inkjet method, the pad width w may be determined by the amount of ink droplets discharged from the inkjet nozzle. For example, when a pad P having a pad width w less than about 10 μm is formed, the amount of ink droplets needs to be reduced, and then the pad thickness t becomes too thin to be used as a pad or wiring. Therefore, in order to reduce resistance and improve reliability, the pad thickness t needs to be greater than a certain level, for example, greater than 10% of the pad width w, and for this purpose, printing may be repeated tens to hundreds of times at the same location to form a pad P with a thickness greater than a certain level. However, this method has the problem of increasing process time and requiring complex equipment.

[0055] Figure 4 , Figure 5 and Figure 6 A conductive pattern forming method according to an embodiment is shown.

[0056] refer to Figure 4 , in order to form a minute conductive pattern (such as a pad P, wiring, and bump each having a minute pad width w) by an inkjet method, a step for controlling the temperature of a substrate SB (for example, heating the substrate SB in which the minute conductive pattern is formed) is included. Intense pulsed light (IPL) may be radiated onto the substrate SB to heat the substrate SB. The IPL may be radiated by using a pulsed thermal treatment (PTP) device including a device capable of applying several to tens of kW / cm in a short period of microseconds (μs) to milliseconds (ms). 2 The peak radiant power of the IPL light source (LS) can be a flash lamp using xenon (Xe). For example, as a pulse heat treatment device, a NovaCentrix series.

[0057] refer to Figure 4 and Figure 5 , IPL may be radiated to the substrate SB just before the conductive ink is dropped. The temperature of the surface of the substrate SB may reach a temperature at which the solvent in the conductive ink is evaporated within a few milliseconds by the high-energy light radiated to the substrate SB. IPL may instantaneously heat the surface temperature of the substrate SB to about 80°C or more, for example, about 100°C to about 200°C, or about 120°C to about 150°C within a certain period of time.

[0058] Unlike laser, IPL can have a broadband wavelength including a visible spectrum range of 400nm to 1200nm. Therefore, a filter FT can be used to selectively filter out a specific wavelength range. For example, when the substrate SB includes a polymer (such as polyimide, polyamide, polyethylene, polyethylene terephthalate, etc.), a filter FT that blocks ultraviolet (UV) light can be used to prevent decomposition of the polymer. Unlike laser, IPL can shorten the processing time because it can irradiate a large area with a single shot of a light source LS (such as a flash lamp). Unlike heat treatment in an oven, IPL heats the surface of the substrate SB to a predetermined temperature in a very short time (e.g., less than milliseconds), thereby preventing or minimizing damage to the substrate SB.

[0059] The conductive ink may be a metal ink in which tiny conductive particles, such as nanoparticles of metals (e.g., copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), tungsten (W), nickel (Ni), tantalum (Ta), bismuth (Bi), lead (Pb), indium (In), tin (Sn), zinc (Zn), titanium (Ti), and aluminum (Al)) are dispersed in a solvent. The conductive ink may be a conductive polymer ink prepared using a conductive polymer (e.g., PEDOT-PSS, polyaniline, polypyrrole, polythiophene, etc.).

[0060] refer to Figure 5 and Figure 6 , the viscosity of the conductive ink printed and drawn with the inkjet IJ in the area of ​​the substrate SB heated to a predetermined temperature increases rapidly, so that the ductility (or wettability) decreases. Therefore, the conductive ink can be quickly solidified on the substrate SB before being extended on the substrate SB, and a conductive pattern CP having a predetermined thickness (for example, about 10% or more of the pad width w) can be formed while maintaining a fine width of about 10 μm or less or about 5 μm or less (see the conductive pattern CP in the middle of the substrate SB). In contrast, the conductive ink printed in the area of ​​the substrate SB that is not heated (see the conductive pattern CP on the left side of the substrate SB) or not fully heated (see the conductive pattern CP on the right side of the substrate SB) does not form a tiny pattern with a sufficient thickness having a tiny pad width due to its low viscosity.

[0061] After the conductive ink is printed on the substrate SB, high-energy IPL is radiated to the conductive pattern CP to sinter the conductive pattern CP to ensure high strength and high adhesion to the substrate SB.

[0062] Figures 7 to 12 A conductive pattern forming method according to an embodiment is shown.

[0063] Unlike the previous embodiment in which the conductive pattern is formed by using an inkjet method, Figures 7 to 12In the embodiment of the present invention, the conductive pattern CP is formed by using the transfer substrate TS and the release layer RL.

[0064] refer to Figure 7 , a release layer RL (such as a dynamic release layer) is stacked on the transfer substrate TS, and a conductive layer CL is formed on the release layer RL.

[0065] As the transfer substrate TS, a transparent substrate such as a glass substrate can be used. The transfer substrate TS may have the property of transmitting IPL so that light energy can be transmitted through the transfer substrate TS. A mask M may be formed in one side of the transfer substrate TS or attached to one side of the transfer substrate TS, and the mask M may transmit light in a predetermined pattern. In the accompanying drawings, the mask M is disposed on a surface of the transfer substrate TS, which is opposite to the surface of the transfer substrate TS on which the release layer RL is disposed. However, the mask M may be disposed between the transfer substrate TS and the release layer RL. The opening OP may be formed to correspond to an area in which a conductive pattern is to be formed.

[0066] The release layer RL may be formed by coating a material such as an ultraviolet degradable photopolymer on the transfer substrate TS, or may be formed by attaching the material to the transfer substrate TS using an adhesive. As the ultraviolet degradable photopolymer, a triazene polymer may be used. The release layer RL may be used as a light-to-heat conversion layer.

[0067] The conductive layer CL may be formed by various methods such as coating, deposition, etc. For example, the conductive layer CL may be a metal layer, and may be a coating layer formed by applying a metal paste or a metal ink.

[0068] refer to Figure 8 As in the above-mentioned inkjet type embodiment, the substrate SB on which the conductive pattern is to be formed is irradiated with IPL so that the surface of the substrate SB is heated to a predetermined temperature. The IPL can be irradiated by using a pulse heat treatment (PTP) device, which includes a device capable of applying several to several tens of kW / cm in a short period of microseconds (μs) to milliseconds (ms). 2 The peak radiant power is the optical energy of the light source (LS).

[0069] refer to Fig. 9 and Fig.10, when the transfer substrate TS is placed on the substrate SB, the IPL is radiated toward the transfer substrate TS. The transfer substrate TS is arranged so that the surface on which the release layer RL and the conductive layer CL are located faces the substrate SB. The IPL passing through the opening OP of the mask M may melt the conductive layer portion CP′ corresponding to the opening OP of the mask M, or may increase the fluidity of the conductive layer portion CP′. In addition, due to the IPL radiated through the opening OP of the mask M, bubbles are generated at the area corresponding to the opening OP of the mask M at the interface between the release layer RL and the transfer substrate TS by local heating. The release layer RL may be a light-to-heat conversion layer that generates heat when illuminated by the IPL, and the bubbles may expand by the generated heat. When the bubbles expand, the release layer RL may melt or may push away the conductive layer portion CP′ having increased fluidity, and accordingly, the conductive layer portion CP′ may be transferred from the transfer substrate TS toward the substrate SB.

[0070] refer to Fig.11 The transferred conductive layer portion CP′ forms a conductive pattern CP on the substrate SB. Figure 8 As described, since the substrate SB is heated before the transferred conductive layer portion CP′ is attached to the substrate SB, the conductive layer portion CP′ attached to the substrate SB can be quickly solidified on the substrate SB without stretching, so that a conductive pattern CP having a minute width and a large thickness can be formed on the substrate SB.

[0071] Next, refer to Fig.12 , high-energy IPL is radiated again to the conductive pattern CP to sinter the conductive pattern CP to provide the conductive pattern CP having high strength and high adhesion to the substrate SB.

[0072] Since the IPL can be radiated uniformly over a large area, the processing time for heating the substrate SB, transferring the conductive layer portion CP' from the transfer substrate TS to the substrate SB, and sintering the conductive pattern CP can be significantly reduced compared to, for example, when a laser is used. In addition, a conductive pattern CP including a plurality of wirings having a small width and a large thickness can be formed at once. The conductive pattern CP may have a width of about 10 μm or less or about 5 μm or less, and a thickness of 10% or more, about 20% or more, or about 30% or more of the width.

[0073] Fig.13 and Fig.14 A conductive pattern forming method according to an embodiment is shown.

[0074] Fig.13 and Fig.14 The embodiment shown in is generally similar to Figures 7 to 12The embodiment of the present invention is different in that the second conductive pattern CP2 is formed on the first conductive pattern CP1 that has been formed. The second conductive pattern CP2 may be a bump.

[0075] The first conductive pattern CP1 may be formed by forming a conductive layer by deposition or the like and then patterning the conductive layer; or may be formed according to Figures 7 to 12 The first conductive pattern CP1 may be a terminal electrode or a wiring.

[0076] The second conductive pattern CP2 may be Figures 7 to 12 The embodiment is formed by using a transfer substrate TS, a release layer RL and an IPL. Therefore, the IPL is radiated to the substrate SB in which the first conductive pattern CP1 is formed to heat the surface of the first conductive pattern CP1 to a predetermined temperature so as to form the second conductive pattern CP2. Next, a transfer substrate TS in which a release layer RL and a conductive layer CL are stacked is placed on the substrate SB, and then the IPL is radiated to the transfer substrate TS to transfer the conductive layer portion CP′ corresponding to the opening OP of the mask M from the transfer substrate TS to the substrate SB. The transferred conductive layer portion CP′ forms the second conductive pattern CP2 on the first conductive pattern CP1. Since the surface of the first conductive pattern CP1 is heated, the conductive layer portion CP′ on the first conductive pattern CP1 can be cured on the substrate SB without stretching, so that a second conductive pattern CP2 with a small width and a large thickness can be formed. The second conductive pattern CP2 may have a width of about 10 μm or less or about 5 μm or less, and the thickness may be about 10% or more, about 20% or more, or about 30% or more of the width.

[0077] After the conductive layer portion CP′ is transferred on the first conductive pattern CP1, IPL is irradiated again on the substrate SB to sinter the conductive layer portion CP′ to form a second conductive pattern CP2 having increased strength and increased adhesion to the first conductive pattern CP1. The second conductive pattern CP2 can be formed by using Figures 4 to 6 The inkjet method in the embodiment is used to form it.

[0078] The second conductive pattern CP2 can function as a bump. A bump is a conductive protrusion formed on a chip pad, which is used to connect an electronic component (such as an IC chip) to a substrate in a manner such as tape automated bonding (TAB) or flip chip. The bump is used to increase the thickness of the pad conductor to facilitate the connection between the IC chip and the substrate.

[0079] When a display panel, printed circuit film, flexible printed circuit (FPC), etc., to which an IC chip having a bump is attached, includes a pad having a large step, it may not be possible to establish a uniform connection between the bump in the IC chip and the pad on the display panel, printed circuit film, flexible printed circuit (FPC), etc., and a poor connection may occur between some bumps and pads. The second conductive pattern CP2 formed on the first conductive pattern CP1 in the present embodiment can be formed by sintering a metal paste (e.g., silver (Ag) paste), so there may be pores between the metal particles forming the second conductive pattern CP2. Therefore, the second conductive pattern CP2 can be easily deformed due to external pressure, compensating for the step between the pads of the display panel, printed circuit film, flexible printed circuit (FPC), etc., and reducing the process pressure during bonding (e.g., reducing the process pressure to about 1 / 20 of the process pressure during bonding of a typical copper / tin (Cu / Sn) bump or solder bump). In addition, compared with conventional solder bumps, the bumps formed by sintering metal paste can reduce the process temperature during bonding. For example, a bump formed by using a silver (Ag) paste may be bonded at about 30° C. to about 80° C. Due to the reduced process temperature during bonding, expansion and deformation of a printed circuit film, a substrate, etc. may be reduced.

[0080] Below, we will refer to Fig.15 and Fig.16 A cross-sectional structure of a display device according to an embodiment is described. Fig.15 and Fig.16 Each of them is a cross-sectional view of a display device according to an embodiment.

[0081] refer to Fig.15 The display device 1 may be a liquid crystal display, and the display panel 10 may include a first substrate 100, a second substrate 200, and a liquid crystal layer 3 disposed between the first substrate 100 and the second substrate 200. The first substrate 100 and the second substrate 200 may be transparent insulating substrates, such as glass.

[0082] A circuit portion including a transistor and signal lines 101 and 102 may be located on the first substrate 100. Such a circuit portion may be formed to charge a data voltage into a liquid crystal capacitor forming each pixel at a predetermined timing. A pixel electrode 191 connected to the transistor may be located on the circuit portion in the display area DA, and an alignment layer may be located on the pixel electrode 191.

[0083] The light shielding layer 220 may be located in the non-display area NA on the second substrate 200. The light shielding layer 220 may prevent light leakage or light reflection due to the metal layer in the non-display area NA. The common electrode 270 may be located on the second substrate 200, and the alignment layer may be located on the common electrode 270. However, the common electrode 270 may be provided on the first substrate 100.

[0084] The pixel electrode 191, the common electrode 270, and the liquid crystal layer 3 may form a liquid crystal capacitor. An electric field corresponding to the difference between the data voltage applied to the pixel electrode 191 and the common voltage applied to the common electrode 270 may be applied to the liquid crystal layer 3. When the intensity of the electric field is changed by changing the magnitude of the data voltage, the orientation of the liquid crystal molecules in the liquid crystal layer 3 may be changed, and the transmittance may be adjusted by changing the orientation of the liquid crystal molecules, thereby adjusting the brightness of each pixel and displaying an image by a combination of pixels.

[0085] The first substrate 100 and the second substrate 200 are bonded by a sealant 60 located in the non-display area NA and surrounding the display area DA. In the non-display area DA, the dam 71a may be located on the first substrate 100 to prevent a solution (alignment solution) including a material for forming an alignment layer from flowing toward the sealant 60. For the same reason, the dam 71b may be located above the second substrate 200. Spacers 73a and 73b may be located on the first substrate 100 and / or the second substrate 200 to maintain a gap between the first substrate 100 and the second substrate 200. The spacers 73a and 73b may include an organic insulating material. The dams 71a and 71b and the spacers 73a and 73b may be formed of the same material by the same process, or may be formed by separate processes.

[0086] The edge filler 75 may be located at the outer edge of the sealant 60 in the display panel 10. The edge filler 75 may fill a gap that may exist between the first substrate 100 and the second substrate 200 on the side of the display panel 10. Therefore, during the process of forming the pad P on the side surface of the display panel 10, the edge filler 75 may prevent the pad P from being lifted by increasing the adhesive force between the pad P and the side surface on which the pad P is formed. The pad P may contact the side surface of the edge filler 75. The edge filler 75 may also prevent the sealant 60 from overflowing the outside of the display panel 10. The edge filler 75 may have a structure in which a structure 75a disposed on the first substrate 100 and a structure 75b disposed on the second substrate 200 are in direct contact with each other. The structures 75a and 75b may be formed of the same material (e.g., the same organic insulating material) as the spacers 73a and 73b by the same process as the spacers 73a and 73b. The side surface of the edge filler 75 may be aligned with the side surfaces of the first substrate 100 and the second substrate 200.

[0087] The pad P may be located on a side surface of the display panel 10. Figure 1 Different from the embodiment of the present invention, the side surface of the first substrate 100 may be aligned with the side surface of the second substrate 200. The pad P may be located on the side surface of the first substrate 100 and the side surface of the second substrate 200. As described, when the pad portion PP of the display panel 10 is formed on the side surface of the display panel 10, the width of the non-display area NA may be more reduced, and the area in which the printed circuit film 20 is bonded may be increased.

[0088] refer to Fig.16 , will mainly describe and Fig.15 The difference in the implementation method and in Fig.16 In the embodiment, the display device 1 is exemplarily provided as a light-emitting display device.

[0089] The display device 1 includes a display area DA and a non-display area NA.

[0090] The display panel 10 includes a first substrate 100, and a semiconductor layer 154 of the transistor TR may be disposed on the first substrate 100. The semiconductor layer 154 may include a channel region, a source region, and a drain region. The source region and the drain region are disposed on opposite sides of the channel region. The semiconductor layer 154 may include polycrystalline silicon, amorphous silicon, or an oxide semiconductor.

[0091] A buffer layer may be disposed between the first substrate 100 and the semiconductor layer 154 to prevent the dispersion of impurities that degrade characteristics of the semiconductor layer 154 and to prevent the penetration of moisture or the like.

[0092] The first insulating layer 140 may be located on the semiconductor layer 154. The first insulating layer 140 may include an inorganic insulating material, such as silicon oxide (SiO x ), Silicon Nitride (SiN x )wait.

[0093] A gate conductor, which may include a gate electrode 124 and a gate line of the transistor TR, may be located on the first insulating layer 140. The gate electrode 124 may overlap a channel region of the semiconductor layer 154. The gate conductor may include a metal such as molybdenum (Mo), copper (Cu), aluminum (Al), silver (Ag), chromium (Cr), tantalum (Ta), titanium (Ti), etc.

[0094] The second insulating layer 160, which may include an inorganic insulating material, may be located on the gate conductor. A data conductor, which may include a source electrode 173 and a drain electrode 175 of the transistor TR, a data line, a driving voltage line, etc., may be located on the second insulating layer 160. The data conductor may include a metal such as aluminum (Al), copper (Cu), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), etc.

[0095] The source electrode 173 and the drain electrode 175 may be respectively connected to the source region and the drain region of the semiconductor layer 154 through the opening of the second insulating layer 160. The gate electrode 124, the source electrode 173, the drain electrode 175, and the semiconductor layer 154 form a transistor TR.

[0096] The third insulating layer 180 may be disposed on the second insulating layer 160 and the data conductor. The third insulating layer 180 may include an organic insulating material.

[0097] The pixel electrode 191 may be disposed on the third insulating layer 180. The pixel electrode 191 may be connected to the source electrode 173 or the drain electrode 175 of the transistor TR through an opening formed in the third insulating layer 180. The pixel electrode 191 may be formed of a reflective conductive material or a semi-transparent conductive material, or may be formed of a transparent conductive material. The pixel electrode 191 may include a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), etc. The pixel electrode 191 may include a metal such as lithium (Li), calcium (Ca), aluminum (Al), silver (Ag), magnesium (Mg), gold (Au), etc.

[0098] The fourth insulating layer 360 may be disposed on the third insulating layer 180 and the pixel electrode 191. The fourth insulating layer 360 may include an opening 61 overlapping the pixel electrode 191. The opening 61 of the fourth insulating layer 360 may define an area corresponding to a light emitting area of ​​the pixel. The fourth insulating layer 360 may include an organic insulating material such as polyimide, polyacrylate, etc.

[0099] The light emitting layer 260 including the emission layer may be disposed on the pixel electrode 191. The common electrode 270 transmitting the common voltage may be disposed on the light emitting layer 260. The common electrode 270 may include a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), etc. The common electrode 270 may be formed to have light transmittance by controlling the thickness of the common electrode forming material (such as calcium (Ca), barium (Ba), magnesium (Mg), aluminum (Al), silver (Ag), etc.). At least one protective layer or functional layer may be disposed on the common electrode 270.

[0100] The pixel electrode 191, the light emitting layer 260 and the common electrode 270 of each pixel may form a light emitting diode LED. The light emitting diode LED may be an organic light emitting diode (OLED). The pixel electrode 191 may be an anode, which is a hole injection electrode, and the common electrode 270 may be a cathode, which is an electron injection electrode, and vice versa. Holes and electrons are injected into the light emitting layer 260 from the pixel electrode 191 and the common electrode 270, respectively, and when the excitons of the injected holes and electrons recombine fall from an excited state to a ground state, light is emitted.

[0101] The display panel 10 may include a second substrate 200 facing the first substrate 100. A touch sensor layer including a touch electrode 420 may be located on the second substrate 200. The touch sensor layer may be used to sense a contact touch and / or a contactless touch of a user. The touch electrode 420 may be located in the display area DA. The touch electrode 420 may be formed of a transparent conductive material, a metal mesh, a conductive polymer, etc. A protective layer 430 (such as an insulating layer) may be provided on the touch electrode 420. The touch electrode 420 may be located on the inner side of the second substrate 200 (i.e., the side facing the first substrate 100), or may be formed on a separate substrate and thus attached to the second substrate 200.

[0102] The sealant 60 disposed between the first substrate 100 and the second substrate 200 may hermetically seal the display panel 10 while bonding the first substrate 100 and the second substrate 200 .

[0103] The pad portion PP in which the pad P is connected with the signal line 101 may be located at a side surface of the display panel 10. The printed circuit film 20 including the lead portion LP may be bonded to the pad portion PP.

[0104] While the inventive concept has been described in conjunction with what are currently considered to be practical embodiments, it should be understood that the inventive concept is not limited to the disclosed embodiments. Rather, it is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A method for forming a conductive pattern, comprising: forming a release layer and a conductive layer in sequence on a transfer substrate including a mask; irradiating a first intense pulse light onto the substrate to heat the surface temperature of the substrate to 120° C. to 150° C.; placing the transfer substrate on the substrate; A portion of the conductive layer corresponding to the opening of the mask is melted or the fluidity of the portion of the conductive layer is increased by irradiating a second intense pulse light to the transfer substrate, and the portion of the conductive layer is transferred to the substrate, and the portion of the conductive layer is solidified on the substrate without being extended, so as to form a conductive pattern on the substrate, The conductive layer is a metal layer formed of one of copper, silver, gold, platinum, palladium, tungsten, nickel, tantalum, bismuth, lead, indium, tin, zinc, titanium and aluminum. 2 . The conductive pattern forming method according to claim 1 , wherein the conductive layer is formed by applying a metal paste or a metal ink. The conductive pattern forming method according to claim 1 , wherein the release layer is a dynamic release layer. 4 . The conductive pattern forming method according to claim 1 , wherein the conductive pattern is the conductive layer corresponding to the opening of the mask. 5 . The conductive pattern forming method according to claim 1 , wherein the placing of the transfer substrate on the substrate comprises placing a surface of the transfer substrate on which the conductive layer is located to face the substrate. 6 . The conductive pattern forming method according to claim 1 , further comprising sintering the conductive pattern by radiating a third intense pulse light to the substrate in which the conductive pattern is formed.

7. A method for forming a conductive pattern, comprising: forming a first conductive pattern on a substrate; forming a release layer and a conductive layer in sequence on a transfer substrate including a mask; irradiating a first intense pulse light to the substrate in which the first conductive pattern is formed, so that the surface temperature of the substrate is heated to 120° C. to 150° C.; placing the transfer substrate on the substrate; A portion of the conductive layer corresponding to the opening of the mask is melted or the fluidity of the portion of the conductive layer is increased by irradiating a second intense pulse light to the transfer substrate, and the portion of the conductive layer is transferred to the substrate, and the portion of the conductive layer is solidified on the substrate without being extended, so as to form a second conductive pattern on the substrate, The conductive layer is a metal layer formed of one of copper, silver, gold, platinum, palladium, tungsten, nickel, tantalum, bismuth, lead, indium, tin, zinc, titanium and aluminum. 8 . The conductive pattern forming method according to claim 7 , wherein the conductive layer is formed by applying a metal paste or a metal ink, or by metal deposition. 9 . The method for forming a conductive pattern according to claim 7 , wherein the release layer is a dynamic release layer.

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