Display device

Abstract

The present disclosure relates to a display device. Based on one embodiment, the display device includes: a substrate; a polycrystalline semiconductor located on the substrate; a first gate insulating film located on the polycrystalline semiconductor; a gate electrode of a driving transistor located on the first gate insulating film; a first electrode of a boost capacitor located on the first gate insulating film; a second gate insulating film located on the gate electrode of the driving transistor and the first electrode of the boost capacitor; a first interlayer insulating film located on the second gate insulating film; an oxide semiconductor located on the first interlayer insulating film; a third gate insulating film located on the oxide semiconductor; a gate electrode of a third transistor located on the third gate insulating film; a gate electrode of a fourth transistor located on the third gate insulating film and overlapping with a channel of the fourth transistor; and a second interlayer insulating film located on the gate electrode of the third transistor and the gate electrode of the fourth transistor.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] An organic light-emitting display device includes two electrodes and an organic light-emitting layer located therebetween. Electrons injected from one electrode and holes injected from the other electrode recombine in the organic light-emitting layer to form excitons. Excitons transition from an excited state to a ground state and emit energy to emit light.

[0003] Such an organic light emitting display device includes a plurality of pixels including an organic light emitting diode as a self-luminous element, and each pixel is provided with a plurality of transistors for driving the organic light emitting diode and one or more capacitors. The plurality of transistors basically include a switching transistor and a driving transistor.

[0004] In order to increase the resolution of the organic light-emitting display device, the number of pixels is increased, and in order to achieve stable video, the aperture ratio may be reduced, the current density may be increased, and the driving voltage may be increased. As a result, spots may occur, and the reliability of components such as transistors may be reduced. Summary of the invention

[0005] The embodiment is to improve the reliability of elements of a display device having high resolution and being driven at high speed.

[0006] A display device according to an embodiment includes: a substrate; a polycrystalline semiconductor located on the substrate and including a channel, a first electrode and a second electrode of a driving transistor; a first gate insulating film located on the polycrystalline semiconductor; a gate electrode of the driving transistor located on the first gate insulating film and overlapping with the channel of the driving transistor; a first electrode of a boosting capacitor located on the first gate insulating film; a second gate insulating film located on the gate electrode of the driving transistor and the first electrode of the boosting capacitor; a first interlayer insulating film located on the second gate insulating film; an oxide semiconductor located on the first interlayer insulating film and including a channel, a first electrode and a second electrode of a third transistor, a channel, a first electrode and a second electrode of a fourth transistor, and a second electrode of the boosting capacitor connected to each other; and a three gate insulating films located on the oxide semiconductor; a gate electrode of a third transistor located on the third gate insulating film and overlapping with a channel of the third transistor; a gate electrode of a fourth transistor located on the third gate insulating film and overlapping with a channel of the fourth transistor; and a second interlayer insulating film located on the gate electrode of the third transistor and the gate electrode of the fourth transistor, the hydrogen concentrations of the first interlayer insulating film, the third gate insulating film and the second interlayer insulating film being lower than the hydrogen concentrations of the first gate insulating film and the second gate insulating film, the first electrode and the second electrode of the third transistor, the first electrode and the second electrode of the fourth transistor, and the second electrode of the boosting capacitor of the oxide semiconductor are doped with at least one of boron, phosphorus, argon, xenon and krypton.

[0007] The third gate insulating film may be located entirely on the oxide semiconductor and the first interlayer insulating film.

[0008] The third gate insulating film may cover the top surface and side surfaces of the oxide semiconductor.

[0009] The hydrogen concentration of the first interlayer insulating film may be less than 1.0E +21 atoms / cm 3 .

[0010] The hydrogen concentration of the third gate insulating film may be less than 1.14E +21 atoms / cm 3 .

[0011] The hydrogen concentration of the second interlayer insulating film may be less than 1.0E +22 atoms / cm 3 .

[0012] It can be that the doping concentration of the source region and the drain region of the oxide semiconductor is 5E + 18 cm -3 above.

[0013] A display device based on one embodiment includes: a light emitting diode, connected between a driving voltage line to which a driving voltage is applied and a common voltage line to which a common voltage is applied; a driving transistor, connected between the driving voltage line and the light emitting diode; a second transistor, connected between a first electrode of the driving transistor connected to the driving voltage line and a data line to which a data voltage is applied; a third transistor, connected between a second electrode of the driving transistor connected to the light emitting diode and a gate electrode of the driving transistor; a fourth transistor, connected between the gate electrode of the driving transistor and a first initialization voltage line to which a first initialization voltage is applied; a holding capacitor, connected between the driving voltage line and the gate electrode of the driving transistor; and a boost capacitor, connected between the gate electrode of the second transistor and the gate electrode of the driving transistor.

[0014] It may be that the gate electrode of the second transistor is connected to a scanning line to which a scanning signal is applied, and the gate electrode of the third transistor is connected to a reverse scanning line to which a reverse scanning signal is applied, and at the same timing, a voltage with a polarity opposite to that of the voltage applied to the scanning line is applied to the reverse scanning line.

[0015] The driving transistor and the second transistor may include polycrystalline semiconductors, the third transistor and the fourth transistor may include oxide semiconductors, and at least a portion of the oxide semiconductors may be doped with at least one of boron, phosphorus, argon, xenon and krypton.

[0016] The driving transistor and the second transistor may be formed of p-type transistors, and the third transistor and the fourth transistor may be formed of n-type transistors.

[0017] The second electrode of the boosting capacitor connected to the gate electrode of the driving transistor may be doped with at least one of boron, phosphorus, argon, xenon and krypton.

[0018] It may be that the display device based on one embodiment also includes: a fifth transistor connected between the driving voltage line and the first electrode of the driving transistor; a sixth transistor connected between the first electrode of the driving transistor and the light-emitting diode; and a seventh transistor connected between the second initialization voltage line to which the second initialization voltage is applied and the light-emitting diode.

[0019] A display device according to an embodiment includes: a substrate; a polycrystalline semiconductor located on the substrate; a first gate insulating film located on the polycrystalline semiconductor; a driving gate electrode located on the first gate insulating film; a second gate insulating film located on the driving gate electrode; a first interlayer insulating film located on the second gate insulating film; an oxide semiconductor located on the first interlayer insulating film; a third gate insulating film located on the oxide semiconductor; a switching gate electrode located on the third gate insulating film; and a second interlayer insulating film located on the switching gate electrode, wherein the hydrogen concentrations of the first interlayer insulating film, the third gate insulating film and the second interlayer insulating film are lower than the hydrogen concentrations of the first gate insulating film and the second gate insulating film, the oxide semiconductor includes a channel located in the center and a source region and a drain region located on both sides of the channel, and the source region and the drain region of the oxide semiconductor are doped with at least one of boron, phosphorus, argon, xenon and krypton.

[0020] The third gate insulating film may be located entirely on the oxide semiconductor and the first interlayer insulating film.

[0021] The third gate insulating film may cover the top surface and side surfaces of the channel, the source region, and the drain region of the oxide semiconductor.

[0022] The hydrogen concentration of the first interlayer insulating film may be less than 1.0E +21 atoms / cm 3 .

[0023] The hydrogen concentration of the third gate insulating film may be less than 1.14E +21 atoms / cm 3 .

[0024] The hydrogen concentration of the second interlayer insulating film may be less than 1.0E +22 atoms / cm 3 .

[0025] It can be that the doping concentration of the source region and the drain region of the oxide semiconductor is 5E + 18 cm -3 above.

[0026] (Effects of the Invention)

[0027] According to the embodiment, element reliability of a display device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1is a cross-sectional view showing a portion of a display device according to an embodiment.

[0029] Figure 2 is a cross-sectional view showing a portion of a first transistor of a display device according to an embodiment.

[0030] Figure 3 is a graph showing the on-state current before and after doping the first semiconductor of the first transistor of the display device according to one embodiment.

[0031] Figure 4 is a circuit diagram of a display device according to an embodiment.

[0032] Figure 5 is a circuit diagram of a display device according to an embodiment.

[0033] Figure 6 is a circuit diagram of a display device according to an embodiment.

[0034] Figure 7 FIG. 1 is a top view showing a display device according to an embodiment.

[0035] Figure 8 is along Figure 7 The VIII-VIII line shows a cross-sectional view.

[0036] Fig. 9 is along Figure 7 The IX-IX line shows a cross-sectional view.

[0037] Fig.10 FIG. 1 is a top view showing a part of layers of a display device according to an embodiment.

[0038] Fig.11 is shown along Fig.10 The XI-XI line shows a cross-sectional view.

[0039] Fig.12 is shown along Fig.10 The XII-XII line shows a cross-sectional view.

[0040] Fig.13 is a graph showing voltage-capacitance characteristics of a boosting capacitor in a display device according to an embodiment.

[0041] Fig.14 is a graph showing the voltage-capacitance characteristics of the boosting capacitor in the display device according to the comparative example.

[0042] (Explanation of Reference Numerals)

[0043] 110: Substrate

[0044] 141: First gate insulating film

[0045] 142: Second gate insulating film

[0046] 143: Third gate insulating film

[0047] 161: First interlayer insulating film

[0048] 162: Second interlayer insulating film

[0049] 171: Data line

[0050] 172: Driving voltage line

[0051] 180: Third interlayer insulating film

[0052] 1132: Channel of driver transistor

[0053] 1151: Gate electrode of driving transistor

[0054] 1135: Second electrode of boost capacitor

[0055] 1155: First electrode of boost capacitor

[0056] 1175: First connection electrode

[0057] 3136: First electrode of the third transistor

[0058] 3137: Channel of the third transistor

[0059] 3138: Second electrode of the third transistor

[0060] 3151: Gate electrode of the third transistor

[0061] 4136: Second electrode of the fourth transistor

[0062] 4137: Channel of the fourth transistor

[0063] 4148: First electrode of the fourth transistor

[0064] 4151: Gate electrode of the fourth transistor DETAILED DESCRIPTION

[0065] Hereinafter, with reference to the attached drawings, multiple embodiments of the present invention are described in detail so that a person having ordinary knowledge in the technical field to which the present invention belongs can easily implement the present invention. The present invention can be implemented in many different forms and is not limited to the embodiments described herein.

[0066] In order to clearly explain the present invention, parts not related to the description are omitted, and the same or similar components are denoted by the same reference numerals throughout the specification.

[0067] In addition, the size and thickness of each structure shown in the drawings are arbitrarily shown for the convenience of explanation, so the present invention is not necessarily limited to the drawings. In the drawings, the thickness is enlarged to clearly express each layer and region. In addition, in the drawings, the thickness of some layers and regions is exaggerated for the convenience of explanation.

[0068] In addition, when a layer, film, region, plate or the like is described as being "on" or "upper" another part, it includes not only the case where it is "directly on" another part, but also the case where there are other parts in between. On the contrary, when a part is described as being "directly on" another part, it means that there are no other parts in between. In addition, being "on" or "upper" a part that becomes a reference means being located above or below the part that becomes the reference, and does not necessarily mean being "on" or "upper" on the side opposite to the gravity.

[0069] Furthermore, throughout the specification, when a certain part is described as “including” a certain constituent element, unless there is a particular description to the contrary, it does not mean that other constituent elements are excluded but means that other constituent elements may be included.

[0070] In addition, throughout the specification, when it is referred to as "on a plane", it means the case where the target part is viewed from above, and when it is referred to as "on a cross section", it means the case where a cross section vertically cutting the target part is viewed from the side.

[0071] First, refer to Figure 1 A display device according to one embodiment is described as follows.

[0072] Figure 1 is a cross-sectional view showing a portion of a display device according to an embodiment. Figure 1 For the convenience of explanation in the display device, the first transistor TR1 and the second transistor TR2 and the light emitting diode LED connected to the second transistor TR2 are mainly shown. The first transistor TR1 may be a switching transistor, and the second transistor TR2 may be a driving transistor.

[0073] The buffer layer 111 may be located on the substrate 110. The substrate 110 may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate. The substrate 110 may include a flexible material that can be bent or folded, and may be a single layer or multiple layers.

[0074] The buffer layer 111 may have a single layer or a multi-layer structure. Figure 1 The buffer layer 111 is shown as a single layer, but may be a multilayer according to embodiments. The buffer layer 111 may include an organic insulating material or an inorganic insulating material. As an example, the buffer layer 111 may include silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0075] The second semiconductor 130 may be located on the buffer layer 111 . The second semiconductor 130 may include polysilicon material. That is, the second semiconductor 130 may be formed of a polycrystalline semiconductor. The second semiconductor 130 may include a source region 131 , a channel region 132 , and a drain region 133 .

[0076] The source region 131 of the second semiconductor 130 may be connected to the second source electrode SE2 , and the drain region 133 of the second semiconductor 130 may be connected to the second drain electrode DE2 .

[0077] The first gate insulating film 141 may be located on the second semiconductor 130. The first gate insulating film 141 may include silicon nitride, silicon oxide, or the like.

[0078] The second gate lower electrode GE2-U may be located on the first gate insulating film 141. The second gate insulating film 142 may be located on the second gate lower electrode GE2-U. The second gate insulating film 142 may include silicon nitride, silicon oxide, or the like.

[0079] The second gate upper electrode GE2-L may be located on the second gate insulating film 142. The second gate lower electrode GE2-U and the second gate upper electrode GE2-L may overlap with the second gate insulating film 142 between them. The second gate upper electrode GE2-L and the second gate lower electrode GE2-U constitute the second gate electrode GE2. The second gate electrode GE2 may overlap with the channel region 132 of the second semiconductor 130 in a direction perpendicular to the substrate 110.

[0080] The second semiconductor 130, the second gate electrode GE2, the second source electrode SE2, and the second drain electrode DE2 constitute a second transistor TR2. The second transistor TR2 may be a driving transistor connected to the light emitting diode LED, and may be formed of a transistor including a polycrystalline semiconductor.

[0081] The first interlayer insulating film 161 may be located on the second gate electrode GE2. The first interlayer insulating film 161 may include silicon nitride, silicon oxide, etc. The first interlayer insulating film 161 may be formed by a multilayer in which a layer including silicon nitride and a layer including silicon oxide are stacked. At this time, in the first interlayer insulating film 161, the layer including silicon nitride may be located closer to the substrate 110 than the layer including silicon oxide.

[0082] The first semiconductor 135 may be located on the first interlayer insulating film 161 .

[0083] The first semiconductor 135 may be formed of an oxide semiconductor. The oxide semiconductor may include a monometallic oxide such as indium oxide (In), tin oxide (Sn), or zinc oxide (Zn), an In-Zn oxide, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In-Mg oxide, or an In-Ga oxide, a binary metal oxide such as an In-Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-Al-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn oxide, In-Pr-Zn oxide, In-Nd- At least one of ternary metal oxides such as In-Zn oxides, In-Sm-Zn oxides, In-Eu-Zn oxides, In-Gd-Zn oxides, In-Tb-Zn oxides, In-Dy-Zn oxides, In-Ho-Zn oxides, In-Er-Zn oxides, In-Tm-Zn oxides, In-Yb-Zn oxides, or In-Lu-Zn ​​oxides, and quaternary metal oxides such as In-Sn-Ga-Zn oxides, In-Hf-Ga-Zn oxides, In-Al-Ga-Zn oxides, In-Sn-Al-Zn oxides, In-Sn-Hf-Zn oxides, or In-Hf-Al-Zn oxides. For example, the first semiconductor 135 may include IGZO (Indium Gallium Zinc Oxide) among the In-Ga-Zn oxides.

[0084] The first semiconductor 135 may include a source region 136, a channel region 137, and a drain region 138. The source region 136 of the first semiconductor 135 may be connected to the first source electrode SE1, and the drain region 138 of the first semiconductor 135 may be connected to the first drain electrode DE1.

[0085] The third gate insulating film 143 may be located on the first semiconductor 135. Figure 1 In the embodiment of the present invention, the third gate insulating film 143 may be located on the entire surface of the first semiconductor 135 and the first interlayer insulating film 161. Therefore, the third gate insulating film 143 covers the top and side surfaces of the source region 136, the channel region 137, and the drain region 138 of the first semiconductor 135.

[0086] In the process of achieving high resolution, the size of each pixel is reduced, and thus the length of the semiconductor channel is reduced. At this time, if the third gate insulating film 143 does not cover the top surface of the source region 136 and the drain region 138, part of the material of the first semiconductor 135 may move to the side of the third gate insulating film 143. For example, in the case where the first semiconductor 135 is formed of an oxide semiconductor containing indium, indium particles may be located on the side of the third gate insulating film 143, and due to such indium particles, the first semiconductor 135 and the first gate electrode GE1 may be short-circuited. In the present embodiment, the third gate insulating film 143 is located on the entire surface above the first semiconductor 135 and the first interlayer insulating film 161, so that the short circuit between the first semiconductor 135 and the first gate electrode GE1 can be prevented.

[0087] However, the present embodiment is not limited thereto, and the third gate insulating film 143 may not be located on the entire surface of the first semiconductor 135 and the first interlayer insulating film 161. For example, the third gate insulating film 143 may be located only between the first gate electrode GE1 and the first semiconductor 135. That is, the third gate insulating film 143 may overlap with the channel region 137 of the first semiconductor 135, but may not overlap with the source region 136 and the drain region 138.

[0088] The first gate electrode GE1 may be located on the third gate insulating film 143. The first gate electrode GE1 may overlap the channel region 137 of the first semiconductor 135 in a direction perpendicular to the substrate 110.

[0089] The first semiconductor 135 , the first gate electrode GE1 , the first source electrode SE1 , and the first drain electrode DE1 constitute a first transistor TR1 . The first transistor TR1 may be a switching transistor for switching the second transistor TR2 , and is formed of a transistor including an oxide semiconductor.

[0090] The second interlayer insulating film 162 may be located on the first gate electrode GE1. The first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 may be located on the second interlayer insulating film 162. A first opening OP1, a second opening OP2, a third opening OP3, and a fourth opening OP4 may be formed in the second interlayer insulating film 162. The first opening OP1 may overlap with the first source electrode SE1, and the second opening OP2 may overlap with the first drain electrode DE1. The third opening OP3 may overlap with the second source electrode SE2, and the fourth opening OP4 may overlap with the second drain electrode DE2.

[0091] The first source electrode SE1 may be connected to the source region 136 of the first semiconductor 135 through the first opening OP1. The first drain electrode DE1 may be connected to the drain region 138 of the first semiconductor 135 through the second opening OP2.

[0092] The second source electrode SE2 may be connected to the source region 131 of the second semiconductor 130 through the third opening OP3. The second drain electrode DE2 may be connected to the drain region 133 of the second semiconductor 130 through the fourth opening OP4.

[0093] The third interlayer insulating film 180 may be located on the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2. An opening 185 may be formed in the third interlayer insulating film 180. The opening 185 of the third interlayer insulating film 180 may overlap with the second drain electrode DE2.

[0094] The anode electrode 191 may be located on the third interlayer insulating film 180 . The anode electrode 191 may be connected to the second drain electrode DE2 through the opening 185 of the third interlayer insulating film 180 .

[0095] The partition wall 350 may be located above the anode electrode 191. An opening may be formed in the partition wall 350, and the opening of the partition wall 350 may overlap with the anode electrode 191. The light emitting element layer 370 may be located in the opening of the partition wall 350.

[0096] The cathode electrode 270 may be located on the light emitting element layer 370 and the partition wall 350. The anode electrode 191, the light emitting element layer 370, and the cathode electrode 270 constitute a light emitting diode LED.

[0097] As described above, in a display device based on an embodiment, the first transistor TR1 as a switching transistor may include an oxide semiconductor, and the second transistor TR2 as a driving transistor may include a polycrystalline semiconductor. For high-speed driving, the frequency of about 60 Hz in the past is increased to about 120 Hz, so that the action of the video can be more naturally expressed, but due to this, the driving voltage will increase. In order to compensate for the rising driving voltage, the frequency when driving a static image can be reduced. For example, when driving a static image, it can be driven at about 1 Hz. In the case of such a reduced frequency, leakage current may occur. In a display device based on an embodiment, the first transistor TR1 as a switching transistor includes an oxide semiconductor, so that the leakage current can be minimized. In addition, the second transistor TR2 as a driving transistor includes a polycrystalline semiconductor, so that it can have a high electron mobility. That is, the switching transistor and the driving transistor contain different semiconductor materials from each other, so that they can be driven more stably and have high reliability.

[0098] As mentioned above, in the process of achieving high resolution, the size of each pixel is reduced, thereby reducing the length of the semiconductor channel. In order to stably control the critical voltage of the oxide semiconductor with a short channel length, the process of forming the insulating film around the first semiconductor 135 located in the first transistor TR1 can be performed in a low hydrogen state. Therefore, the first interlayer insulating film 161 connected to the lower side of the first semiconductor 135 can have a low hydrogen concentration. For example, the hydrogen concentration of the first interlayer insulating film 161 can be less than 1.0E +21 atoms / cm 3 In addition, the third gate insulating film 143 in contact with the upper side of the first semiconductor 135 may have a low hydrogen concentration. For example, the hydrogen concentration of the third gate insulating film 143 may be less than 1.14E +21 atoms / cm 3 In addition, the second interlayer insulating film 162 that is in contact with the third gate insulating film 143 may have a low hydrogen concentration. For example, the hydrogen concentration of the second interlayer insulating film 162 may be less than 1.0E +22 atoms / cm 3 .

[0099] In this way, the first interlayer insulating film 161, the third gate insulating film 143, and the second interlayer insulating film 162 located around the first semiconductor 135 including an oxide semiconductor may have a low hydrogen concentration. On the contrary, the first gate insulating film 141 and the second gate insulating film 142 may have a high hydrogen concentration. Therefore, the hydrogen concentration of the first interlayer insulating film 161, the third gate insulating film 143, and the second interlayer insulating film 162 may be lower than the hydrogen concentration of the first gate insulating film 141 and the second gate insulating film 142.

[0100] However, the first semiconductor 135 of the first transistor TR1 including an oxide semiconductor has a low concentration of hydrogen that can act as a carrier, so the on-current of the first transistor TR1 can be reduced. Figure 2 As shown, carrier substances are doped into the first semiconductor 135, thereby preventing the on-current of the first transistor TR1 from being reduced. Figure 2 is a cross-sectional view showing a portion of a first transistor of a display device according to an embodiment, Figure 3 is a graph showing the on-state current before and after doping the first semiconductor of the first transistor of the display device according to one embodiment.

[0101] Reference Figure 2, a third gate insulating film 143 is formed on the first semiconductor 135, and a first gate electrode GE1 is formed on the third gate insulating film 143. Boron (B) is injected into the entire surface of the third gate insulating film 143 using the first gate electrode GE1 as a mask. Boron (B) is not injected into the channel region 137 overlapping with the first gate electrode GE1, but is injected into the source region 136 and the drain region 138 that do not overlap with the first gate electrode GE1. Therefore, the source region 136 and the drain region 138 of the first semiconductor 135 can be doped with boron (B). The doping concentration of the source region 136 and the drain region 138 of the first semiconductor 135 can be 5E +18 cm -3 At this time, the first semiconductor 135 may be doped with phosphorus (P), argon (Ar), xenon (Xe), krypton (Kr), etc. instead of boron (B). In this way, the carrier concentration of the first semiconductor 135 is increased by the doping process of the first semiconductor 135, and the on-current of the first transistor TR1 can be increased.

[0102] like Figure 3 As shown, the on-state current (Ion) of the first transistor TR1 (Ref.) not doped with boron (B) exhibits a high frequency at about 9 μA to 10 μA. The doping concentration of the source region 136 and the drain region 138 of the first semiconductor 135 of the first transistor TR1 (B+Impla.) doped with boron (B) under the condition of about 35 kV can be about 1E +19 cm -3 At this time, the on-current (Ion) of the first transistor TR1 shows a high frequency at about 13 μA to 14 μA. That is, it can be confirmed that the on-current of the first transistor TR1 increases by doping boron (B).

[0103] A circuit diagram of a display device according to an embodiment is described below. Figure 4 is a circuit diagram of a display device according to an embodiment.

[0104] Reference Figure 4 One pixel may include a second transistor TR2 for controlling a light emitting diode LED, a first transistor TR1 for switching the second transistor TR2, and a holding capacitor Cst connected to a driving voltage line 172. The first transistor TR1 as a switching transistor may include an oxide semiconductor, and the second transistor TR2 as a driving transistor may include a polycrystalline semiconductor.

[0105] The first transistor TR1 may include a gate electrode, a source electrode, and a drain electrode. The gate electrode of the first transistor TR1 may be connected to the i-th scan wiring Si, and the source electrode may be connected to the j-th data wiring Dj. The drain electrode of the first transistor TR1 may be connected to the gate electrode of the second transistor TR2. The first transistor TR1 may transmit a data signal applied to the j-th data wiring Dj according to a scan signal applied to the i-th scan wiring Si to the second transistor TR2.

[0106] The second transistor TR2 may include a gate electrode, a source electrode, and a drain electrode. The gate electrode of the second transistor TR2 may be connected to the first transistor TR1, the source electrode may be connected to the driving voltage line 172, and the drain electrode may be connected to the light emitting diode LED.

[0107] The light emitting diode LED may include a light emitting layer, an anode electrode and a cathode electrode with the light emitting layer disposed therebetween and facing each other. The anode electrode may be connected to the drain electrode of the second transistor TR2. The cathode electrode may be connected to the common voltage line 741 and a common voltage ELVSS may be applied thereto. The light emitting layer may emit light according to an output signal of the second transistor TR2, thereby displaying an image by emitting or not emitting light.

[0108] Here, the light emitted from the light emitting layer may differ depending on the material of the light emitting layer, and may be colored light or white light.

[0109] The holding capacitor Cst may be connected between the gate electrode and the source electrode of the second transistor TR2 , and charges and holds the data signal input to the gate electrode of the second transistor TR2 .

[0110] Figure 4 It is described that one pixel includes two transistors TR1 and TR2, but the present invention is not limited thereto and may include one transistor and a capacitor, or may include three or more transistors and two or more capacitors. Figure 5 As shown, one pixel may include first to seventh transistors T1 ˜ T7 and a holding capacitor Cst.

[0111] Below, refer to Figure 5 A display device according to one embodiment is described as follows.

[0112] Figure 5 The display device according to the embodiment shown in Figures 1 to 4 The same parts of the display device according to the embodiment shown in the figure are equivalent, so the description of the same parts is omitted. In this embodiment, it is different from the previous embodiment in that more than three transistors are included, which is further described below.

[0113] Figure 5is a circuit diagram of a display device according to an embodiment. Figure 5 According to one embodiment, a pixel PX of a display device includes a plurality of transistors T1, T2, T3, T4, T5, T6, and T7 connected to a plurality of signal lines, a holding capacitor Cst, and a light emitting diode LED.

[0114] The display device according to an embodiment includes a display area for displaying an image, and such pixels PX are arranged in various forms in the display area.

[0115] The plurality of transistors T1, T2, T3, T4, T5, T6, and T7 include a driving transistor T1, and include a switching transistor connected to the scan line Sn, namely, a second transistor T2 and a third transistor T3, and the remaining transistors are transistors for performing operations required to operate the light emitting diode LED (hereinafter referred to as compensation transistors T4, T5, T6, and T7). Such compensation transistors T4, T5, T6, and T7 may include a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.

[0116] The plurality of signal lines may include a scan line Sn, a front-end scan line Sn-1, a light emitting control line 155, a bypass control line 154, a data line 171, a driving voltage line 172, an initialization voltage line 127, and a common voltage line 741. The bypass control line 154 may be a part of the front-end scan line Sn-1 or electrically connected to the front-end scan line Sn-1. Alternatively, the bypass control line 154 may be a part of the scan line Sn or electrically connected to the scan line Sn.

[0117] The scanning line Sn is connected to the gate driving unit and transmits the scanning signal to the second transistor T2 and the third transistor T3. The front scanning line Sn-1 is connected to the gate driving unit and transmits the front scanning signal applied to the pixel PX at the front end to the fourth transistor T4. The light emitting control line 155 is connected to the light emitting control unit and transmits the light emitting control signal EM for controlling the light emitting time of the light emitting diode LED to the fifth transistor T5 and the sixth transistor T6. The bypass control line 154 transmits the bypass signal GB to the seventh transistor T7.

[0118] The data line 171 is a wiring for transmitting the data voltage Dm generated in the data driving unit, and the brightness of the light emitted by the light emitting diode LED changes according to the data voltage Dm. The driving voltage line 172 applies the driving voltage ELVDD. The initialization voltage line 127 transmits the initialization voltage Vint for initializing the driving transistor T1. The common voltage line 741 applies the common voltage ELVSS. The voltages applied to the driving voltage line 172, the initialization voltage line 127, and the common voltage line 741 can be constant voltages.

[0119] Next, a plurality of transistors T1 , T2 , T3 , T4 , T5 , T6 , and T7 are observed.

[0120] The driving transistor T1 adjusts the output driving current I according to the applied data voltage Dm. d The output drive current I d The data voltage Dm is applied to the light emitting diode LED to adjust the brightness of the light emitting diode LED according to the data voltage Dm. To this end, the first electrode S1 of the driving transistor T1 is configured to receive the application of the driving voltage ELVDD. The first electrode S1 is connected to the driving voltage line 172 via the fifth transistor T5. In addition, the first electrode S1 of the driving transistor T1 is also connected to the second electrode D2 of the second transistor T2 and also receives the application of the data voltage Dm. The second electrode (output electrode) D1 of the driving transistor T1 is configured to output a driving current I toward the light emitting diode LED. d The second electrode D1 of the driving transistor T1 is connected to the anode electrode of the light emitting diode LED via the sixth transistor T6. On the other hand, the gate electrode G1 is connected to one electrode (second holding electrode E2) of the holding capacitor Cst. Thus, the voltage of the gate electrode G1 changes according to the voltage stored in the holding capacitor Cst, and the driving current I output by the driving transistor T1 changes according to the voltage stored in the holding capacitor Cst. d has been changed.

[0121] The second transistor T2 is a transistor for receiving the data voltage Dm into the pixel PX. The gate electrode G2 is connected to the scan line Sn, and the first electrode S2 is connected to the data line 171. The second electrode D2 of the second transistor T2 is connected to the first electrode S1 of the driving transistor T1. If the second transistor T2 is activated according to the scan signal transmitted through the scan line Sn, the data voltage Dm transmitted through the data line 171 is transmitted to the first electrode S1 of the driving transistor T1.

[0122] The third transistor T3 is a transistor that transmits the data voltage Dm to the second holding electrode E2 of the holding capacitor Cst through the compensation voltage changed by the driving transistor T1. The gate electrode G3 is connected to the scan line Sn, and the first electrode S3 is connected to the second electrode D1 of the driving transistor T1. The second electrode D3 of the third transistor T3 is connected to the second holding electrode E2 of the holding capacitor Cst and the gate electrode G1 of the driving transistor T1. The third transistor T3 is activated according to the scanning signal transmitted through the scan line Sn and connects the gate electrode G1 and the second electrode D1 of the driving transistor T1, and also connects the second electrode D1 of the driving transistor T1 and the second holding electrode E2 of the holding capacitor Cst.

[0123] The fourth transistor T4 serves to initialize the gate electrode G1 of the driving transistor T1 and the second holding electrode E2 of the holding capacitor Cst. The gate electrode G4 is connected to the front-end scanning line Sn-1, and the first electrode S4 is connected to the initialization voltage line 127. The second electrode D4 of the fourth transistor T4 is connected to the second holding electrode E2 of the holding capacitor Cst and the gate electrode G1 of the driving transistor T1 via the second electrode D3 of the third transistor T3. The fourth transistor T4 transmits the initialization voltage Vint to the gate electrode G1 of the driving transistor T1 and the second holding electrode E2 of the holding capacitor Cst according to the front-end scanning signal received and transmitted through the front-end scanning line Sn-1. Thus, the gate voltage of the gate electrode G1 of the driving transistor T1 and the holding capacitor Cst are initialized. The initialization voltage Vint can be a voltage having a low voltage value that can turn on the driving transistor T1.

[0124] The fifth transistor T5 transmits the driving voltage ELVDD to the driving transistor T1. The gate electrode G5 is connected to the light emission control line 155, and the first electrode S5 is connected to the driving voltage line 172. The second electrode D5 of the fifth transistor T5 is connected to the first electrode S1 of the driving transistor T1.

[0125] The sixth transistor T6 serves to output the driving current I from the driving transistor T1. d The gate electrode G6 is connected to the light emitting control line 155, the first electrode S6 is connected to the second electrode D1 of the driving transistor T1, and the second electrode D6 of the sixth transistor T6 is connected to the anode electrode of the light emitting diode LED.

[0126] The fifth transistor T5 and the sixth transistor T6 are simultaneously activated according to the light emitting control signal EM transmitted through the light emitting control line 155. If the driving voltage ELVDD is applied to the first electrode S1 of the driving transistor T1 through the fifth transistor T5, the driving transistor T1 outputs the driving current I according to the voltage of the gate electrode G1 of the driving transistor T1 (that is, the voltage of the second holding electrode E2 of the holding capacitor Cst). d The output drive current I d The current I flows through the sixth transistor T6 and is transmitted to the light emitting diode LED. led And the light emitting diode LED emits light.

[0127] The seventh transistor T7 serves to initialize the anode electrode of the light emitting diode LED. The gate electrode G7 is connected to the bypass control line 154, the first electrode S7 is connected to the anode electrode of the light emitting diode LED, and the second electrode D7 is connected to the initialization voltage line 127. The bypass control line 154 can be connected to the front-end scanning line Sn-1, and the bypass signal GB is applied with a signal with the same timing as the front-end scanning signal. The bypass control line 154 can also be not connected to the front-end scanning line Sn-1 and transmit a signal independent of the front-end scanning signal. If the seventh transistor T7 is turned on according to the bypass signal GB, the initialization voltage Vint is applied to the anode electrode of the light emitting diode LED and the anode electrode of the light emitting diode LED is initialized.

[0128] The first holding electrode E1 of the holding capacitor Cst is connected to the driving voltage line 172, and the second holding electrode E2 is connected to the gate electrode G1 of the driving transistor T1, the second electrode D3 of the third transistor T3, and the second electrode D4 of the fourth transistor T4. As a result, the second holding electrode E2 determines the voltage of the gate electrode G1 of the driving transistor T1, and receives the application of the data voltage Dm through the second electrode D3 of the third transistor T3, or receives the application of the initialization voltage Vint through the second electrode D4 of the fourth transistor T4.

[0129] On the other hand, the anode electrode of the light emitting diode LED is connected to the second electrode D6 of the sixth transistor T6 and the first electrode S7 of the seventh transistor T7 , and the cathode electrode is connected to the common voltage line 741 transmitting the common voltage ELVSS.

[0130] In the above description, one pixel is described as including seven transistors T1 to T7 and one storage capacitor Cst, but the present invention is not limited thereto, and the number of transistors and capacitors and the connection relationship between them can be changed in various ways.

[0131] In this embodiment, the driving transistor T1 may include a polycrystalline semiconductor. In addition, the third transistor T3 and the fourth transistor T4 may include an oxide semiconductor. The second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include a polycrystalline semiconductor. However, it is not limited to this, and any one or more of the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include an oxide semiconductor. In this embodiment, the third transistor T3 and the fourth transistor T4 include a semiconductor material different from that of the driving transistor T1, so that the driving can be more stably performed and the reliability can be improved.

[0132] In the present embodiment, the third transistor T3 and the fourth transistor T4 may have a structure similar to the first transistor TR1 in the previous embodiment. In addition, in the present embodiment, the driving transistor T1 may have a structure similar to the second transistor TR2 in the previous embodiment. Therefore, the insulating film located around the third transistor T3 and the fourth transistor T4 may have a low hydrogen concentration, and the insulating film located around the driving transistor T1 may have a high hydrogen concentration. In addition, the semiconductor of the third transistor T3 and the fourth transistor T4 is doped with substances such as boron (B), phosphorus (P), argon (Ar), xenon (Xe) and krypton (Kr).

[0133] Below, refer to Figures 6 to 14 A display device according to one embodiment is described as follows.

[0134] Figure 6 The display device according to the embodiment shown in Figures 1 to 4 The display device according to the embodiment shown in Figure 5 The same parts of the display device according to the embodiment shown in the figure are equivalent, so the description of the same parts is omitted. In this embodiment, it is different from the previous embodiment in that a boost capacitor is also included, which is further described below.

[0135] First, refer to Figure 6 A pixel of a display device according to an embodiment is described.

[0136] Figure 6 A pixel PX of a display device according to an embodiment includes a plurality of transistors T1, T2, T3, T4, T5, T6, and T7 connected to a plurality of signal lines, a holding capacitor Cst, a boost capacitor Cboost, and a light emitting diode LED.

[0137] The display device according to an embodiment includes a display area for displaying an image, and such pixels PX are arranged in various forms in the display area.

[0138] A plurality of signal lines 127, 128, 151, 152, 153, 154, 155, 171, 172, 741 are connected to one pixel PX. The plurality of signal lines 127, 128, 151, 152, 153, 154, 155, 171, 172, 741 include a first initialization voltage line 127, a second initialization voltage line 128, a scan line 151, a reverse scan line 152, an initialization control line 153, a bypass control line 154, a light emission control line 155, a data line 171, a driving voltage line 172, and a common voltage line 741.

[0139] The scanning line 151 is connected to a gate driving unit (not shown) and transmits a scanning signal GW to the second transistor T2. A voltage having a polarity opposite to that applied to the scanning line 151 may be applied to the reverse scanning line 152 at the same timing as the signal of the scanning line 151. For example, when a high voltage is applied to the scanning line 151, a low voltage may be applied to the reverse scanning line 152. The reverse scanning line 152 transmits a reverse scanning signal GC to the third transistor T3.

[0140] The initialization control line 153 transmits the initialization control signal GI to the fourth transistor T4. The bypass control line 154 transmits the bypass signal GB to the seventh transistor T7. The bypass control line 154 may be formed by the rear scan line 151. The emission control line 155 transmits the emission control signal EM to the fifth transistor T5 and the sixth transistor T6.

[0141] The data line 171 is a wiring for transmitting a data voltage DATA generated by a data driving unit (not shown), and the brightness of light emitted by the light emitting diode LED changes according to the data voltage DATA applied to the pixel PX.

[0142] The driving voltage line 172 applies a driving voltage ELVDD. The first initialization voltage line 127 transmits a first initialization voltage VINT, and the second initialization voltage line 128 transmits a second initialization voltage AINT. The common voltage line 741 applies a common voltage ELVSS to the cathode electrode of the light emitting diode LED. In this embodiment, the voltages applied to the driving voltage line 172, the first initialization voltage line 127, the second initialization voltage line 128, and the common voltage line 741 can be certain voltages.

[0143] The following is a detailed look at the structures and connection relationships of multiple transistors.

[0144] The driving transistor T1 may have a p-type transistor characteristic and may include a polycrystalline semiconductor. The driving transistor T1 is a transistor that adjusts the size of the driving current output to the anode electrode of the light emitting diode LED according to the data voltage DATA applied to the gate electrode. The brightness of the light emitting diode LED is adjusted according to the size of the driving current output to the anode electrode of the light emitting diode LED, so the brightness of the light emitting diode LED can be adjusted according to the data voltage DATA applied to the pixel PX. To this end, the first electrode of the driving transistor T1 is configured to receive the application of the driving voltage ELVDD and is connected to the driving voltage line 172 via the fifth transistor T5. In addition, the first electrode of the driving transistor T1 is also connected to the second electrode of the second transistor T2 and also receives the application of the data voltage DATA. On the other hand, the second electrode of the driving transistor T1 is configured to output a driving current toward the light emitting diode LED and is connected to the anode electrode of the light emitting diode LED via the sixth transistor T6. In addition, the second electrode of the driving transistor T1 transmits the data voltage DATA applied to the first electrode to the third transistor T3. On the other hand, the gate electrode of the driving transistor T1 is connected to an electrode of the holding capacitor Cst (hereinafter also referred to as the second holding electrode). The gate voltage of the driving transistor T1 thus changes according to the voltage stored in the holding capacitor Cst, thereby changing the driving current output by the driving transistor T1. The holding capacitor Cst also plays a role in keeping the gate voltage of the driving transistor T1 constant during one frame period.

[0145] The second transistor T2 may have p-type transistor characteristics and may include a polycrystalline semiconductor. The second transistor T2 is a transistor that receives the data voltage DATA into the pixel PX. The gate electrode of the second transistor T2 is connected to the scan line 151 and the first electrode of the boost capacitor Cboost. The first electrode of the second transistor T2 is connected to the data line 171. The second electrode of the second transistor T2 is connected to the first electrode of the driving transistor T1. If the second transistor T2 is turned on at a low voltage in the scan signal GW transmitted through the scan line 151, the data voltage DATA transmitted through the data line 171 is transmitted to the first electrode of the driving transistor T1.

[0146] The third transistor T3 may have n-type transistor characteristics and may include an oxide semiconductor. The third transistor T3 electrically connects the second electrode of the driving transistor T1 and the gate electrode of the driving transistor T1. As a result, the third transistor T3 is a transistor that transmits the compensation voltage of the data voltage DATA through the driving transistor T1 to the second holding electrode of the holding capacitor Cst. The gate electrode of the third transistor T3 is connected to the reverse scan line 152, and the first electrode of the third transistor T3 is connected to the second electrode of the driving transistor T1. The second electrode of the third transistor T3 is connected to the second holding electrode of the holding capacitor Cst, the gate electrode of the driving transistor T1, and the second electrode of the boost capacitor Cboost. The third transistor T3 is turned on at a high voltage in the reverse scan signal GC received and transmitted through the reverse scan line 152, and the gate electrode of the driving transistor T1 is connected to the second electrode of the driving transistor T1, and the voltage applied to the gate electrode of the driving transistor T1 is transmitted to the second holding electrode of the holding capacitor Cst and stored in the holding capacitor Cst.

[0147] The fourth transistor T4 may have n-type transistor characteristics and may include an oxide semiconductor. The fourth transistor T4 serves to initialize the gate electrode of the driving transistor T1 and the second holding electrode of the holding capacitor Cst. The gate electrode of the fourth transistor T4 is connected to the initialization control line 153, and the first electrode of the fourth transistor T4 is connected to the first initialization voltage line 127. The second electrode of the fourth transistor T4 is connected to the second holding electrode of the holding capacitor Cst, the gate electrode of the driving transistor T1, and the second electrode of the boost capacitor Cboost via the second electrode of the third transistor T3. The fourth transistor T4 is turned on at a high voltage in the initialization control signal GI received and transmitted through the initialization control line 153. At this time, the first initialization voltage VINT is transmitted to the gate electrode of the driving transistor T1 and the second holding electrode of the holding capacitor Cst. Thus, the voltage of the gate electrode of the driving transistor T1 and the holding capacitor Cst are initialized.

[0148] The fifth transistor T5 may have p-type transistor characteristics and may include a polycrystalline semiconductor. The fifth transistor T5 serves to transmit the driving voltage ELVDD to the driving transistor T1. The gate electrode of the fifth transistor T5 is connected to the light emitting control line 155, the first electrode of the fifth transistor T5 is connected to the driving voltage line 172, and the second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T1.

[0149] The sixth transistor T6 may have p-type transistor characteristics and may include a polycrystalline semiconductor. The sixth transistor T6 plays a role in transmitting the driving current output from the driving transistor T1 to the light emitting diode LED. The gate electrode of the sixth transistor T6 is connected to the light emitting control line 155, the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T1, and the second electrode of the sixth transistor T6 is connected to the anode electrode of the light emitting diode LED.

[0150] The seventh transistor T7 may have p-type transistor characteristics and may include a polycrystalline semiconductor. The seventh transistor T7 serves to initialize the anode electrode of the light emitting diode LED. The gate electrode of the seventh transistor T7 is connected to the bypass control line 154, the first electrode of the seventh transistor T7 is connected to the anode electrode of the light emitting diode LED, and the second electrode of the seventh transistor T7 is connected to the second initialization voltage line 128. If the seventh transistor T7 is turned on at a low voltage in the bypass signal GB, the second initialization voltage AINT is applied to the anode electrode of the light emitting diode LED and the anode electrode of the light emitting diode LED is initialized.

[0151] In the above description, one pixel includes seven transistors T1 to T7 , one holding capacitor Cst, and one boosting capacitor Cboost, but the present invention is not limited thereto, and the number of transistors and capacitors and their connection relationship may be variously changed.

[0152] In this embodiment, the driving transistor T1 may include a polycrystalline semiconductor. In addition, the third transistor T3 and the fourth transistor T4 may include an oxide semiconductor. The second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include a polycrystalline semiconductor. However, it is not limited to this, and any one or more of the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may include an oxide semiconductor. In this embodiment, the third transistor T3 and the fourth transistor T4 include a semiconductor material different from that of the driving transistor T1, so that the driving can be more stably performed and the reliability can be improved.

[0153] As described above, when a high voltage is applied to the scan line 151, a low voltage is applied to the reverse scan line 152, and when a low voltage is applied to the scan line 151, a high voltage is applied to the reverse scan line 152. That is, the reverse scan signal GC applied to the reverse scan line 152 is formed as a signal opposite to the scan signal GW applied to the scan line 151, which will pull down the gate voltage of the driving transistor T1 after the data is written. On the contrary, the scan signal GW will pull up the gate voltage of the driving transistor T1. Therefore, when the black voltage is written, the black voltage can be reduced. In this embodiment, the boost capacitor Cboost is located between the scan line 151 to which the scan signal GW is applied and the gate electrode of the driving transistor T1, so that the gate voltage of the driving transistor T1 can be increased and the black voltage can be stably output.

[0154] The rising portion of the gate voltage of the driving transistor T1 based on the boost capacitor Cboost is defined as a boost voltage. The boost voltage is determined by Equation 1.

[0155] [Mathematical formula 1]

[0156]

[0157] (Vb: boost voltage, Cboost: capacity of boost capacitor, Cst: capacity of hold capacitor, VGH: high voltage, VGL: low voltage)

[0158] Therefore, the larger the capacity of the boost capacitor Cboost is, the more the gate voltage of the driving transistor T1 can be increased. By adjusting the capacity of the boost capacitor Cboost, the gate voltage of the driving transistor T1 can be controlled.

[0159] In this embodiment, the third transistor T3 and the fourth transistor T4 may have Figures 1 to 4 In addition, in this embodiment, the driving transistor T1 may have a structure similar to that of the first transistor TR1 in the embodiment shown in FIG. Figures 1 to 4 . Therefore, the insulating film located around the third transistor T3 and the fourth transistor T4 can have a low hydrogen concentration, and the insulating film located around the driving transistor T1 can have a high hydrogen concentration. In addition, the semiconductors of the third transistor T3 and the fourth transistor T4 are doped with substances such as boron (B), phosphorus (P), argon (Ar), xenon (Xe) and krypton (Kr). In addition, the boost capacitor Cboost is also doped with substances such as boron (B), phosphorus (P), argon (Ar), xenon (Xe) and krypton (Kr).

[0160] Below, refer to Figures 7 to 9The planar and cross-sectional structures of the driving transistor T1 , the third transistor T3 , the fourth transistor T4 , and the boost capacitor Cboost are further described.

[0161] Figure 7 is a top view showing a display device according to an embodiment, Figure 8 is along Figure 7 The cross-sectional view shown on line VIII-VIII, Fig. 9 is along Figure 7 The IX-IX line shows a cross-sectional view. Figures 7 to 9 Two adjacent pixels are shown, and the two pixels may have mutually symmetrical shapes. Hereinafter, the pixel located on the left side is mainly described. In addition, in the case of the seventh transistor T7, since it is connected to the scan line 151 at the rear end, it is omitted and the seventh transistor T7 at the front end is shown instead.

[0162] like Figures 7 to 9 As shown, a polycrystalline semiconductor including a channel 1132, a first electrode 1131, and a second electrode 1133 of a driving transistor T1 may be located on a substrate 110. The polycrystalline semiconductor may include not only the driving transistor T1 but also channels, first electrodes, and second electrodes of second, fifth, sixth, and seventh transistors T2, T5, T6, and T7.

[0163] The channel 1132 of the driving transistor T1 can be formed in a curved shape on a plane. However, the shape of the channel 1132 of the driving transistor T1 is not limited thereto, and various changes can be made. For example, the channel 1132 of the driving transistor T1 can also be bent in other shapes, or can be formed in a strip shape. The first electrode 1131 and the second electrode 1133 of the driving transistor T1 can be located on both sides of the channel 1132 of the driving transistor T1. The first electrode 1131 of the driving transistor T1 extends up and down on a plane, and the portion extending to the upper side can be connected to the second electrode of the second transistor T2, and the portion extending to the lower side can be connected to the second electrode of the fifth transistor T5. The second electrode 1133 of the driving transistor T1 can extend downward on a plane and be connected to the first electrode of the sixth transistor T6.

[0164] The buffer layer 111 may be located between the substrate 110 and the polycrystalline semiconductor including the channel 1132 of the driving transistor T1, the first electrode 1131, and the second electrode 1133. The buffer layer 111 may have a single layer or a multi-layer structure. The buffer layer 111 may include an organic insulating material or an inorganic insulating material.

[0165] The first gate insulating film 141 may be located on the polycrystalline semiconductor including the channel 1132 of the driving transistor T1, the first electrode 1131, and the second electrode 1133. The first gate insulating film 141 may include silicon nitride, silicon oxide, or the like.

[0166] The first gate conductor including the gate electrode 1151 of the driving transistor T1 and the first electrode 1155 of the boost capacitor Cboost may be located on the first gate insulating film 141. The first gate conductor may further include a scan line 151 and a light emission control line 155. The scan line 151 and the light emission control line 155 may extend in a substantially lateral direction.

[0167] The gate electrode 1151 of the driving transistor T1 may overlap the channel 1132 of the driving transistor T1. The channel 1132 of the driving transistor T1 is covered by the gate electrode 1151 of the driving transistor T1. The first electrode 1155 of the boost capacitor Cboost may extend horizontally on the plane and be connected to the gate electrode of the second transistor T2 and the scan line 151.

[0168] After forming the first gate conductor including the gate electrode 1151 of the driving transistor T1 and the first electrode 1155 of the boost capacitor Cboost, a doping process may be performed. The polycrystalline semiconductor blocked by the first gate conductor is not doped, and the portion of the polycrystalline semiconductor not covered by the first gate conductor is doped and may have the same characteristics as the conductor. At this time, a doping process may be performed with a p-type dopant, and the driving transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 including the polycrystalline semiconductor may have p-type transistor characteristics.

[0169] The second gate insulating film 142 may be located on the first gate conductor including the gate electrode 1151 of the driving transistor T1, the first electrode 1155 of the boosting capacitor Cboost, and the first gate insulating film 141. The second gate insulating film 142 may include silicon nitride, silicon oxide, or the like.

[0170] The second gate conductor including the first holding electrode 1153 of the holding capacitor Cst may be located on the second gate insulating film 142 .

[0171] The first holding electrode 1153 overlaps with the gate electrode 1151 of the driving transistor T1 to form a holding capacitor Cst. An opening 1152 is formed in the first holding electrode 1153 of the holding capacitor Cst. The opening 1152 of the first holding electrode 1153 of the holding capacitor Cst may overlap with the gate electrode 1151 of the driving transistor T1.

[0172] The second gate conductor may further include an initialization voltage line 127, a lower initialization control line 153a, and a lower reverse scan line 152a. The initialization voltage line 127, the lower initialization control line 153a, and the lower reverse scan line 152a may extend in a substantially lateral direction. The second gate conductor may further include a light blocking layer 3155 of the third transistor T3 and a light blocking layer 4155 of the fourth transistor T4. The light blocking layer 3155 of the third transistor T3 may overlap with the channel 3137 and the gate electrode 3151 of the third transistor T3. The light blocking layer 4155 of the fourth transistor T4 may overlap with the channel 4137 and the gate electrode 4151 of the fourth transistor T4.

[0173] The first interlayer insulating film 161 may be located on the second gate conductor including the first holding electrode 1153 of the holding capacitor Cst. The first interlayer insulating film 161 may include silicon nitride, silicon oxide, or the like.

[0174] An oxide semiconductor including a channel 3137, a first electrode 3136, and a second electrode 3138 of the third transistor T3, a channel 4137, a first electrode 4138, and a second electrode 4136 of the fourth transistor T4, and a second electrode 1135 of the boost capacitor Cboost may be located on the first interlayer insulating film 161. The oxide semiconductor may include a metal oxide, for example, IGZO (Indium-Gallium-Zinc Oxide).

[0175] The channel 3137, the first electrode 3136 and the second electrode 3138 of the third transistor T3, the channel 4137, the first electrode 4138 and the second electrode 4136 of the fourth transistor T4, and the second electrode 1135 of the boost capacitor Cboost are connected to each other. The first electrode 3136 and the second electrode 3138 of the third transistor T3 may be located on both sides of the channel 3137 of the third transistor T3. The first electrode 4138 and the second electrode 4136 of the fourth transistor T4 may be located on both sides of the channel 4137 of the fourth transistor T4. The second electrode 1135 of the boost capacitor Cboost is connected to the second electrode 3138 of the third transistor T3. The second electrode 1135 of the boost capacitor Cboost is connected to the second electrode 4136 of the fourth transistor T4. The second electrode 1135 of the boost capacitor Cboost may overlap with the first electrode 1155. The capacity of the boost capacitor Cboost can be determined by the overlapping area of ​​the first electrode 1155 and the second electrode 1135 of the boost capacitor Cboost, the thickness of the second gate insulating film 142 and the first interlayer insulating film 161 located between the first electrode 1155 and the second electrode 1135, and the like.

[0176] The third gate insulating film 143 may be located on the oxide semiconductor including the channel 3137, the first electrode 3136, and the second electrode 3138 of the third transistor T3, the channel 4137, the first electrode 4138, and the second electrode 4136 of the fourth transistor T4, and the second electrode 1135 of the boost capacitor Cboost. The third gate insulating film 143 may be located on the entire surface of the oxide semiconductor and the first interlayer insulating film 161. Therefore, the third gate insulating film 143 covers the top surface and side surfaces of the channel 3137, the first electrode 3136, and the second electrode 3138 of the third transistor T3, and the channel 4137, the first electrode 4138, and the second electrode 4136 of the fourth transistor T4.

[0177] As described in the previous embodiment, in the process of achieving high resolution, the size of each pixel is reduced, thereby reducing the length of the semiconductor channel. At this time, if the third gate insulating film 143 does not cover the top surfaces of the first electrode 3136 and the second electrode 3138 of the third transistor T3, the first electrode 4138 and the second electrode 4136 of the fourth transistor T4, a part of the oxide semiconductor material may move to the side of the third gate insulating film 143. In this embodiment, the third gate insulating film 143 is located on the entire surface of the oxide semiconductor and the first interlayer insulating film 161, so as to prevent the oxide semiconductor and the gate electrode 3151 of the third transistor T3 from being short-circuited, and to prevent the oxide semiconductor and the gate electrode 4151 of the fourth transistor T4 from being short-circuited.

[0178] However, the present embodiment is not limited thereto, and the third gate insulating film 143 may not be located on the entire surface of the oxide semiconductor and the first interlayer insulating film 161. For example, the third gate insulating film 143 may overlap with the channel 3137 of the third transistor T3, but may not overlap with the first electrode 3136 and the second electrode 3138. In addition, the third gate insulating film 143 may overlap with the channel 4137 of the fourth transistor T4, but may not overlap with the first electrode 4138 and the second electrode 4136.

[0179] A third gate conductor including a gate electrode 3151 of the third transistor T3 and a gate electrode 4151 of the fourth transistor T4 may be located on the third gate insulating film 143 .

[0180] The gate electrode 3151 of the third transistor T3 may overlap with the channel 3137 of the third transistor T3. The gate electrode 3151 of the third transistor T3 may be connected to the reverse scan line 152. At this time, the gate electrode 3151 of the third transistor T3 may be connected to the upper reverse scan line 152b. The gate electrode 4151 of the fourth transistor T4 may overlap with the channel 4137 of the fourth transistor T4. The gate electrode 4151 of the fourth transistor T4 may be connected to the initialization control line 153. At this time, the gate electrode 4151 of the fourth transistor T4 may be connected to the upper initialization control line 153b.

[0181] The third gate conductor may further include an upper initialization control line 153b and an upper reverse scan line 152b. The upper initialization control line 153b and the upper reverse scan line 152b may extend in a substantially lateral direction. The upper initialization control line 153b and the lower initialization control line 153a together form the initialization control line 153. The upper reverse scan line 152b and the lower reverse scan line 152a together form the reverse scan line 152.

[0182] The second interlayer insulating film 162 may be located on the third gate conductor including the gate electrode 3151 of the third transistor T3 and the gate electrode 4151 of the fourth transistor T4 .

[0183] The first opening 165, the second opening 166, the third opening 167, and the fourth opening 168 may be formed in the second interlayer insulating film 162 and the third gate insulating film 143. The first opening 165 may overlap with at least a portion of the gate electrode 1151 of the driving transistor T1. The first opening 165 may be formed not only in the second interlayer insulating film 162 and the third gate insulating film 143, but also in the first interlayer insulating film 161 and the second gate insulating film 142. The first opening 165 may overlap with the opening 1152 of the first holding electrode 1153. The first opening 165 may be located inside the opening 1152 of the first holding electrode 1153. The second opening 166 may overlap with at least a portion of the second electrode 1135 of the boost capacitor Cboost. The third opening 167 may overlap with at least a portion of the first electrode 3136 of the third transistor T3. The fourth opening 168 may overlap with at least a portion of the first electrode 4138 of the fourth transistor T4.

[0184] The first connection electrode 1175, the second connection electrode 3175, and the third connection electrode 4175 may be located on the second interlayer insulating film 162. The first connection electrode 1175 may be connected to the gate electrode 1151 of the driving transistor T1 through the first opening 165 and the opening 1152 of the first holding electrode 1153. The first connection electrode 1175 may be connected to the second electrode 1135 of the boost capacitor Cboost through the second opening 166. Therefore, through the first connection electrode 1175, the gate electrode 1151 of the driving transistor T1 and the second electrode 1135 of the boost capacitor Cboost may be connected. The second connection electrode 3175 may be connected to the first electrode 3136 of the third transistor T3 through the third opening 167. The second connection electrode 3175 may also be connected to the sixth transistor T6. Therefore, through the second connection electrode 3175, the first electrode 3136 of the third transistor T3 and the sixth transistor T6 may be connected. The third connection electrode 4175 may be connected to the first electrode 4138 of the fourth transistor T4 through the fourth opening 168. The third connection electrode 4175 may be connected to the initialization voltage line 127. Therefore, through the third connection electrode 4175, the first electrode 4138 of the fourth transistor T4 and the initialization voltage line 127 may be connected.

[0185] The third interlayer insulating film 180 may be located on the first connection electrode 1175 , the second connection electrode 3175 , and the third connection electrode 4175 .

[0186] The data line 171 and the driving voltage line 172 may be located on the third interlayer insulating film 180. The data line 171 and the driving voltage line 172 may extend in a substantially longitudinal direction. The data line 171 may be connected to the second transistor T2. The driving voltage line 172 may be connected to the fifth transistor T5.

[0187] The protective film 182 may be located above the data line 171 and the driving voltage line 172. Although not shown, the anode electrode may be located above the protective film 182. The anode electrode may be connected to the sixth transistor T6 and may receive the transmission of the output current of the driving transistor T1. The partition wall may be located above the anode electrode. An opening is formed in the partition wall, and the opening of the partition wall may overlap with the anode electrode. The light-emitting element layer may be located in the opening of the partition wall. The cathode electrode may be located above the light-emitting element layer and the partition wall. The anode electrode, the light-emitting element layer, and the cathode electrode constitute a light-emitting diode LED.

[0188] As described above, in a display device according to an embodiment, the driving transistor T1 may include a polycrystalline semiconductor, and the third transistor T3 and the fourth transistor T4 may include an oxide semiconductor. As described above, the third transistor T3 and the fourth transistor T4 include semiconductor materials different from the driving transistor T1, so that the driving can be more stably performed and the reliability can be improved.

[0189] In addition, in the process of achieving high resolution, the size of each pixel is reduced, thereby reducing the length of the semiconductor channel. In order to stably control the critical voltage of the oxide semiconductor with a short channel length, the process of forming the insulating film around the oxide semiconductor of the third transistor T3 and the fourth transistor T4 can be performed in a low hydrogen state. Therefore, the first interlayer insulating film 161 connected to the lower side of the oxide semiconductor can have a low hydrogen concentration. For example, the hydrogen concentration of the first interlayer insulating film 161 can be less than 1.0E +21 atoms / cm 3 In addition, the third gate insulating film 143 in contact with the upper side of the oxide semiconductor may have a low hydrogen concentration. For example, the hydrogen concentration of the third gate insulating film 143 may be less than 1.14E +21 atoms / cm 3 In addition, the second interlayer insulating film 162 that is in contact with the third gate insulating film 143 may have a low hydrogen concentration. For example, the hydrogen concentration of the second interlayer insulating film 162 may be less than 1.0E +22 atoms / cm 3 .

[0190] In this way, the first interlayer insulating film 161, the third gate insulating film 143, and the second interlayer insulating film 162 located around the oxide semiconductor may have a low hydrogen concentration. On the contrary, the first gate insulating film 141 and the second gate insulating film 142 may have a high hydrogen concentration. Therefore, the hydrogen concentration of the first interlayer insulating film 161, the third gate insulating film 143, and the second interlayer insulating film 162 may be lower than the hydrogen concentration of the first gate insulating film 141 and the second gate insulating film 142.

[0191] However, the concentration of hydrogen that can act as a carrier of an oxide semiconductor is low, so the on-state current of the third transistor T3 and the fourth transistor T4 may be reduced, and the second electrode 1135 of the boost capacitor Cboost may exhibit semiconductor characteristics. Figures 10 to 12 As shown, carrier substances are doped into the oxide semiconductor, so that the on-state current of the third transistor T3 and the fourth transistor T4 can be prevented from being reduced, and the second electrode 1135 of the boost capacitor Cboost can be prevented from having semiconductor characteristics. Fig.10is a top view showing a part of the layers of a display device according to an embodiment, Fig.11 is shown along Fig.10 The cross-sectional view shown on line XI-XI, Fig.12 is shown along Fig.10 The XII-XII line shows a cross-sectional view. Fig.13 is a graph showing voltage-capacitance characteristics of a boost capacitor in a display device according to an embodiment, Fig.14 is a graph showing the voltage-capacitance characteristics of the boosting capacitor in the display device according to the comparative example.

[0192] Reference Figures 10 to 13 , a third gate insulating film 143 is formed on the oxide semiconductor, and a gate electrode 3151 of the third transistor T3 and a gate electrode 4151 of the fourth transistor T4 are formed on the third gate insulating film 143. The gate electrode 3151 of the third transistor T3 and the gate electrode 4151 of the fourth transistor T4 are used as masks, and boron (B) is injected into the entire surface above the third gate insulating film 143. Boron (B) is not injected into the channel 3137 of the third transistor T3 and the channel 4137 of the fourth transistor T4 that overlap with the gate electrode 3151 of the third transistor T3 and the gate electrode 4151 of the fourth transistor T4. Boron (B) is injected into the first electrode 3136 and the second electrode 3138 that do not overlap with the gate electrode 3151 of the third transistor T3, and into the first electrode 4138 and the second electrode 4136 that do not overlap with the gate electrode 4151 of the fourth transistor T4. In addition, boron (B) is injected into the entire region of the second electrode 1135 of the boost capacitor Cboost. Therefore, the first electrode 3136 and the second electrode 3138 of the third transistor T3, the first electrode 4138 and the second electrode 4136 of the fourth transistor T4, and the second electrode 1135 of the boost capacitor Cboost may be doped with boron (B). The doping concentration of the first electrode 3136 and the second electrode 3138 of the third transistor T3, the first electrode 4138 and the second electrode 4136 of the fourth transistor T4, and the second electrode 1135 of the boost capacitor Cboost may be 5E +18 cm -3 At this time, phosphorus (P), argon (Ar), xenon (Xe) and krypton (Kr) etc. may be used to dope the oxide semiconductor instead of boron (B). In this way, through the doping process of the oxide semiconductor, the carrier concentration of the oxide semiconductor will be increased, and the on-current of the third transistor T3 and the fourth transistor T4 can be increased. In addition, the semiconductor behavior of the second electrode 1135 of the boost capacitor Cboost can be improved.

[0193] exist Fig.14In the figure, it can be confirmed that in the case of the boost capacitor Cboost (Ref.) without boron (B) doping, although it has good capacitance characteristics in the range of 0V to 10V, the capacitance decreases sharply in the range of 0V to -10V. This is because the second electrode 1135 of the boost capacitor Cboost has semiconductor behavior. Fig.13 It can be confirmed that the doping concentration of the boost capacitor Cboost (B+Impla.) doped with boron (B) under the condition of about 35 kV can be about 1E +19 cm -3 In this case, the second electrode 1135 of the boost capacitor Cboost has good capacitance characteristics in the entire voltage range. That is, this is because the second electrode 1135 of the boost capacitor Cboost is doped as a whole and exhibits conductor characteristics.

[0194] The embodiments of the present invention are described in detail above, but the scope of the present invention is not limited thereto. Various modifications and improvements made by those skilled in the art using the basic concepts of the present invention defined in the following claims also fall within the scope of the present invention.

Claims

1. A display device, wherein: include: substrate; A polycrystalline semiconductor, located on the substrate, and comprising a channel of a driving transistor, a first electrode and a second electrode; a first gate insulating film, located on the polycrystalline semiconductor; a gate electrode of the driving transistor, located on the first gate insulating film and overlapping with the channel of the driving transistor; a first electrode of a boost capacitor, located on the first gate insulating film; a second gate insulating film, located on the gate electrode of the driving transistor and the first electrode of the boosting capacitor; a first interlayer insulating film, located on the second gate insulating film; an oxide semiconductor located on the first interlayer insulating film and including a channel of a third transistor, a first electrode of the third transistor, a second electrode of the third transistor, a channel of a fourth transistor, a first electrode of the fourth transistor, a second electrode of the fourth transistor, and a second electrode of the boosting capacitor connected to each other; a third gate insulating film, located on the oxide semiconductor; a gate electrode of a third transistor, located on the third gate insulating film and overlapping with a channel of the third transistor; a gate electrode of a fourth transistor, located on the third gate insulating film and overlapping with a channel of the fourth transistor; as well as a second interlayer insulating film located on the gate electrode of the third transistor and the gate electrode of the fourth transistor, The hydrogen concentrations of the first interlayer insulating film, the third gate insulating film, and the second interlayer insulating film are lower than the hydrogen concentrations of the first gate insulating film and the second gate insulating film. The first electrode and the second electrode of the third transistor, the first electrode and the second electrode of the fourth transistor, and the second electrode of the boosting capacitor of the oxide semiconductor are doped with at least one of boron, phosphorus, argon, xenon, and krypton.

2. The display device according to claim 1, wherein: The third gate insulating film is located entirely on the oxide semiconductor and the first interlayer insulating film.

3. The display device according to claim 2, wherein: The third gate insulating film covers the top surface and side surfaces of the oxide semiconductor.

4. The display device according to claim 1, wherein: The hydrogen concentration of the first interlayer insulating film is less than 1.0E +21 atoms / cm 3 .

5. The display device according to claim 1, wherein: The hydrogen concentration of the third gate insulating film is less than 1.14E +21 atoms / cm 3 .

6. The display device according to claim 1, wherein: The hydrogen concentration of the second interlayer insulating film is less than 1.0E +22 atoms / cm 3 .

7. The display device according to claim 1, wherein: The doping concentration of the first electrode region and the second electrode region of the oxide semiconductor is 5E +18 cm -3 above.

8. A display device, wherein: include: A light emitting diode connected between a driving voltage line to which a driving voltage is applied and a common voltage line to which a common voltage is applied; A driving transistor connected between the driving voltage line and the light emitting diode; a second transistor connected between the first electrode of the driving transistor connected to the driving voltage line and the data line to which the data voltage is applied; a third transistor connected between the second electrode of the driving transistor connected to the light emitting diode and the gate electrode of the driving transistor; a fourth transistor connected between the gate electrode of the driving transistor and a first initialization voltage line to which a first initialization voltage is applied; A holding capacitor connected between the driving voltage line and the gate electrode of the driving transistor; as well as A boost capacitor is connected between the gate electrode of the second transistor and the gate electrode of the driving transistor.

9. The display device according to claim 8, wherein: The gate electrode of the second transistor is connected to a scanning line to which a scanning signal is applied, The gate electrode of the third transistor is connected to a reverse scanning line to which a reverse scanning signal is applied. At the same timing, a voltage having a polarity opposite to that of the voltage applied to the scanning line is applied to the reverse scanning line.

10. The display device according to claim 8, wherein: The driving transistor and the second transistor include polycrystalline semiconductors, The third transistor and the fourth transistor include an oxide semiconductor, At least a portion of the oxide semiconductor is doped with at least any one of boron, phosphorus, argon, xenon, and krypton.

11. The display device according to claim 10, wherein: The driving transistor and the second transistor are formed of p-type transistors, The third transistor and the fourth transistor are formed of n-type transistors.

12. The display device according to claim 10, wherein: The second electrode of the boosting capacitor connected to the gate electrode of the driving transistor is doped with at least any one of boron, phosphorus, argon, xenon, and krypton.

13. The display device according to claim 10, wherein: The display device further includes: a fifth transistor connected between the driving voltage line and the first electrode of the driving transistor; a sixth transistor connected between the first electrode of the driving transistor and the light emitting diode; and The seventh transistor is connected between the second initialization voltage line to which the second initialization voltage is applied and the light emitting diode.

14. A display device, wherein: include: substrate; a polycrystalline semiconductor disposed on the substrate; a first gate insulating film, located on the polycrystalline semiconductor; A driving gate electrode, located on the first gate insulating film; a second gate insulating film, located on the driving gate electrode; a first interlayer insulating film, located on the second gate insulating film; an oxide semiconductor located on the first interlayer insulating film; a third gate insulating film, located on the oxide semiconductor; a switch gate electrode, located on the third gate insulating film; as well as A second interlayer insulating film is located on the switch gate electrode, The hydrogen concentrations of the first interlayer insulating film, the third gate insulating film, and the second interlayer insulating film are lower than the hydrogen concentrations of the first gate insulating film and the second gate insulating film. The oxide semiconductor includes a channel located in the center and a source region and a drain region located on both sides of the channel. The source region and the drain region of the oxide semiconductor are doped with at least one substance selected from boron, phosphorus, argon, xenon and krypton.

15. The display device according to claim 14, wherein: The third gate insulating film is located entirely on the oxide semiconductor and the first interlayer insulating film.

16. The display device according to claim 15, wherein: The third gate insulating film covers the top surface and side surfaces of the channel, the source region, and the drain region of the oxide semiconductor.

17. The display device according to claim 14, wherein: The hydrogen concentration of the first interlayer insulating film is less than 1.0E +21 atoms / cm 3 .

18. The display device according to claim 14, wherein: The hydrogen concentration of the third gate insulating film is less than 1.14E +21 atoms / cm 3 .

19. The display device according to claim 14, wherein: The hydrogen concentration of the second interlayer insulating film is less than 1.0E +22 atoms / cm 3 .

20. The display device according to claim 14, wherein: The doping concentration of the source region and the drain region of the oxide semiconductor is 5E +18 cm -3 above.

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