Magnetic random access memory unit and method for forming magnetic random access memory

Abstract

A magnetic random access memory unit and a method for forming a magnetic random access memory, wherein the magnetic random access memory unit comprises: a substrate, wherein the substrate comprises a plurality of active regions and isolation regions between the active regions; a gate structure located on the active regions; and a word line structure located on the active regions and the isolation regions, wherein the sidewalls of the word line structure are in contact with the sidewalls of the gate structure. The performance of the magnetic random access memory unit is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a magnetic random access memory unit and a method for forming a magnetic random access memory. Background Art

[0002] Magnetic random access memory is a non-volatile memory technology that is being widely accepted by the industry as a mainstream data storage technology. It integrates a magnetoresistive device and a silicon-based selection matrix. Key attributes are non-volatility, low voltage operation, unlimited read and write endurance, fast read and write operations, and easy integration as a back-end technology. These characteristics make magnetic random access memory a potential replacement for many types of memory in various applications.

[0003] However, as semiconductor technology nodes shrink, the size of semiconductor devices is also getting smaller and smaller. The existing magnetic random access memory is large in size and is not suitable for advanced semiconductor processes. Summary of the invention

[0004] The technical problem solved by the present invention is to provide a magnetic random access memory unit and a method for forming a magnetic random access memory so as to reduce the size of the magnetic random access memory.

[0005] To solve the above technical problems, the technical solution of the present invention provides a magnetic random access memory unit, comprising: a substrate, the substrate comprising a plurality of active areas and isolation areas between the active areas; a gate structure located on the active areas; a word line structure located on the active areas and on the isolation areas, the side walls of the word line structure being in contact with the side walls of the gate structure.

[0006] Optionally, it also includes: a source region and a drain region located in the substrate on both sides of the gate structure; and a dielectric structure located on the substrate, wherein the gate structure and the word line structure are located in the dielectric structure.

[0007] Optionally, it further includes: a source line structure electrically connected to the source region, the source line structure extending along a first direction parallel to the substrate surface, and the source line structure is located in the dielectric structure.

[0008] Optionally, it also includes: a magnetic tunnel structure, the bottom of which is electrically connected to the drain region; a bit line structure, the bit line structure is electrically connected to the top of the magnetic tunnel structure, the bit line structure extends along a second direction parallel to the substrate surface, and the second direction is perpendicular to the first direction; the bit line structure and the magnetic tunnel structure are located in the dielectric structure.

[0009] Optionally, a bottom plane of the magnetic tunnel structure is higher than a top plane of the source line structure.

[0010] Optionally, the magnetic tunnel structure includes: a fixed layer; an insulating layer located on the fixed layer; and a free layer located on the insulating layer.

[0011] Optionally, the source line structure is parallel to the word line structure and the gate structure.

[0012] Optionally, a bottom plane of the source line structure is higher than a top plane of the word line structure and a top plane of the gate structure.

[0013] Optionally, the substrate includes a base, a fin structure located on the base, and an isolation layer located on a partial side wall of the fin structure, the fin structure is located in the active area; the word line structure and the gate structure span the fin structure, and the first direction is perpendicular to an extension direction of the fin structure.

[0014] Optionally, the interval between adjacent fin structures is a first size, the width of the fin structure is a second size, and the first size is less than or equal to the second size.

[0015] Correspondingly, the technical solution of the present invention also provides a method for forming a magnetic random access memory, comprising: providing a substrate, the substrate comprising a plurality of active areas and isolation areas located between the active areas; forming a gate structure and a word line structure on the substrate, the gate structure being located in the active area, the word line structure being located in the active area and in the isolation area, and the sidewalls of the word line structure being in contact with the sidewalls of the gate structure.

[0016] Optionally, the method for forming the gate structure and the word line structure includes: forming a gate material layer on the substrate; forming a word line material layer on the gate material layer; forming a patterned mask layer on the word line material layer; and etching the word line material layer and the gate material layer using the patterned mask layer as a mask to form the gate structure and the word line structure.

[0017] Optionally, after forming the word line structure and the gate structure, the method further includes: forming a source region and a drain region in the substrate on both sides of the gate structure; and forming a dielectric structure on the substrate, wherein the gate structure and the word line structure are located in the dielectric structure.

[0018] Optionally, a source line structure is formed in the dielectric structure, the source line structure is electrically connected to the source region, and the source line structure extends along a first direction parallel to the substrate surface.

[0019] Optionally, it also includes: forming a magnetic tunnel structure in the dielectric structure, the bottom of the magnetic tunnel structure is electrically connected to the drain region; forming a bit line structure in the dielectric structure, the bit line structure is electrically connected to the top of the magnetic tunnel structure, the bit line structure extends along a second direction parallel to the substrate surface, and the second direction is perpendicular to the first direction; the magnetic tunnel structure includes: a buffer layer; a fixed layer located on the buffer layer; an insulating layer located on the fixed layer; a free layer located on the insulating layer; and a covering layer located on the free layer.

[0020] Optionally, a bottom plane of the magnetic tunnel structure is higher than a top plane of the source line structure.

[0021] Optionally, the word line structure and the gate structure are parallel to the source line structure.

[0022] Optionally, a bottom plane of the source line structure is higher than top planes of the word line structure and the gate structure.

[0023] Optionally, the substrate includes a base, a fin structure located on the base, and an isolation layer located on a partial side wall of the fin structure, the fin structure is located in the active area; the word line structure and the gate structure span the fin structure, and the first direction is perpendicular to an extension direction of the fin structure.

[0024] Optionally, the interval between adjacent fin structures is a first size, the width of the fin structure is a second size, and the first size is less than or equal to the second size.

[0025] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0026] In the magnetic random access memory unit of the technical solution of the present invention, the side wall of the word line structure is in contact with the side wall of the gate structure, and the word line structure and the gate structure are in the same layer, thereby leaving sufficient space for the device that needs to be formed on the word line structure later, so that the formation of the device has a larger process window, and the device can be better isolated from the word line structure and the gate structure, which is beneficial to improving the performance of the magnetic random access memory unit.

[0027] Furthermore, the source line structure extends along a first direction parallel to the substrate surface, thereby reducing the size of the magnetic random access memory unit in the first direction, reducing the area of ​​the magnetic random access memory unit, which is beneficial to improving the integration of the magnetic random access memory unit and further saving the area of ​​the magnetic random access memory.

[0028] In the method for forming a magnetic random access memory of the technical solution of the present invention, the side wall of the word line structure is in contact with the side wall of the gate structure, and the word line structure and the gate structure are in the same layer, thereby leaving enough space for the device that needs to be formed on the word line structure later, so that the formation of the device has a larger process window, and the device can be better isolated from the word line structure and the gate structure, which is beneficial to improving the performance of the magnetic random access storage unit, and further improving the performance of the magnetic random access memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 and Figure 2 is a schematic diagram of a magnetic random access memory in one embodiment;

[0030] Figures 3 to 14 It is a schematic diagram of the formation process of the magnetic random access memory in an embodiment of the present invention. DETAILED DESCRIPTION

[0031] As described in the background art, the size of the existing magnetic random access memory is relatively large and is not suitable for advanced semiconductor processes.

[0032] Figure 1 and Figure 2 is a schematic diagram of a magnetic random access memory in one embodiment.

[0033] Please refer to Figure 1 and Figure 2 , Figure 1 for Figure 2 Omit the top view of the dielectric structure. Figure 2 for Figure 1The schematic cross-sectional structure diagram along the section line MN includes: a substrate 100, the substrate 100 having a fin 101; a gate structure 104 spanning the fin 101, the fins 101 on both sides of the gate structure 104 having a source region 103 and a drain region 102; a dielectric structure located on the substrate 100, the dielectric structure including a first dielectric layer 105, a second dielectric layer 106, a third dielectric layer 107, a fourth dielectric layer 108, a fifth dielectric layer 109, a sixth dielectric layer 110 and a seventh dielectric layer 111 overlapping in sequence, the gate structure 104 being located The first dielectric layer 105 includes a word line structure 112 located in the second dielectric layer 106, the word line structure 102 being electrically connected to the top of the gate structure 104; a source line structure 113 located in the fourth dielectric layer 108, the source line structure 113 being electrically connected to the source region 103; a magnetic tunnel structure 114 located in the sixth dielectric layer 110, the magnetic tunnel structure 114 being electrically connected to the drain region 102; and a bit line structure 115 located on the surface of the seventh dielectric layer 111, the bit line structure 115 being electrically connected to the top of the magnetic tunnel structure 114.

[0034] In the storage unit of the magnetic random access memory, on the one hand, the source line structure 113 is electrically connected to the source region 103 through a second plug (not labeled) located in the third dielectric layer 107, a first metal layer (not labeled) located in the second dielectric layer 106, and a first plug (not labeled) located in the first dielectric layer 105; the word line structure 102 is electrically connected to the top of the gate structure 104 through a first plug (not labeled) located in the first dielectric layer 105. The source line structure 113 and the word line structure 102 are isolated from each other by the third dielectric layer 107. The source line structure 113 and the word line structure 102 are relatively close to each other. In order to avoid the situation in which the process of forming the source line structure 113 damages the third dielectric layer 107 and then causes damage to the word line structure 102, the process conditions for forming the source line structure 113 are subject to certain restrictions, so that the process window for forming the source line structure 113 is small, which increases the process difficulty. At the same time, the source line structure 113 and the word line structure 102, which are relatively close to each other, may be short-circuited, thereby affecting the performance of the magnetic random access memory.

[0035] On the other hand, in the memory cell of the magnetic random access memory, the word line structure 112 extends along a second direction Y parallel to the surface of the substrate 100, and the second direction Y is perpendicular to the extension direction of the fin 101; the source line structure 113 and the bit line structure 115 extend along a first direction X parallel to the surface of the substrate 100, and the first direction X is perpendicular to the second direction Y, and the first direction X is the extension direction of the fin 101. The source line structure 113 and the bit line structure 115 have a certain width, so that in the second direction Y, the source line structure 113 and the bit line structure 115 need to occupy a certain space to meet the size requirements of the source line structure 113 and the bit line structure 115.

[0036] However, in the structure of the magnetic random access memory formed by a plurality of memory cells, the adjacent fins 101 have a spacing P, and as the semiconductor technology node is reduced, the size of the fin spacing P is getting smaller and smaller. The memory cell is formed on a single fin, and the source line structure 113 and the bit line structure 115 still need to occupy a certain space, that is, the formed fin unit requires a certain process window, and a certain space is required between adjacent fins to form the fin unit, so that the size of the fin spacing P cannot be further reduced, so that the magnetic random access memory cannot meet the technical requirements of advanced semiconductors.

[0037] In order to solve the above problems, the technical solution of the present invention provides a method for forming a magnetic random access memory cell and a magnetic random access memory, by forming a word line structure and a gate structure on a substrate, the sidewall of the word line structure is in contact with the sidewall of the gate structure, and the word line structure and the gate structure are in the same layer, so that sufficient space is reserved for the device to be formed on the word line structure later, so that the formation of the device has a large process window, and the device can be well isolated from the word line structure and the gate structure, which is conducive to improving the performance of the magnetic random access memory cell. At the same time, the source line structure extends along a first direction parallel to the substrate surface, thereby reducing the size of the magnetic random access memory cell in a direction perpendicular to the first direction, so that the area of ​​the magnetic random access memory cell is reduced, which is conducive to improving the integration of the magnetic random access memory cell.

[0038] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] Figures 3 to 14 It is a schematic diagram of the formation process of the magnetic random access memory in an embodiment of the present invention.

[0040] Please refer to Figure 3 and Figure 4 , Figure 3 yes Figure 4 A top view of Figure 4 yes Figure 3 A schematic structural diagram along the section line DD' direction is provided, wherein a substrate is provided, and the substrate includes a plurality of active regions I and isolation regions II located between the active regions I.

[0041] The active region I is a region on the substrate where active devices are formed, and the active devices include diodes, triodes, transistors or integrated circuits; the isolation region II is a region on the substrate where an isolation structure is formed to electrically isolate the active devices.

[0042] In this embodiment, the substrate includes a base 200 , a plurality of fin structures 201 located on the base 200 , and an isolation layer 202 located on a portion of the sidewalls of the fin structures 201 . The fin structures 201 are located in the active region I.

[0043] The arrangement direction of the plurality of fin structures 201 is a first direction X, and the first direction X is parallel to the substrate surface; the extension direction of the fin structures 201 is a second direction Y, and the second direction Y is perpendicular to the first direction X.

[0044] In this embodiment, the memory cell of the magnetic random access memory is formed on a single fin structure 201. In other embodiments, the memory cell of the magnetic random access memory can be formed on a plurality of fin structures.

[0045] The interval B between adjacent fin structures 201 is a first size, the width A of the fin structure 201 is a second size, and the first size is less than or equal to the second size.

[0046] Since the subsequently formed source line structure extends along the first direction X parallel to the substrate surface, the size of the magnetic random access memory unit in the first direction X is reduced, so that the area of ​​the magnetic random access memory unit is reduced, so that the spacing B between adjacent fin structures 201 can be further reduced, so that the first size is less than or equal to the second size, thereby improving the integration of the magnetic random access memory unit and reducing the area of ​​the magnetic random access memory.

[0047] In other embodiments, the substrate comprises a planar substrate.

[0048] In this embodiment, the material of the substrate 200 is single crystal silicon; the material of the fin structure 201 is single crystal silicon; and the material of the isolation layer 202 includes silicon oxide.

[0049] In other embodiments, the substrate may also be a semiconductor material such as polysilicon, germanium, silicon germanium, gallium arsenide or silicon on insulator; the fin structure may also be a semiconductor material such as polysilicon, germanium, silicon germanium, gallium arsenide or silicon on insulator; the material of the isolation layer includes silicon nitride, silicon oxynitride or silicon carbide.

[0050] A gate structure and a word line structure are formed on a substrate, wherein the gate structure is located in the active region I, and the word line structure is located in the active region I and in an isolation region II, and a sidewall of the word line structure contacts a sidewall of the gate structure.

[0051] Please refer to Figures 5 to 7 , Figure 5 for Figure 6 A top view of Figure 5 for Figure 7 A top view of Figure 6 for Figure 5 Schematic diagram of the structure along the section line EE'. Figure 7 for Figure 5 Schematic diagram of the local structure along the section line II', a gate structure 203 and a word line structure 204 are formed on the substrate, the gate structure 203 is located in the active area I, the word line structure 204 is located in the active area I and the isolation area II, and the sidewall of the word line structure 204 is in contact with the sidewall of the gate structure 203.

[0052] In this embodiment, the gate structure 203 spans across the fin structure 201 ; in other embodiments, the gate structure is located on the substrate.

[0053] The method for forming the gate structure 203 and the word line structure 204 includes: forming a gate material layer (not shown) on the substrate; forming a word line material layer (not shown) on the gate material layer; forming a patterned mask layer (not shown) on the word line material layer; etching the word line material layer and the gate material layer using the patterned mask layer as a mask until the substrate surface is exposed to form the gate structure 203 and the word line structure 204.

[0054] The material of the gate structure 203 includes metal, and the metal includes one or more combinations of tungsten, aluminum, cobalt, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium and copper; the material of the word line structure 204 includes metal, and the metal includes one or more combinations of tungsten, aluminum, cobalt, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium and copper.

[0055] In this embodiment, the gate structure 203 is made of tungsten, and the word line structure 204 is made of tungsten. The gate structure 203 and the word line structure 204 are made of the same material.

[0056] In other embodiments, the material of the gate structure is different from the material of the word line structure.

[0057] The process for forming the gate material layer includes a physical vapor deposition process, an atomic layer deposition process or an electroplating process; the process for forming the word line material layer includes a physical vapor deposition process, an atomic layer deposition process or an electroplating process; the process for etching the word line material layer and the gate material layer includes a combination of one or more of a dry etching process and a wet etching process.

[0058] In this embodiment, the process of forming the gate material layer includes a physical vapor deposition process; the process of forming the word line material layer includes a physical vapor deposition process; the process of etching the word line material layer and the gate material layer includes a dry etching process, and the dry etching process can form a gate structure 203 and a word line structure 204 with good sidewall morphology.

[0059] In this embodiment, the gate material layer and the word line material layer are formed simultaneously using one forming process. In other embodiments, the gate material layer and the word line material layer can be formed separately using different processes.

[0060] The side walls of the word line structure 204 are in contact with the side walls of the gate structure 203, so that the word line structure 204 and the gate structure 203 are in the same layer, thereby leaving enough space for devices that need to be formed on the word line structure later, so that the formation of the device has a larger process window, and the device can be better isolated from the word line structure 204 and the gate structure 203, which is beneficial to improving the performance of the magnetic random access storage unit.

[0061] Please refer to Figure 8 and Fig. 9 , Figure 8 yes Fig. 9 A top view of Fig. 9 yes Figure 8 , a schematic cross-sectional structure diagram of a single magnetic random access memory cell along the direction of the cross-sectional line FF′, wherein a source region 205 and a drain region 206 are formed in the fin structure 201 on both sides of the gate structure 203 .

[0062] In other embodiments, source and drain regions are formed in the substrate on both sides of the gate structure.

[0063] The process of forming the source region 205 and the drain region 206 includes an epitaxial growth process or an ion implantation process.

[0064] In this embodiment, the process of forming the source region 205 and the drain region 206 includes an epitaxial growth process.

[0065] When the magnetic random access memory cell is an N-type device, the material of the source region 205 and the material of the drain region 206 include carbon silicon. When the magnetic random access memory cell is a P-type device, the material of the source region 205 and the material of the drain region 206 include silicon germanium.

[0066] Next, a dielectric structure is formed on the substrate, wherein the gate structure 203 and the word line structure 204 are located in the dielectric structure, and the dielectric structure includes a first dielectric structure, a second dielectric structure and a third dielectric structure; a magnetic tunnel structure is formed in the dielectric structure, wherein the bottom of the magnetic tunnel structure is electrically connected to the drain region 206; a bit line structure is formed in the dielectric structure, wherein the bit line structure is electrically connected to the top of the magnetic tunnel structure, and wherein the bit line structure extends along a second direction Y parallel to the substrate surface; and a source line structure is formed in the dielectric structure, wherein the source line structure is electrically connected to the source region 205, and wherein the source line structure extends along a first direction X parallel to the substrate surface.

[0067] Please refer to Fig.10 and Fig.11 , Fig.10 for Fig.11 The top view of the first dielectric layer 301 and the second dielectric layer 302 is omitted. Fig.11 for Fig.10 A schematic cross-sectional structure diagram of a single magnetic random access memory unit along the cross-sectional line GG′ direction, wherein a first dielectric structure is formed on a substrate; a source line structure 208 is formed in the first dielectric structure, and the source line structure 208 is electrically connected to the source region 205 .

[0068] The bottom plane of the source line structure 208 is higher than the top plane of the word line structure 204 and the top plane of the gate structure 203 .

[0069] Since the sidewalls of the word line structure 204 are in contact with the sidewalls of the gate structure 203, the word line structure 204 and the gate structure 203 are in the same layer, thereby leaving enough space for the source line structure formed on the word line structure 204, so that the formation of the source line structure has a larger process window, and the source line structure can be better isolated from the sidewalls of the word line structure 204 and the gate structure 203, which is beneficial to improving the performance of the magnetic random access storage unit, and further improving the performance of the magnetic random access memory.

[0070] The source line structure 208 is parallel to the word line structure 204 and the gate structure 203 , and the source line structure extends along a first direction X parallel to the surface of the substrate.

[0071] Since the formed source line structure 208 extends along the first direction X parallel to the substrate surface, the size of the magnetic random access memory unit in the first direction X is reduced, so that the area of ​​the magnetic random access memory unit is reduced, so that the spacing B between adjacent fin structures 201 can be further reduced, avoiding the situation that when the source line structure extends along the second direction Y, the source line structure needs to occupy the size of the magnetic random access memory unit in the first direction X, making the area of ​​the magnetic random access memory unit larger and unable to reduce the spacing between adjacent fin structures. In summary, the integration of the magnetic random access memory unit is improved, thereby saving the area of ​​the magnetic random access memory.

[0072] In this embodiment, the first dielectric structure includes: a first dielectric layer 301 and a second dielectric layer 302 located on the first dielectric layer 301 .

[0073] The second dielectric layer 302 is used to provide spatial support for the source line structure 208; the first dielectric layer 301 is used to provide spatial support for the plug that plays a conductive connection role when the bottom of the source line structure 208 is electrically connected to the source region 205, and also electrically isolates each structure.

[0074] The method for forming the source line structure 208 comprises: forming a first dielectric layer 301 on a substrate, wherein the gate structure 203 and the word line structure 204 are located in the first dielectric layer 301; forming a first opening (not shown) in the first dielectric layer 301, wherein the first opening exposes the surface of the source region 205; forming a plug material layer (not shown) in the first opening and on the surface of the first dielectric layer 301; planarizing the plug material layer until the surface of the first dielectric layer 301 is exposed, and forming a first plug 207 in the first opening, wherein the first plug 207 is in contact with the first dielectric layer 301; The source region 205 is electrically connected; a second dielectric layer 302 is formed on the first dielectric layer 301; a second opening (not shown) is formed in the second dielectric layer 302, and the second opening exposes the top surface of the first plug 207 and a portion of the surface of the first dielectric layer 301; a source line material layer (not shown) is formed in the second opening and on the surface of the second dielectric layer 302; the source line material layer is planarized until the surface of the second dielectric layer 302 is exposed, and a source line structure 208 is formed in the second opening, and the source line structure 208 is electrically connected to the first plug 207.

[0075] The material of the first dielectric layer 301 includes a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride and silicon carbide; the material of the second dielectric layer 302 includes a combination of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride and silicon carbide; the material of the first plug 207 includes a metal, and the metal includes a combination of one or more of tungsten, aluminum, cobalt, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium and copper; the material of the source line structure 208 includes a metal, and the metal includes a combination of one or more of tungsten, aluminum, cobalt, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium and copper.

[0076] In this embodiment, the material of the first dielectric layer 301 includes silicon oxide; the material of the second dielectric layer 302 includes silicon oxide; the material of the first plug 207 includes titanium; and the material of the source line structure 208 includes tungsten.

[0077] The process of forming the plug material layer includes a physical vapor deposition process, an atomic layer deposition process or an electroplating process; the process of forming the source line material layer includes a physical vapor deposition process, an atomic layer deposition process or an electroplating process.

[0078] In this embodiment, the process of forming the plug material layer includes a physical vapor deposition process; the process of forming the source line material layer includes a physical vapor deposition process; the process of planarizing the plug material layer includes a chemical mechanical polishing process; the process of planarizing the source line material layer includes a chemical mechanical polishing process.

[0079] In this embodiment, while the first plug 207 is formed in the first dielectric layer 301, a second plug 209 is also formed in the first dielectric layer 301, and the second plug 209 is electrically connected to the drain region 206; while the source line structure 208 is formed, a first metal layer 210 is also formed on the second plug 209, and the first metal layer 210 is electrically connected to the second plug 209.

[0080] The second plug 209 and the first metal layer 210 located on the second plug 209 are used to realize electrical connection between a subsequently formed magnetic tunnel structure and the drain region 206 .

[0081] In other embodiments, the first plug and the first metal layer may not be formed at the same time.

[0082] The method for forming the first dielectric layer 301 includes: forming a dielectric material layer (not shown) on the substrate; and planarizing the dielectric material layer to a preset thickness to form the first dielectric layer 301 .

[0083] The method for forming the second dielectric layer 302 includes: forming a dielectric material layer (not shown) on the first dielectric layer 301 ; and planarizing the dielectric material layer to a preset thickness to form the second dielectric layer 302 .

[0084] Please refer to Fig.12 , Fig.12 For Fig.11 A schematic structural diagram of a substrate, a second dielectric structure is formed on a substrate; a magnetic tunnel structure 214 is formed in the second dielectric structure, and the bottom of the magnetic tunnel structure 214 is electrically connected to the drain region 206.

[0085] The magnetic tunnel structure 214 includes: a fixed layer (not labeled); an insulating layer (not labeled) located on the fixed layer; and a free layer (not labeled) located on the insulating layer.

[0086] The material of the fixed layer includes a ferromagnetic material, which includes cobalt iron boron, cobalt iron, nickel iron or cobalt iron nickel; the material of the insulating layer includes magnesium oxide or aluminum oxide; the material of the free layer includes a ferromagnetic material, which includes cobalt iron boron, cobalt iron, nickel iron or cobalt iron nickel.

[0087] A bottom plane of the magnetic tunnel structure 214 is higher than a top plane of the source line structure 208 .

[0088] In this embodiment, the second dielectric structure includes: a third dielectric layer 303 , a fourth dielectric layer 304 located on the third dielectric layer 303 , a fifth dielectric layer 305 located on the fourth dielectric layer 304 , and a sixth dielectric layer 306 located on the fifth dielectric layer 305 .

[0089] The sixth dielectric layer 306 is used to provide spatial support for the magnetic tunnel structure 214; the third dielectric layer 303, the fourth dielectric layer 304 and the fifth dielectric layer 305 are used to provide spatial support for several metal layers and plugs that play a conductive connection role when the bottom of the magnetic tunnel structure 214 is electrically connected to the drain region 206, and also to electrically isolate each structure.

[0090] The method for forming the magnetic tunnel structure 214 includes: forming a third dielectric layer 303 on the second dielectric layer 302; forming a third plug 211 in the third dielectric layer 303, wherein the third plug 211 is electrically connected to the first metal layer 210; forming a fourth dielectric layer 304 on the third dielectric layer 303; forming a second metal layer 212 in the fourth dielectric layer 304, wherein the second metal layer 212 is electrically connected to the third plug 211; forming a fifth dielectric layer 305 on the fourth dielectric layer 304; and forming a fifth dielectric layer 306 on the fifth dielectric layer 307. 5, wherein a bottom electrode 213 is formed in the bottom electrode 213, and the bottom electrode 213 is electrically connected to the second metal layer 212; a magnetic tunnel structure material layer (not shown) is formed on the fifth dielectric layer 305; a patterned mask layer (not shown) is formed on the magnetic tunnel structure material layer, and the patterned mask layer exposes a portion of the surface of the magnetic tunnel structure material layer on the surface of the bottom electrode 213; the magnetic tunnel structure material layer is etched using the patterned mask layer as a mask until the surface of the fifth dielectric layer 305 is exposed, thereby forming the magnetic tunnel structure 214.

[0091] The materials and forming methods of the third dielectric layer 303, the fourth dielectric layer 304 and the fifth dielectric layer 305 are the same as those of the first dielectric layer 301 and the second dielectric layer 302. Fig.11 , I will not go into details here.

[0092] The materials and forming methods of the third plug 211 and the bottom electrode 213 are the same as those of the first plug 207. Fig.11 , I will not go into details here.

[0093] After the magnetic tunnel structure 214 is formed, a sixth dielectric layer 306 is formed on the fifth dielectric layer 305 , and the sixth dielectric layer 306 exposes the top surface of the magnetic tunnel structure 214 .

[0094] The material of the sixth dielectric layer 306 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbon nitride and silicon carbide. In this embodiment, the material of the sixth dielectric layer 306 includes silicon oxide.

[0095] The method for forming the sixth dielectric layer 306 includes: forming a dielectric material layer (not shown) on the fifth dielectric layer 305 and the top surface and sidewall surface of the magnetic tunnel structure 214; and planarizing the dielectric material layer until the surface of the magnetic tunnel structure 214 is exposed to form the sixth dielectric layer 306.

[0096] Please refer to Fig.13 and Fig.14 , Fig.13 for Fig.14 Omit the top view of the dielectric structure. Fig.14 for Fig.13 A schematic cross-sectional structure diagram of a single magnetic random access memory cell along the cross-sectional line HH′ direction, wherein a third dielectric structure is formed on the substrate; a bit line structure 216 is formed on the third dielectric structure, and the bit line structure 216 is electrically connected to the top of the magnetic tunnel structure 214 .

[0097] The third dielectric structure includes a seventh dielectric layer 307 ; the seventh dielectric layer 307 provides spatial support for the bit line structure 216 electrically connected to the top of the magnetic tunnel structure 214 , and also electrically isolates each structure.

[0098] The method for forming the bit line structure 216 includes: forming a seventh dielectric layer 307 on the sixth dielectric layer 306; forming a top electrode 215 in the seventh dielectric layer 307, wherein the top electrode 215 is electrically connected to the top of the magnetic tunnel structure 214; forming a bit line material layer (not shown) on the seventh dielectric layer 307; forming a patterned mask layer (not shown) on the bit line material layer; etching the bit line material layer using the patterned mask layer as a mask until the surface of the seventh dielectric layer 307 is exposed, thereby forming the bit line structure 216, wherein the bit line structure 216 is electrically connected to the top electrode 215.

[0099] The material and forming method of the top electrode 215 are the same as those of the first plug 207. Fig.11 , I will not go into details here.

[0100] The material and forming method of the seventh dielectric layer 307 are the same as those of the first dielectric layer 301 and the second dielectric layer 302. Fig.11 , I will not go into details here.

[0101] The material of the bit line structure 216 includes metal, and the metal includes one or more combinations of tungsten, aluminum, cobalt, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium and copper; the process of forming the bit line material layer includes physical vapor deposition process, atomic layer deposition process or electroplating process.

[0102] In this embodiment, the material of the source line structure 208 includes tungsten; and the process of forming the bit line material layer includes a physical vapor deposition process.

[0103] The bit line structure 214 extends along a second direction Y parallel to the substrate surface, and the second direction Y is perpendicular to the first direction X.

[0104] The bit line structure 214 extends along a second direction Y parallel to the substrate surface. Since the formed source line structure 208 extends along a first direction X parallel to the substrate surface, the size of the magnetic random access memory unit in the first direction X is reduced, so that the area of ​​the magnetic random access memory unit is reduced, so that the spacing B between adjacent fin structures 201 can be further reduced, avoiding the situation that when the source line structure extends along the second direction Y, the source line structure and the bit line structure need to occupy a certain space in the first direction X, making the area of ​​the magnetic random access memory unit larger and unable to reduce the spacing between adjacent fin structures. In summary, the integration of the magnetic random access memory unit is improved, thereby saving the area of ​​the magnetic random access memory.

[0105] Accordingly, the embodiment of the present invention also provides a magnetic random access memory and a storage unit, please continue to refer to Fig.13 and Fig.14 ,include:

[0106] A substrate, wherein the substrate comprises a plurality of active regions I and an isolation region II located between the active regions I;

[0107] A gate structure 203 located on the active area I;

[0108] The word line structure 204 is located on the active region I and the isolation region II, and the sidewall of the word line structure 204 is in contact with the sidewall of the gate structure 203 .

[0109] In this embodiment, it also includes: a source region 205 and a drain region 206 located in the fin structure 201 on both sides of the gate structure 203; and a dielectric structure located on the substrate, wherein the gate structure 203 and the word line structure 204 are located in the dielectric structure.

[0110] In this embodiment, it further includes: a source line structure 208 located in the dielectric structure, the source line structure 208 is electrically connected to the source region 205, and the source line structure 208 extends along a first direction X parallel to the substrate surface.

[0111] In this embodiment, it also includes: a magnetic tunnel structure 214 located in the dielectric structure, the bottom of the magnetic tunnel structure 214 is electrically connected to the drain region 206; a bit line structure 216 located in the dielectric structure, the bit line structure 216 is electrically connected to the top of the magnetic tunnel structure 214, and the bit line structure 216 extends along a second direction Y parallel to the substrate surface, and the second direction Y is perpendicular to the first direction X.

[0112] In this embodiment, a bottom plane of the magnetic tunnel structure 214 is higher than a top plane of the source line structure 208 .

[0113] In this embodiment, the magnetic tunnel structure 214 includes: a buffer layer; a fixed layer located on the buffer layer; an insulating layer located on the fixed layer; a free layer located on the insulating layer; and a capping layer located on the free layer.

[0114] In this embodiment, the word line structure 204 and the gate structure 203 are parallel to the source line structure 208 .

[0115] In this embodiment, a bottom plane of the source line structure 208 is higher than top planes of the word line structure 204 and the gate structure 203 .

[0116] In this embodiment, the substrate includes a base 200, a fin structure 201 located on the base 200, and an isolation layer 202 located on a partial side wall of the fin structure 201, and the fin structure 201 is located in the active area I; the gate structure 203 and the word line structure 204 span the fin structure 201, and the first direction X is perpendicular to the extension direction of the fin structure.

[0117] In this embodiment, the interval B between adjacent fin structures 201 is a first size, the width A of the fin structure 201 is a second size, and the first size is less than or equal to the second size.

[0118] In the magnetic random access memory unit of the technical solution of the present invention, the side wall of the word line structure is in contact with the side wall of the gate structure, and the word line structure and the gate structure are in the same layer, thereby leaving sufficient space for the device that needs to be formed on the word line structure later, so that the formation of the device has a larger process window, and the device can be better isolated from the word line structure and the gate structure, which is beneficial to improving the performance of the magnetic random access memory unit.

[0119] The source line structure extends along a first direction parallel to the substrate surface, thereby reducing the size of the magnetic random access memory unit in the first direction, reducing the area of ​​the magnetic random access memory unit, which is beneficial to improving the integration of the magnetic random access memory unit and further saving the area of ​​the magnetic random access memory.

[0120] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A magnetic random access memory unit, characterized in that: include: A substrate, the substrate comprising a plurality of active regions and an isolation region between the active regions, the substrate comprising a base and a fin structure on the base, the fin structure being located in the active region, and the arrangement direction of the plurality of fin structures being a first direction; A gate structure and a word line structure spanning the fin structure, the gate structure is located on the active area, the word line structure is located on the active area and the isolation area, and a sidewall of the word line structure is in contact with a sidewall of the gate structure; A source line structure is located on the substrate, the source line structure extends along a first direction parallel to the surface of the substrate, and the source line structure is parallel to the word line structure and the gate structure.

2. The magnetic random access memory unit according to claim 1, wherein: Also includes: Source and drain regions located in the substrate on both sides of the gate structure; A dielectric structure is located on the substrate, and the gate structure and the word line structure are located in the dielectric structure.

3. The magnetic random access memory unit according to claim 2, characterized in that: The source line structure is electrically connected to the source region, and the source line structure is located in the dielectric structure.

4. The magnetic random access memory unit according to claim 3, characterized in that: Also includes: A magnetic tunnel structure, the bottom of which is electrically connected to the drain region; A bit line structure is electrically connected to the top of the magnetic tunnel structure, and the bit line structure extends along a second direction parallel to the substrate surface, and the second direction is perpendicular to the first direction; the bit line structure and the magnetic tunnel structure are located in the dielectric structure.

5. The magnetic random access memory unit according to claim 4, characterized in that: A bottom plane of the magnetic tunnel structure is higher than a top plane of the source line structure.

6. The magnetic random access memory unit according to claim 4, characterized in that: The magnetic tunnel structure includes: a fixed layer; an insulating layer located on the fixed layer; and a free layer located on the insulating layer.

7. The magnetic random access memory unit according to claim 3, characterized in that: A bottom plane of the source line structure is higher than a top plane of the word line structure and a top plane of the gate structure.

8. The magnetic random access memory unit according to claim 1, wherein: The substrate further includes: an isolation layer located on a sidewall of a portion of the fin structure, and the first direction is perpendicular to an extension direction of the fin structure.

9. The magnetic random access memory unit according to claim 1, wherein: The spacing between adjacent fin structures is a first size, the width of the fin structure is a second size, and the first size is less than or equal to the second size.

10. A method for forming a magnetic random access memory, characterized in that: include: Providing a substrate, the substrate comprising a plurality of active regions and an isolation region between the active regions, the substrate comprising a base, a fin structure on the base, the fin structure being located in the active region, and the arrangement direction of the plurality of fin structures being a first direction; Forming a gate structure and a word line structure on a substrate, wherein the gate structure is located in the active area, the word line structure is located in the active area and in an isolation area, the gate structure and the word line structure span the fin structure, and a sidewall of the word line structure contacts a sidewall of the gate structure; A source line structure is formed on the substrate, wherein the source line structure extends along a first direction parallel to the surface of the substrate, and the source line structure is parallel to the word line structure and the gate structure.

11. The method for forming a magnetic random access memory according to claim 10, wherein: The method for forming the gate structure and the word line structure comprises: forming a gate material layer on the substrate; A word line material layer is formed on the gate material layer; a patterned mask layer is formed on the word line material layer; and the word line material layer and the gate material layer are etched using the patterned mask layer as a mask to form the gate structure and the word line structure.

12. The method for forming a magnetic random access memory according to claim 10, wherein: After forming the word line structure and the gate structure, the method further includes: forming a source region and a drain region in the substrate on both sides of the gate structure; and forming a dielectric structure on the substrate, wherein the gate structure and the word line structure are located in the dielectric structure.

13. The method for forming a magnetic random access memory according to claim 12, wherein: The source line structure is located in the dielectric structure, and the source line structure is electrically connected to the source region.

14. The method for forming a magnetic random access memory according to claim 12, wherein: Also includes: forming a magnetic tunnel structure in the dielectric structure, wherein the bottom of the magnetic tunnel structure is electrically connected to the drain region; forming a bit line structure in the dielectric structure, the bit line structure being electrically connected to the top of the magnetic tunnel structure, the bit line structure extending along a second direction parallel to the substrate surface, the second direction being perpendicular to the first direction; The magnetic tunnel structure comprises: A buffer layer; a fixed layer located on the buffer layer; an insulating layer located on the fixed layer; a free layer located on the insulating layer; and a covering layer located on the free layer.

15. The method for forming a magnetic random access memory according to claim 14, wherein: A bottom plane of the magnetic tunnel structure is higher than a top plane of the source line structure.

16. The method for forming a magnetic random access memory according to claim 10, wherein: A bottom plane of the source line structure is higher than top planes of the word line structure and the gate structure.

17. The method for forming a magnetic random access memory according to claim 10, wherein: The substrate further includes: an isolation layer located on a sidewall of a portion of the fin structure, and the first direction is perpendicular to an extension direction of the fin structure.

18. The method for forming a magnetic random access memory according to claim 10, wherein: The spacing between adjacent fin structures is a first size, the width of the fin structure is a second size, and the first size is less than or equal to the second size.

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